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CSD87381P
SLPS405F – MARCH 2013 – REVISED MARCH 2015
CSD87381P Synchronous Buck NexFET™ Power Block II
1 Features
3 Description
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The CSD87381P NexFET™ power block II is a highly
optimized design for synchronous buck applications
offering high current and high efficiency capability in a
small 3 mm × 2.5 mm outline. Optimized for 5 V gate
drive applications, this product offers an efficient and
flexible solution capable of providing a high density
power supply when paired with any 5 V gate driver
from an external controller/driver.
1
Half-Bridge Power Block
90% System Efficiency at 10 A
Up to 15 A Operation
High Density – 3 × 2.5 mm LGA Footprint
Double Side Cooling Capability
Ultra-Low Profile – 0.48 mm Max
Optimized for 5 V Gate Drive
Low Switching Losses
Low Inductance Package
RoHS Compliant
Halogen Free
Pb Free
TEXT ADDED FOR SPACING
Device Information(1)
Device
Media
Qty
CSD87381P
13-Inch Reel
2500
CSD87381PT
7-Inch Reel
250
•
•
Ship
3 × 2.5 LGA
Tape and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
Package
TEXT ADDED FOR SPACING
Synchronous Buck Converters
– High Current, Low Duty Cycle Applications
Multiphase Synchronous Buck Converters
POL DC-DC Converters
1
VIN
TG
PGND
BG
VSW
Typical Circuit
Typical Power Block Efficiency and Power Loss
VIN
VDD
VDD
100
7
90
6
BOOT
VIN
ENABLE
PWM
ENABLE
PWM
VOUT
LL
BG
DRVL
PGND
Driver IC
VGS = 5V
VIN = 12V
VOUT = 1.3V
LOUT = 0.95µH
fSW = 500kHz
TA = 25ºC
80
VSW
Efficiency (%)
GND
70
60
5
4
3
50
2
40
1
Power Loss (W)
TG
DRVH
CSD87381P
30
0
3
6
9
Output Current (A)
12
15
0
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD87381P
SLPS405F – MARCH 2013 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1
5.2
5.3
5.4
5.5
5.6
5.7
3
3
3
4
4
5
7
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Power Block Performance ........................................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Power Block Characteristics.........................
Typical Power Block MOSFET Characteristics.........
Application and Implementation ........................ 10
6.1 Application Information............................................ 10
7
Layout ................................................................... 14
7.1 Layout Guidelines ................................................... 14
7.2 Layout Example ...................................................... 14
8
Device and Documentation Support.................. 15
8.1 Trademarks ............................................................. 15
8.2 Electrostatic Discharge Caution .............................. 15
8.3 Glossary .................................................................. 15
9
Mechanical, Packaging, and Orderable
Information ........................................................... 16
9.1
9.2
9.3
9.4
9.5
9.6
CSD87381P Package Dimensions .........................
Land Pattern Recommendation ..............................
Stencil Recommendation (100 µm).........................
Stencil Recommendation (125 µm).........................
Pin Drawing.............................................................
CSD87381P Embossed Carrier Tape Dimensions .
16
17
18
18
19
19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (June 2014) to Revision F
Page
•
Changed capacitance units to read pF in Figure 15 ............................................................................................................. 8
•
Changed capacitance units to read pF in Figure 16 ............................................................................................................. 8
Changes from Revision D (May 2014) to Revision E
•
Page
Changed "Pb Free terminal plating" feature to state "Pb Free" ............................................................................................ 1
Changes from Revision C (January 2014) to Revision D
Page
•
Updated data sheet to reflect new standards......................................................................................................................... 1
•
Corrected device dimensions ................................................................................................................................................ 1
Changes from Revision B (May 2013) to Revision C
Page
•
Updated title............................................................................................................................................................................ 1
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Added small reel info .............................................................................................................................................................. 1
•
Added unit to test condition in Electrical Characteristics........................................................................................................ 4
•
Added a link for Figure 29 in Electrical Performance ........................................................................................................... 14
Changes from Revision A (March 2013) to Revision B
Page
•
Changed RθJC-PCB To: RθJC in the Thermal Information table.................................................................................................. 4
•
Changed Figure 15................................................................................................................................................................. 7
Changes from Original (March 2013) to Revision A
•
2
Page
Changes to a Product Preview device .................................................................................................................................. 1
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Copyright © 2013–2015, Texas Instruments Incorporated
CSD87381P
www.ti.com
SLPS405F – MARCH 2013 – REVISED MARCH 2015
5 Specifications
5.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted)
(1)
VIN to PGND
MIN
MAX
–0.8
30
VSW to PGND
Voltage
UNIT
30
VSW to PGND (10 ns)
32
TG to VSW
–8
10
BG to PGND
–8
10
V
IDM
Pulsed Current Rating (2)
PD
Power Dissipation (3)
EAS
Avalanche Energy
TJ
Operating Junction
–55
150
°C
Tstg
Storage Temperature Range
–55
150
°C
(1)
(2)
(3)
40
A
4
W
Sync FET, ID = 27, L = 0.1 mH
36
Control FET, ID = 20, L = 0.1 mH
20
mJ
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
Pulse Duration ≤50 µs, duty cycle ≤0.01
Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu
5.2 Recommended Operating Conditions
TA = 25° (unless otherwise noted)
MIN
VGS
Gate Drive Voltage
VIN
Input Supply Voltage
ƒSW
Switching Frequency
4.5
8
24
CBST = 0.1 μF (min)
Operating Current
TJ
MAX
200
1500
No Airflow
15
With Airflow (200 LFM)
20
With Airflow + Heat Sink
25
Operating Temperature
125
UNIT
V
V
kHz
A
°C
5.3 Power Block Performance
TA = 25° (unless otherwise noted)
PARAMETER
CONDITIONS
PLOSS
Power Loss (1)
VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 8 A,
ƒSW = 500 kHz,
LOUT = 0.3 µH, TJ = 25ºC
IQVIN
VIN Quiescent Current
TG to TGR = 0 V
BG to PGND = 0 V
(1)
MIN
TYP
MAX
UNIT
1
W
10
µA
Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5 V driver IC.
Copyright © 2013–2015, Texas Instruments Incorporated
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5.4 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
RθJC
(1)
(2)
Junction-to-ambient thermal resistance (min Cu)
Junction-to-ambient thermal resistance (max Cu)
TYP
MAX
UNIT
184
(2) (1)
Junction-to-case thermal resistance (top of package)
Junction-to-case thermal resistance (PGND pin)
MIN
(1)
84
(1)
4.9
(1)
°C/W
1.65
RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu.
5.5 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
Q1 Control FET
MIN
TYP
Q2 Sync FET
MAX
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-Source Voltage
VGS = 0 V, IDS = 250
μA
30
30
Drain-to-Source Leakage Current VGS = 0 V, VDS = 24
V
IDSS
Gate-to-Source Leakage Current
VDS = 0 V, VGS = 10
V
VGS(th)
Gate-to-Source Threshold
Voltage
VDS = VGS, IDS = 250
μA
RDS(on)
Drain-to-Source On-Resistance
gƒs
Transconductance
IGSS
1.1
V
1
1
μA
100
100
nA
1.7
V
1.9
1
VGS = 4.5 V, IDS = 8 A
15.7
18.9
7
8.4
VGS = 8 V, IDS = 8 A
13.6
16.3
6.3
7.6
VDS = 10 V, IDS = 8 A
40
89
mΩ
S
DYNAMIC CHARACTERISTICS
CISS
Input Capacitance
(1)
(1)
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
RG
Series Gate Resistance
Qg
Gate Charge Total (4.5 V)
Qgd
Gate Charge – Gate-to-Drain
Qgs
Gate Charge – Gate-to-Source
Qg(th)
Gate Charge at Vth
QOSS
td(on)
(1)
VGS = 0 V, VDS = 15
V,
ƒ = 1 MHz
(1)
Output Charge
(1)
Rise Time
td(off)
Turn Off Delay Time
tƒ
Fall Time
564
1020
1320
pF
225
293
308
400
pF
9.1
11.8
40
52
pF
5
6.4
1.25
2.5
Ω
3.9
5
8.9
11.5
nC
0.9
2.5
nC
1.2
2
nC
0.7
1.3
nC
4.9
8.5
nC
6.7
7.9
ns
19.3
16.3
ns
10.6
16.8
ns
3
2.9
ns
IDS = 8 A, VGS = 0 V
0.85
0.79
Vdd = 15 V, IF = 8 A,
di/dt = 300 A/μs
8
16
nC
13
17
ns
VDS = 15 V,
IDS = 8 A
VDD = 12 V, VGS = 0
V
Turn On Delay Time
tr
434
VDS = 15 V, VGS = 4.5
V,
IDS = 8 A, RG = 2 Ω
DIODE CHARACTERISTICS
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
(1)
4
V
Specified by design
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Copyright © 2013–2015, Texas Instruments Incorporated
CSD87381P
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SLPS405F – MARCH 2013 – REVISED MARCH 2015
Max RθJA = 84°C/W
when mounted on
1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick)
Cu.
Max RθJA = 184°C/W
when mounted on
minimum pad area of 2
oz. (0.071 mm thick)
Cu.
5.6 Typical Power Block Characteristics
TJ = 125°C, unless stated otherwise. For Figure 3 and Figure 4, the Typical Power Block System Characteristic curves are
based on measurements made on a PCB design with dimensions of 4 inches (W) × 3.5 inches (L) × 0.062 inch (H) and 6
copper layers of 1 oz. copper thickness. See Application and Implementation for detailed explanation.
1.1
5
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.95µH
Power Loss (W)
4
3.5
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.95µH
1
Power Loss, Normalized
4.5
3
2.5
2
1.5
1
0.9
0.8
0.7
0.6
0.5
0
1
2
3
4
5
0.5
−50
6 7 8 9 10 11 12 13 14 15
Output Current (A)
G001
20
15
15
10
400LFM
200LFM
100LFM
Nat Conv
5
0
0
10
20
30
40
50
60
70
Ambient Temperature (ºC)
90
G001
Figure 3. Safe Operating Area – PCB Horizontal Mount
Copyright © 2013–2015, Texas Instruments Incorporated
25
50
75
100
Junction Temperature (ºC)
125
150
G001
10
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
LOUT = 0.95µH
5
80
0
Figure 2. Normalized Power Loss vs Temperature
20
Output Current (A)
Output Current (A)
Figure 1. Power Loss vs Output Current
−25
0
0
20
40
60
80
100
Board Temperature (ºC)
120
140
G001
Figure 4. Typical Safe Operating Area
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Typical Power Block Characteristics (continued)
4.5
1.3
3.3
1.2
2.2
1.1
1.1
1
VIN = 12V
VGS = 5V
VOUT = 1.3V
LOUT = 0.95µH
IOUT = 15A
0.9
0.8
0.7
0
200
400
600
800 1000 1200
Switching Frequency (kHz)
1400
0.0
−1.1
2.3
1.15
1.7
1.1
1.1
1.05
0.6
VGS = 5V
VOUT = 1.3V
LOUT = 0.95µH
fSW = 500kHz
IOUT = 15A
1
0.95
−2.2
−3.3
1600
0.9
0
G001
1.4
4.5
4
1.35
1.3
3.4
1.25
2.8
1.2
2.3
1.15
1.7
1.1
VIN = 12V
VGS = 5V
fSW = 500kHz
LOUT = 0.95µH
IOUT = 15A
1.05
1
0.95
0.9
0.3
0.8
1.3
1.8
2.3 2.8 3.3 3.8
Output Voltage (V)
4.3
4.8
1.1
0.6
0
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8
10 12 14 16
Input Voltage (V)
18
20
22
24
−0.6
−1.1
G001
Figure 6. Normalized Power Loss vs Input Voltage
3.37
VIN = 12V
VGS = 5V
VOUT = 1.3V
fSW = 500kHz
IOUT = 15A
1.25
1.2
2.81
2.25
1.15
1.68
1.1
1.12
1.05
0.56
0
1
−0.6
−1.1
5.3
Figure 7. Normalized Power Loss vs Output Voltage
6
4
1.3
Power Loss, Normalized
5.1
SOA Temperature Adj (ºC)
Power Loss, Normalized
Figure 5. Normalized Power Loss vs Switching Frequency
1.45
2
0.0
SOA Temperature Adj (ºC)
1.4
1.2
SOA Temperature Adj (ºC)
5.6
Power Loss, Normalized
1.5
SOA Temperature Adj (ºC)
Power Loss, Normalized
TJ = 125°C, unless stated otherwise. For Figure 3 and Figure 4, the Typical Power Block System Characteristic curves are
based on measurements made on a PCB design with dimensions of 4 inches (W) × 3.5 inches (L) × 0.062 inch (H) and 6
copper layers of 1 oz. copper thickness. See Application and Implementation for detailed explanation.
0.95
G001
0
−0.56
100 200 300 400 500 600 700 800 900 1000 1100
Output Inductance (nH)
G001
Figure 8. Normalized Power Loss vs Output Inductance
Copyright © 2013–2015, Texas Instruments Incorporated
CSD87381P
www.ti.com
SLPS405F – MARCH 2013 – REVISED MARCH 2015
5.7 Typical Power Block MOSFET Characteristics
20
100
18
90
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
TA = 25°C, unless stated otherwise.
16
14
12
10
8
6
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
4
2
0
0
0.2
0.4
0.6
0.8
VDS - Drain-to-Source Voltage (V)
80
70
60
50
40
30
10
0
1
VGS = 8.0V
VGS = 4.5V
VGS = 4.0V
20
0
Figure 9. Control MOSFET Saturation
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
VDS = 5V
0.1
0.01
0.001
TC = 125°C
TC = 25°C
TC = −55°C
0.0001
1.2
G001
0
0.5
1
1.5
2
2.5
VGS - Gate-to-Source Voltage (V)
3
VDS = 5V
10
1
0.1
0.01
0.001
TC = 125°C
TC = 25°C
TC = −55°C
0.0001
0.00001
0
0.5
G001
Figure 11. Control MOSFET Transfer
1
1.5
2
2.5
VGS - Gate-to-Source Voltage (V)
3
G001
Figure 12. Sync MOSFET Transfer
10
10
ID = 8A
VDS =15V
9
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
1
100
1
8
7
6
5
4
3
2
1
0
0.4
0.6
0.8
VDS - Drain-to-Source Voltage (V)
Figure 10. Sync MOSFET Saturation
10
0.00001
0.2
G001
0
1
2
3
4
5
Qg - Gate Charge (nC)
6
7
Figure 13. Control MOSFET Gate Charge
Copyright © 2013–2015, Texas Instruments Incorporated
8
G001
ID = 8A
VDS = 15V
9
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
Qg - Gate Charge - nC (nC)
16
18
20
G001
Figure 14. Sync MOSFET Gate Charge
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Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise.
10000
10000
1000
C − Capacitance (pF)
C − Capacitance (pF)
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
100
10
1
0
5
10
15
20
25
VDS - Drain-to-Source Voltage (V)
1000
100
10
1
30
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0
Figure 15. Control MOSFET Capacitance
ID = 250µA
VGS(th) - Threshold Voltage (V)
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
−25
25
75
125
TC - Case Temperature (ºC)
ID = 250µA
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.6
−75
175
−25
G001
Figure 17. Control MOSFET VGS(th)
25
75
125
TC - Case Temperature (ºC)
175
G001
Figure 18. Sync MOSFET VGS(th)
40
20
ID = 8A
36
RDS(on) - On-State Resistance (mΩ)
RDS(on) - On-State Resistance (mΩ)
G001
0.7
0.9
−75
32
28
24
20
16
12
8
TC = 25°C
TC = 125ºC
4
0
1
2
3
4
5
6
7
8
VGS - Gate-to- Source Voltage (V)
9
Figure 19. Control MOSFET RDS(on) vs VGS
8
30
1.6
1.8
0
10
15
20
25
VDS - Drain-to-Source Voltage (V)
Figure 16. Sync MOSFET Capacitance
1.9
VGS(th) - Threshold Voltage (V)
5
G001
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G001
ID = 8A
18
16
14
12
10
8
6
4
TC = 25°C
TC = 125ºC
2
0
0
1
2
3
4
5
6
7
8
VGS - Gate-to- Source Voltage (V)
9
10
G001
Figure 20. Sync MOSFET RDS(on) vs VGS
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CSD87381P
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SLPS405F – MARCH 2013 – REVISED MARCH 2015
Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise.
1.6
Normalized On-State Resistance
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
−75
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
Normalized On-State Resistance
ID = 8A
VGS = 8V
1.5
−25
25
75
125
TC - Case Temperature (ºC)
ID = 8A
VGS = 8V
1
0.9
0.8
0.7
0.6
−75
175
G001
Figure 21. Control MOSFET Normalized RDS(on)
ISD − Source-to-Drain Current (A)
ISD − Source-to-Drain Current (A)
175
G001
100
10
1
0.1
0.01
0.001
TC = 25°C
TC = 125°C
0
0.2
0.4
0.6
0.8
1
VSD − Source-to-Drain Voltage (V)
1.2
10
1
0.1
0.01
0.001
0.0001
TC = 25°C
TC = 125°C
0
G001
Figure 23. Control MOSFET Body Diode
1
G001
I(AV) - Peak Avalanche Current (A)
100
10
TC = 25°C
TC = 125°C
1
0.01
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
Figure 24. Sync MOSFET Body Diode
100
I(AV) - Peak Avalanche Current (A)
25
75
125
TC - Case Temperature (ºC)
Figure 22. Sync MOSFET Normalized RDS(on)
100
0.0001
−25
0.1
t(AV) - Time in Avalanche (ms)
1
G001
Figure 25. Control MOSFET Unclamped Inductive Switching
Copyright © 2013–2015, Texas Instruments Incorporated
10
TC = 25°C
TC = 125°C
1
0.01
0.1
t(AV) - Time in Avalanche (ms)
1
G001
Figure 26. Sync MOSFET Unclamped Inductive Switching
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6 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI ’ s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information
The CSD87381P NexFET power block is an optimized design for synchronous buck applications using 5 V gate
drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and highest
system efficiency. As a result, a new rating method is needed, which is tailored towards a more systems-centric
environment. System-level performance curves such as Power Loss, Safe Operating Area, and normalized
graphs allow engineers to predict the product performance in the actual application.
6.1.1 Power Loss Curves
MOSFET-centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, TI has provided measured power loss performance
curves. Figure 1 plots the power loss of the CSD87381P as a function of load current. This curve is measured by
configuring and running the CSD87381P as it would be in the final application (see Figure 27). The measured
power loss is the CSD87381P loss and consists of both input conversion loss and gate drive loss. Equation 1 is
used to generate the power loss curve.
(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = Power Loss
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
6.1.2 Safe Operating Curves (SOA)
The SOA curves in the CSD87381P data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 4 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 inches
(W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1 oz. copper thickness.
6.1.3 Normalized Curves
The normalized curves in the CSD87381P data sheet provide guidance on the power loss and SOA adjustments
based on their application-specific needs. These curves show how the power loss and SOA boundaries adjust for
a given set of systems conditions. The primary y-axis is the normalized change in power loss, and the secondary
y-axis is the change is system temperature required in order to comply with the SOA curve. The change in power
loss is a multiplier for the power loss curve, and the change in temperature is subtracted from the SOA curve.
10
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Application Information (continued)
Input Current (IIN)
A
VDD
A
VDD
V
VIN
Gate Drive V
Voltage (VDD)
VIN
BOOT
DRVH
ENABLE
Input Voltage (VIN)
TG
Output Current (IOUT)
VSW
LL
PWM
PWM
DRVL
GND
Driver IC
A
VOUT
BG
PGND
CSD87381P
Averaging
Circuit
Averaged Switch
V Node Voltage
(VSW_AVG)
Figure 27. Typical Application
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Application Information (continued)
6.1.4 Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though
the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following
procedure outlines the steps the user should take to predict product performance for any set of system
conditions.
6.1.4.1 Design Example
Operating Conditions:
• Output Current = 8 A
• Input Voltage = 4 V
• Output Voltage = 1 V
• Switching Frequency = 800 kHz
• Inductor = 0.2 µH
6.1.4.2 Calculating Power Loss
•
•
•
•
•
•
Power Loss at 8 A = 1.44 W (Figure 1)
Normalized Power Loss for input voltage ≈ 1.06 (Figure 6)
Normalized Power Loss for output voltage ≈ 0.97 (Figure 7)
Normalized Power Loss for switching frequency ≈ 1.11 (Figure 5)
Normalized Power Loss for output inductor ≈ 1.13 (Figure 8)
Final calculated power loss = 1.44 W × 1.06 × 0.97 × 1.11 × 1.13 ≈ 1.86 W
6.1.4.3 Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 0.7ºC (Figure 6)
SOA adjustment for output voltage ≈ –0.3ºC (Figure 7)
SOA adjustment for switching frequency ≈ 1.03ºC (Figure 5)
SOA adjustment for output inductor ≈ 1.5ºC (Figure 8)
Final calculated SOA adjustment = 0.7 + (–0.3) + 1.3 + 1.5 ≈ 2.2ºC
In the previous design example, the estimated power loss of the CSD87381P would increase to 1.86 W. In
addition, the maximum allowable board or ambient temperature, or both, would have to decrease by 2.2ºC.
Figure 28 graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board or ambient temperature.
3. Adjust the SOA board or ambient temperature by subtracting the temperature adjustment value.
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Application Information (continued)
In the design example, the SOA temperature adjustment yields a reduction in allowable board or ambient
temperature of 2.2ºC. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board or ambient temperature.
Figure 28. Power Block SOA
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7 Layout
7.1 Layout Guidelines
7.1.1 Recommended PCB Design Overview
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. The
following provides a brief description on how to address each parameter.
7.1.2 Electrical Performance
The CSD87381P has the ability to switch voltages at rates greater than 10 kV/µs. Take care with the PCB layout
design and placement of the input capacitors, inductor, and output capacitors.
• The placement of the input capacitors relative to VIN and PGND pins of CSD87381P device should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 29).
The example in Figure 29 uses 1 x 10 nF 0402 25 V and 4 x 10 μF 1206 25 V ceramic capacitors (TDK part
number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board
with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the
power stage, C21, C5, C8, C19, and C18 should follow in order.
• The switching node of the output inductor should be placed relatively close to the Power Block II CSD87381P
VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction
losses and actually reduce the switching noise level. See Figure 29. (1)
7.1.3 Thermal Performance
The CSD87381P has the ability to utilize the PGND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that wicks down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 29 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
• Tent the opposite side of the via with solder-mask.
The number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
7.2 Layout Example
Figure 29. Recommended PCB Layout (Top Down View)
(1)
14
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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8 Device and Documentation Support
8.1 Trademarks
NexFET is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
8.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 CSD87381P Package Dimensions
Pin Configuration
Position
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Designation
Pin 1
TG
Pin 2
VIN
Pin 3
PGND
Pin 4
BG
Pin 5
VSW
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1.500 PKG REF
0.717
1.118
1.500 PKG REF
9.2 Land Pattern Recommendation
1.250 PKG REF
1.250
0.663
2
0.000
0.043
0.343
1
0.663
5
3
4
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1.250
1.500
0.879
0.559
0.033
0.000
0.259
0.758
PACKAGE OUTLINE
1.250
1.078
1.250 PKG REF
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9.3 Stencil Recommendation (100 µm)
Text For Spacing
9.4 Stencil Recommendation (125 µm)
Text
For
Spacing
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
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9.5 Pin Drawing
87381P
TI YMS
LLLL
Text For Spacing
9.6 CSD87381P Embossed Carrier Tape Dimensions
(1)
Pin 1 is oriented in the top-left quadrant of the tape enclosure (closest to the carrier tape sprocket holes).
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CSD87381P
ACTIVE
PTAB
MPC
5
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 150
87381P
CSD87381PT
ACTIVE
PTAB
MPC
5
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-55 to 150
87381P
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
