CSD87502Q2

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD87502Q2 SLPS560 – DECEMBER 2015 CSD87502Q2 30 V Dual N-Channel NexFET™ Power MOSFETs 1 Features • • • • • • • 1 Low On-Resistance Dual Independent MOSFETs Space Saving SON 2 × 2 mm Plastic Package Optimized for 5 V Gate Driver Avalanche Rated Pb and Halogen Free RoHS Compliant Product Summary TA = 25°C TYPICAL VALUE Drain-to-Source Voltage 30 V Qg Gate Charge Total (4.5 V) 2.2 nC Qgd Gate Charge Gate to Drain RDS(on) VGS(th) • • Point-of-Load Synchronous Buck Converter for Applications in Networking, Telecom, and Computing Systems Adaptor or USB Input Protection for Notebook PCs and Tablets Battery Protection nC VGS = 3.8 V 42.0 mΩ VGS = 4.5 V 35.5 mΩ VGS = 10 V 27.0 mΩ Threshold Voltage 1.6 V . Ordering Information(1) DEVICE MEDIA QTY PACKAGE SHIP CSD87502Q2 7-Inch Reel 3000 CSD87502Q2T 7-Inch Reel 250 SON 2 x 2 mm Plastic Package Tape and Reel (1) For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings 3 Description The CSD87502Q2 is a 30 V, 27 mΩ N-Channel device with dual independent MOSFETs in a SON 2 x 2 mm plastic package. The two FETs were designed to be used in a half-bridge configuration for synchronous buck and other power supply applications. Additionally, these NexFET™ power MOSFETs can be used for adaptor, USB input protection, and battery charging applications. The dual FETs feature low drain-to-source on-resistance that minimizes losses and offers low component count for space-constrained applications. Top View and Circuit Image Drain Drain S1 0.5 Drain-to-Source On Resistance 2 Applications • UNIT VDS TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 30 V VGS Gate-to-Source Voltage ±20 V ID Continuous Drain Current (Package limited) 5.0 A IDM Pulsed Drain Current(1) 23 A PD Power Dissipation(2) 2.3 W TJ, Tstg Operating Junction Temperature, Storage Temperature –55 to 150 °C EAS Avalanche Energy, single pulse ID = 7.9 A, L = 0.1 mH, RG = 25 Ω 3.1 mJ (1) Max RθJA = 185 °C/W, pulse duration ≤100 μs, duty cycle ≤1%. (2) Typical RθJA = 55 °C/W on a 1 inch2, 2 oz. Cu pad on a 0.06 inch thick FR4 PCB. D1 D1 G1 G2 Gate Gate D2 D2 S2 Source Source RDS(on) vs VGS Gate Charge 10 TC = 25°C, I D = 4 A TC = 125°C, I D = 4 A 70 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (m:) 80 60 50 40 30 20 10 0 ID = 4 A 9 VDS = 15 V 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 0 0.5 1 1.5 2 2.5 3 3.5 Qg - Gate Charge (nC) 4 4.5 5 D004 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD87502Q2 SLPS560 – DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 6.1 6.2 6.3 6.4 1 1 1 2 3 7 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Device and Documentation Support.................... 7 Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... Package Dimensions ................................................ 8 PCB Land Pattern ..................................................... 9 Recommended Stencil Opening ............................... 9 Q2 Tape and Reel Information................................ 10 4 Revision History 2 DATE REVISION NOTES December 2015 * Initial release. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD87502Q2 CSD87502Q2 www.ti.com SLPS560 – DECEMBER 2015 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V 1 μA IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 4 μA VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-source on-resistance gfs Transconductance 30 V 1.6 2.0 V VGS = 3.8 V, ID = 4 A 1.2 42.0 60.0 mΩ VGS = 4.5 V, ID = 4 A 35.5 42.0 mΩ VGS = 10 V, ID = 4 A 27.0 32.4 mΩ VDS = 3 V, ID = 4 A 75 S DYNAMIC CHARACTERISTICS Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance RG Series gate resistance 6.9 Qg Gate charge total (4.5 V) 2.2 2.9 nC Qg Gate charge total (10 V) 4.6 6.0 nC Qgd Gate charge gate to drain Qgs Qg(th) Qoss Output charge td(on) Turn on delay time tr Rise time td(off) Turn off delay time tf Fall time VGS = 0 V, VDS = 15 V, ƒ = 1 MHz VDS = 15 V, ID = 4 A 272 353 pF 42 55 pF 22 29 pF Ω 0.5 nC Gate charge gate to source 1.0 nC Gate charge at Vth 0.5 nC 1.4 nC 3 ns 11 ns 12 ns 3 ns VDS = 15 V, VGS = 0 V VDS = 15 V, VGS = 5 V, IDS = 4 A, RG = 0 Ω DIODE CHARACTERISTICS VSD Diode forward voltage Qrr Reverse recovery charge trr Reverse recovery time ISD = 4 A, VGS = 0 V 0.85 VDS= 15 V, IF = 4 A, di/dt = 300 A/μs 4.0 1.0 nC V 6.4 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC RθJA (1) (2) MIN TYP MAX Junction-to-ambient thermal resistance (1) 70 Junction-to-ambient thermal resistance (2) 185 UNIT °C/W Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu. Device mounted on FR4 material with minimum Cu mounting area. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD87502Q2 3 CSD87502Q2 SLPS560 – DECEMBER 2015 GATE www.ti.com GATE Source Source N-Chan N-Chan Max RθJA = 70 when mounted on 1 inch2 (6.45 cm2) of 2 oz. (0.071 mm thick) Cu. Max RθJA = 185 when mounted on minimum pad area of 2 oz. (0.071 mm thick) Cu. DRAIN DRAIN M0164-02 M0164-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD87502Q2 CSD87502Q2 www.ti.com SLPS560 – DECEMBER 2015 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 10 18 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 20 16 14 12 10 8 6 4 VGS = 3.8 V VGS = 4.5 V VGS = 10 V 2 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 VDS - Drain-to-Source Voltage (V) 1.8 TC = 125°C TC = 25°C TC = -55°C 8 6 4 2 0 0.8 2 1.2 1.6 2 2.4 2.8 3.2 VGS - Gate-to-Source Voltage (V) D002 3.6 4 D003 VDS = 5 V Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 1000 9 8 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 7 6 5 4 3 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 100 2 1 10 0 0 0.5 1 ID = 4 A 1.5 2 2.5 3 3.5 Qg - Gate Charge (nC) 4 4.5 0 5 3 6 D004 30 D005 Figure 5. Capacitance 80 RDS(on) - On-State Resistance (m:) 2.2 VGS(th) - Threshold Voltage (V) 27 VDS = 15 V Figure 4. Gate Charge 2 1.8 1.6 1.4 1.2 1 0.8 -75 9 12 15 18 21 24 VDS - Drain-to-Source Voltage (V) TC = 25°C, I D = 4 A TC = 125°C, I D = 4 A 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 175 0 2 D006 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 ID = 4 A Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD87502Q2 5 CSD87502Q2 SLPS560 – DECEMBER 2015 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 100 1.6 VGS = 3.8 V VGS = 4.5 V VGS = 10 V ISD - Source-to-Drain Current (A) Normalized On-State Resistance 1.8 1.4 1.2 1 0.8 0.6 -75 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 0 175 0.2 D008 0.4 0.6 0.8 1 VSD - Source-to-Drain Voltage (V) 1.2 1.4 D009 ID = 4 A Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage 10 10 1 0.1 100 ms 10 ms 1 ms 0.01 0.1 TC = 25qC TC = 125qC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 100 100 µs 10 µs 1 10 VDS - Drain-to-Source Voltage (V) 100 1 0.001 0.01 0.1 TAV - Time in Avalanche (ms) D010 1 D011 Single Pulse, Max RθJA = 185°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature (° C) 150 175 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD87502Q2 CSD87502Q2 www.ti.com SLPS560 – DECEMBER 2015 6 Device and Documentation Support 6.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.2 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 6.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD87502Q2 7 CSD87502Q2 SLPS560 – DECEMBER 2015 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Package Dimensions 2.1 1.9 B A PIN 1 INDEX AREA 2.1 1.9 4X 0.05 C 0.05 C 0.8 MAX C SEATING PLANE 0.05 0.00 2X 0.9 0.05 0.05 C A (0.203) TYP 2X 0.625 0.05 B 0.05 C A 3 B 4 4X 0.65 2X 0.488 2X 1.3 (0.35) 1 6 6X PIN 1 ID (45 X0.2) 6X 0.3 0.2 0.35 0.25 0.1 C A 0.05 C B All dimensions are in mm, unless otherwise stated. 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD87502Q2 CSD87502Q2 www.ti.com SLPS560 – DECEMBER 2015 7.2 PCB Land Pattern 6X (0.45) 6X (0.3) SYMM 1 6 (0.488) SYMM 4 3 4X (0.65) 2X (0.625) 2X (0.9) (1.95) For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 7.3 Recommended Stencil Opening 6X (0.45) SYMM METAL TYP 1 6 6X (0.3) (0.488) 4X (0.65) SYMM 2X (0.59) 4 3 2X (0.85) (1.95) All dimensions are in mm, unless otherwise stated. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD87502Q2 9 CSD87502Q2 SLPS560 – DECEMBER 2015 www.ti.com 7.4 Q2 Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 1.00 ±0.25 1.00 ±0.05 2.30 ±0.05 10° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 2.30 ±0.05 10° Max M0168-01 Notes: 1. Measured from centerline of sprocket hole to centerline of pocket 2. Cumulative tolerance of 10 sprocket holes is ±0.20 3. Other material available 4. Typical SR of form tape Max 109 OHM/SQ 5. All dimensions are in mm, unless otherwise specified. 10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD87502Q2 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD87502Q2 ACTIVE WSON DQK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 150 8752 CSD87502Q2T ACTIVE WSON DQK 6 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 150 8752 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of