CY74FCT823CTQCTE4

CY74FCT823T 9-BIT BUS-INTERFACE REGISTER WITH 3-STATE OUTPUTS SCCS069A – OCTOBER 2001 – REVISED NOVEMBER 2001 D D D D D D D D D D D P, Q, OR SO PACKAGE (TOP VIEW) Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29823 Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully Compatible With TTL Input and Output Logic Levels ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 64-mA Output Sink Current 32-mA Output Source Current High-Speed Parallel Register With Positive-Edge-Triggered D-Type Flip-Flops Buffered Common Clock-Enable (EN) and Asynchronous-Clear (CLR) Inputs 3-State Outputs OE D0 D1 D2 D3 D4 D5 D6 D7 D8 CLR GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 EN CP description This bus-interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider address/data paths or buses carrying parity. The CY74FCT823T is a 9-bit-wide buffered register with clock-enable (EN) and clear (CLR) inputs that are ideal for parity bus interfacing in high-performance microprogrammed systems. It is ideal for use as an output port requiring high IOL/IOH. This device is designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CY74FCT823T 9-BIT BUS-INTERFACE REGISTER WITH 3-STATE OUTPUTS SCCS069A – OCTOBER 2001 – REVISED NOVEMBER 2001 ORDERING INFORMATION QSOP – Q SOIC – SO –40°C 40°C to 85°C SPEED (ns) ORDERABLE PART NUMBER Tape and reel 6 CY74FCT823CTQCT Tube 6 CY74FCT823CTSOC Tape and reel 6 CY74FCT823CTSOCT PACKAGE† TA TOP-SIDE MARKING FCT823C FCT823C DIP – P Tube 7.5 CY74FCT823BTPC CY74FCT823BTPC DIP – P Tube 10 CY74FCT823ATPC CY74FCT823ATPC QSOP – Q Tape and reel 10 CY74FCT823ATQCT FCT823A Tube 10 CY74FCT823ATSOC Tape and reel 10 CY74FCT823ATSOCT SOIC – SO FCT823A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. PIN DESCRIPTION NAME I/O D I D flip-flop data inputs CLR I When CLR is low and OE is low, Q outputs are low. When CLR is high, data can be entered into the register. CP O Clock pulse for the register. Enters data into the register on the low-to-high clock transition. Y O Register 3-state outputs EN I Clock enable. When EN is low, data on the D input is transferred to the Q output on the low-to-high clock transition. When EN is high, the Q outputs do not change state, regardless of the data or clock input transitions. OE I Output control. When OE is high, the Y outputs are in the high-impedance state. When OE is low, true register data is present at the Y outputs. DESCRIPTION FUNCTION TABLE INTERNAL OUTPUTS INPUTS OE CLR EN D CP Q Y H H H H L L L H ↑ L Z ↑ H Z H L X X X L Z L L X X X L L H H L H H X X NC Z H X X NC NC H H H H L L ↑ L Z L H ↑ H L Z H L L ↑ L L L H L H ↑ H H FUNCTION Z Clear Hold Load H = High logic level, L = Low logic level, X = Don’t care, NC = No change, ↑ = Low-to-high transition, Z = High-impedance state 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY74FCT823T 9-BIT BUS-INTERFACE REGISTER WITH 3-STATE OUTPUTS SCCS069A – OCTOBER 2001 – REVISED NOVEMBER 2001 logic diagram (positive logic) OE CLR EN CP 1 11 14 CL 13 CP Q D0 2 23 Y0 D0 To Eight Other Channels absolute maximum rating over operating free-air temperature range (unless otherwise noted)† Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, qJA (see Note 1): P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W (see Note 2): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W (see Note 2): SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN NOM MAX UNIT 4.75 5 5.25 V VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 V High-level output current –32 mA IOL TA Low-level output current 64 mA 85 °C High-level input voltage 2 Operating free-air temperature –40 V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CY74FCT823T 9-BIT BUS-INTERFACE REGISTER WITH 3-STATE OUTPUTS SCCS069A – OCTOBER 2001 – REVISED NOVEMBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 4.75 V, VOH VCC = 4 4.75 75 V VOL Vhys VCC = 4.75 V, All inputs II IIH VCC = 5.25 V, VCC = 5.25 V, VIN = VCC VIN = 2.7 V IIL IOZH VCC = 5.25 V, VCC = 5.25 V, VIN = 0.5 V VOUT = 2.7 V IOZL IOS‡ VCC = 5.25 V, VCC = 5.25 V, VOUT = 0.5 V VOUT = 0 V Ioff ICC VCC = 0 V, VCC = 5.25 V, ∆ICC ICCD¶ IC# MIN IIN = –18 mA IOH = –32 mA MAX UNIT –0.7 –1.2 V 2 IOH = –15 mA IOL = 64 mA 2.4 V 3.3 0.3 0.55 V 5 µA ±1 µA ±1 µA 10 µA 0.2 –10 µA mA ±1 µA 0.1 0.2 mA 0.5 2 mA 0.06 0.12 mA/ MHz 0.7 1.4 VIN = 3.4 V or GND VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 1.2 3.4 1.6 3.2|| VIN = 3.4 V or GND 3.9 12.2|| 5 10 VCC = 5.25 V, One bit switching at 50% duty cycle, Outputs open, OE = EN = GND, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V One bit switching at f1 = 5 MHz at 50% duty cycle Eight bits switching at f1 = 2.5 MHz at 50% duty cycle V –225 –60 VOUT = 4.5 V VIN ≤ 0.2 V, VIN ≥ VCC – 0.2 V VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open VCC = 5.25 V, Outputs open, open OE = EN = GND TYP† Ci –120 mA pF Co 9 12 pF † Typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. § Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND ¶ This parameter is derived for use in total power-supply calculations. # IC = ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1) Where: IC = Total supply current ICC = Power-supply current with CMOS input levels ∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V) DH = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH ICCD = Dynamic current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. || Values for these conditions are examples of the ICC formula. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY74FCT823T 9-BIT BUS-INTERFACE REGISTER WITH 3-STATE OUTPUTS SCCS069A – OCTOBER 2001 – REVISED NOVEMBER 2001 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER TEST LOAD CP tw Pulse duration tsu time before CP↑ Setup time, th Hold time, time after CP↑ trec Recovery time CLR low Data EN Data EN CLR before CP↑ CY74FCT823AT MIN MAX CY74FCT823BT MIN MAX CY74FCT823CT MIN CL = 50 pF,, RL = 500 Ω 7 6 6 6 6 6 CL = 50 pF,, RL = 500 Ω 4 3 3 4 3 3 CL = 50 pF,, RL = 500 Ω 2 1.5 1.5 2 0 0 6 6 6 CL = 50 pF, RL = 500 Ω MAX UNIT ns ns ns ns switching characteristics over operating free-air temperature range (see Figure 1) CY74FCT823AT CY74FCT823BT CY74FCT823CT PARAMETER FROM (INPUT) TO (OUTPUT) TEST LOAD tPLH tPHL CP Y CL = 50 pF,, RL = 500 Ω 10 7.5 6 10 7.5 6 tPLH tPHL CP Y CL = 300 pF,, RL = 500 Ω 20 15 12.5 20 15 12.5 tPLH CLR Y CL = 50 pF, RL = 500 Ω 14 9 8 tPZH tPZL OE Y CL = 50 pF,, RL = 500 Ω 12 8 7 12 8 7 tPZH tPZL OE Y CL = 300 pF,, RL = 500 Ω 23 15 12.5 23 15 12.5 tPHZ tPLZ OE Y CL = 5 pF,, RL = 500 Ω 7 6.5 6 7 6.5 6 tPHZ tPLZ OE Y CL = 50 pF, RL = 500 Ω 8 7.5 6.5 8 7.5 6.5 POST OFFICE BOX 655303 MIN MAX • DALLAS, TEXAS 75265 MIN MAX MIN MAX UNIT ns ns ns ns ns ns ns 5 CY74FCT823T 9-BIT BUS-INTERFACE REGISTER WITH 3-STATE OUTPUTS SCCS069A – OCTOBER 2001 – REVISED NOVEMBER 2001 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test From Output Under Test Test Point CL = 50 pF (see Note A) Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 500 Ω S1 Open 7V Open tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ ≈3.5 V 1.5 V tPZH VOH 1.5 V VOL 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CY74FCT823ATQCT ACTIVE SSOP DBQ 24 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT823A CY74FCT823ATSOC ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT823A CY74FCT823CTSOC ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT823C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of