CY74FCT841ATSOCT

CY54FCT841T, CY74FCT841T 10-BIT LATCHES WITH 3-STATE OUTPUTS SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001 D D D D D D D D D D D D CY54FCT841T . . . D PACKAGE CY74FCT841T . . . P, Q, OR SO PACKAGE (TOP VIEW) Function, Pinout, and Drive Compatible With FCT, F, and AM29841 Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Fully Compatible With TTL Input and Output Logic Levels High-Speed Parallel Latches Buffered Common Latch-Enable Input 3-State Outputs CY54FCT841T – 32-mA Output Sink Current – 12-mA Output Source Current CY74FCT841T – 64-mA Output Sink Current – 32-mA Output Source Current OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 LE description The ’FCT841T bus-interface latches are designed to eliminate additional packages required to buffer existing latches and provide additional data width for wider address/data paths or buses carrying parity. The ’FCT841T devices are buffered 10-bit-wide versions of the FCT373 function. The ’FCT841T devices’ high-performance interface is designed for high-capacitance-load drive capability, while providing low-capacitance bus loading at both inputs and outputs. Outputs are designed for low-capacitance bus loading in the high-impedance state. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. PIN DESCRIPTION NAME I/O D I Latch data inputs LE I Latch-enable input. The latches are transparent when LE is high. Input data is latched on the high-to-low transition. Y O 3-state latch outputs OE I Output-enable control. When OE is low, the outputs are enabled. When OE is high, the outputs are in the high-impedance (off) state. DESCRIPTION Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CY54FCT841T, CY74FCT841T 10-BIT LATCHES WITH 3-STATE OUTPUTS SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001 ORDERING INFORMATION QSOP – Q SOIC – SO 40°C to 85°C –40°C SPEED (ns) ORDERABLE PART NUMBER Tape and reel 5.5 CY74FCT841CTQCT Tube 5.5 CY74FCT841CTSOC Tape and reel 5.5 CY74FCT841CTSOCT Tube 6.5 CY74FCT841BTPC Tube 9 CY74FCT841ATSOC Tape and reel 9 CY74FCT841ATSOCT PACKAGE† TA DIP – P SOIC – SO TOP-SIDE MARKING FCT841C FCT841C CY74FCT841BTPC FCT841A –55°C to 125°C CDIP – D Tube 10 CY54FCT841ATDMB † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INTERNAL OUTPUTS INPUTS OE LE D O Y H X X X Z H H L L Z H H H H Z H L X NC Z L H L L L L H H H H L L X NC NC FUNCTION Z Latched (Z) Transparent Latched H = High logic level, L = Low logic level, X = Don’t care, NC = No change, Z = High-impedance state logic diagram (positive logic) OE LE 1 13 LE 2 D0 D 23 Q To Nine Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Y0 CY54FCT841T, CY74FCT841T 10-BIT LATCHES WITH 3-STATE OUTPUTS SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, θJA (see Note 1): P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W (see Note 2): Q package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W (see Note 2): SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) CY54FCT841T CY74FCT841T MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –12 –32 mA IOL TA Low-level output current 32 64 mA 85 °C High-level input voltage 2 Operating free-air temperature –55 2 125 –40 V V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CY54FCT841T, CY74FCT841T 10-BIT LATCHES WITH 3-STATE OUTPUTS SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL Vhys VCC = 4.5 V, IIN = –18 mA VCC = 4.75 V, IIN = –18 mA VCC = 4.5 V, IOH = –12 mA 75 V VCC = 4 4.75 VCC = 4.5 V, IOL = 32 mA VCC = 4.75 V, IOL = 64 mA VIN = 2.7 V VIN = 2.7 V VCC = 5.5 V, VIN = 0.5 V VCC = 5.25 V, VIN = 0.5 V VCC = 5.5 V, VOUT = 2.7 V VCC = 5.25 V, VOUT = 2.7 V VCC = 5.5 V, VOUT = 0.5 V VCC = 5.25 V, VCC = 5.5 V, VOUT = 0.5 V VOUT = 0 V VCC = 5.25 V, VOUT = 0 V Ioff VCC = 0 V, VOUT = 4.5 V ICC VCC = 5.5 V, VCC = 5.25 V, ∆ICC ICCD¶ –1.2 0.3 V 0.55 0.55 0.2 5 ±1 ±1 ±1 ±1 10 10 –10 –10 –120 –225 –60 –120 ±1 VCC = 5.5 V, One input switching at 50% duty cycle, Outputs open, OE = GND, LE = VCC, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V VCC = 5.25 V, One input switching at 50% duty cycle, Outputs open, OE = GND, LE = VCC, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 0.1 0.5 0.06 V V 5 VIN ≤ 0.2 V, VIN ≥ VCC – 0.2 V VIN ≤ 0.2 V, VIN ≥ VCC – 0.2 V § VCC = 5.5 V, VIN = 3.4 V , f1 = 0, Outputs open VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open V 3.3 0.3 –60 UNIT 3.3 0.2 VCC = 5.25 V, IOS‡ 2.4 All inputs VCC = 5.5 V, IOZL –0.7 2.4 VIN = VCC IOZH –1.2 IOH = –15 mA VCC = 5.25 V, IIL –0.7 CY74FCT841T TYP† MAX MIN 2 VIN = VCC IIH MIN IOH = –32 mA VCC = 5.5 V, II CY54FCT841T TYP† MAX TEST CONDITIONS –225 ±1 0.2 0.1 0.2 0.5 2 2 µA µA µA µA µA mA µA mA mA 0.12 mA/ MHz 0.06 0.12 † Typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. § Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND ¶ This parameter is derived for use in total power-supply calculations. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY54FCT841T, CY74FCT841T 10-BIT LATCHES WITH 3-STATE OUTPUTS SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER CY54FCT841T TYP† MAX TEST CONDITIONS 5V VCC = 5 5.5 V, Outputs open,, OE = GND, LE = VCC IC# VCC = 5 5.25 25 V V, Outputs open,, OE = GND, LE = VCC One bit switching at f1 = 10 MHz at 50% duty cycle 10 bits switching at f1 = 2.5 MHz at 50% duty cycle One bit switching at f1 = 10 MHz at 50% duty cycle 10 bits switching at f1 = 2.5 MHz at 50% duty cycle MIN VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 0.7 1.4 VIN = 3.4 V or GND VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 1 2.4 1 3.2|| VIN = 3.4 V or GND VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 4.1 13.2|| CY74FCT841T TYP† MAX MIN UNIT mA 0.7 1.4 VIN = 3.4 V or GND VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 1 2.4 1 3.2|| VIN = 3.4 V or GND 4.1 13.2|| Ci 5 10 5 10 pF Co 9 12 9 12 pF † Typical values are at VCC = 5 V, TA = 25°C. # IC = ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1) Where: IC = Total supply current ICC = Power-supply current with CMOS input levels ∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V) DH = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH ICCD = Dynamic current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. || Values for these conditions are examples of the ICC formula. timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) CY54FCT841AT MIN tw tsu Pulse duration, LE high th Hold time, data after LE↑ Setup time, data before LE↑ MAX CY74FCT841AT MIN MAX CY74FCT841BT MIN MAX CY74FCT841CT MIN MAX UNIT 5 4 4 4 ns 2.5 2.5 2.5 2.5 ns 3 2.5 2.5 2.5 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CY54FCT841T, CY74FCT841T 10-BIT LATCHES WITH 3-STATE OUTPUTS SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001 switching characteristics over operating free-air temperature range (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST LOAD tPLH tPHL D Y tPLH tPHL D tPLH tPHL CY54FCT841AT CY74FCT841AT MIN MAX MIN MAX CL = 50 pF,, RL = 500 Ω 1.5 10 1.5 9 1.5 10 1.5 9 Y CL = 300 pF,, RL = 500 Ω 1.5 15 1.5 13 1.5 15 1.5 13 LE Y CL = 50 pF,, RL = 500 Ω 1.5 13 1.5 12 1.5 13 1.5 12 tPLH tPHL LE Y CL = 300 pF,, RL = 500 Ω 1.5 20 1.5 16 1.5 20 1.5 16 tPZH tPZL Y CL = 50 pF,, RL = 500 Ω 1.5 13 1.5 11.5 OE 1.5 13 1.5 11.5 tPZH tPZL Y CL = 300 pF,, RL = 500 Ω 1.5 25 1.5 23 OE 1.5 25 1.5 23 tPHZ tPLZ Y CL = 5 pF,, RL = 500 Ω 1.5 9 1.5 7 OE 1.5 9 1.5 7 Y CL = 50 pF, RL = 500 Ω 1.5 10 1.5 8 OE 1.5 10 1.5 8 tPHZ tPLZ UNIT ns ns ns ns ns ns ns ns switching characteristics over operating free-air temperature range (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TEST LOAD tPLH tPHL D Y tPLH tPHL D tPLH tPHL CY74FCT841CT MIN MAX MIN MAX CL = 50 pF,, RL = 500 Ω 1.5 6.5 1.5 5.5 1.5 6.5 1.5 5.5 Y CL = 50 pF,, RL = 500 Ω 1.5 13 1.5 13 1.5 13 1.5 13 LE Y CL = 50 pF,, RL = 500 Ω 1.5 8 1.5 6.4 1.5 8 1.5 6.4 tPLH tPHL LE Y CL = 300 pF,, RL = 500 Ω 1.5 15.5 1.5 15 1.5 15.5 1.5 15 tPZH tPZL Y CL = 50 pF,, RL = 500 Ω 1.5 8 1.5 6.5 OE 1.5 8 1.5 6.5 tPZH tPZL Y CL = 300 pF,, RL = 500 Ω 1.5 14 1.5 12 OE 1.5 14 1.5 12 tPHZ tPLZ Y CL = 5 pF,, RL = 500 Ω 1.5 6 1.5 5.7 OE 1.5 6 1.5 5.7 Y CL = 50 pF RL = 500 Ω, 1.5 7 1.5 6 OE 1.5 7 1.5 6 tPHZ tPLZ 6 CY74FCT841BT POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns ns ns ns ns CY54FCT841T, CY74FCT841T 10-BIT LATCHES WITH 3-STATE OUTPUTS SCCS035A – SEPTEMBER 1994 – REVISED OCTOBER 2001 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test From Output Under Test Test Point CL = 50 pF (see Note A) Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 500 Ω S1 Open 7V Open tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ ≈3.5 V 1.5 V tPZH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 4-Feb-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CY54FCT841ATDMB ACTIVE CDIP JT 24 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CY54FCT841ATDM B CY74FCT841ATSOC ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT841A CY74FCT841ATSOCT ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT841A CY74FCT841CTQCT ACTIVE SSOP DBQ 24 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 FCT841C CY74FCT841CTSOC ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT841C CY74FCT841CTSOCT ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 FCT841C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of