September 19, 2006
Rev -1.1
PEL
National Semiconductor
Evaluation Board User's Guide
DAC124S085 12-Bit Quad, DAC104S085 10-Bit Quad,
DAC084S085 8-Bit Quad, DAC122S085 12-Bit Dual,
DAC102S085 10-Bit Dual, DAC082S085 8-Bit Dual
Micro Power Digital-to-Analog Converter
with Rail-to-Rail Output
© 2006 National Semiconductor Corporation.
1
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Table of Contents
1.0 Introduction........................................................................................................................................ 4
2.0 Board Assembly................................................................................................................................ 5
2.1 WaveVision 4.0 Board Modifications ................................................................................... 5
3.0 Quick Start......................................................................................................................................... 5
3.1 Stand-Alone Mode ................................................................................................................ 5
3.2 Computer Mode..................................................................................................................... 5
4.0 Functional Description ..................................................................................................................... 6
4.1 Serial Interface.................................................................................................................... 6
4.2 DAC Reference Circuitry................................................................................................... 6
4.3 Analog Output..................................................................................................................... 6
4.4 Power Supply Connections ............................................................................................... 6
5.0 Software Operation and Settings ................................................................................................... 6
6.0 Evaluation Board Specifications ..................................................................................................... 6
7.0 Hardware Schematic ............................................................................................................................ 7
8.0 Evaluation Board Bill of Materials................................................................................................... 8
A1.0 Summary Tables of Test Points, Jumpers, and Connectors................................................... 9
A2.0 Enlarged Timing Diagram ............................................................................................................. 9
3
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compatible DACs, will be referenced throughout this
document as the DAC124S085.
1.0 Introduction
The DAC124S085EB Design Kit (consisting of the
DAC124S085 Evaluation Board and this User's Guide)
is designed to ease evaluation and design-in of the
National Semiconductor DAC124S085 12-Bit Quad,
DAC104S085 10-Bit Quad, DAC084S085 8-Bit Quad,
DAC122S085 12-Bit Dual, DAC102S085 10-Bit Dual,
DAC082S085 8-Bit Dual Micro-Power Digital-to-Analog
Converter with Rail-to-Rail Output. This family of pin-
JP4
Output Load
The evaluation board can be used with suitable test
equipment, such as a pattern generator and signal
analyzer, to evaluate the DAC124S085 performance.
Data transmitted to the DAC124S085 via a serial
interface is converted to an analog waveform by U2/U4,
the DAC124S085.
JP3
Output Load
J6
VOUT_DC
J1
VA_REMOTE
U2/U4
DAC124S085
JP2
VREF Selection
JP1
VA Selection
J3
Serial Interface
J5
WV4S
Connector
Figure 1: Component and Test Point Location
4
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2.0 Board Assembly
4. Connect your Pattern Generator to Serial
Interface header J3. Refer to Figure 3 below for
connection details.
The DAC124S085 evaluation board comes fully
assembled and ready for use. Refer to the Bill of
Materials for a description of components, to Figure 1
for major component placement, and to Figure 6 for the
Evaluation Board schematic.
3.0 Quick Start
The DAC124S085 evaluation board may be used in the
Stand-Alone mode while a Pattern Generator is used to
drive the DAC124S085, and a Signal Analyzer is used
to evaluate the analog output signal
3.1 Stand-Alone Mode
Refer to Figure 1 for locations of test points and major
components.
1.
Figure 3: J3 Serial Interface Header
(*Pins 7&8 are used for SCL and SDA, respectively,
when modified for WV4.0)
Connect a clean analog (not switching) +5V power
source to Power Connector J1 on the
DAC124S085 board and turn on the power. Place
a jumper across pins 2 and 3 of JP1 to select
VA_REMOTE.
Place a jumper across the appropriate pins of JP2
to select the desired reference voltage. For the
default selection of VREF = VA, place a jumper
across pins 2 & 3. Please see Table 1 for details.
Create the digital waveforms seen in Figure 2 with
your Pattern Generator. Ensure that SCLK doesn’t
exceed 40MHz. Refer to “Section 1.4: Serial
Interface” and the DAC124S085 Datasheet for
further details.
2.
3.
5.
The Analog Output signals of each channel can be
seen DC coupled at header J6. See the header
schematic of Figure 4 for details.
6.
Select the desired output load by adding jumpers
to headers JP3 & JP4. See Figure 5 and Table 1 in
Section 4.0 for jumper configurations.
Figure 4: J6 Output Header
≈
1 / fSCLK
SCLK
1
2
13
tSS
tSYNC
t CL
14
15
16
t CH
t CFSR
≈
SYNC
D IN
≈ ≈
t DH
DB15
DB0
t DS
Figure 2: Digital Input Timing Diagram
(Refer to Appendix 2.0 for an enlarged version)
Figure 5: JP3 & JP4 Load Select Headers
5
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SYNC line may be kept low or brought high. In either
case, it must be brought high for the minimum specified
time before the next write sequence as a falling edge of
SYNC will initiate the next write cycle.
4.0 Functional Description
Table 1 describes the function of the various jumpers
on the DAC124S085 evaluation board. The Evaluation
Board schematic is shown in Figure 6.
Pins 1 & 2
Pins 2 & 3
JP1
Select VA=5.5V
from WV4.1 Board
Select VA_REMOTE
from J1
JP2
Select 2.5V as
VREF
Select VA as VREF
JP3
JP4
Select 200pF
Output Load
Capacitance
VOUT_A
Select 200pF
Output Load
Capacitance
VOUT_C
3&4
Select 2kΩ Output
Load Resistance
VOUT_A
Select 2kΩ Output
Load Resistance
VOUT_C
5&6
Select 200pF
Output Load
Capacitance
VOUT_B
Select 200pF
Output Load
Capacitance
VOUT_D
7&8
Select 2kΩ Output
Load Resistance
VOUT_B
Select 2kΩ Output
Load Resistance
VOUT_D
Since the SYNC and DIN buffers draw more current
when they are high, they should be idled low between
write sequences to minimize power consumption.
Jumper
Please refer to the DAC124S085 datasheet for more
information.
4.2 DAC Reference Circuitry
The reference voltage for the DAC124S085 is selected
by JP2. (See Table 1 for details.) The reference can
either be selected as a fixed 2.5 volts, or as the supply
voltage. In the latter case, the analog output range of
the DAC124S085 can be scaled by adjusting the
supply voltage (VA). This voltage can be set anywhere
from +2.7V to +5.5V.
Pin
1&2
4.3 Analog Output
The analog output of this Eval board is available DC
coupled at the header J6. An AC coupled output is not
provided, however SMA footprints are available at J2
and J4. These footprints can be used along with the
prototype field to design another output circuit, should it
be desired.
4.4 Power Supply Connections
In Stand-alone mode, the DAC124S085 board must be
powered by an external supply.
Connect a DC voltage supply to connector J1 and
place a jumper across pins 2 and 3 of JP1 to select
VA_REMOTE. This voltage (VA) can be set anywhere
from +2.7V to +5.5V.
Table 1: Jumper Configurations
4.1 Serial Interface
If the supply voltage (VA) serves as the reference for
the DAC124S085, ensure a clean power supply is
used.
In Stand-Alone Mode, the serial interface must be
driven by an external device. The three-wire interface
(SCLK, SYNC, DIN) is compatible with SPI, QSPI and
MICROWIRE, as well as most DSPs. See the Timing
Diagram (Figure 2) for information on a write sequence.
6.0 Evaluation Board Specifications
Board Size:
Power Requirements
Max Clock Frequency:
Analog Output
Impedance:
The maximum digital input level of the three-wire
interface is independent of the analog supply voltage
(VA). The range of all digital inputs is 0V to 5.25V
regardless of VA.
A write sequence begins by bringing the SYNC line low.
Once SYNC is low, the Binary data on the DIN line is
clocked into the 16-bit serial input register on the falling
edges of SCLK. On the 16th falling clock edge, the last
data bit is clocked in and the programmed function (a
change in the mode of operation and/or a change in the
DAC register contents) is executed. At this point the
6
3.70" x 3.15" (9.4 cm x 8 cm)
Min: +2.7V , 3mA Max: +5.5V, 5 mA
40 MHz
User Selectable: 2KΩ, 200pF, or ∞.
http://www.national.com
A
B
C
7
5
3
1
8
6
4
2
NS
C9
0.1uF
C10
9
10
3P3V
11
12
13
14
SCL
D3
RED LED
3P3V
1
2
5P5V
3P3V
R10
200
3
4
5P5V
5
6
J5
HEADER 7X2
7
8
SYNCB
SCLK
DIN
SDA
3P3V
3P3V
SYNCB
SCLK
DIN
R12
0
3P3V
R11
NS
3P3V
U3
24C02
1
VA
VIA5
NS
NS
NS
R3
R4
R5
100 mil spaced
standard grid
Prototype
Area
VIA9
VIA7
TP3
AGND
VIA6
GND
VA
VIA10 VIA8
1
NS
C13
NS
C14
JP5
5
12) All components should be placed outside of the U2 and U4 socket areas.
10) Make the U2 footprint a 10-lead MSOP and the U4 footprint a 10-lead dual-inline LLP.
Both footprints need rainbow clamp sockets.
9) Silkcreen the standard NSC logo and name as well as part number, DAC124S105, in a convienient location.
4
8) Make all VIA test points standard size (37 mil drill holes, and 60 mil diameter pads). This applies to the Prototype Area as well.
7) In the Prototype Areas, make the top row of vias Power (VA) and the bottom row of vias Ground (GND).
6) Flood the top layer of the board with Power (VA) and the bottom layer of the board with Ground (GND).
5) The Reference circuitry of the board (U1 & JP2) should be placed as close to the Vref pin of the DUT as possible.
4) All decoupling capacitors should be placed near the DUT pins, smallest value closest.
3) SYNCB, DIN, and SCLK should be controlled impedances. As a rule of thumb, please separate
all these nets by four times the traces width to minimize crosstalk.
JP7
0.1uF
1uF
JP6
C2
C1
100uH
L1
VREF SELECTION
U1
LM4040/SOT23
JP2
VREF SELECTION
2) Make this a four layer board where the top layer is signal, 2nd layer is ground, 3rd layer is power and the bottom layer is signal.
1) All text in green should appear on the board as Top Silkscreen.
Layout Notes:
3P3V
TP5
3P3V
1
J3
HEADER 4X2
1
D
7
VCC
A0
1
8
WP
A1
2
6
SCL
A2
3
5
SDA
GND
4
1
1
1
1
1
1
2
1
2
3
10
9
8
7
6
10
9
8
7
6
VA
VOUTB
VOUTC
VOUTD
1uF
C7
VA
VOUTB
VOUTC
VOUTD
SCLK
VA
SYNCB VOUTA
DIN
VREF
GND
U4
DAC124S085LLP
VA
SCLK
SYNCB VOUTA
DIN
VREF
GND
C8
1
2
3
4
5
AGND
1
2
3
4
5
0.1uF
TP4
AGND
VA
U2
DAC124S085CIMT
R1
2K
5P5V
VA
VA
TP2
VA
VA_REMOTE
JP1
VA SELECTION
VA SELECTION
1
2
3
1
3
LOAD_SELECT
200pF
C3
C
2K
R6
VIA4
VIA3
VIA2
VA
D2
RED LED
VIA1
200
R2
VA_REMOTE
1
VA_REMOTE
D1
1N4001
AGND
2
1
200pF
C4
VA
R
C
R
2K
R7
200pF
C5
100 mil spaced
standard grid
Prototype
Area
1
1
3
2
1
5
4
AGND
1
J1
VA_REMOTE
JP3
HEADER 4X2_0
TP1
AGND
2K
R8
GND
VA
C
R
C
R
1
2
3
3
4
4
VIA11
VIA12
J2
J4
R9
2K
C6
1
1
200pF
JP4
HEADER 4X2_0
1
7
6
VOUT_A
5
6
VOUT_C
8
VOUT_B
7
8
VOUT_D
1
1
NS
2
NS
5
4
3
2
2
5
4
3
2
5
TP6
AGND
1
7
5
3
1
AGND
GND
VOUT_D
VOUT_C
VOUT_B
VOUT_A
2
4
6
8
J6
HEADER 4X2
Date:
Size
C
Title
1
Wednesday, January 04, 2006
Document Number
870012729-100A
DAC124S085 Evaluation Board
1
Sheet
1
of
1
Rev
1.0
A
B
C
D
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Description Value
CAP
1uF
NS
CAP
0.1uF
CAP
200pF
NS
Dio
1N4001
LED
RED LED
Hdr
Hdr 1x3
Hdr
Hdr 1x3
Hdr
Hdr 2x4
Term
term block 2 Pos
NS
SMA-5
HDR
Hdr 2x4
HDR
Hdr 2X7
IND
100uH
RES
2K
RES
200
NS
RES
0.0
HDR
Hdr 1X1
HDR
Hdr 1X1
HDR
Hdr 1X1
REF
LM4040/SOT23
IC
DAC124S085CIMT
IC
24C02
IC
DAC124S085LLP
SHUNT
Hdr Jumper
Blank PC BoardImmersion Gold
Revision: 1.1 CS
August 1, 2006
Quantity Reference
2
C7,C1
1
C14
3
C2,C8,C10
4
C3,C4,C5,C6
2
C13,C9
1
D1
2
D3,D2
1
JP1
1
JP2
2
JP3, JP4
1
J1
2
J2,J4
2
J3, J6
1
J5
1
L1
5
R1,R6,R7,R8,R9
2
R10,R2
4
R3,R4,R5,R11
1
R12
4
TP1,TP3,TP4,TP6
1
TP2
1
TP5
1
U1
1
U2
1
U3
1
U4
10
1
-
870012729-100A
Bill Of Materials
7/31/06
DAC124S085_BOM
Package
1206
0805
0805
0805
sm/c_1206
50V
DAX2/DO41
2.1V
1206
.100 Singl Str 36 Pos.
.100 Singl Str 36 Pos.
.100 dual str 60 Pos
term block 2 Pos
rf/sma/v_clr
.100 dual str 60 Pos
rt angle hdr
100mA
1210
5%
0805
1%
0805
sm/r_0805
5%
0805
.100 Singl Str 36 Pos.
.100 Singl Str 36 Pos.
.100 Singl Str 36 Pos.
SOT23
socket
1.8 - 5.5V 8- SOIC
LLP
Hdr Jumper
Rating
50V
10V
50V
100V
Manufacturer
TDK
NS
Panasonic
Murata
NS
Micro Comm
Avago Tech
Sullins Elect
Sullins Elect
Sullins Elect
On Shore Tech
NS
Sullins Elect
Sullins Elect
TDK Corp
Panasonic
Panasonic
NS
ROHM
Sullins Elect
Sullins Elect
Sullins Elect
National Semi
National Semi
ATMEL
National Semi
Sullins Elect
Manufacturer P/N
C3216X7R1H105K
NS
ECJ-2YB1H104K
GRM2165C2A201JA01D
NS
1N4001-TP
HSMS-C150
PBC36SAAN
PBC36SAAN
PBC30DADN
ED120/2DS
NS
PBC30DADN
PRPN212PARN-RC
NLCV32T-101K-PF
ERJ-6GEYJ202V
ERJ-6ENF2000V
NS
MCR1-0EZHJ000
PBC36SAAN
PBC36SAAN
PBC36SAAN
LM4040DIM3-2.5
DAC124S085CIMT
AT24C02BN-10SU-1.8
DAC124S085LLP
SPC02SYAN
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Digikey
Source
Digikey
Source P/N
445-1423-2-ND
NS
PCC1840TR-ND
490-1606-1-ND
NS
1N4001-TPMSTR-ND
516-1440-1-ND
S1011E-36-ND
S1011E-36-ND
S2041E-30-ND
ED1609-ND
NS
S2041E-30-ND
S5803-21-ND
445-1543-1-ND
P2.0KATR-ND
P200CTR-ND
NS
RHM0.0ATR-ND
S1011E-36-ND
S1011E-36-ND
S1011E-36-ND
LM4040DIM3-2.5TR
National Semi
AT24C02BN-10SU-1.8-ND
National Semi
S9001-ND
APPENDIX
A1.0 Summary Tables of Test Points, Jumpers, and Connectors
Test Points on the DAC124S085 Evaluation Board
TP1: AGND
Ground. Located at the lower left of the board.
TP2: VA
VA Test Point. Located in the lower left of the board.
TP3: AGND
Ground. Located at the lower right of the board.
TP4: AGND
Ground. Located in the center of the board
TP5: 3P3V
3.3V test point. Located at the lower right edge of the board.
TP6: AGND
Ground. Located in the center of the board.
Connectors on the DAC124S085 Evaluation Board
J1: Terminal Block
VA_REMOTE. External power supply connector.
J2: SMA Footprint
Not Used
J3: Serial Interface
Header
Serial Interface connector. Logic Input. (Refer to Figure 3 for a pin-out diagram.)
J4: SMA Footprint
J5: WV4.1 Connector
Not Used
WaveVision 4.1 connector (for future use)
J6: Output Header
DC Coupled output for channels A-D
Selection Jumpers on the DAC124S085 Evaluation Board (Refer to Table 1 in Section 4.0 for configuration details)
JP1: VA_SELECTION
Selects source of VA.
JP2: VREF_SELECT
Selects VREF Level
JP3: LOAD SELECT
Configures the output load for channels A & B
JP4: LOAD SELECT
Configures the output load for channels C & D
A2.0 Enlarged Timing Diagram
≈
1 / fSCLK
SCLK
1
2
13
tSS
tSYNC
tCL
14
15
16
tCH
tCFSR
≈
SYNC
D IN
≈ ≈
tDH
DB15
DB0
tDS
9
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SEMICONDUCTOR'S END USER LICENSE AGREEMENT. DO NOT USE THIS PRODUCT UNTIL YOU HAVE READ AND
AGREED TO THE TERMS AND CONDITIONS OF THAT AGREEMENT. IF YOU DO NOT AGREE WITH THEM, CONTACT THE
VENDOR WITHIN TEN (10) DAYS OF RECEIPT FOR INSTRUCTIONS ON RETURN OF THE UNUSED PRODUCT FOR A
REFUND OF THE PURCHASE PRICE PAID, IF ANY.
The DAC124S085 Evaluation Board is intended for product evaluation purposes only and is not intended for resale to end
consumers, is not authorized for such use and is not designed for compliance with European EMC Directive 89/336/EEC, or for
compliance with any other electromagnetic compatibility requirements.
National Semiconductor Corporation does not assume any responsibility for use of any circuitry or software supplied or described.
No circuit patent licenses are implied.
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