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DAC101S101, DAC101S101-Q1
SNAS321G – JUNE 2005 – REVISED APRIL 2016
DAC101S101 and DAC101S101Q-1 10-Bit Micro Power, RRO Digital-to-Analog Converter
1 Features
3 Description
•
The DAC101S101 is a full-featured, general purpose
10-bit voltage-output digital-to-analog converter
(DAC) that can operate from a single +2.7 V to 5.5 V
supply and consumes just 175 µA of current at 3.6
Volts. The on-chip output amplifier allows rail-to-rail
output swing and the three wire serial interface
operates at clock rates up to 30 MHz over the
specified supply voltage range and is compatible with
standard SPI, QSPI, MICROWIRE and DSP
interfaces. Competitive devices are limited to 20 MHz
clock rates at supply voltages in the 2.7 V to 3.6 V
range.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DAC101S101Q is AEC-Q100 Grade 1 Qualified
and is Manufactured on an Automotive Grade
Flow.
Ensured Monotonicity
Low Power Operation
Rail-to-Rail Voltage Output
Power-on Reset to Zero Volts Output
Wide Temperature Range of −40°C to +125°C
Wide Power Supply Range of 2.7 V to 5.5 V
Small Packages
Power Down Feature
Resolution 10 bits
DNL +0.15, –0.05 LSB (typical)
Output Settling Time 8 μs (typical)
Zero Code Error 3.3 mV (typical)
Full-Scale Error −0.06 %FS (typical)
Power Consumption
– Normal Mode, 0.63 mW (3.6 V) / 1.41 mW (5.5
V) typical
– Power Down Mode, 0.14 μW (3.6 V) / 0.33 μW
(5.5 V) typical
2 Applications
•
•
•
•
•
The supply voltage for the DAC101S101 serves as its
voltage reference, providing the widest possible
output dynamic range. A power-on reset circuit
ensures that the DAC output powers up to zero volts
and remains there until there is a valid write to the
device. A power-down feature reduces power
consumption to less than a microWatt.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DAC101S101
VSSOP (8)
3.00 mm × 3.00 mm
DAC101S101,
DAC101S101-Q1
SOT-23 (6)
1.60 mm × 2.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage & Current Sources
Programmable Attenuators
Automotive
DNL at VA = 3 V
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC101S101, DAC101S101-Q1
SNAS321G – JUNE 2005 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings DAC101S101 ...................................... 4
ESD Ratings DAC101S101-Q1 ................................ 4
Recommended Operating Conditions ...................... 5
Thermal Information .................................................. 5
Electrical Characteristics.......................................... 6
A.C. and Timing Requirements................................ 9
Typical Characteristics ............................................ 11
Detailed Description ............................................ 17
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 18
8.5 Programming .......................................................... 19
9
Application and Implementation ........................ 21
9.1 Application Information............................................ 21
9.2 Typical Application .................................................. 21
10 Power Supply Recommendations ..................... 23
10.1 Using References as Power Supplies................... 23
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 26
12 Device and Documentation Support ................. 27
12.1
12.2
12.3
12.4
12.5
12.6
Device Support ....................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
27
28
28
28
28
28
13 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2013) to Revision G
Page
•
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
•
Updated Operating Conditions table to a Recommended Operating Conditions table .......................................................... 5
•
Updated Layout, Grounding, and Bypassing section to a Layout Guidelines section.......................................................... 26
Changes from Revision E (March 2013) to Revision F
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 26
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Product Folder Links: DAC101S101 DAC101S101-Q1
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SNAS321G – JUNE 2005 – REVISED APRIL 2016
5 Description (continued)
The low power consumption and small packages of the DAC101S101 make it an excellent choice for use in
battery operated equipment.
The DAC101S101 is a direct replacement for the AD5310 and is one of a family of pin compatible DACs,
including the 8-bit DAC081S101 and the 12-bit DAC121S101. The DAC101S101 operates over the extended
industrial temperature range of −40°C to +105°C while the DAC101S101Q operates over the Grade 1 automotive
temperature range of −40°C to +125°C. The DAC101S101 is available in a 6-lead SOT and an 8-lead VSSOP
and the DAC101S101Q is availabe in the 6-lead SOT only.
6 Pin Configuration and Functions
DAC101S101 and DAC101S101-Q1 DDC Package
6-Pin (SOT-23)
Top View
VOUT
1
6
SYNC
GND
2
5
SCLK
VA
3
4
DIN
DAC101S101 DGK Package
8-Pin (VSSOP)
Top View
VA
1
8
GND
NC
2
7
DIN
NC
3
6
SCLK
VOUT
4
5
SYNC
Pin Functions
PIN
NAME
DAC101S101
DAC101S101-Q1
I/O (1)
DESCRIPTION
SOT-23
VSSOP
SOT-23
DIN
4
7
4
I
Serial Data Input. Data is clocked into the 16-bit shift register on the
falling edges of SCLK after the fall of SYNC.
GND
2
8
2
G
Ground reference for all on-chip circuitry.
NC
–
2,3
–
–
No Connect. There is no internal connection to these pins.
SCLK
5
6
5
I
Serial Clock Input. Data is clocked into the input shift register on the
falling edges of this pin.
SYNC
6
5
6
I
Frame synchronization input for the data input. When this pin goes low, it
enables the input shift register and data is transferred on the falling
edges of SCLK. The DAC is updated on the 16th clock cycle unless
SYNC is brought high before the 16th clock, in which case the rising
edge of SYNC acts as an interrupt and the write sequence is ignored by
the DAC.
VA
3
1
3
S
Power supply and Reference input. Should be decoupled to GND.
VOUT
1
4
1
O
DAC Analog Output Voltage.
(1)
G = Ground, I = Input, O = Output, S = Supply
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SNAS321G – JUNE 2005 – REVISED APRIL 2016
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
MIN
MAX
UNIT
6.5
V
Supply voltage, VA
Voltage on any input pin
Input current at any pin
Package input current
–0.3
(VA + 0.3)
V
10
mA
(4)
(4)
20
Power consumption at TA = 25°C
See
−65
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
mA
(5)
150
°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
All voltages are measured with respect to GND = 0V, unless otherwise specified
When the input voltage at any pin exceeds the power supplies (that is, less than GND, or greater than VA), the current at that pin should
be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of 10 mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe
fault condition (e.g., when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
7.2 ESD Ratings DAC101S101
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2)
±2500
Machine Model
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO
Ohms.
7.3 ESD Ratings DAC101S101-Q1
VALUE
V(ESD)
(1)
4
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±2500
Machine Model
±250
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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SNAS321G – JUNE 2005 – REVISED APRIL 2016
7.4 Recommended Operating Conditions (1)
(2)
MIN
Operating temperature
Any input voltage
(4)
Output load
2.7
5.5
–0.1
(VA + 0.1)
V
0
1500
pF
SCLK frequency
(1)
(2)
(3)
(4)
UNIT
−40°C ≤ TA ≤ +125°C
DAC101S101-Q1
Supply voltage, VA (3)
MAX
−40°C ≤ TA ≤ +105°C
DAC101S101
V
Up to 30 MHz
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to GND = 0V, unless otherwise specified
To ensure accuracy, it is required that VA be well bypassed.
The analog inputs are protected as shown below. Input voltage magnitudes up to VA + 300 mV or to 300 mV below GND will not
damage this device. However, errors in the conversion result can occur if any input goes above VA or below GND by more than 100 mV.
For example, if VA is 2.7VDC, ensure that −100mV ≤ input voltages ≤2.8VDC to ensure accurate conversions.
I/O
TO INTERNAL
CIRCUITRY
GND
7.5 Thermal Information
THERMAL METRIC (1)
DAC101S101,
DAC101S101-Q1
DAC101S101
DDC (SOT-23)
DGK (VSSOP)
6 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
250
240
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
58.8
70.0
°C/W
RθJB
Junction-to-board thermal resistance
30.6
100.2
°C/W
ψJT
Junction-to-top characterization parameter
1.6
11.3
°C/W
ψJB
Junction-to-board characterization parameter
30.1
98.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2005–2016, Texas Instruments Incorporated
Product Folder Links: DAC101S101 DAC101S101-Q1
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DAC101S101, DAC101S101-Q1
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7.6
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Electrical Characteristics
The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input
code range 12 to 1011, TA = 25°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP
(1)
MAX
(1)
UNIT
STATIC PERFORMANCE
Resolution
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q:
−40°C ≤ TA ≤ +125°C
10
Bits
Monotonicity
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q:
−40°C ≤ TA ≤ +125°C
10
Bits
INL
Integral non-linearity
Over decimal
codes 12 to
DAC101S101: −40°C ≤ TA ≤ +105°C,
1011
DAC101S101Q: −40°C ≤ TA ≤ +125°C
DNL
Differential
non-linearity
VA = 2.7 V to
5.5 V
ZE
Zero code error
IOUT = 0
FSE
Full-scale error
IOUT = 0
GE
Gain error
All ones
Loaded to
DAC register
ZCED
Zero code error drift
±0.6
–2.8
2.8
LSB
−0.05/+0.15
DAC101S101: −40°C ≤ TA ≤ +105°C,
DAC101S101Q: −40°C ≤ TA ≤ +125°C
−0.2
0.35
LSB
3.3
DAC101S101: −40°C ≤ TA ≤ +105°C,
DAC101S101Q: −40°C ≤ TA ≤ +125°C
15
mV
−0.06
TC GE
Gain error tempco
DAC101S101: −40°C ≤ TA ≤ +105°C,
DAC101S101Q: −40°C ≤ TA ≤ +125°C
–1
%FSR
−0.1
DAC101S101: −40°C ≤ TA ≤ +105°C,
DAC101S101Q: −40°C ≤ TA ≤ +125°C
–1
1
%FSR
−20
µV/°C
VA = 3 V
−0.7
ppm/°C
VA = 5 V
−1
ppm/°C
OUTPUT CHARACTERISTICS
Output voltage range
DAC101S101: −40°C ≤ TA ≤ +105°C, DAC101S101Q:
−40°C ≤ TA ≤ +125°C (2)
0
VA = 3 V, IOUT = 10 µA
ZCO
Zero code output
VA = 3 V, IOUT = 100 µA
VA = 5 V, IOUT = 10 µA
VA = 5 V, IOUT = 100 µA
FSO
Full scale output
Maximum load
capacitance
(1)
(2)
6
Output short circuit
current
V
1.8
mV
5
mV
3.7
mV
5.4
mV
VA = 3 V, IOUT = 10 µA
2.997
V
VA = 3 V, IOUT = 100 µA
2.99
V
VA = 5 V, IOUT = 10 µA
4.995
V
VA = 5 V, IOUT = 100 µA
4.992
V
RL = ∞
1500
pF
RL = 2 kΩ
1500
pF
1.3
Ω
VA = 5 V, VOUT = 0 V,
Input code = 3FFh
−63
mA
VA = 3 V, VOUT = 0 V,
Input code = 3FFh
−50
mA
VA = 5 V, VOUT = 5 V,
Input code = 000h
74
mA
VA = 3 V, VOUT = 3 V,
Input code = 000h
53
mA
DC output Impedance
IOS
VA
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
This parameter is ensured by design and/or characterization and is not tested in production.
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SNAS321G – JUNE 2005 – REVISED APRIL 2016
Electrical Characteristics (continued)
The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input
code range 12 to 1011, TA = 25°C, unless otherwise specified.
(1)
UNIT
1
µA
VA = 5 V, DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C
0.8
V
VA = 3 V, DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: −40°C ≤ TA ≤ +125°C
0.5
V
PARAMETER
TEST CONDITIONS
MIN (1)
TYP
(1)
MAX
LOGIC INPUT
IIN
VIL
VIH
CIN
Input current
DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q:
–40°C ≤ TA ≤ +125°C
(2)
Input low voltage
(2)
Input high voltage
Input capacitance
(2)
(2)
–1
VA = 5 V, DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C
2.4
V
VA = 3 V, DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C
2.1
V
DAC101S101: –40°C ≤ TA ≤ +105°C, DAC101S101Q:
–40°C ≤ TA ≤ +125°C
3
pF
POWER REQUIREMENTS
256
VA = 5.5 V
Normal Mode
fSCLK = 30
MHz
DAC101S101: –40°C
≤ TA ≤ +105°C,
DAC101S101Q:
–40°C ≤ TA ≤ +125°C
332
µA
174
VA = 3.6 V
DAC101S101: −40°C
≤ TA ≤ +105°C,
DAC101S101Q:
−40°C ≤ TA ≤ +125°C
226
µA
221
VA = 5.5 V
Normal Mode
fSCLK = 20
MHz
Supply current
(output unloaded)
297
µA
154
VA = 3.6 V
IA
DAC101S101: −40°C
≤ TA ≤ +105°C,
DAC101S101Q:
−40°C ≤ TA ≤ +125°C
DAC101S101: −40°C
≤ TA ≤ +105°C,
DAC101S101Q:
−40°C ≤ TA ≤ +125°C
Normal Mode VA = 5.5 V
fSCLK = 0
VA = 3.6 V
207
145
µA
113
All PD
Modes,
fSCLK = 30
MHz
VA = 5 V
83
VA = 3 V
42
All PD
Modes,
fSCLK = 20
MHz
VA = 5 V
56
VA = 3 V
28
µA
µA
µA
0.06
VA = 5.5 V
All PD
Modes,
fSCLK = 0
DAC101S101: −40°C
≤ TA ≤ +105°C,
DAC101S101Q:
−40°C ≤ TA ≤ +125°C
1
µA
0.04
(2)
VA = 3.6 V
DAC101S101: −40°C
≤ TA ≤ +105°C,
DAC101S101Q:
−40°C ≤ TA ≤ +125°C
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DAC101S101, DAC101S101-Q1
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Electrical Characteristics (continued)
The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input
code range 12 to 1011, TA = 25°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP
(1)
MAX
(1)
UNIT
1.41
VA = 5.5 V
Normal Mode
fSCLK = 30
MHz
DAC101S101: −40°C
≤ TA ≤ +105°C,
DAC101S101Q:
−40°C ≤ TA ≤ +125°C
1.83
mW
0.63
VA = 3.6 V
DAC101S101: −40°C
≤ TA ≤ +105°C,
DAC101S101Q:
−40°C ≤ TA ≤ +125°C
0.81
mW
1.22
VA = 5.5 V
Normal Mode
fSCLK = 20
MHz
Power consumption
(output unloaded)
1.63
mW
0.55
VA = 3.6 V
PC
DAC101S101: −40°C
≤ TA ≤ +105°C,
DAC101S101Q:
−40°C ≤ TA ≤ +125°C
DAC101S101: −40°C
≤ TA ≤ +105°C,
DAC101S101Q:
−40°C ≤ TA ≤ +125°C
0.74
Normal Mode VA = 5.5 V
fSCLK = 0
VA = 3.6 V
mW
0.8
µW
0.41
µW
All PD
Modes,
fSCLK = 30
MHz
VA = 5 V
0.42
µW
VA = 3 V
0.13
µW
All PD
Modes,
fSCLK = 20
MHz
VA = 5 V
0.28
µW
VA = 3 V
0.08
µW
0.33
VA = 5.5 V
All PD
Modes,
fSCLK = 0
8
ILOAD = 2 mA
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5.5
µW
0.14
(2)
VA = 3.6 V
IOUT / IA Power efficiency
DAC101S101: –40°C
≤ TA ≤ +105°C,
DAC101S101Q:
–40°C ≤ TA ≤ +125°C
DAC101S101: –40°C
≤ TA ≤ +105°C,
DAC101S101Q:
–40°C ≤ TA ≤ +125°C
3.6
VA = 5 V
91%
VA = 3 V
94%
µW
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Product Folder Links: DAC101S101 DAC101S101-Q1
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7.7
SNAS321G – JUNE 2005 – REVISED APRIL 2016
A.C. and Timing Requirements
The following specifications apply for VA = +2.7 V to +5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, fSCLK = 30 MHz, input
code range 12 to 1011, TA = 25°C, unless otherwise specified.
MIN (1)
fSCLK
SCLK Frequency
DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C
ts
Output voltage
settling time (2)
100h to 300h code change,
RL = 2 kΩ
SR
Output slew rate
Glitch impulse
CL ≤
200
pF
Wake-up time
1/fSCL
SCLK Cycle time
K
MAX (1)
UNIT
30
MHz
5
DAC101S101: –40°C ≤ TA ≤
+105°C, DAC101S101Q:
–40°C ≤ TA ≤ +125°C
µs
7.5
Code change from 200h to 1FFh
Digital feedthrough
tWU
TYP (1)
1
V/µs
12
nV-sec
0.5
nV-sec
VA = 5 V
6
µs
VA = 3 V
39
µs
DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C
33
ns
5
tH
SCLK High time
DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C
tL
SCLK Low time
DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C
tSUCL
Set-up time SYNC
to SCLK rising
edge
tSUD
Data set-up time
tDHD
Data hold time
ns
13
5
ns
13
−15
DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C
ns
0
2.5
DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C
ns
5
2.5
DAC101S101: –40°C ≤ TA ≤ +105°C,
DAC101S101Q: –40°C ≤ TA ≤ +125°C
ns
4.5
0
DAC101S101: −40°C ≤ TA ≤
+105°C, DAC101S101Q:
−40°C ≤ TA ≤ +125°C
VA = 5 V
SCLK fall to rise of
SYNC
tCS
ns
3
−2
DAC101S101: −40°C ≤ TA ≤
+105°C, DAC101S101Q:
−40°C ≤ TA ≤ +125°C
VA = 3 V
ns
1
9
tSYNC
(1)
(2)
2.7 ≤ VA ≤ 3.6
DAC101S101: −40°C ≤ TA ≤
+105°C, DAC101S101Q:
−40°C ≤ TA ≤ +125°C
3.6 ≤ VA ≤ 5.5
DAC101S101: −40°C ≤ TA ≤
+105°C, DAC101S101Q:
−40°C ≤ TA ≤ +125°C
SYNC High time
ns
20
5
10
ns
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
This parameter is ensured by design and/or characterization and is not tested in production.
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FSE
1023 x VA
1024
GE = FSE - ZE
FSE = GE + ZE
OUTPUT
VOLTAGE
ZE
0
0
1023
DIGITAL INPUT CODE
Figure 1. Input / Output Transfer Characteristic
SCLK
1
tSUCL
13
14
15
16
tL
tH
tCS
|
tSYNC
2
|
|
1
fCLK
|
SYNC
DB15
|
DIN
| |
tDHD
DB0
tSUD
Figure 2. Serial Timing Diagram
10
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7.8 Typical Characteristics
fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated
Figure 3. DNL at VA = 3 V
Figure 4. DNL at VA = 5 V
Figure 5. INL at VA = 3 V
Figure 6. INL at VA = 5 V
Figure 7. TUE at VA = 3 V
Figure 8. TUE at VA = 5 V
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Typical Characteristics (continued)
fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated
12
Figure 9. DNL vs. VA
Figure 10. INL vs. VA
Figure 11. 3-V DNL vs. fSCLK
Figure 12. 5-V DNL vs. fSCLK
Figure 13. 3-V DNL vs. Clock Duty Cycle
Figure 14. 5-V DNL vs. Clock Duty Cycle
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Typical Characteristics (continued)
fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated
Figure 15. 3-V DNL vs. Temperature
Figure 16. 5-V DNL vs. Temperature
Figure 17. 3-V INL vs. fSCLK
Figure 18. 5-V INL vs. fSCLK
Figure 19. 3-V INL vs. Clock Duty Cycle
Figure 20. 5-V INL vs. Clock Duty Cycle
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Typical Characteristics (continued)
fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated
14
Figure 21. 3-V INL vs. Temperature
Figure 22. 5-V INL vs. Temperature
Figure 23. Zero Code Error vs. fSCLK
Figure 24. Zero Code Error vs. Clock Duty Cycle
Figure 25. Zero Code Error vs. Temperature
Figure 26. Full-Scale Error vs. fSCLK
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Typical Characteristics (continued)
fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated
Figure 27. Full-Scale Error vs. Clock Duty Cycle
Figure 28. Full-Scale Error vs. Temperature
Figure 29. Supply Current vs. VA
Figure 30. Supply Current vs. Temperature
Figure 31. 5-V Glitch Response
Figure 32. Power-On Reset
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Typical Characteristics (continued)
fSCLK = 30 MHz, TA = 25°C, Input Code Range 12 to 1011, unless otherwise stated
Figure 33. 3-V Wake-Up Time
16
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Figure 34. 5-V Wake-Up Time
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8 Detailed Description
8.1 Overview
The DAC101S101 is a full-featured, general purpose 10-bit voltage-output digital-to-analog converter (DAC)
that can operate from a single +2.7 V to 5.5 V supply and consumes just 175 µA of current at 3.6 Volts. The
on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock
rates up to 30 MHz over the specified supply voltage range and is compatible with standard SPI, QSPI,
MICROWIRE and DSP interfaces.
The supply voltage for the DAC101S101 serves as its voltage reference, providing the widest possible output
dynamic range. A power-on reset circuit ensures that the DAC output powers up to zero volts and remains
there until there is a valid write to the device. A power-down feature reduces power consumption to less than
a microWatt.
8.2 Functional Block Diagram
VA
GND
POWER-ON
RESET
DAC101S101
REF(+) REF(-)
DAC
REGISTER
10
10-BIT DAC
BUFFER
VOUT
10
POWER-DOWN
CONTROL
LOGIC
INPUT
CONTROL
LOGIC
SYNC
SCLK
1k
100k
DIN
8.3 Feature Description
8.3.1 DAC Section
The DAC101S101 is fabricated on a CMOS process with an architecture that consists of a resistor string and
switches that are followed by an output buffer. The power supply serves as the reference voltage. The input
coding is straight binary with an ideal output voltage of:
VOUT = VA x (D / 1024)
where
•
D is the decimal equivalent of the binary code that is loaded into the DAC register and can take on any value
between 0 and 1023
(1)
8.3.2 Resistor String
The resistor string is shown in Figure 35. This string consists of 1024 equal valued resistors in series with a
switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register
determines which switch is closed, connecting the proper node to the amplifier. This configuration ensures that
the DAC is monotonic.
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Feature Description (continued)
VA
R
R
R
To Output Amplifier
R
R
Figure 35. DAC Resistor String
8.3.3 Output Amplifier
The output buffer amplifier is a rail-to-rail type, providing an output voltage range of 0V to VA. All amplifiers, even
rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA, in this case). For
this reason, linearity is specified over less than the full output range of the DAC. The output capabilities of the
amplifier are described in the Electrical Characteristics Tables.
8.3.4 Power-On Reset
The power-on reset circuit controls the output voltage during power-up. The DAC register is filled with zeros and
the output voltage is 0 Volts and remains there until a valid write sequence is made to the DAC.
8.4 Device Functional Modes
8.4.1 Power-Down Modes
The DAC101S101 has four modes of operation. These modes are set with two bits (DB13 and DB12) in the
control register.
Table 1. Modes of Operation
18
DB13
DB12
0
0
Normal Operation
0
1
Power-Down with 1 kΩ to GND
1
0
Power-Down with 100 kΩ to GND
1
1
Power-Down with Hi-Z
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When both DB13 and DB12 are 0, the device operates normally. For the other three possible combinations of
these bits the supply current drops to its power-down level and the output is pulled down with either a 1kΩ or a
100KΩ resistor, or is in a high impedance state, as described in Table 1.
The bias generator, output amplifier, the resistor string and other linear circuitry are all shut down in any of the
power-down modes. However, the contents of the DAC register are unaffected when in power-down. Minimum
power consumption is achieved in the power-down mode with SCLK disabled and SYNC and DIN idled low. The
time to exit power-down (Wake-Up Time) is typically tWU µsec as stated in the A.C. and Timing Requirements
Table.
8.5 Programming
8.5.1 Serial Interface
The three-wire interface is compatible with SPI, QSPI and MICROWIRE as well as most DSPs. See the Serial
Timing Diagram for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked
into the 16-bit serial input register on the falling edges of SCLK. On the 16th falling clock edge, the last data bit is
clocked in and the programmed function (a change in the mode of operation and/or a change in the DAC register
contents) is executed. At this point the SYNC line may be kept low or brought high. In either case, it must be
brought high for the minimum specified time before the next write sequence so that a falling edge of SYNC can
initiate the next write cycle.
Because the SYNC and DIN buffers draw more current when they are high, they should be idled low between
write sequences to minimize power consumption.
8.5.2 Input Shift Register
The input shift register, Figure 36, has sixteen bits. The first two bits are "don't cares" and are followed by two
bits that determine the mode of operation (normal mode or one of three power-down modes). The contents of the
serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Figure 2.
LSB
MSB
X
X
PD1 PD0 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
DATA BITS
0
0
1
1
0 Normal Operation
1 1 k: to GND
0 100 k: to GND
1 High Impedance
Power-Down Modes
Figure 36. Input Register Contents
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the shift register is reset and
the write sequence is invalid. The DAC register is not updated and there is no change in the mode of operation.
8.5.3 DSP/Microprocessor Interfacing
Interfacing the DAC101S101 to microprocessors and DSPs is quite simple. The following guidelines are offered
to hasten the design process.
8.5.3.1 ADSP-2101/ADSP2103 Interfacing
Figure 37 shows a serial interface between the DAC101S101 and the ADSP-2101/ADSP2103. The DSP should
be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control
register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
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Programming (continued)
ADSP-2101/
ADSP2103
TFS
DT
SCLK
DAC101S101
SYNC
DIN
SCLK
Figure 37. ADSP-2101/2103 Interface
8.5.3.2 80C51/80L51 Interface
A serial interface between the DAC101S101 and the 80C51/80L51 microcontroller is shown in Figure 38. The
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line
P3.3. This line is taken low when data is to transmitted to the DAC101S101. Since the 80C51/80L51 transmits 8bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must
be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of
data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the
80C51/80L51 transmits data with the LSB first while the DAC101S101 requires data with the MSB first.
80C51/80L51
DAC101S101
P3.3
SYNC
TXD
SCLK
RXD
DIN
Figure 38. 80C51/80L51 Interface
8.5.3.3 68HC11 Interface
A serial interface between the DAC101S101 and the 68HC11 microcontroller is shown in Figure 39. The SYNC
line of the DAC101S101 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.
The 68HC11 should be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the
second byte of data to the DAC, after which PC7 should be raised to end the write sequence.
68HC11
DAC101S101
PC7
SCK
MOSI
SYNC
SCLK
DIN
Figure 39. 68HC11 Interface
8.5.3.4 Microwire Interface
Figure 40 shows an interface between a Microwire compatible device and the DAC101S101. Data is clocked out
on the rising edges of the SCLK signal.
MICROWIRE
DEVICE
DAC101S101
CS
SYNC
SK
SCLK
SO
DIN
Figure 40. Microwire Interface
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DAC101S101 is designed for single supply operation and thus has a unipolar output. However, a bipolar
output may be obtained with the circuit in Figure 41. This circuit will provide an output voltage range of ±5 Volts.
A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5V.
9.2 Typical Application
10 pF
R2
+5V
+5V
10 PF
R1
+
-
0.1 PF
±5V
+
DAC101S101
-5V
SYNC
VOUT
DIN
SCLK
Figure 41. Bipolar Operation
9.2.1 Design Requirements
•
•
•
The DAC101S101 will use a single supply.
The output is required to be bipolar with a voltage range of ±5 V.
Dual supplies will be used for the output amplifier.
9.2.2 Detailed Design Procedure
The output voltage of this circuit for any code is found to be
VO = (VA x (D / 1024) x ((R1 + R2) / R1) - VA x R2 / R1)
where
• D is the input code in decimal form
• With VA = 5V and R1 = R2
VO = (10 x D / 1024) - 5V
(2)
(3)
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.
Table 2. Some Rail-To-Rail Amplifiers
AMP
PKGS
LMC7111
SOT-23-5
0.9 mV
Typ VOS
25 µA
LM7301
SOIC-8
SOT-23-5
0.03 mV
620 µA
LM8261
SOT-23-5
0.7 mV
1 mA
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9.2.3 Application Curve
5V
OUTPUT
VOLTAGE
-5V
0
1023
DIGITAL INPUT CODE
Figure 42. Bipolar Input / Output Transfer Characteristic
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10 Power Supply Recommendations
The simplicity of the DAC101S101 implies ease of use. However, it is important to recognize that any data
converter that utilizes its supply voltage as its reference voltage will have essentially zero PSRR (Power Supply
Rejection Ratio). Therefore, it is necessary to provide a noise-free supply voltage to the device.
10.1 Using References as Power Supplies
Since the DAC101S101 consumes very little power, a reference source may be used as the supply voltage. The
advantages of using a reference source over a voltage regulator are accuracy and stability. Some low noise
regulators can also be used for the power supply of the DAC101S101. Listed below are a few power supply
options for the DAC101S101.
10.1.1 LM4130
The LM4130 reference, with its 0.05% accuracy over temperature, is a good choice as a power source for the
DAC101S101. Its primary disadvantage is the lack of a 3V and 5V versions. However, the 4.096V version is
useful if a 0 to 4.095V output range is desirable or acceptable. Bypassing the VIN pin with a 0.1µF capacitor and
the VOUT pin with a 2.2µF capacitor will improve stability and reduce output noise. The LM4130 comes in a
space-saving 5-pin SOT-23.
Input
Voltage
LM4130-4.1
C2
2.2 PF
C1
0.1 PF
DAC101S101
SYNC
VOUT = 0V to 4.092V
DIN
SCLK
Figure 43. The LM4130 as a Power Supply
10.1.2 LM4050
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a power regulator for the
DAC101S101. It does not come in a 3 Volt version, but 4.096V and 5V versions are available. It comes in a
space-saving 3-pin SOT-23.
Input
Voltage
R
VZ
LM4050-4.1
or
LM4050-5.0
0.47 PF
DAC101S101
SYNC
VOUT = 0V to 5V
DIN
SCLK
Figure 44. The LM4050 as a Power Supply
The minimum resistor value in the circuit of Figure 44 should be chosen such that the maximum current through
the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at
its maximum, the LM4050 voltage at its minimum, the resistor value at its minimum due to tolerance, and the
DAC101S101 draws zero current. The maximum resistor value must allow the LM4050 to draw more than its
minimum current for regulation plus the maximum DAC101S101 current in full operation. The conditions for
minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value
at its maximum due to tolerance, and the DAC101S101 draws its maximum current. These conditions can be
summarized as
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Using References as Power Supplies (continued)
R(min) = ( VIN(max) − VZ(min) / (IA(min) + IZ(max))
where
•
•
•
VZ(min) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature
IZ(max) is the maximum allowable current through the LM4050
IA(min) is the minimum DAC101S101 supply current
(4)
and
R(max) = ( VIN(min) − VZ(max) / (IA(max) + IZ(min) )
where
•
•
•
VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over temperature
IZ(min) is the minimum current required by the LM4050 for proper regulation
IA(max) is the maximum DAC101S101 supply current
(5)
10.1.3 LP3985
The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good
choice for applications that do not require a precision reference for the DAC101S101. It comes in 3.0V, 3.3V and
5V versions, among others, and sports a low 30 µV noise specification at low frequencies. Because low
frequency noise is relatively difficult to filter, this specification could be important for some applications. The
LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump micro SMD packages.
Input
Voltage
LP3985
1 PF
0.1 PF
0.01 PF
DAC101S101
SYNC
VOUT = 0V to 5V
DIN
SCLK
Figure 45. Using The Lp3985 Regulator
An input capacitance of 1 µF without any ESR requirement is required at the LP3985 input, while a 1-µF ceramic
capacitor with an ESR requirement of 5 mΩ to 500 mΩ is required at the output. Careful interpretation and
understanding of the capacitor specification is required to ensure correct device operation.
10.1.4 LP2980
The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon
grade. It is available in 3 V, 3.3 V and 5 V versions, among others.
Input
Voltage
VIN
ON / OFF
LP2980
VOUT
1 PF
DAC101S101
SYNC
VOUT = 0V to 5V
DIN
SCLK
Figure 46. Using The Lp2980 Regulator
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Using References as Power Supplies (continued)
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor
must be at least 1-µF over temperature, but values of 2.2 µF or more provide better performance. The ESR of
this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum
capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to their small
size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors
are typically not a good choice due to their large size and have ESR values that may be too high at low
temperatures.
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11 Layout
11.1 Layout Guidelines
For best accuracy and minimum noise, the printed circuit board containing the DAC101S101 should have
separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.
Both of these planes should be located in the same board layer. There should be a single ground plane. A single
ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a
single ground plane design will utilize a "fencing" technique to prevent the mixing of analog and digital ground
current. Separate ground planes should only be utilized when the fencing technique is inadequate. The separate
ground planes must be connected in one place, preferably near the DAC101S101. Special care is required to
ensure that digital signals with fast edge rates do not pass over split ground planes. They must always have a
continuous return path below their traces.
The DAC101S101 power supply should be bypassed with a 10-µF and a 0.1-µF capacitor as close as possible to
the device with the 0.1-µF right at the device supply pin. The 10-µF capacitor should be a tantalum type and the
0.1-µF capacitor should be a low ESL, low ESR type. The power supply for the DAC101S101 should only be
used for analog circuits.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the
board. The clock and data lines should have controlled impedances.
11.2 Layout Example
Figure 47. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB, which is VREF / 1024 = VA / 1024.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the
data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (3FFh) loaded
into the DAC and the value of VA x 1023 / 1024.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is
Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register
changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line
is measured from the center of that code value. The end point method is used. INL for this product
is specified over a limited range, per the Electrical Characteristics Tables.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value
is
LSB = VREF / 2n
where
•
•
VREF is the supply voltage for this product
"n" is the DAC resolution in bits, which is 10 for the DAC101S101
(6)
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output
stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when
the output code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VREF.
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Device Support (continued)
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from
the power supply. The difference between the supply and output currents, is the power consumed
by the device without a load.
SETTLING TIME is the time for the output to settle within 1/2 LSB of the final value.
WAKE-UP TIME is the time for the output to settle within 1/2 LSB of the final value after the device is
commanded to the active mode from any of the power down modes.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been
entered.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DAC101S101
Click here
Click here
Click here
Click here
Click here
DAC101S101-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
28
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Copyright © 2005–2016, Texas Instruments Incorporated
Product Folder Links: DAC101S101 DAC101S101-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC101S101CIMK/NOPB
ACTIVE
SOT-23-THIN
DDC
6
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
X63C
DAC101S101CIMKX/NOPB
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
X63C
DAC101S101CIMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
X62C
DAC101S101QCMK/NOPB
ACTIVE
SOT-23-THIN
DDC
6
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
X63Q
DAC101S101QCMKX/NOPB
ACTIVE
SOT-23-THIN
DDC
6
3000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
X63Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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