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DAC104S085, DAC104S085-Q1
SNAS362G – MAY 2006 – REVISED APRIL 2016
DAC104S085-xx 10-Bit Micro Power QUAD Digital-to-Analog Converter With Rail-to-Rail
Output
1 Features
3 Description
•
•
The DAC104S085 device is a full-featured, generalpurpose QUAD 10-bit voltage-output digital-to-analog
converter (DAC) that can operate from a single 2.7-V
to 5.5-V supply and consumes 1.1 mW at 3 V and
2.5 mW at 5 V. The DAC104S085 is packaged in 10pin SON and VSSOP packages. The 10-pin SON
package makes the DAC104S085 the smallest QUAD
DAC in its class. The on-chip output amplifier allows
rail-to-rail output swing and the three wire serial
interface operates at clock rates up to 40 MHz over
the entire supply voltage range. Competitive devices
are limited to 25-MHz clock rates at supply voltages
in the 2.7-V to 3.6-V range. The serial interface is
compatible with standard SPI, QSPI, MICROWIRE,
and DSP interfaces.
1
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature
Ensured Monotonicity
Low Power Operation
Rail-to-Rail Voltage Output
Power-On Reset to 0 V
Simultaneous Output Updating
Wide Power Supply Range (2.7 V to 5.5 V)
Key Specifications
– Resolution: 10 bits
– INL: ±2 LSB (Maximum)
– DNL: +0.35 / −0.25 LSB (Maximum)
– Settling Time: 6 μs (Maximum)
– Zero Code Error: 15 mV (Maximum)
– Full-Scale Error: −0.75% FS (Maximum)
– Typical Supply Power
– Normal Mode: 1.1 mW (3 V), 2.5 mW (5 V)
– Power Down: 0.3 μW (3 V), 0.8 μW (5 V)
The reference for the DAC104S085 serves all four
channels and can vary in voltage between 1 V and
VA, providing the widest possible output dynamic
range. The DAC104S085 has a 16-bit input shift
register that controls the outputs to be updated, the
mode of operation, the power-down condition, and
the binary input data. All four outputs can be updated
simultaneously or individually depending on the
setting of the two mode of operation bits.
Device Information(1)
2 Applications
•
•
•
•
•
PART NUMBER
Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Automotives
DAC104S085-xx
PACKAGE
BODY SIZE (NOM)
VSSOP (10)
3.00 mm × 3.00 mm
WSON (10)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
VREFIN
DAC104S085
REF
POWER-ON
RESET
1
0
10 BIT DAC
VOUTA
BUFFER
2.5k
100k
REF
1
0
10 BIT DAC
VOUTB
BUFFER
DAC
REGISTER
2.5k
100k
REF
1
0
1
0
10 BIT DAC
2.5k
100k
2.5k
100k
VOUTD
BUFFER
POWER-DOWN
CONTROL
LOGIC
INPUT
CONTROL
LOGIC
SCLK
VOUTC
BUFFER
REF
1
0
SYNC
10 BIT DAC
DIN
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC104S085, DAC104S085-Q1
SNAS362G – MAY 2006 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
4
4
5
5
7
9
Absolute Maximum Ratings .....................................
ESD Ratings – DAC104S085 ...................................
ESD Ratings – DAC104S085-Q1 .............................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 15
8.5 Programming........................................................... 16
9
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 21
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 23
12 Device and Documentation Support ................. 24
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (March 2013) to Revision G
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision E (March 2013) to Revision F
•
2
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 23
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SNAS362G – MAY 2006 – REVISED APRIL 2016
5 Description (continued)
A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a
valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three
different termination options.
The low power consumption and small packages of the DAC104S085 make it an excellent choice for use in
battery-operated equipment.
The DAC104S085 is one of a family of pin-compatible DACs, including the 8-bit DAC084S085 and the 12-bit
DAC124S085. The DAC104S085 operates over the extended industrial temperature range of −40°C to +125°C.
6 Pin Configuration and Functions
DSC Package
10-Pin SON
Top View
VA 1
VOUTA 2
VOUTB 3
VOUTC 4
VOUTD 5
DGS Package
10-Pin VSSOP
Top View
10 SCLK
9 SYNC
SON 8 DIN
7 VREFIN
VA
1
VOUTA
2
VOUTB
VOUTC
6 GND
VOUTD
10
SCLK
9
3 VSSOP 8
4
7
5
6
SYNC
DIN
VREFIN
GND
Pin Functions
PIN
NO.
TYPE
NAME
DESCRIPTION
1
VA
Supply
Power supply input. Must be decoupled to GND.
2
VOUTA
Analog Output
Channel A Analog Output Voltage.
3
VOUTB
Analog Output
Channel B Analog Output Voltage.
4
VOUTC
Analog Output
Channel C Analog Output Voltage.
5
VOUTD
Analog Output
Channel D Analog Output Voltage.
6
GND
Ground
7
VREFIN
Analog Input
Unbuffered reference voltage shared by all channels. Must be decoupled
to GND.
8
DIN
Digital Input
Serial Data Input. Data is clocked into the 16-bit shift register on the
falling edges of SCLK after the fall of SYNC.
Ground reference for all on-chip circuitry.
9
SYNC
Digital Input
Frame synchronization input for the data input. When this pin goes low, it
enables the input shift register and data is transferred on the falling edges
of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is
brought high before the 16th clock, in which case the rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the DAC.
10
SCLK
Digital Input
Serial Clock Input. Data is clocked into the input shift register on the
falling edges of this pin.
11
PAD
(SON only)
Ground
Exposed die attach pad can be connected to ground or left floating.
Soldering the pad to the PCB offers optimal thermal performance and
enhances package self-alignment during reflow.
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DAC104S085, DAC104S085-Q1
SNAS362G – MAY 2006 – REVISED APRIL 2016
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
(1) (2) (3)
MIN
Supply voltage, VA
−0.3
Voltage on any input pin
Input current at any pin (4)
Package input current (4)
Power consumption at TA = 25°C
See
Junction temperature
−65
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
MAX
UNIT
6.5
V
6.5
V
10
mA
20
mA
150
°C
150
°C
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are measured with respect to GND = 0 V, unless otherwise specified.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10
mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation is reached only when the device is operated in a severe fault
condition (that is, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).
7.2 ESD Ratings – DAC104S085
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2)
±2500
Machine model (MM)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
Human body model is 100-pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω.
7.3 ESD Ratings – DAC104S085-Q1
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
VALUE
UNIT
±2500
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.4 Recommended Operating Conditions (1)
MIN
MAX
UNIT
Operating temperature
–40
125
°C
Supply voltage, VA
2.7
5.5
V
Reference voltage, VREFIN
1
VA
V
Digital input voltage (2)
0
5.5
V
Output load
0
1500
pF
(1)
(2)
All voltages are measured with respect to GND = 0 V, unless otherwise specified.
The inputs are protected as shown. Input voltage magnitudes up to 5.5 V, regardless of VA, does not cause errors in the conversion
result. For example, if VA is 3 V, the digital input pins can be driven with a 5-V logic device.
I/O
TO INTERNAL
CIRCUITRY
GND
4
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SNAS362G – MAY 2006 – REVISED APRIL 2016
Recommended Operating Conditions(1) (continued)
MIN
MAX
UNIT
40
MHz
SCLK frequency
7.5 Thermal Information
DAC104S085-xx
THERMAL METRIC (1) (2) (3)
DGS (VSSOP)
DSC (SON)
10 PINS
10 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
159
48.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
53.3
40.7
°C/W
RθJB
Junction-to-board thermal resistance
78.9
23.7
°C/W
ψJT
Junction-to-top characterization parameter
4.8
0.4
°C/W
ψJB
Junction-to-board characterization parameter
77.6
23.8
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
4.7
°C/W
(1)
(2)
(3)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Soldering process must comply with Reflow Temperature Profile specifications. See the Absolute Maximum Ratings for Soldering
application report, SNOA549, for more information.
Reflow temperature profiles are different for lead-free packages.
7.6 Electrical Characteristics
The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range
from 12 to 1011. All limits are at TA = 25°C, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN (1)
TYP (1)
MAX (1)
UNIT
STATIC PERFORMANCE
Resolution
TMIN ≤ TA ≤ TMAX
10
Monotonicity
TMIN ≤ TA ≤ TMAX
10
Integral non-linearity
DNL
Differential non-linearity
VA = 2.7 V to 5.5 V
ZE
Zero code error
IOUT = 0 mA
FSE
Full-scale error
IOUT = 0 mA
GE
Gain error
All ones Loaded to
DAC register
ZCED
Zero code error drift
Gain error tempco
Bits
±0.7
INL
TC GE
Bits
TMIN ≤ TA ≤ TMAX
LSB
±2
−0.03
TMIN ≤ TA ≤ TMAX
0.08
−0.25
LSB
0.35
5
TMIN ≤ TA ≤ TMAX
mV
15
−0.1
TMIN ≤ TA ≤ TMAX
−0.75
−0.2
TMIN ≤ TA ≤ TMAX
−1
−20
VA = 3 V
−0.7
VA = 5 V
−1
%FSR
%FSR
µV/°C
ppm/°C
OUTPUT CHARACTERISTICS
IOZ
Output voltage range
See (2), TMIN ≤ TA ≤ TMAX
High-impedance output
leakage current (2)
TMIN ≤ TA ≤ TMAX
VA = 3 V, IOUT = 200 µA
ZCO
Zero code output
(2)
0
VREFIN
V
±1
µA
1.3
VA = 3 V, IOUT = 1 mA
6
VA = 5 V, IOUT = 200 µA
7
VA = 5 V, IOUT = 1 mA
(1)
0
VREFIN
mV
10
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
This parameter is ensured by design and/or characterization and is not tested in production.
Copyright © 2006–2016, Texas Instruments Incorporated
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Electrical Characteristics (continued)
The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range
from 12 to 1011. All limits are at TA = 25°C, unless otherwise specified.
PARAMETER
FSO
Full-scale output
Output short-circuit current
(source)
IOS
Output short-circuit current
(sink)
IOS
IO
Continuous output
current (2)
CL
Maximum load capacitance
ZOUT
DC output impedance
MIN (1)
TEST CONDITIONS
TYP (1)
VA = 3 V, IOUT = 200 µA
2.984
VA = 3 V, IOUT = 1 mA
2.934
VA = 5 V, IOUT = 200 µA
4.989
VA = 5 V, IOUT = 1 mA
4.958
VA = 3 V, VOUT = 0 V,
Input Code = 3FFh
–56
VA = 5 V, VOUT = 0 V,
Input Code = 3FFh
–69
VA = 3 V, VOUT = 3 V,
Input Code = 000h
52
VA = 5 V, VOUT = 5 V,
Input Code = 000h
75
MAX (1)
UNIT
V
mA
mA
Available on each DAC output, TMIN ≤ TA ≤ TMAX
11
RL = ∞
1500
RL = 2 kΩ
1500
mA
pF
Ω
7.5
REFERENCE INPUT CHARACTERISTICS
Input range minimum
VREFIN
Input range maximum
0.2
TMIN ≤ TA ≤ TMAX
V
1
TMIN ≤ TA ≤ TMAX
VA
Input impedance
30
V
kΩ
LOGIC INPUT CHARACTERISTICS
IIN
Input current (2)
TMIN ≤ TA ≤ TMAX
VA = 3 V
VIL
Input low voltage (2)
VA = 5 V
VA = 3 V
VIH
Input high voltage (2)
VA = 5 V
CIN
Input capacitance (2)
±1
0.9
TMIN ≤ TA ≤ TMAX
0.6
1.5
TMIN ≤ TA ≤ TMAX
0.8
1.4
TMIN ≤ TA ≤ TMAX
2.1
TMIN ≤ TA ≤ TMAX
2.4
V
V
V
2.1
TMIN ≤ TA ≤ TMAX
µA
V
3
pF
POWER REQUIREMENTS
VA (3)
Supply voltage minimum
TMIN ≤ TA ≤ TMAX
Supply voltage maximum
TMIN ≤ TA ≤ TMAX
2.7
Normal supply current (output
unloaded)
fSCLK = 0 MHz
IPD
(3)
6
Power-down supply current
(output unloaded, SYNC =
DIN = 0V after PD mode
loaded)
350
VA = 2.7 V
to 3.6 V
TMIN ≤ TA ≤ TMAX
VA = 4.5 V
to 5.5 V
TMIN ≤ TA ≤ TMAX
fSCLK = 30 MHz
IN
V
5.5
485
500
650
V
µA
µA
VA = 2.7 V
to 3.6 V
330
µA
VA = 4.5 V
to 5.5 V
460
µA
0.1
VA = 2.7 V
to 3.6 V
TMIN ≤ TA ≤ TMAX
VA = 4.5 V
to 5.5 V
TMIN ≤ TA ≤ TMAX
All PD Modes, (2)
1
0.15
1
µA
µA
To ensure accuracy, it is required that VA and VREFIN be well bypassed.
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Electrical Characteristics (continued)
The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range
from 12 to 1011. All limits are at TA = 25°C, unless otherwise specified.
PARAMETER
Normal supply power (output
unloaded)
fSCLK = 0 MHz
Power-down supply power
(output unloaded, SYNC =
DIN = 0V after PD mode
loaded)
PPD
TYP (1)
MAX (1)
UNIT
1.1
VA = 2.7 V
to 3.6 V
TMIN ≤ TA ≤ TMAX
VA = 4.5 V
to 5.5 V
TMIN ≤ TA ≤ TMAX
fSCLK = 30 MHz
PN
MIN (1)
TEST CONDITIONS
mW
1.7
2.5
mW
3.6
VA = 2.7 V
to 3.6 V
1
mW
VA = 4.5 V
to 5.5 V
2.3
mW
0.3
VA = 2.7 V
to 3.6 V
TMIN ≤ TA ≤ TMAX
VA = 4.5 V
to 5.5 V
TMIN ≤ TA ≤ TMAX
All PD Modes, (2)
µW
3.6
0.8
µW
5.5
7.7 Timing Requirements
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range
from 12 to 1011. All limits are at TA = 25°C, unless otherwise specified.
MIN (1)
fSCLK
SCLK frequency
ts
Output voltage settling time (2)
SR
Output slew rate
TMIN ≤ TA ≤ TMAX
100h to 300h code
change
RL = 2 kΩ, CL = 200
pF
30
TMIN ≤ TA ≤ TMAX
MHz
µs
6
Code change from 200h to 1FFh
Digital crosstalk
DAC-to-DAC crosstalk
1
V/µs
12
nV-sec
0.5
nV-sec
1
nV-sec
3
nV-sec
Multiplying bandwidth
VREFIN = 2.5 V ± 0.1 Vpp
160
kHz
Total harmonic distortion
VREFIN = 2.5 V ± 0.1 Vpp
input frequency = 10 kHz
70
dB
VA = 3 V
6
µsec
VA = 5 V
39
µsec
Wake-up time
1/fSCLK
SCLK cycle time
tCH
SCLK high time
tCL
SCLK low Time
25
TMIN ≤ TA ≤ TMAX
33
TMIN ≤ TA ≤ TMAX
10
TMIN ≤ TA ≤ TMAX
10
tSS
SYNC set-up time prior to SCLK falling
edge
TMIN ≤ TA ≤ TMAX
10
tDS
Data set-up time prior to SCLK falling
edge
TMIN ≤ TA ≤ TMAX
3.5
tDH
Data hold time after SCLK falling edge
TMIN ≤ TA ≤ TMAX
3.5
tCFSR
SCLK fall prior to rise of SYNC
TMIN ≤ TA ≤ TMAX
3
(2)
UNIT
4.5
Digital feedthrough
(1)
MAX (1)
40
Glitch impulse
tWU
TYP (1)
7
7
4
1.5
1.5
0
ns
ns
ns
ns
ns
ns
ns
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
Quality Level).
This parameter is ensured by design and/or characterization and is not tested in production.
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Timing Requirements (continued)
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code range
from 12 to 1011. All limits are at TA = 25°C, unless otherwise specified.
MIN (1)
tSYNC
TYP (1)
6
SYNC high time
TMIN ≤ TA ≤ TMAX
10
MAX (1)
UNIT
ns
|
1 / fSCLK
SCLK
1
2
13
tSS
tSYNC
tCL
14
15
16
tCH
tCFSR
|
SYNC
DIN
| |
tDH
DB15
DB0
tDS
Figure 1. Serial Timing Diagram
FSE
1023 x VREFIN
1024
GE = FSE - ZE
FSE = GE + ZE
OUTPUT
VOLTAGE
ZE
0
0
1024
DIGITAL INPUT CODE
Input / Output Transfer Characteristic
8
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7.8 Typical Characteristics
VREF = VA, fSCLK = 30 MHz, TA = 25°C, Input Code Range from 12 to 1011, unless otherwise stated
Figure 2. INL at VA = 3 V
Figure 3. INL at VA = 5 V
Figure 4. DNL at VA = 3 V
Figure 5. DNL at VA = 5 V
Figure 6. INL/DNL vs VREFIN at VA = 3 V
Figure 7. INL/DNL vs VREFIN at VA = 5 V
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Typical Characteristics (continued)
VREF = VA, fSCLK = 30 MHz, TA = 25°C, Input Code Range from 12 to 1011, unless otherwise stated
10
Figure 8. INL/DNL vs fSCLK at VA = 2.7 V
Figure 9. INL/DNL vs VA
Figure 10. INL/DNL vs Clock Duty Cycle at VA = 3 V
Figure 11. INL/DNL vs Clock Duty Cycle at VA = 5 V
Figure 12. INL/DNL vs Temperature at VA = 3 V
Figure 13. INL/DNL vs Temperature at VA = 5 V
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Typical Characteristics (continued)
VREF = VA, fSCLK = 30 MHz, TA = 25°C, Input Code Range from 12 to 1011, unless otherwise stated
Figure 14. Zero Code Error vs VA
Figure 15. Zero Code Error vs. VREFIN
Figure 16. Zero Code Error vs fSCLK
Figure 17. Zero Code Error vs Clock Duty Cycle
Figure 18. Zero Code Error vs Temperature
Figure 19. Full-Scale Error vs VA
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Typical Characteristics (continued)
VREF = VA, fSCLK = 30 MHz, TA = 25°C, Input Code Range from 12 to 1011, unless otherwise stated
12
Figure 20. Full-Scale Error vs VREFIN
Figure 21. Full-Scale Error vs fSCLK
Figure 22. Full-Scale Error vs Clock Duty Cycle
Figure 23. Full-Scale Error vs Temperature
Figure 24. Supply Current vs VA
Figure 25. Supply Current vs Temperature
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8 Detailed Description
8.1 Overview
The DAC104S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor
strings that are followed by an output buffer. The reference voltage is externally applied at VREFIN and is shared
by all four DACs.
For simplicity, Figure 26 shows a single resistor string. This string consists of 1024 equal valued resistors with a
switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register
determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight
binary with an ideal output voltage found in Equation 1:
VOUTA,B,C,D = VREFIN × (D / 1024)
where
•
D is the decimal equivalent of the binary code that is loaded into the DAC register. D can take on any value
between 0 and 1023. This configuration ensures that the DAC is monotonic.
(1)
VA
R
R
R
To Output Amplifier
R
R
Figure 26. DAC Resistor String
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8.2 Functional Block Diagram
VREFIN
DAC104S085
REF
POWER-ON
RESET
1
0
10 BIT DAC
VOUTA
BUFFER
2.5k
100k
REF
1
0
10 BIT DAC
VOUTB
BUFFER
DAC
REGISTER
2.5k
100k
REF
1
0
10 BIT DAC
VOUTC
BUFFER
2.5k
1
0
1
0
10 BIT DAC
VOUTD
BUFFER
2.5k
SCLK
100k
POWER-DOWN
CONTROL
LOGIC
INPUT
CONTROL
LOGIC
SYNC
100k
REF
DIN
Copyright © 2016, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Output Amplifiers
The output amplifiers are rail-to-rail, providing an output voltage range of 0 V to VA when the reference is VA. All
amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and VA,
in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the
reference is less than VA, there is only a loss in linearity in the lowest codes. The output capabilities of the
amplifier are described in Electrical Characteristics.
The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or to VA. The zerocode and full-scale outputs for given load currents are available in Electrical Characteristics.
8.3.2 Reference Voltage
The DAC104S085 uses a single external reference that is shared by all four channels. The reference pin, VREFIN,
is not buffered and has an input impedance of 30 kΩ. TI recommends driving the VREFIN by a voltage source with
low output impedance. The reference voltage range is 1 V to VA, providing the widest possible output dynamic
range.
8.3.3 Power-On Reset
The power-on reset circuit controls the output voltages of the four DACs during power up. Upon application of
power, the DAC registers are filled with zeros and the output voltages are 0 V. The outputs remain at 0 V until a
valid write sequence is made to the DAC.
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8.4 Device Functional Modes
8.4.1 Power-Down Modes
The DAC104S085 has four power-down modes, two of which are identical. In power-down mode, the supply
current drops to 20 µA at 3 V and 30 µA at 5 V. The DAC104S085 is set in power-down mode by setting OP1
and OP0 to 11. Because this mode powers down all four DACs, the address bits, A1 and A0, are used to select
different output terminations for the DAC outputs. Setting A1 and A0 to 00 or 11 causes the outputs to be tristated (a high impedance state). While setting A1 and A0 to 01 or 10 causes the outputs to be terminated by
2.5 kΩ or 100 kΩ to ground respectively (see Table 1).
Table 1. Power-Down Modes
A1
A0
OP1
OP0
OPERATING MODE
0
0
1
1
High-Z outputs
0
1
1
1
2.5 kΩ to GND
1
0
1
1
100 kΩ to GND
1
1
1
1
High-Z outputs
The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the
power-down modes. However, the contents of the DAC registers are unaffected when in power down. Each DAC
register maintains its value prior to the DAC104S085 being powered down unless it is changed during the write
sequence that instructed it to recover from power down. Minimum power consumption is achieved in the powerdown mode with SYNC and DIN idled low and SCLK disabled. The time to exit power down (Wake-Up Time) is
typically tWU µs as stated in Timing Requirements.
8.4.2 Bipolar Operation
The DAC104S085 is designed for single-supply operation and thus has a unipolar output. However, a bipolar
output may be obtained with the circuit in Figure 27. This circuit provides an output voltage range of ±5 V. A railto-rail amplifier should be used if the amplifier supplies are limited to ±5 V.
10 pF
R2
+5V
R1
+5V
10 PF
+
-
0.1 PF
±5V
+
DAC104S085
-5V
SYNC
VOUT
DIN
SCLK
Copyright © 2016, Texas Instruments Incorporated
Figure 27. Bipolar Operation
The output voltage of this circuit for any code is found in Equation 2 and Equation 3.
VO = (VA × (D / 1024) × ((R1 + R2) / R1) – VA × R2 / R1)
where
•
•
D is the input code in decimal form
With VA = 5 V and R1 = R2
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VO = (10 × D / 1024) – 5 V
(3)
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.
Table 2. Some Rail-to-Rail Amplifiers
AMP
PKGS
LMC7111
DIP-8
SOT23-5
TYP VOS
TYP ISUPPLY
0.9 mV
25 µA
LM7301
SO-8
SOT23-5
0.03 mV
620 µA
LM8261
SOT23-5
0.7 mV
1 mA
8.5 Programming
8.5.1 Serial Interface
The three-wire interface is compatible with SPI, QSPI, and MICROWIRE, as well as most DSPs and operates at
clock rates up to 40 MHz. See the Figure 1 for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked
into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register,
it is critical that SYNC not be brought low simultaneously with a falling edge of SCLK (see Figure 1). On the 16th
falling clock edge, the last data bit is clocked in and the programmed function (a change in the DAC channel
address, mode of operation and/or register contents) is executed. At this point the SYNC line may be kept low or
brought high. Any data and clock pulses after the 16th falling clock edge is ignored. In either case, SYNC must
be brought high for the minimum specified time before the next write sequence is initiated with a falling edge of
SYNC.
Because the SYNC and DIN buffers draw more current when they are high, they must be idled low between write
sequences to minimize power consumption.
8.5.2 Input Shift Register
The input shift register, Figure 28, has sixteen bits. The first two bits are address bits. They determine whether
the register data is for DAC A, DAC B, DAC C, or DAC D. The address bits are followed by two bits that
determine the mode of operation (writing to a DAC register without updating the outputs of all four DACs, writing
to a DAC register and updating the outputs of all four DACs, writing to the register of all four DACs and updating
their outputs, or powering down all four outputs). The final twelve bits of the shift register are the data bits. The
data format is straight binary (MSB first, LSB last), with all 0s corresponding to an output of 0 V and all 1s
corresponding to a full-scale output of VREFIN – 1 LSB. The contents of the serial input register are transferred to
the DAC register on the sixteenth falling edge of SCLK. See Figure 1.
LSB
MSB
A1
A0
OP1 OP0 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
0
0
1
1
0
1
0
1
DAC A
DAC B
DAC C
DAC D
0
0
1
1
0
1
0
1
Write to specified register but do not update outputs.
Write to specified register and update outputs.
Write to all registers and update outputs.
Power-down outputs.
Figure 28. Input Register Contents
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift
register is aborted and the write sequence is invalid. Under this condition, the DAC register is not updated and
there is no change in the mode of operation or in the DAC output voltages.
8.5.3 DSP and Microprocessor Interfacing
Interfacing the DAC104S085 to microprocessors and DSPs is quite simple. The following guidelines are offered
to hasten the design process.
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Programming (continued)
8.5.3.1 ADSP-2101 and ADSP2103 Interfacing
Figure 29 shows a serial interface between the DAC104S085 and the ADSP-2101 or ADSP2103. The DSP must
be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control
register and must be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
ADSP-2101/
ADSP2103
TFS
DT
SCLK
DAC104S085
SYNC
DIN
SCLK
Figure 29. ADSP-2101 and ADSP2103 Interface
8.5.3.2 80C51 and 80L51 Interface
Figure 30 shows a serial interface between the DAC104S085 and the 80C51/80L51 microcontroller. The SYNC
signal comes from a bit-programmable pin on the microcontroller. The example shown in Figure 30 uses port line
P3.3. This line is taken low when data is transmitted to the DAC104S085. Because the 80C51 and 80L51
transmits 8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the
P3.3 line must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the
second byte of data, after which port line P3.3 is brought high. The 80C51 and 80L51 transmit routine must
recognize that the 80C51 and 80L51 transmits data with the LSB first while the DAC104S085 requires data with
the MSB first.
80C51/80L51
DAC104S085
P3.3
SYNC
TXD
SCLK
RXD
DIN
Figure 30. 80C51 and 80L51 Interface
8.5.3.3 68HC11 Interface
Figure 31 shows a serial interface between the DAC104S085 and the 68HC11 microcontroller. The SYNC line of
the DAC104S085 is driven from a port line (PC7 in Figure 31), similar to the 80C51/80L51.
The 68HC11 must be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the
second byte of data to the DAC, after which PC7 must be raised to end the write sequence.
68HC11
DAC104S085
PC7
SYNC
SCK
SCLK
MOSI
DIN
Figure 31. 68HC11 Interface
8.5.3.4 Microwire Interface
Figure 32 shows an interface between a Microwire compatible device and the DAC104S085. Data is clocked out
on the rising edges of the SK signal. As a result, the SK of the Microwire device needs to be inverted before
driving the SCLK of the DAC104S085.
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Programming (continued)
MICROWIRE
DEVICE
CS
SYNC
SK
SCLK
SO
DIN
DAC104S085
Figure 32. Microwire Interface
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
While the simplicity of the DAC104S085 implies ease of use, it is important to recognize that the path from the
reference input (VREFIN) to the VOUTs has essentially zero Power Supply Rejection Ratio (PSRR). Therefore, it is
necessary to provide a noise-free supply voltage to VREFIN. To use the full dynamic range of the DAC104S085,
the supply pin (VA) and VREFIN can be connected together and share the same supply voltage. Because the
DAC104S085 consumes very little power, a reference source may be used as the reference input and/or the
supply voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability.
Some low noise regulators can also be used. Listed below are a few reference and power-supply options for the
DAC104S085.
9.1.1 LM4130
The LM4130, with its 0.05% accuracy over temperature, is a good choice as a reference source for the
DAC104S085. The 4.096-V version is useful if a 0 to 4.095-V output range is desirable or acceptable. Bypassing
the LM4130 VIN pin with a 0.1-µF capacitor and the VOUT pin with a 2.2-µF capacitor improves stability and
reduces output noise. The LM4130 comes in a space-saving, 5-pin SOT-23.
Input
Voltage
LM4132-4.1
C3
0.1 PF
C2
2.2 PF
C1
0.1 PF
VA VREFIN
DAC104S085
VOUT = 0V to 4.092V
SYNC
DIN
SCLK
Copyright © 2016, Texas Instruments Incorporated
Figure 33. LM4130 as a Power Supply
9.1.2 LP3985
The LP3985 is a low-noise, ultra-low dropout voltage regulator with a 3% accuracy over temperature. It is a good
choice for applications that do not require a precision reference for the DAC104S085. It comes in 3-V, 3.3-V, and
5-V versions, among others, and sports a low 30-µV noise specification at low frequencies. Because lowfrequency noise is relatively difficult to filter, this specification could be important for some applications. The
LP3985 device comes in a space-saving, 5-pin SOT-23 and 5-bump DSBGA packages.
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Application Information (continued)
Input
Voltage
LP3985
0.1 PF
1 PF
0.01 PF
0.1 PF
VA VREFIN
DAC104S085
VOUT = 0V to 5V
SYNC
DIN
SCLK
Copyright © 2016, Texas Instruments Incorporated
Figure 34. Using the LP3985 Regulator
An input capacitance of 1-µF without any ESR requirement is required at the LP3985 input, while a 1-µF ceramic
capacitor with an ESR requirement of 5 mΩ to 500 mΩ is required at the output. Careful interpretation and
understanding of the capacitor specification is required to ensure correct device operation.
9.1.3 LP2980
The LP2980 is an ultra-low dropout regulator with a 0.5% or 1% accuracy over temperature, depending upon
grade. It is available in 3-V, 3.3-V, and 5-V versions, among others.
Input
Voltage
VIN
VOUT
LP2980
ON /OFF
1 PF
0.1 PF
VA VREFIN
DAC104S085
VOUT = 0V to 5V
SYNC
DIN
SCLK
Copyright © 2016, Texas Instruments Incorporated
Figure 35. Using the LP2980 Regulator
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor
must be at least 1 µF over temperature, but values of 2.2 µF or more provides even better performance. The
ESR of this capacitor should be within the range specified in the LP2980 data sheet (SNOS733). Surface-mount
solid tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due
to their small size, but, generally have ESR values that are too low for use with the LP2980. Aluminum
electrolytic capacitors are typically not a good choice due to their large size and have ESR values that may be
too high at low temperatures.
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9.2 Typical Application
Input
Voltage
R
VZ
IDAC
IZ
0.1 PF
0.47 PF
LM4050-4.1
or
LM4050-5.0
VA VREFIN
DAC104S085
VOUT = 0V to 5V
SYNC
DIN
SCLK
Copyright © 2016, Texas Instruments Incorporated
Figure 36. The LM4050 as a Power Supply
9.2.1 Design Requirements
While the simplicity of the DAC104S085 implies ease of use, it is important to recognize that the path from the
reference input (VREFIN) to the VOUTs has essentially zero Power Supply Rejection Ratio (PSRR). Therefore, it is
necessary to provide a noise-free supply voltage to VREFIN. To use the full dynamic range of the DAC104S085,
the supply pin (VA) and VREFIN can be connected together and share the same supply voltage. Figure 36 uses an
LM4050 as a voltage reference source for the DAC104S085.
9.2.2 Detailed Design Procedure
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the
DAC104S085. It is available in 4.096-V and 5-V versions and comes in a space-saving, 3-pin SOT-23.
The minimum resistor value in the circuit of Figure 36 must be chosen so that the maximum current through the
LM4050 does not exceed its 15-mA rating. The conditions for maximum current include the input voltage at its
maximum, the LM4050 voltage at its minimum, and the DAC104S085 drawing zero current. The maximum
resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum
DAC104S085 current in full operation. The conditions for minimum current include the input voltage at its
minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the
DAC104S085 draws its maximum current. Equation 4 and Equation 5 summerize these conditions.
R(min) = ( VIN(max) − VZ(min) ) /IZ(max)
(4)
and
R(max) = ( VIN(min) − VZ(max) ) / ( (IDAC(max) + IZ(min) )
where
•
•
•
•
VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over
temperature
IZ(max) is the maximum allowable current through the LM4050
IZ(min) is the minimum current required by the LM4050 for proper regulation
IDAC(max) is the maximum DAC104S085 supply current.
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Typical Application (continued)
9.2.3 Application Curves
Figure 37. 5-V Glitch Response
Figure 38. Power-On Reset
10 Power Supply Recommendations
The DAC104S085 power supply should be bypassed with a 10-µF and a 0.1-µF capacitor as close as possible to
the device with the 0.1 µF right at the device supply pin. The 10-µF capacitor should be a tantalum type and the
0.1-µF capacitor must be a low ESL, low ESR type. The power supply for the DAC104S085 must only be used
for analog circuits.
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11 Layout
11.1 Layout Guidelines
For best accuracy and minimum noise, the printed-circuit board containing the DAC104S085 must have separate
analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of
these planes should be located in the same board layer. There must be a single ground plane. A single ground
plane is preferred if digital return current does not flow through the analog ground area. Frequently a single
ground plane design uses a fencing technique to prevent the mixing of analog and digital ground current.
Separate ground planes must only be used when the fencing technique is inadequate. The separate ground
planes must be connected in one place, preferably near the DAC104S085. Special care is required to ensure
that digital signals with fast edge rates do not pass over split ground planes. They must always have a
continuous return path below their traces.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the
board. The clock and data lines must have controlled impedances.
11.2 Layout Example
2 GND
2
GND
3
1 NetC1_1
GND
G
N
D
1
NetC1_1
1 NetC1_1
10
2
3
2
1
NetC1_1
9
11
GND
4
5
8
1 NetC1_1
1
NetC1_1
GND
1 NetC1_1
2
GND
1
1_
1
tC
Ne
1 NetC1_1
Figure 39. DAC104S085 Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
12.1.1.1 Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB, which is VREF / 1024 = VA / 1024.
DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change
in the output of another DAC.
DIGITAL CROSSTALK is the glitch impulse transferred to a DAC output at mid-scale in response to a full-scale
change in the input register of another DAC.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the
data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (3FFh) loaded
into the DAC and the value of VA x 1023 / 1024.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is
Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register
changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line
is measured from the center of that code value. The end point method is used. INL for this product
is specified over a limited range.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is
LSB = VREF / 2n
where
•
where VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 10 for
the DAC104S085.
(6)
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output
stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when
the input code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VA.
MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave
on VREFIN with a full-scale code loaded into the DAC.
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from
the power supply. The difference between the supply and output currents is the power consumed
by the device without a load.
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is
updated.
TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs
with an ideal sine wave applied to VREFIN. THD is measured in dB.
WAKE-UP TIME is the time for the output to exit power-down mode. This is the time from the falling edge of the
16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0V.
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Device Support (continued)
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been
entered.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DAC104S085
Click here
Click here
Click here
Click here
Click here
DAC104S085-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2006–2016, Texas Instruments Incorporated
Product Folder Links: DAC104S085 DAC104S085-Q1
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25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC104S085CIMM/NOPB
ACTIVE
VSSOP
DGS
10
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
X68C
DAC104S085CIMMX/NOPB
ACTIVE
VSSOP
DGS
10
3500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
X68C
DAC104S085CISD/NOPB
ACTIVE
WSON
DSC
10
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
X69C
DAC104S085CISDX/NOPB
ACTIVE
WSON
DSC
10
4500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 105
X69C
DAC104S085QIMM/NOPB
ACTIVE
VSSOP
DGS
10
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
X68Q
DAC104S085QIMMX/NOPB
ACTIVE
VSSOP
DGS
10
3500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
X68Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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