Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
DAC121C081 and DAC121C085 12-Bit Micro Power Digital-to-Analog Converter With an
I2C-Compatible Interface
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
Ensured Monotonicity to 12-Bits
Low Power Operation: 156-µA Maximum at 3.3 V
Extended Power Supply Range (2.7 V to 5.5 V)
I2C-Compatible 2-Wire Interface Which Supports
Standard (100-kHz), Fast (400-kHz), and HighSpeed (3.4-MHz) Modes
Rail-to-Rail Voltage Output
Very Small Package
Resolution: 12 bits
INL: ±8 LSB (Maximum)
DNL: 0.6 / –0.5 LSB (Maximum)
Settling Time: 8.5 µs (Maximum)
Zero Code Error: 10 mV (Maximum)
Full-Scale Error: −0.7%FS (Maximum)
Supply Power
– Normal: 380 µW (3 V) / 730 µW (5 V) (Typical)
– Power Down: 0.5 µW (3 V) / 0.9 µW (5 V)
(Typical)
Industrial Process Control
Portable Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Test Equipment
3 Description
The DAC121C081 is a 12-bit, single-channel,
voltage-output digital-to-analog converter (DAC) that
operates from a 2.7-V to 5.5-V supply. The output
amplifier allows rail-to-rail output swing and has an
8.5-µs settling time. The DAC121C081 uses the
supply voltage as the reference to provide the widest
dynamic output range, and typically consumes 132
µA while operating at 5 V. It is available in 6-pin SOT
and WSON packages, and provides three address
options (pin selectable).
As an alternative, the DAC121C085 provides nine I2C
addressing options and uses an external reference. It
has the same performance and settling time as the
DAC121C081, and is available in an 8-lead VSSOP.
Device Information(1)
PART NUMBER
DAC121C081
DAC121C085
PACKAGE
BODY SIZE (NOM)
WSON (6)
2.20 mm × 2.50 mm
SOT (6)
1.60 mm × 2.90 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
VA*
VREF*
GND
DAC121C081 / DAC121C085
POWER-ON
RESET
REF
DAC
REGISTER
12 BIT DAC
VOUT
BUFFER
12
12
2.5k
100k
POWER-DOWN
CONTROL
LOGIC
2
I C
INTERFACE
* NOTE: ADR1 and VREF are for the DAC121C085 only. The DAC121C085 uses an external
reference (VREF), whereas, the DAC121C081 uses the supply (VA) as the reference.
ADR1* ADR0
SCL
SDA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
1
1
1
2
3
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
AC and Timing Characteristics ................................. 9
Typical Characteristics ............................................ 12
Detailed Description ............................................ 15
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
15
20
8.5 Programming........................................................... 20
8.6 Registers ................................................................. 21
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 24
10 Power Supply Recommendations ..................... 26
10.1 Using References as Power Supplies................... 26
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 29
12 Device and Documentation Support ................. 30
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
31
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (January 2016) to Revision F
Page
•
Changed VOUT and VA descriptions. ....................................................................................................................................... 4
•
Added column to Table 1. ................................................................................................................................................... 19
Changes from Revision D (March 2013) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
•
Added addresses that the DAC responds to on the I2C bus. ............................................................................................. 18
Changes from Revision C (March 2013) to Revision D
•
2
Page
Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 29
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
5 Description (continued)
The DAC121C081 and DAC121C085 use a 2-wire, I2C-compatible serial interface that operates in all three
speed modes, including high-speed mode (3.4 MHz). An external address selection pin allows up to three
DAC121C081 or nine DAC121C085 devices per 2-wire bus. Pin compatible alternatives to the DAC121C081 are
available that provide additional address options.
The DAC121C081 and DAC121C085 each have a 16-bit register that controls the mode of operation, the powerdown condition, and the output voltage. A power-on reset circuit ensures that the DAC output powers up to 0 V.
A power-down feature reduces power consumption to less than a microWatt. Their low power consumption and
small packages make these DACs an excellent choice for use in battery-operated equipment. Each DAC
operates over the extended industrial temperature range of −40°C to +125°C.
The DAC121C081 and DAC121C085 are each part of a family of pin compatible DACs that also provide 8 and
10 bit resolution. For 8-bit DACs see the DAC081C081 and DAC081C085. For 10-bit DACs see the
DAC101C081 and DAC101C085.
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
3
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
6 Pin Configuration and Functions
NGF Package
6-Pins WSON
Top View
ADR0 1
SCL
SDA
6 VOUT
2 WSON 5
3
DDC Package
6-Pin SOT
Top View
4
VOUT
1
VA
2
GND
3
VA
SOT
6
ADR0
5
SCL
4
SDA
GND
DAC121C081
DAC121C081
DGK Package
8-Pins VSSOP
Top View
ADR0
1
ADR1
2
8
VOUT
7
VREF
VSSOP
SCL
3
6
VA
SDA
4
5
GND
DAC121C085
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
WSON
SOT
VSSOP
ADR0
1
6
1
Digital
Tri-state Address Selection Input. Sets the two
Input,
Least Significant Bits (A1 and A0) of the 7-bit
three levels slave address. (see Table 1)
2
Digital
Tri-state Address Selection Input. Sets Bits A6
Input,
and A3 of the 7-bit slave address. (see Table 1)
three levels
ADR1
—
—
GND
4
3
5
SCL
2
5
3
SDA
3
4
4
Ground
EQUIVALENT CIRCUIT
V+
PIN
Snap
Back
Serial Data bi-directional connection. Data is
Digital
clocked into or out of the internal 16-bit register
Input/Outpu relative to the clock edges of SCL. This is an
t
open-drain data line that must be pulled to the
supply (VA) by an external pullup resistor.
—
PIN
Snap
Back
1
8
Analog
Output
Analog Output Voltage
—
VA
5
2
6
Supply
Power supply input. For the SOT and WSON
versions, this supply is used as the reference.
Must be decoupled to GND.
—
VREF
—
—
7
Supply
Unbufferred reference voltage. For the VSSOP,
this supply is used as the reference. VREF must
be free of noise and decoupled to GND.
—
(LLP only)
—
—
Ground
Exposed die attach pad can be connected to
ground or left floating. Soldering the pad to the
PCB offers optimal thermal performance and
enhances package self-alignment during reflow.
—
Submit Documentation Feedback
D1
GND
6
4
41.5k
41.5k
VOUT
PAD
2.1k
GND
Ground for all on-chip circuitry
Serial Clock Input. SCL is used together with SDA
Digital Input to control the transfer of data in and out of the
device.
D1
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN
MAX
UNIT
Supply voltage, VA
–0.3
6.5
V
Voltage on any input pin
–0.3
6.5
V
Input current at any pin (4)
±10
mA
Package input current (4)
±20
mA
Power consumption at TA = 25°C
See
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
(4)
(5)
–65
(5)
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are measured with respect to GND = 0 V, unless otherwise specified.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin should be limited to 10 mA. The 20-mA
maximum package input current ratings limits the number of pins that can safely exceed the power supplies with an input current of 10
mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe
fault condition (for example, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).
7.2 ESD Ratings
VALUE
UNIT
DAC081C081 in NGF Package
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic discharge
All pins except 2 and 3
±2500
Pins 2 and 3
±5000
Charged-device model (CDM), per JEDEC All pins except 2 and 3
specification JESD22-C101
Pins 2 and 3
±1000
All pins except 2 and 3
±250
Pins 2 and 3
±350
All pins except 4 and 5
±2500
Pins 4 and 5
±5000
Machine model (MM)
±1000
V
DAC081C081 in DDC Package
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC All pins except 4 and 5
specification JESD22-C101
Pins 4 and 5
±1000
All pins except 4 and 5
±250
Pins 4 and 5
±350
All pins except 3 and 4
±2500
Pins 3 and 4
±5000
Machine model (MM)
±1000
V
DAC081C085 in DGK Package
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001
V(ESD)
Electrostatic discharge
Charged-device model (CDM), per JEDEC All pins except 3 and 4
specification JESD22-C101
Pins 3 and 4
±1000
All pins except 3 and 4
±250
Pins 3 and 4
±350
Machine model (MM)
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
±1000
Submit Documentation Feedback
V
5
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
−40
125
°C
2.7
5.5
V
Reference voltage, VREFIN
1
VA
V
Digital input voltage (2)
0
5.5
V
Output load
0
1500
pF
Operating temperature, TA
Supply voltage, VA
(1)
(2)
All voltages are measured with respect to GND = 0 V, unless otherwise specified.
The inputs are protected as shown in the following. Input voltage magnitudes up to 5.5 V, regardless of VA, will not cause errors in the
conversion result. For example, if VA is 3 V, the digital input pins can be driven with a 5-V logic device.
7.4 Thermal Information
DAC121C081
THERMAL METRIC
RθJA
(1)
(2)
(3)
6
(1) (2) (3)
Junction-to-ambient thermal resistance
DAC121C085
NGF (WSON)
DDC (SOT)
DGK (VSSOP)
6 PINS
6 PINS
8 PINS
190
250
240
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Soldering process must comply with Texas Instruments' Reflow Temperature Profile Specifications, SNOA549.
Reflow temperature profiles are different for lead-free packages.
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
7.5 Electrical Characteristics
The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, CL = 200 pF to GND, input code range 48 to 4047. All
Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C, unless otherwise specified. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP (2)
MAX (2)
UNIT
STATIC PERFORMANCE
INL
Resolution
12
Monotonicity
12
Bits
Bits
2.2
Integral Non-Linearity
–8
–1.5
–0.5
–0.12
0.18
8
0.6
LSB
LSB
DNL
Differential Non-Linearity
ZE
Zero Code Error
IOUT = 0
1.1
10
FSE
Full-Scale Error
IOUT = 0
–0.1
−0.7
%FSR
GE
Gain Error
All ones Loaded to DAC register
–0.2
−0.7
%FSR
ZCED
Zero Code Error Drift
TC GE
Gain Error Tempco
LSB
mV
–20
µV/°C
VA = 3 V
–0.7
VA = 5 V
–1
ppm
FSR/°C
ANALOG OUTPUT CHARACTERISTICS (VOUT)
Output voltage range (3)
ZCO
Zero code output
FSO
Full scale output
IOS
Output short-circuit current
(ISOURCE)
Output short-circuit current
(ISINK)
IOS
IO
Continuous output current (3)
CL
Maximum load capacitance
ZOUT
DC output impedance
DAC121C085
0
VREF
DAC121C081
0
VA
VA = 3 V, IOUT = 200 µA
1.3
VA = 5 V, IOUT = 200 µA
7
VA = 3 V, IOUT = 200 µA
2.984
VA = 5 V, IOUT = 200 µA
4.989
VA = 3 V, VOUT = 0 V,
Input Code = FFFh.
56
VA = 5 V, VOUT = 0 V,
Input Code = FFFh.
69
VA = 3 V, VOUT = 3 V,
Input Code = 000h.
–52
VA = 5 V, VOUT = 5 V,
Input Code = 000h.
–75
V
mV
V
mA
mA
Available on the DAC output
11
RL = ∞
1500
RL = 2 kΩ
1500
mA
pF
Ω
7.5
REFERENCE INPUT CHARACTERISTICS (DAC121C085 only)
Input range minimum
VREF
1
0.2
Input range maximum
V
VA
Input impedance
120
V
kΩ
LOGIC INPUT CHARACTERISTICS (SCL, SDA)
VIH
Input high voltage
VIL
Input low voltage
IIN
Input current
CIN
Input pin capacitance (3)
VHYST
Input hysteresis
0.7 × VA
V
0.3 × VA
V
±1
µA
3
pF
0.1 × VA
V
VA- 0.5
V
LOGIC INPUT CHARACTERISTICS (ADR0, ADR1)
VIH
(1)
(2)
(3)
Input high voltage
Values shown in this table are design targets and are subject to change before product release.
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing
Quality Level).
This parameter is specified by design and/or characterization and is not tested in production.
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
7
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
Electrical Characteristics (continued)
The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, CL = 200 pF to GND, input code range 48 to 4047. All
Maximum and Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C, unless otherwise specified.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP (2)
MAX (2)
UNIT
VIL
Input low voltage
0.5
V
IIN
Input current
±1
µA
LOGIC OUTPUT CHARACTERISTICS (SDA)
VOL
Output low voltage
IOZ
High-impedence output leakage
current
ISINK = 3 mA
0.4
ISINK = 6 mA
0.6
±1
V
µA
POWER REQUIREMENTS
Supply voltage minimum
VA
2.7
Supply voltage maximum
5.5
V
Normal -- VOUT set to midscale. 2-wire interface quiet (SCL = SDA = VA). (output unloaded)
VA = 2.7 V to 3.6 V
105
156
VA = 4.5 V to 5.5 V
132
214
VA = 2.7 V to 3.6 V
86
118
VA = 4.5 V to 5.5 V
98
152
VREF supply current
(DAC121C085 only)
VA = 2.7 V to 3.6 V
37
43
VA = 4.5 V to 5.5 V
53
61
Power consumption
(VA and VREF for
DAC121C085) (4)
VA = 3 V
380
VA = 5 V
730
IST_VA-1
VADAC121C081 supply current
IST_VA-5
VADAC121C085 supply current
IST_VREF
PST
µA
µA
µA
µW
Continuous Operation -- 2-wire interface actively addressing the DAC and writing to the DAC register. (output unloaded)
fSCL=400 kHz
ICO_VA-1
VADAC121C081 supply current
fSCL = 3.4 MHz
fSCL = 400 kHz
ICO_VA-5
VADAC121C085 supply current
fSCL = 3.4 MHz
ICO_VREF
VREF supply current
(DAC121C085 only)
PCO
Power consumption
(VA and VREF for DAC121C085)
fSCL = 400 kHz
fSCL = 3.4 MHz
VA = 2.7 V to 3.6 V
134
220
VA = 4.5 V to 5.5 V
192
300
VA = 2.7 V to 3.6 V
225
320
VA = 4.5 V to 5.5 V
374
500
VA = 2.7 V to 3.6 V
101
155
VA = 4.5 V to 5.5 V
142
220
VA = 2.7 V to 3.6 V
193
235
VA = 4.5 V to 5.5 V
325
410
VA = 2.7 V to 3.6 V
33.5
55
VA = 4.5 V to 5.5 V
49.5
71.4
µA
µA
µA
µA
µA
VA = 3 V
480
µW
VA = 5 V
1.06
mW
VA = 3 V
810
µW
VA = 5 V
2.06
mW
Power Down -- 2-wire interface quiet (SCL = SDA = VA) after PD mode written to DAC register. (output unloaded)
IPD
Supply current
All power-down
(VA and VREF for DAC121C085) modes
VA = 2.7 V to 3.6
0.13
1.52
VA = 4.5 V to 5.5 V
0.15
3.25
PPD
Power consumption
All power-down
(VA and VREF for DAC121C085) modes
VA = 3 V
0.5
VA = 5 V
0.9
(4)
8
µA
µW
To ensure accuracy, it is required that VA and VREF be well bypassed.
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
7.6 AC and Timing Characteristics
The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, RL = Infinity, CL = 200 pF to GND. All Maximum and
Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C, unless otherwise specified. (1)
TEST CONDITIONS (2)
PARAMETER
ts
Output Voltage Settling Time (4)
SR
Output Slew Rate
Glitch Impulse
MIN
400h to C00h code change
RL = 2 kΩ, CL = 200 pF
Code change from 800h to 7FFh
Digital Feedthrough
Multiplying Bandwidth
(5)
Total Harmonic Distortion
tWU
VREF = 2.5 V ± 0.1 Vpp
(5)
Wake-Up Time
TYP (3)
MAX (2) (3)
6
8.5
UNIT
µs
1
V/µs
12
nV-sec
0.5
nV-sec
160
kHz
VREF = 2.5 V ± 0.1 Vpp
input frequency = 10 kHz
70
dB
VA = 3 V
0.8
µs
VA = 5 V
0.5
µs
DIGITAL TIMING SPECS (SCL, SDA)
fSCL
Serial Clock Frequency
tLOW
SCL Low Time
Standard Mode
100
Fast Mode
400
High Speed Mode, Cb = 100 pF
3.4
High Speed Mode, Cb = 400 pF
1.7
Standard Mode
4.7
Fast Mode
1.3
High Speed Mode, Cb = 100 pF
160
High Speed Mode, Cb = 400 pF
320
Standard Mode
tHIGH
tSU;DAT
SCL High Time
Data Setup Time
0.6
High Speed Mode, Cb = 100 pF
60
High Speed Mode, Cb = 400 pF
120
Standard Mode
250
Fast Mode
100
High Speed Mode
tHD;DAT
tSU;STA
Data Hold Time
Setup time for a start or a
repeated start condition
tHD;STA
Hold time for a start or a
repeated start condition
tBUF
Bus free time between a stop
and start condition
tSU;STO
Setup time for a stop condition
(4)
(5)
µs
ns
ns
10
0
3.45
Fast Mode
0
0.9
High Speed Mode, Cb = 100 pF
0
70
High Speed Mode, Cb = 400 pF
0
150
Standard Mode
4.7
Fast Mode
0.6
High Speed Mode
160
4
Fast Mode
0.6
High Speed Mode
160
Standard Mode
4.7
Fast Mode
1.3
Standard Mode
(1)
(2)
(3)
ns
Standard Mode
Standard Mode
MHz
µs
4
Fast Mode
kHz
4
Fast Mode
0.6
High Speed Mode
160
µs
ns
µs
ns
µs
ns
µs
µs
ns
Values shown in this table are design targets and are subject to change before product release.
Cb refers to the capacitance of one bus line. Cb is expressed in pF units.
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing
Quality Level).
This parameter is specified by design and/or characterization and is not tested in production.
Applies to the Multiplying DAC configuration. In this configuration, the reference is used as the analog input. The value loaded in the
DAC Register will digitally attenuate the signal at Vout.
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
9
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
AC and Timing Characteristics (continued)
The following specifications apply for VA = 2.7 V to 5.5 V, VREF = VA, RL = Infinity, CL = 200 pF to GND. All Maximum and
Minimum limits apply for TMIN ≤ TA ≤ TMAX and all Typical limits are at TA = 25°C, unless otherwise specified.(1)
PARAMETER
TEST CONDITIONS (2)
MIN
TYP (3)
Standard Mode
trDA
Rise time of SDA signal
Fast Mode
20+0.1Cb
300
High Speed Mode, Cb = 100 pF
10
80
High Speed Mode, Cb = 400 pF
20
160
Fall time of SDA signal
Fast Mode
250
High Speed Mode, Cb = 100 pF
10
80
High Speed Mode, Cb = 400 pF
20
160
Standard Mode
trCL
Rise time of SCL signal
300
High Speed Mode, Cb = 100 pF
10
40
High Speed Mode, Cb = 400 pF
20
Rise time of SCL signal after a
Fast Mode
repeated start condition and after
High Speed Mode, Cb = 100 pF
an acknowledge bit.
High Speed Mode, Cb = 400 pF
80
20+0.1Cb
300
10
80
20
160
300
High Speed Mode, Cb = 100 pF
10
40
High Speed Mode, Cb = 400 pF
20
80
Fall time of a SCL signal
Cb
Capacitive load for each bus line
(SCL and SDA)
tSP
Pulse Width of spike
suppressed (6) (4)
Fast Mode
50
High Speed Mode
10
SDA output delay (see the
Additional Timing Information
section)
Fast Mode
87
270
toutz
High Speed Mode
38
60
10
ns
300
20+0.1Cb
tfCL
(6)
ns
1000
Standard Mode
Fast Mode
ns
1000
20+0.1Cb
Standard Mode
trCL1
ns
250
20+0.1Cb
Fast Mode
UNIT
1000
Standard Mode
tfDA
MAX (2) (3)
400
ns
pF
ns
ns
Spike suppression filtering on SCL and SDA will supress spikes that are less than 50 ns for standard-fast mode and less than 10ns for
hs-mode.
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
FSE
4095 x VREF
4096
GE = FSE - ZE
FSE = GE + ZE
OUTPUT
VOLTAGE
ZE
0
0
4095
DIGITAL INPUT CODE
Figure 1. Input / Output Transfer Characteristic
SDA
tLOW
tf
tr
tHD;STA
tr
tf
tBUF
tSP
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
tSU;DAT
REPEATED
START
START
tSU;STO
STOP
START
Figure 2. Serial Timing Diagram
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
11
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
7.7 Typical Characteristics
VREF = VA, fSCL = 3.4 MHz, TA = 25°C, Input Code Range 48 to 4047, unless otherwise stated.
12
Figure 3. INL
Figure 4. DNL
Figure 5. INL/DNL vs Temperature at VA = 3 V
Figure 6. INL/DNL vs Temperature at VA = 5 V
Figure 7. INL/DNL vs VREFIN at VA = 3 V
Figure 8. INL/DNL vs VREFIN at VA = 5 V
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
Typical Characteristics (continued)
VREF = VA, fSCL = 3.4 MHz, TA = 25°C, Input Code Range 48 to 4047, unless otherwise stated.
Figure 9. INL/DNL vs VA
Figure 10. Zero Code Error vs VA
Figure 11. Zero Code Error vs Temperature
Figure 12. Full Scale Error vs VA
Figure 13. Full Scale Error vs Temperature
Figure 14. Total Supply Current vs VA
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
13
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
Typical Characteristics (continued)
VREF = VA, fSCL = 3.4 MHz, TA = 25°C, Input Code Range 48 to 4047, unless otherwise stated.
Figure 15. VREF Supply Current vs VA
Figure 16. Total Supply Current vs Temperature at VA = 3 V
Figure 17. Total Supply Current vs Temperature at VA = 5 V
Figure 18. 5-V Glitch Response
Figure 19. Power-On Reset
14
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
8 Detailed Description
8.1 Overview
The DAC121C081 is fabricated on a CMOS process with an architecture that consists of switches and resistor
strings that are followed by an output buffer.
8.2 Functional Block Diagram
VA*
VREF*
GND
DAC121C081 / DAC121C085
POWER-ON
RESET
REF
DAC
REGISTER
12 BIT DAC
VOUT
BUFFER
12
12
2.5k
100k
POWER-DOWN
CONTROL
LOGIC
2
I C
INTERFACE
* NOTE: ADR1 and VREF are for the DAC121C085 only. The DAC121C085 uses an external
reference (VREF), whereas, the DAC121C081 uses the supply (VA) as the reference.
ADR1* ADR0
SCL
SDA
8.3 Feature Description
8.3.1 DAC Section
The DAC121C081 is fabricated on a CMOS process with an architecture that consists of switches and resistor
strings that are followed by an output buffer.
For simplicity, a single resistor string is shown in Figure 20. This string consists of 4096 equal valued resistors
with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register
determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight
binary with an ideal output voltage of:
VOUT = VREF × (D / 4096)
where D is the decimal equivalent of the binary code that is loaded into the DAC register.
(1)
D can take on any integer value from 0 to 4095. This configuration ensures that the DAC is monotonic.
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
15
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
Feature Description (continued)
VREF
R
R
R
To Output Amplifier
R
R
Figure 20. DAC Resistor String
8.3.2 Output Amplifier
The output amplifier is rail-to-rail, providing an output voltage range of 0 V to VA when the reference is VA. All
amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and VA,
in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the
reference is less than VA, there is only a loss in linearity in the lowest codes. The output capabilities of the
amplifier are described in the Electrical Characteristics.
The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or to VA. The zerocode and full-scale outputs for given load currents are available in the Electrical Characteristics.
8.3.3 Reference Voltage
The DAC121C081 uses the supply (VA) as the reference. With that said, VA must be treated as a reference. The
analog output is only as clean as the reference (VA). TI recommends driving the reference with a voltage source
with low-output impedance.
The DAC121C085 comes with an external reference supply pin (VREF). For the DAC121C085, it is important that
VREF be kept as clean as possible.
Applications Information describes a handful of ways to drive the reference appropriately. See Using References
as Power Supplies for details.
16
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
Feature Description (continued)
8.3.4 Serial Interface
The I2C-compatible interface operates in all three speed modes. Standard mode (100 kHz) and Fast mode (400
kHz) are functionally the same and will be referred to as Standard-Fast mode in this document. High-Speed
mode (3.4MHz) is an extension of Standard-Fast mode and will be referred to as Hs-mode in this document. The
following diagrams describe the timing relationships of the clock (SCL) and data (SDA) signals. Pullup resistors
or current sources are required on the SCL and SDA busses to pull them high when they are not being driven
low. A logic zero is transmitted by driving the output low. A logic high is transmitted by releasing the output and
allowing it to be pulled up externally. The appropriate pullup resistor values depends on the total bus capacitance
and operating speed.
8.3.4.1 Basic I2C Protocol
The I2C interface is bi-directional and allows multiple devices to operate on the same bus. To facilitate this bus
configuration, each device has a unique hardware address which is referred to as the slave address. To
communicate with a particular device on the bus, the controller (master) sends the slave address and listens for
a response from the slave. This response is referred to as an acknowledge bit. If a slave on the bus is addressed
correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't match a
device's slave address, it Not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs also occur
on the bus when data is being transmitted. When the master is writing data, the slave ACKs after every data byte
is successfully received. When the master is reading data, the master ACKs after every data byte is received to
let the slave know it wants to receive another data byte. When the master wants to stop reading, it NACKs after
the last data byte and creates a Stop condition on the bus.
All communication on the bus begins with either a Start condition or a Repeated Start condition. The protocol for
starting the bus varies between Standard-Fast mode and Hs-mode. In Standard-Fast mode, the master
generates a Start condition by driving SDA from high to low while SCL is high. In Hs-mode, starting the bus is
more complicated. See High-Speed (Hs) Mode for the full details of a Hs-mode Start condition. A Repeated Start
is generated to either address a different device, or switch between read and write modes. The master generates
a Repeated Start condition by driving SDA low while SCL is high. Following the Repeated Start, the master
sends out the slave address and a read/write bit as shown in Figure 21. The bus continues to operate in the
same speed mode as before the Repeated Start condition.
All communication on the bus ends with a Stop condition. In either Standard-Fast mode or Hs-Mode, a Stop
condition occurs when SDA is pulled from low to high while SCL is high. After a Stop condition, the bus remains
idle until a master generates a Start condition.
See the Phillips I2C® Specification (Version 2.1 Jan, 2000) for a detailed description of the serial interface.
SDA
1
2
6
MSB
R/W
Direction
Bit
Acknowledge
from the Device
7-bit Slave Address
SCL
ACK
LSB
MSB
7
8
9
LSB
N/ACK
Data Byte
*Acknowledge
or Not-ACK
1
2
8
Repeated for the Lower Data Byte
and Additional Data Transfers
START or
REPEATED
START
9
STOP
*Note: In continuous mode, this bit must be an ACK from
the data receiver. Immediately preceding a STOP
condition, this bit must be a NACK from the master.
Figure 21. Basic Operation
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
17
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
Feature Description (continued)
8.3.4.2 Standard-Fast Mode
In Standard-Fast mode, the master generates a start condition by driving SDA from high to low while SCL is
high. The Start condition is always followed by a 7-bit slave address and a Read/Write bit. After these eight bits
have been transmitted by the master, SDA is released by the master and the DAC121C081 either ACKs or
NACKs the address. If the slave address matches, the DAC121C081 ACKs the master. If the address doesn't
match, the DAC121C081 NACKs the master.
For a write operation, the master follows the ACK by sending the upper eight data bits to the DAC121C081.
Then the DAC121C081 ACKs the transfer by driving SDA low. Next, the lower eight data bits are sent by the
master. The DAC121C081 then ACKs the transfer. At this point, the DAC output updates to reflect the contents
of the 16-bit DAC register. Next, the master either sends another pair of data bytes, generates a Stop condition
to end communication, or generates a Repeated Start condition to communicate with another device on the bus.
For a read operation, the DAC121C081 sends out the upper eight data bits of the DAC register. This is followed
by an ACK by the master. Next, the lower eight data bits of the DAC register are sent to the master. The master
then produces a NACK by letting SDA be pulled high. The NACK is followed by a master-generated Stop
condition to end communication on the bus, or a Repeated Start to communicate with another device on the bus.
8.3.4.3 High-Speed (Hs) Mode
For Hs-mode, the sequence of events to begin communication differ slightly from Standard-Fast mode. Figure 22
describes this in further detail. Initially, the bus begins running in Standard-Fast mode. The master generates a
Start condition and sends the 8-bit Hs master code (00001XXX) to the DAC121C081. Next, the DAC121C081
responds with a NACK. Once the SCL line has been pulled to a high level, the master switches to Hs-mode by
increasing the bus speed and generating a Repeated Start condition (driving SDA low while SCL is pulled high).
At this point, the master sends the slave address to the DAC121C081, and communication continues as shown
in Figure 21.
When the master generates a Repeated Start condition while in Hs-mode, the bus stays in Hs-mode awaiting the
slave address from the master. The bus continues to run in Hs-mode until a Stop condition is generated by the
master. When the master generates a Stop condition on the bus, the bus must be started in Standard-Fast mode
again before increasing the bus speed and switching to Hs-mode. ns16705
SDA
NACK
MSB
8-ELW 0DVWHU FRGH ³00001[[[´
7-bit Slave
Address
Not-Acknowledge
from the Device
1
SCL
2
5
6
7
8
9
1
2
Repeated
START
START
Standard-Fast Mode
Hs-Mode
Figure 22. Beginning Hs-Mode Communication
8.3.4.4 I2C Slave (Hardware) Address
The DAC has a seven-bit I2C slave address. For the VSSOP version of the DAC, this address is configured by
the ADR0 and ADR1 address selection inputs. For the DAC121C081, the address is configured by the ADR0
address selection input. ADR0 and ADR1 can be grounded, left floating, or tied to VA. If desired, the address
selection inputs can be set to VA/2 rather than left floating. The state of these inputs sets the address the DAC
responds to on the I2C bus (see Table 1). In addition to the selectable slave address, there is also a broadcast
address (1001000) for all DAC121C081's and DAC121C085's on the 2-wire bus. When the bus is addressed by
the broadcast address, all the DAC121C081's and DAC121C085's will respond and update synchronously.
Figure 24 and Figure 25 describe how the master device should address the DAC through the I2C-Compatible
interface.
18
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
Feature Description (continued)
Keep in mind that the address selection inputs (ADR0 and ADR1) are only sampled until the DAC is correctly
addressed with a non-broadcast address. At this point, the ADR0 and ADR1 inputs TRI-STATE and the slave
address is locked. Changes to ADR0 and ADR1 will not update the selected slave address until the device is
power-cycled.
Table 1. Slave Addresses
Slave Address
[A6 - A0]
DAC121C081 (SOT
AND WSON) (1)
Do Not Use (2)
ADR1
ADR0
ADR0
0001100
Floating
Floating
Floating
1000110
0001101
Floating
GND
GND
1000110
0001110
Floating
VA
VA
1000111
0001000
GND
Floating
---------------
1000100
0001001
GND
GND
---------------
1000100
0001010
GND
VA
---------------
1000101
1001100
VA
Floating
---------------
1100110
1001101
VA
GND
---------------
1100110
1001110
VA
VA
---------------
1100111
1001000
(1)
(2)
DAC121C085 (VSSOP)
--------------- Broadcast Address ---------------
1100100
Pin-compatible alternatives to the DAC121C081 options are available with additional address options.
These addresses should not be used by other I2C devices on the I2C bus. Using these addresses can cause the DAC121C081/085 to
not respond when addressed by the assigned Slave Address.
8.3.5 Power-On Reset
The power-on reset circuit controls the output voltage of the DAC during power up. Upon application of power,
the DAC register is filled with zeros and the output voltage is 0 V. The output remains at 0 V until a valid write
sequence is made to the DAC.
When resetting the device, it is crutial that the VA supply be lowered to a maximum of 200 mV before the supply
is raised again to power up the device. Dropping the supply to within 200 mV of GND during a reset will ensure
the ADC performs as specified.
8.3.6 Simultaneous Reset
The broadcast address allows the I2C master to write a single word to multiple DACs simultaneously. Provided
that all of the DACs exist on a single I2C bus, every DAC updates when the broadcast address is used to
address the bus. This feature allows the master to reset all of the DACs on a shared I2C bus to a specific digital
code. For instance, if the master writes a power-down code to the bus with the broadcast address, all of the
DACs powers down simultaneously.
8.3.7 Additional Timing Information: toutz
The toutz specification is provided to aid the design of the I2C bus. After the SCL bus is driven low by the I2C
master, the SDA bus will be held for a short time by the DAC121C081. This time is referred to as toutz. The
following figure illustrates the relationship between the fall of SCL, at the 30% threshold, to the time when the
DAC begins to transition the SDA bus. The toutz specification only applies when the DAC is in control of the SDA
bus. The DAC is only in control of the bus during an ACK by the DAC121C081 or a data byte read from the DAC
(see Figure 25).
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
19
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
SCL
SDA
toutz
Figure 23. Data Output Timing
The toutz specification is typically 87 ns in Standard-Fast Mode and 38 ns in Hs-Mode.
8.4 Device Functional Modes
8.4.1 Power-Down Modes
The DAC121C081 has three power-down modes. In power-down mode, the supply current drops to 0.13 µA at 3
V and 0.15 µA at 5 V (typical). The DAC121C081 is put into power-down mode by writing a one to PD1 and/or
PD0. The outputs can be set to high impedance, terminated by 2.5 kΩ to GND, or terminated by 100 kΩ to GND
(see Figure 26).
The bias generator, output amplifier, resistor string, and other linear circuitry are all shut down in any of the
power-down modes. When the DAC121C081 is powered down, the value written to the DAC register, including
the power-down bits, is saved. While the DAC is in power-down, the saved DAC register contents can be read
back. When the DAC is brought out of power-down mode, the DAC register contents will be overwritten and VOUT
will be updated with the new 12-bit data value.
The time to exit power-down (Wake-Up Time) is typically 0.8 µs at 3 V and 0.5 µs at 5 V.
8.5 Programming
8.5.1 Writing to the DAC Register
To write to the DAC, the master addresses the part with the correct slave address (A6-A0) and writes a zero to
the read/write bit. If addressed correctly, the DAC returns an ACK to the master. The master then sends out the
upper data byte. The DAC responds by sending an ACK to the master. Next, the master sends the lower data
byte to the DAC. The DAC responds by sending an ACK again. At this point, the master either sends the upper
byte of the next data word to be converted by the DAC, generates a Stop condition to end communication, or
generates a Repeated Start condition to begin communication with another device on the bus. Until generating a
Stop condition, the master can continuously write the upper and lower data bytes to the DAC register. This
allows for a maximum DAC conversion rate of 188.9 kilo-conversions per second in Hs-mode.
1
9
1
9
1
9
SCL
SDA
A6
Start by
Master
A5
A4
A3
A2
A1
A0 R/W
0
ACK
by
DAC121C081
Frame 1
Address Byte
from Master
0
PD1 PD0 D11 D10 D9
Frame 2
Data Byte from
Master
D7
ACK
by
DAC121C081
D8
D6
D5
D4
D3
D2
Frame 3
Data Byte from
Master
D1
D0
ACK Stop by
by
Master
DAC121C081
Repeat Frames
2 & 3 for
Continuous Mode
Figure 24. Typical Write to the DAC Register
20
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
Programming (continued)
8.5.2 Reading from the DAC Register
To read from the DAC register, the master addresses the part with the correct slave address (A6-A0) and writes
a one to the read/write bit. If addressed correctly, the DAC returns an ACK to the master. Next, the DAC sends
out the upper data byte. The master responds by sending an ACK to the DAC to indicate that it wants to receive
another data byte. Then the DAC sends the lower data byte to the master. Assuming only one 16-bit data word is
read, the master sends a NACK after receiving the lower data byte. At this point, the master either generates a
Stop condition to end communication, or a Repeated Start condition to begin communication with another device
on the bus.
1
9
1
9
1
9
SCL
SDA
A6
A5
A4
A3
A2
A1
A0 R/W
0
ACK
by
DAC121C081
Start by
Master
Frame 1
Address Byte
from Master
0
PD1 PD0 D11 D10 D9
Frame 2
Data Byte from
DAC121C081
D8
D7
D6
D5
ACK
by
Master
D4
D3
D2
Frame 3
Data Byte from
DAC121C081
D1
D0
NACK
by
Master
Stop by
Master
Figure 25. Typical Read from the DAC Register
8.6 Registers
8.6.1 DAC Register
The DAC register, Figure 26, has sixteen bits. The first two bits are always zero. The next two bits determine the
mode of operation (normal mode or one of three power-down modes). The final twelve bits of the shift register
are the data bits. The data format is straight binary (MSB first, LSB last), with twelve 0s corresponding to an
output of 0 V and twelve 1s corresponding to a full-scale output of VA – 1 LSB. When writing to the DAC
Register, VOUT will update on the rising edge of the ACK following the lower data byte.
LSB
MSB
X
X PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
0
0
1
1
0
1
0
1
Normal Operation.
2.5kÖ to GND.
100kÖ to GND.
High Impedance.
Power-Down Modes
Figure 26. DAC Register Contents
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
21
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Bipolar Operation
The DAC121C081 is designed for single supply operation and thus has a unipolar output. However, a bipolar
output may be obtained with the circuit in Figure 27. This circuit provides an output voltage range of ±5 V. A railto-rail amplifier should be used if the amplifier supplies are limited to ±5 V.
10 pF
R2
+5V
R1
+5V
10 PF
+
-
0.1 PF
±5V
+
DAC121C081
SDA
-5V
VOUT
SCL
Figure 27. Bipolar Operation
The output voltage of this circuit for any code is found to be, as shown in Equation 2:
VO = (VA × (D / 4096) × ((R1 + R2) / R1) – VA × R2 / R1)
where D is the input code in decimal form.
(2)
Equation 3 shows that with VA = 5 V and R1 = R2,
VO = (10 × D / 4096) – 5 V
(3)
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.
Table 2. Some Rail-to-Rail Amplifiers
22
AMP
PKGS
LMP7701
SOT-23
37 uV
LMV841
SC70-5
50 uV
1 mA
LMC7111
SOT-23
0.9 mV
25 µA
LM7301
SO-8, SOT-23
0.03 mV
620 µA
LM8261
SOT-23
0.7 mV
1 mA
Submit Documentation Feedback
Typ VOS
Typ ISUPPLY
0.79 mA
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
9.1.2 DSP/Microprocessor Interfacing
Interfacing the DAC121C081 to microprocessors and DSPs is quite simple. The following guidelines are offered
to simplify the design process.
9.1.2.1 Interfacing to the 2-wire Bus
Figure 28 shows a microcontroller interfacing to the DAC121C081 through the 2-wire bus. Pullup resistors (Rp)
should be chosen to create an appropriate bus rise time and to limit the current that will be sunk by the opendrain outputs of the devices on the bus. See the I2C® Specification for further details. Typical pullup values to use
in Standard-Fast mode bus applications are 2 kΩ to 10 kΩ. SCL and SDA series resisters (RS) near the
DAC121C081 are optional. If high-voltage spikes are expected on the 2-wire bus, series resistors should be used
to filter the voltage on SDA and SCL. The value of the series resistance must be picked to ensure the VIL
threshold can be achieved. If used, RS is typically 51 Ω.
DAC121C081/5
10 PF
VREF
4.7 PF
VA
0.1 PF
Regulated Supply
RP RP
VDD
uController
R S*
SDA
SDA
SCL
SCL
R S*
ADC121C021
SDA
SCL
I2C Device
SDA
SCL
*NOTE: RS is optional.
Figure 28. Serial Interface Connection Diagram
9.1.2.2 Interfacing to a Hs-mode Bus
Interfacing to a Hs-mode bus is very similar to interfacing to a Standard-Fast mode bus. In Hs-mode, the
specified rise time of SCL is shortened. To create a faster rise time, the master device (microcontroller) can drive
the SCL bus high and low. In other words, the microcontroller can drive the line high rather than leaving it to the
pullup resistor. It is also possible to decrease the value of the pullup resistors or increase the pullup current to
meet the tighter timing specs. See the I2C® Specification for further details.
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
23
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
9.2 Typical Application
2
4 SDA
VA
1
VOUT
DAC121C081CIMK
5 SCL
6 ADR0
+5
120pF
+5
LM4132-3.3
4
5
3
2
3
+
.1uF
1uF
5
1
A2
4
3
-
.2uF
2
180
+5
+3.3
100K
1
2
470pF
+IN
9
10
VREF
VA
VIO
ADC161S626
AV = 100
2.02K
3
-IN
8
SCLK
7
DOUT
6
/CS
4,5
+5
.2uF
100K
3
-
5
1
A1
Pressure
Sensor
0.2mV/Volt/PSI
4
470pF
180
+
2
A1 and A2 = LMP7701
Figure 29. Pressure Sensor Gain Adjust
9.2.1 Design Requirements
A positive supply only data acquisition system capable of digitizing a pressure sensor output. In addition to
digitizing the pressure sensor output, the system designer can use the DAC121C081 to correct for gain errors in
the pressure sensor output by adjusting the bias voltage to the bridge pressure sensor.
9.2.2 Detailed Design Procedure
As shown in Equation 4, the output of the pressure sensor is relative to the imbalance of the resistive bridge
times the output of the DAC121C081, thus providing the desired gain correction.
Pressure Sensor Output = (DAC_Output × [(R2 / (R1 + R2) – (R4 / (R3 + R4)]
(4)
Likewise for the ADC161S626, Equation 5 shows that the ADC output is function of the Pressure Sensor Output
times relative to the ratio of the ADC input divided by the DAC121C081 output voltage.
ADC161S626 Output = (Pressure Sensor Output × 100 /(2 × VREF) ) × 216
24
Submit Documentation Feedback
(5)
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
Typical Application (continued)
9.2.3 Application Curve
Figure 30. INL vs Input Code
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
25
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
10 Power Supply Recommendations
10.1 Using References as Power Supplies
While the simplicity of the DAC121C081 implies ease of use, it is important to recognize that the path from the
reference input (VA for the DAC121C081 and VREF for the DAC121C085) to VOUT will have essentially zero
Power Supply Rejection Ratio (PSRR). Therefore, it is necessary to provide a noise-free supply voltage to the
reference. To use the full dynamic range of the DAC121C085, the supply pin (VA) and VREF can be connected
together and share the same supply voltage. Because the DAC121C081 consumes very little power, a reference
source may be used as the supply voltage. The advantages of using a reference source over a voltage regulator
are accuracy and stability. Some low noise regulators can also be used. Listed below are a few reference and
power supply options for the DAC121C081. When using the DAC121C081, it is important to treat the analog
supply (VA) as the reference.
10.1.1 LM4132
The LM4132, with its 0.05% accuracy over temperature, is a good choice as a reference source for the
DAC121C081. The 4.096-V version is useful if a 0-V to 4.095-V output range is desirable or acceptable.
Bypassing the LM4132 VIN pin with a 0.1-µF capacitor and the VOUT pin with a 2.2-µF capacitor improves stability
and reduces output noise. The LM4132 comes in a space-saving 5-pin SOT-23.
Input
Voltage
LM4132-4.1
C2
2.2 PF
C1
0.1 PF
C3
0.1 PF
VA VREF
DAC121C081/5
VOUT = 0V to 4.092V
SDA
SCL
Figure 31. The LM4132 as a Power Supply
10.1.2 LM4050
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the
DAC121C081. It is available in 4.096-V and 5-V versions and comes in a space-saving, 3-pin SOT-23.
Input
Voltage
R
IDAC
VZ
IZ
0.1 PF
0.47 PF
LM4050-4.1
or
LM4050-5.0
VA VREF
DAC121C081/5
VOUT = 0V to 5V
SDA
SCL
Figure 32. The LM4050 as a Power Supply
26
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
Using References as Power Supplies (continued)
The minimum resistor value in the circuit of Figure 32 must be chosen such that the maximum current through
the LM4050 does not exceed its 15-mA rating. The conditions for maximum current include the input voltage at
its maximum, the LM4050 voltage at its minimum, and the DAC121C081 drawing zero current. The maximum
resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum
DAC121C081 current in full operation. The conditions for minimum current include the input voltage at its
minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the
DAC121C081 draws its maximum current. These conditions can be summarized as
R(min) = ( VIN(max) − VZ(min) ) / IZ(max)
where
•
•
VZ(min) is the nominal LM4050 output voltage ± the LM4050 output tolerance over temperature.
IZ(max) is the maximum allowable current through the LM4050.
(6)
and
R(max) = ( VIN(min) − VZ(max) ) / ( (IDAC(max) + IZ(min) )
where
•
•
•
VZ(max) is the nominal LM4050 output voltage ± the LM4050 output tolerance over temperature.
IDAC(max) is the maximum DAC121C081 supply current.
IZ(min) is the minimum current required by the LM4050 for proper regulation.
(7)
10.1.3 LP3985
The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good
choice for applications that do not require a precision reference for the DAC121C081. It comes in 3-V, 3.3-V and
5-V versions, among others, and sports a low 30-µV noise specification at low frequencies. Because lowfrequency noise is relatively difficult to filter, this specification could be important for some applications. The
LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages.
Input
Voltage
LP3985
0.1 PF
1 PF
0.01 PF
0.1 PF
VA
VREF
DAC121C081/5
VOUT = 0V to 5V
SDA
SCL
Figure 33. Using the LP3985 Regulator
An input capacitance of 1 µF without any ESR requirement is required at the LP3985 input, while a 1-µF ceramic
capacitor with an ESR requirement of 5 mΩ to 500 mΩ is required at the output. Careful interpretation and
understanding of the capacitor specification is required to ensure correct device operation.
10.1.4 LP2980
The LP2980 is an ultra low dropout regulator with a 0.5% or 1% accuracy over temperature, depending upon
grade. It is available in 3-V, 3.3-V, and 5-V versions, among others.
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
27
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
Using References as Power Supplies (continued)
Input
Voltage
VIN
VOUT
LP2980
ON /OFF
1 PF
0.1 PF
VA VREF
DAC121C081/5
VOUT = 0V to 5V
SDA
SCL
Figure 34. Using the LP2980 Regulator
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor
must be at least 1-µF over temperature, but values of 2.2 µF or more will provide even better performance. The
ESR of this capacitor should be within the range specified in the LP2980 (SNOS733) data sheet. Surface-mount
solid tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due
to their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic
capacitors are typically not a good choice due to their large size and have ESR values that may be too high at
low temperatures.
28
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
11 Layout
11.1 Layout Guidelines
For best accuracy and minimum noise, the printed-circuit board containing the DAC121C081 should have
separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.
Both of these planes should be located on the same board layer. There should be a single ground plane. A
single ground plane is preferred if digital return current does not flow through the analog ground area. Frequently
a single ground plane design uses a fencing technique to prevent the mixing of analog and digital ground current.
Separate ground planes should only be used when the fencing technique is inadequate. The separate ground
planes must be connected in one place, preferably near the DAC121C081. Special care is required to ensure
that digital signals with fast edge rates do not pass over split ground planes. They must always have a
continuous return path below their traces.
The DAC121C081 power supply should be bypassed with a 4.7-µF and a 0.1-µF capacitor as close as possible
to the device with the 0.1 µF right at the device supply pin. The 4.7-µF capacitor should be a tantalum type and
the 0.1-µF capacitor should be a low ESL, low ESR type. The power supply for the DAC121C081 should only be
used for analog circuits.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the
board. These clock and data lines should have controlled impedances.
11.2 Layout Example
VOUT
ADR0
SOT
VA
SCL
C1
SDA
GND
Figure 35. Layout Example
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
29
DAC121C081, DAC121C085
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Device Nomenclature
12.1.1.1 Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB, which is VREF / 4096 = VA / 4096.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC output is not updated. It is measured with a full-scale code change on the data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded
into the DAC and the value of VA × 4095 / 4096.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register
changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input-to-output transfer function. The deviation of any given code from this straight line is measured
from the center of that code value. The end point method is used. INL for this product is specified over a limited
range, per the Electrical Characteristics.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is
LSB = VREF / 2n
where VREF is the supply voltage for this product, and n is the DAC resolution in bits, which is 12 for the
DAC121C081.
(8)
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output
stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when
the input code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VA.
MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3 dB below the input sine wave
on VREFIN with a full-scale code loaded into the DAC.
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from
the power supply. The difference between the supply and output currents is the power consumed by the device
without a load.
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is
updated.
TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs
with an ideal sine wave applied to VREFIN. THD is measured in dB.
WAKE-UP TIME is the time for the output to exit power-down mode. This time is measured from the rising edge
of SCL during the ACK bit of the lower data byte to the time the output voltage deviates from the power-down
voltage of 0 V.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been
entered.
30
Submit Documentation Feedback
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
DAC121C081, DAC121C085
www.ti.com
SNAS395F – DECEMBER 2007 – REVISED OCTOBER 2016
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• LP2980-N Micropower 50 mA Ultra Low-Dropout Regulator In SOT-23 Package, SNOS733.
12.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DAC121C081
Click here
Click here
Click here
Click here
Click here
DAC121C085
Click here
Click here
Click here
Click here
Click here
12.4 Trademarks
I2C is a registered trademark of Phillips Corporation..
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2007–2016, Texas Instruments Incorporated
Product Folder Links: DAC121C081 DAC121C085
Submit Documentation Feedback
31
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DAC121C081CIMK/NOPB
ACTIVE
SOT-23-THIN
DDC
6
1000
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
-40 to 125
X84C
DAC121C081CISD/NOPB
ACTIVE
WSON
NGF
6
1000
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
X87
DAC121C081CISDX/NOPB
ACTIVE
WSON
NGF
6
4500
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
X87
DAC121C085CIMM/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
X90C
DAC121C085CIMMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
SN
Level-1-260C-UNLIM
-40 to 125
X90C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
