DAC14135PCASM

DAC14135 DAC14135 14-Bit, 135MSPS D/A Converter Literature Number: SNAS115 N DAC14135 14-bit, 135MSPS D/A Converter General Description Features The DAC14135 is a monolithic 14-bit, 135MSPS digital-to-analog converter. The device has been optimized for use in cellular base stations and other applications where high resolution, high sampling rate, wide dynamic range, and compact size are required. The DAC14135 has many integrated features including a proprietary segmented DAC core, differential current outputs, a band-gap voltage reference, and TTL/CMOS compatible inputs. The converter features an 85dBc spurious free dynamic range (SFDR) at low frequencies and a 70dBc SFDR with 20MHz output signals. The 48-pin TSSOP package provides an extremely small footprint for applications where space is a critical consideration. The DAC14135 operates from a single +5V power supply. The digital power supply can also operate from +3.3V for lower power consumption and compatibility with +3.3V data inputs. The DAC14135 is fabricated in a 0.5µm CMOS process and is specified over the industrial temperature range of -40°C to +85°C. National Semiconductor thoroughly tests each part to verify full compliance with the guaranteed specifications. • 135 MSPS • Wide dynamic range SFDR @ 1MHz fout: 85dBc SFDR @ 5MHz fout: 79dBc SFDR @ 20MHz fout: 70dBc • Differential Current Outputs • Low power consumption: 185mW • Very small package: 48-pin TSSOP • TTL/CMOS (+3.3V or +5V) inputs Applications • Cellular Basestations: GSM, WCDMA, DAMPS, etc. • Multi-carrier Basestations • Multi-standard Basestations • Direct digital synthesis (DDS) • ADSL modems • HFC modems W-CDMA ACPR Four-Tone SFDR -30 0 Fs = 32.768MSPS -40 ACPR Lower 72.1dB Fs = 135MSPS Fout1 = 6.2MHz Fout2 = 9.31MHz Fout3 = 18.8MHz Fout4 = 21.95MHz Ampl. = 0dBFS SFDR > 70dBc -20 ACPR Upper 73dB -60 Power (dB) Power (dB) -50 DAC14135 14-bit, 135MSPS D/A Converter November 1999 -70 -80 -90 -100 -40 -60 -80 -110 -100 -120 2 4 6 8 10 Frequency (MHz) © 1999 National Semiconductor Corporation Printed in the U.S.A. 12 14 16 5 10 15 20 25 30 Frequency (MHz) http://www.national.com DAC14135 Electrical Characteristics (sample rate = 135MSPS, Tmin = -40°C, Tmax = +85°C, AVDD = +5V, DVDD = +5V, CVDD = +5V, full scale current = 20mA, differential 50Ω doubly terminated output, unless specified otherwise) PARAMETERS CONDITIONS TEMP RATINGS UNITS NOTES 1 MIN TYP MAX 135 75 70 64 14 20 150 85 79 70 -146 Bits mA MSPS dBc dBc dBc dBFS/Hz 85 79 70 90 72 dBc dBc dBc dBc dBc RESOLUTION FULL SCALE CURRENT MAXIMUM CONVERSION RATE SFDR (1ST Nyquist band) SFDR (1ST Nyquist band) SFDR (1ST Nyquist band) NOISE FLOOR fout = 1MHz, 0dBFS fout = 5MHz, 0dBFS fout = 20MHz, 0dBFS fout = 5MHz, 0dBFS Full Full Full Full Full Full +25°C DYNAMIC LINEARITY @ DVDD = +5V spurious-free dynamic range fout = 1MHz fout = 5MHz fout = 20MHz SFDR within a band four-tone SFDR sample rate = 135MSPS 1ST Nyquist band 0dBFS 0dBFS 0dBFS fout = 20MHz, 4MHz band 6.2, 9.31, 18.8, 21.95 MHz Full Full Full +25°C +25°C DYNAMIC LINEARITY @ DVDD = +3.3V spurious-free dynamic range fout = 1MHz fout = 5MHz fout = 20MHz sample rate = 100MSPS 1ST Nyquist band 0dBFS, DVDD = +3.3V 0dBFS, DVDD = +3.3V 0dBFS, DVDD = +3.3V +25°C +25°C +25°C 83 77 70 dBc dBc dBc DYNAMIC CHARACTERISTICS glitch impulse settling time to 0.1% rise time fall time step size = Ifullscale/2 +25°C +25°C +25°C +25°C 1 30 0.4 0.4 pV-s ns ns ns DC ACCURACY AND PERFORMANCE differential non-linearity integral non-linearity gain error gain drift 20mA output current offset error reference voltage +25°C +25°C +25°C Full +25°C +25°C ±1.0 ±1.5 ±5.0 ±75 10 1.235 LSB LSB % of FS ppm/°C nA V ANALOG OUTPUT PERFORMANCE full scale current compliance voltage (high) compliance voltage (low) output resistance output capacitance +25°C +25°C +25°C +25°C +25°C DATA INPUTS input logic low voltage, VIL input logic high voltage, VIH input logic low voltage, VIL input logic high voltage, VIH input logic low current, IIL input logic high current, IIH at mid-scale at mid-scale Full Full Full Full Full Full DVDD = +3.3V DVDD = +3.3V TIMING maximum conversion rate setup time (TS) hold time (TH) propagation delay (TPD) latency Full +25°C +25°C +25°C +25°C CLOCK INPUTS clock inputs internal self bias differential clock input swing differential clock input slew rate clock input impedance (single-ended) +25°C Full Full +25°C 75 70 64 1.111 1.358 20 1.25 -0.5 150 8.5 1.3 0.9 135 0.5 4.5 10 10 150 2 1 1.5 1.5 1 1.2 2 2 1, 2 3 mA V V kΩ pF 3.5 2.4 -10 -10 1, 2 2 2 1, 2 V V V V µA µA 1 1 1 1 1 1 MSPS ns ns ns 1, 2 clk cycles V Vpp V/ns kΩ Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. http://www.national.com 2 DAC14135 Electrical Characteristics PARAMETERS (sample rate = 135MSPS, Tmin = -40°C, Tmax = +85°C, AVDD = +5V, DVDD = +5V, CVDD = +5V, full scale current = 20mA, differential 50Ω doubly terminated output, unless specified otherwise) CONDITIONS TEMP RATINGS MIN POWER REQUIREMENTS analog supply current digital supply current digital supply current power consumption power consumption AVDD power supply rejection ratio +25°C +25°C +25°C +25°C +25°C +25°C 135MSPS, DVDD = +5V 100MSPS, DVDD = +3.3V 135MSPS, DVDD = +5V 100MSPS, DVDD = +3.3V at mid-scale TYP MAX 28 9 4.5 185 150 1.0 35 15 UNITS NOTES mA mA mA mW mW %FS/V 1 1 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. CLC5958Notes Timing Diagram 1) 2) These parameters are 100% tested at 25°C. These parameters are sample tested at -40°C, +25°C and +85°C. 3) Absolute Maximum Ratings positive supply voltage (VDD) analog output voltage range digital input voltage range output short circuit duration junction temperature storage temperature range lead solder duration (+300°C) Defined as the net area of undesired output transients in pV-s at a major transition. Recommended Operating Conditions -0.5V to +6V -0.7V to +VDD -0.5V to +VDD infinite 175°C -65°C to 150°C 10sec positive analog supply voltage positive digital supply voltage positive clock supply voltage operating temperature range +5V ±5% +3.3V or +5V ±5% +5V ±5% -40°C to +85°C Package Thermal Resistance Note: Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to maximum ratings for extended periods may affect device reliability. Package θJA θJC 48-pin TSSOP 56°C/W 16°C/W Package Transistor Count Transistor count 8,600 Ordering Information Model Temperature Range DAC14135MT DAC14135MTX DAC14135PCASM -40°C to +85°C -40°C to +85°C D0 – D13 Description 48-pin TSSOP (industrial temperature range) 48-pin TSSOP (TNR 1000 pc reel) Fully loaded evaluation board with DAC14135 … ready for test. N-1 N N+1 TH TS CLOCK T TPD N IoutT or IoutF N-1 N-2 NOTE: 1 clock cycle latency DAC14135 Timing Diagram 3 http://www.national.com DAC14135 Pin Definitions DGND 1 48 DGND DGND 2 47 DGND DGND 3 46 DGND DVDD 4 45 DVDD DVDD 5 44 DVDD (MSB) D13 6 43 CVDD D12 7 42 Clock T D11 8 41 Clock F D10 9 40 CGND D9 10 39 NC D8 11 38 AGND D7 12 37 IOUTT D6 13 36 IOUTF D5 14 35 AGND D4 15 34 AVDD D3 16 33 AVDD D2 17 32 AGND DAC14135 D1 18 31 REFCOMP (LSB) D0 19 30 FSADJ DS 20 29 REFIO NC 21 28 REFLO AGND 22 27 AGND AGND 23 26 AGND AGND 24 25 AGND IOUTT IOUTF (Pins 37, 36) Differential current outputs. Output compliance range is -0.5V to +1.25V. Clock T Clock F (Pins 42, 41) Differential clock inputs. Bypass CLOCKF with a 0.1µF capacitor to CGND if using single-ended clock on CLOCKT. Both inputs have internal self-bias at approximately 1.5V. D0 - D13 (Pins 6 - 19) Digital data inputs. CMOS (+3.3V and +5V) and TTL (with +3.3V DVDD) compatible. D13 is the MSB. DS (Pin 20) Data scramble input. If not used, either connect to ground or leave unconnected. AGND (Pins 22 - 27, 32, 35, 38) Analog ground. DGND (Pins 1 - 3, 46 - 48) Digital ground. CGND (Pin 40) Clock ground. Connect to AGND. AVDD (Pins 33, 34) +5V power supply for the analog section. Bypass to analog ground with a 0.1µF capacitor. DVDD (Pins 4, 5, 44, 45) +5V or +3.3V power supply for the digital section. Bypass to digital ground with a 0.1µF capacitor. CVDD (Pin 43) Internal clock buffer power supply. Bypass to clock ground with 0.1µF capacitor. REFIO (Pin 29) Internal voltage reference output (Vref) or voltage reference input. Nominally +1.235V. Can be overdriven with an external reference. Bypass to AGND with 0.1µF capacitor. REFLO (Pin 28) Ground for reference circuitry. Should be connected to AGND. FSADJ (Pin 30) Full scale current adjust. Must be connected with an external resistor (Rset) or an external current source (Iref) to analog ground. Ifullscale (mA) = 42.67 x Iref = 42.67 x REFIO/Rset REFCOMP (Pin 31) Compensation pin for the internal reference circuitry. Bypass to analog ground with a 0.1µF capacitor. NC http://www.national.com (Pins 21, 39) No connect. 4 DAC14135 Typical Performance Characteristics (AVDD= +5V, DVDD = +5V, CVDD = +5V, TA = 25°C) Single-Tone SFDR Single-Tone SFDR 0 0 Fs = 135MSPS Fout = 1MHz Ampl. = 0dBFS Fs = 135MSPS Fout = 5MHz Ampl. = 0dBFS -20 -40 Power (dB) Power (dB) -20 -60 -80 -100 -40 -60 -80 -100 -120 -120 0 20 0 60 40 20 Frequency (MHz) Single-Tone SFDR Two-Tone SFDR 0 0 Fs = 135MSPS Fout = 20MHz Ampl. = 0dBFS -20 -40 Power (dB) Power (dB) -20 -60 -80 -120 -40 -60 -100 0 20 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 60 40 Frequency (MHz) Frequency (MHz) Four-Tone SFDR Four-Tone SFDR 0 0 SFDR > 70dBc -40 Fs = 135MSPS Fout1 = 10MHz Fout2 = 10.6MHz Fout3 = 12.4MHz Fout4 = 13.0MHz Ampl. = 0dBFS -20 Power (dB) Power (dB) SFDR > 75dBc Fs = 135MSPS Fout1 = 6.2MHz Fout2 = 9.31MHz Fout3 = 18.8MHz Fout4 = 21.95MHz Ampl. = 0dBFS -20 -60 -80 -40 -60 -80 -100 -100 5 10 15 20 25 30 9 10 Frequency (MHz) 11 12 13 14 Frequency (MHz) W-CDMA ACPR GSM EDGE Modulation -30 Fs = 121.3MSPS Fs = 65.536MSPS -40 -50 Power (dB) -30 Power (dB) SFDR > 77dBc Fs = 135MSPS Fout1 = 5MHz Fout2 = 5.2MHz Ampl. = 0dBFS -80 -100 0 -10 -20 60 40 Frequency (MHz) -40 -50 -60 -70 ACPR Lower 70.5dB ACPR Upper 71.5dB -60 -70 -80 -90 -80 -90 -100 -100 -110 -120 -110 14 14.5 15 15.5 16 2 16.5 4 6 8 10 12 14 16 Frequency (MHz) Frequency (MHz) 5 http://www.national.com DAC14135 Typical Performance Characteristics (AVDD= +5V, DVDD = +5V, CVDD = +5V, TA = 25°C) SFDR vs. Fout, 0dBFS SFDR vs. Fout @ 135MSPS 90 90 85 85 80 80 0dBFS dB dB -6dBFS 75 75 -12dBFS 70 70 135MSPS 65MSPS 65 65 100MSPS 60 60 0 10 20 0 40 30 10 20 Fout (MHz) HD vs. Fout @ 135MSPS, 0dBFS HD vs. Fout @ 100MSPS, DVDD = +3.3V 100 100 90 90 dB dB 40 30 Fout (MHz) 80 80 HD4 HD4 70 HD2 HD2 60 0 10 20 30 60 0 50 40 HD3 70 HD3 10 20 Fout (MHz) 30 50 40 Fout (MHz) SNR vs. Fs @ 0dBFS 20mA, DC to Fs/2 SFDR vs. Temp @ 135MSPS, 0dBFS 80 90 75 85 dB dB Fout = 1MHz 70 80 Fout = 5MHz 65 75 60 70 Fout = 20MHz 70 90 110 -45 130 Fs(MSPS) 0 50 85 Temperature (°C) INL DNL 1.0 2.0 0.8 0.6 1.0 0.4 LSB LSB 0.2 0 0 -0.2 -0.4 -1.0 -0.6 -0.8 -2.0 -1.0 0 5000 10000 0 15000 Code http://www.national.com 5000 10000 Code 6 15000 DAC14135 Application Information The transformer converts the single ended clock signal to a differential signal. The diodes in the secondary limit the input swing to the DAC14135. Digital Data Inputs The DAC14135’s 14-bit binary inputs are CMOS compatible. The input voltage thresholds are approximately half of the digital supply voltage (DVDD/2). For a 3.3V DVDD, the inputs are also compatible with standard TTL levels. Digital data is standard binary coded, D13 is the most significant bit and D0 is the least significant bit. For all 1’s at the input, IOUTT = Ifullscale, IOUTF = 0. For all 0’s at the input, IOUTT = 0, IOUTF = Ifullscale. Latching the Input Data Inputs of the DAC14135 include a master-slave flip-flop. Due to internal clock buffer delay, the DAC14135 requires more hold time than setup time. This timing should be observed at the DAC data and clock pins. Refer to the timing diagram and the specifications for proper setup and hold time requirements. To prevent or reduce digital data feedthrough, keep digital data lines short and ensure separate digital grounding (DGND). 75Ω resistors in series with the digital data input path may be used to reduce overshoot and data feedthrough to the analog outputs. Digital supply (DVDD) should be decoupled to DGND using a 0.1µF bypass capacitor. Data Scramble (DS) Input Pin The DAC14135 is equipped with a data scramble input pin (DS) that may be used to troubleshoot possible spurious or harmonic distortion degradation due to digital data feedthrough on the printed circuit board. In the DAC14135, the digital data inputs are logically XORed with the DS input pin as shown in Figure 2. Driving the Clock Inputs The differential clock inputs, Clock T and Clock F, may be driven by a variety of input sources. These pins are internally self-biased at about 1.5V and therefore can be differentially AC coupled. Alternatively, a single clock source on Clock T with Clock F bypassed to CGND using a 0.1µF capacitor, may be used to clock the DAC14135. The clock driver supply voltage (CVDD) should be 5V ±5% and should be decoupled to the clock ground (CGND) using a 0.1µF capacitor. For best SFDR performance, use a differential clock input. Minimum input voltage swing (1.5Vpp) and slew rate (1.0V/ns) requirements should be met for optimum performance. Low noise and low jitter clocks provide the best SNR performance for the DAC14135. Figure 1 shows one method of driving the clock inputs. A low noise sinusoidal clock source (2-4 Vpp) may be used to drive the transformer primary. 0.1µF 25Ω 0.1µF 25Ω 0.1µF DAC14135 D13 D Q Q D12 D Q • • • • • Q • • • • D0 D Q Q CLK DS Figure 2: Digital Data Inputs with DS Input Pin If the DS pin is at logic low (DGND) the input data is left unchanged and if this pin is at logic high (DVDD) the input data is inverted. If the input data is XORed with a random bit stream and if the same random bit stream is used to drive the DS pin, low order harmonics due to data feedthrough on the printed circuit board can be reduced. If this feature is not used, tie DS pin to ground or leave it floating (DS pin has internal active pulldown). Clock T Voltage Reference Loop The DAC14135 has an internal bandgap voltage reference nominally at 1.235V. The output of this bandgap is connected to the REFIO pin. The REFIO pin is a high impedance output and therefore can be easily over- Clock F T1- 1T Figure 1: Method of Driving Clock Inputs 7 http://www.national.com ridden by an external bandgap reference voltage. The reference ground (REFLO) should always be tied to analog ground. The REFIO pin should be bypassed to REFLO using a 0.1µF capacitor. For reduced noise, an external compensation capacitor (0.1µF) should also be used to bypass the internal reference loop from pin REFCOMP to AGND. Figure 3 shows the internal voltage reference loop functional schematic. Analog Outputs The differential analog outputs, IOUTT and IOUTF, are high impedance current source outputs. These outputs, if terminated into 50Ω at 20mA full scale current, will generate a differential voltage output at 2Vpp. The output compliance of each of the current outputs of the DAC14135 is -0.5V to +1.25V. The differential outputs can be converted to a single-ended output using an RF center-tapped transformer or a differential to singleended amplifier. The IOUTT and IOUTF traces on the printed circuit board should be short and matched with adequate analog grounding nearby. One example of an AC coupled differential to single-ended topology is shown in Figure 4. DAC14135 Bandgap 1.235V PMOS mirrors REFCOMP 0.1µF REFIO DAC14135 0.1µF FSADJ IOUTT Iref Rset 50Ω 100Ω T1-1T REFLO IOUTF 50Ω Figure 3: Internal Voltage Loop Functional Schematic A reference current source (Iref) from pin FSADJ to ground may be used to set the full scale output current (Ifs) of the DAC14135. The full scale current is given by, Figure 4: AC Coupled Differential to Single-ended Topology Ifs = 42.67 x Iref DAC14135 Grounding Information In the DAC14135, all the grounds AGND, REFLO, DGND and CGND are shorted together inside the package. The purpose of having separate grounds on the printed circuit board is to prevent digital data currents from returning through the analog or reference grounds, and corrupting the analog outputs. Refer to the evaluation board layout. Alternatively, a resistor (Rset) from FSADJ to AGND may be used to set the full scale output current of the DAC. Ifs (mA) = 42.67 x REFIO/Rset The voltage at REFIO is nominally set by the internal bandgap at 1.235V. For a full scale output current of 20mA, the value of Rset is 2.635kΩ. http://www.national.com 8 DAC14135 Evaluation Board Description To use the board in the dual supply mode, connect a 5V supply to the +AVDD terminal block, connect a 3.3V supply to the +DVDD terminal block and connect the jumper between the DIRECT pin (pin 1) and the middle pin (pin 2). This bypasses the on-board voltage regulator, although the regulator still draws power. General Description The DAC14135 Evaluation Board is intended to aid in evaluating the performance of the DAC14135. The board allows the user to exercise the inputs to the DAC and examine the output in either differential or single ended mode. The board comes complete with the DAC14135, a transformer network to convert a single ended clock to a differential clock, a transformer to convert the differential output from IOUTT and IOUTF to a single ended output, and an edge connector. This is a 5V part, but if a 3.3V CMOS or TTL digital data interface is required, the digital supply (DVDD) should be 3.3V. A 3.3V regulator is provided so that the board can be run off of a single 5V supply. For the best distortion performance at the maximum clock frequency, DVDD should be set to 5V. Getting Data to the Evaluation Board The DAC14135 evaluation board is shipped with the edge connectors J1 and J2 being the default data input interface. J1 and J2 are AMP 536511-1 and 536511-3 edge connectors respectively. Data should be at the same voltage level as DVDD. Figure 5 below, is an edgeon view of J2. Pins 24D-11D are the data lines with 24D being the MSB. The ground pins are 23C, 23A, 21C, 19C, 17C, 17A, 15C, 13C, 11C, 11A, 9C, 7C, 6A, 5C, 3C, and 1C. All ground pins are tied together on-board. Also, pin 10D should be at logic LOW (0V) if the data scramble feature on the DAC14135 is not used. Setup and Configuration There are two terminal blocks on the DAC14135 evaluation board, one in the upper left corner next to the AMP connectors, and one in the upper right corner. The upper right corner has the analog power supply connector, marked +AVDD. The connector in the upper left is for the digital power supply and is marked +DVDD. There is also a jumper next to the +DVDD terminal block marked DVDD with one end marked DIRECT and the other end marked +3.3V REG. Driving the Clock Input The evaluation board has an on-board transformer, T2, that converts a single ended clock to a differential clock to drive the DAC14135. For best results drive the CLOCK SMA connector with a low jitter 50Ω source. If a sinusoidal source is used, its peak-to-peak amplitude should be at least 2.5V to meet the minimum clock input slew rate requirement. Back-to-back diodes at the secondary of the transformer T2 limit the voltage swing at the DAC14135 Clock T and Clock F input pins. There are three ways to power the evaluation board. The default method of use is to connect the 5V power supply to both the +AVDD terminal block and the +DVDD terminal block and connect the jumper between the DIRECT pin (pin 1) and the middle pin (pin 2). Measuring the Analog Outputs The evaluation board is shipped with transformer T1 installed to convert the differential output to a single ended output. However, the 0Ω resistors R38 and R39 are not installed. To take single ended measurements, install R38 and R39 and attach your instrument to the SMA connector marked ‘SINGLE’. For differential output measurements, remove R38 and R39 if they are installed. Note that both outputs, IOUTT and IOUTF, are terminated with 50Ω. If a 3.3V CMOS or TTL digital data interface is required, connect the jumper between the +3.3V REG pin (pin 3) and the middle pin (pin 2). This enables the 3.3V regulator on the back side of the board. The output of the regulator is filtered and powers the digital portion of the DAC. 24D 23D 22D 21D 20D 19D 18D 17D 16D 15D 14D 13D 12D 11D 10D 9D 8D 7D 6D 5D 4D 3D 2D 1D 24C 23C 22C 21C 20C 19C 18C 17C 16C 15C 14C 13C 12C 11C 10C 9C 8C 7C 6C 5C 4C 3C 2C 1C 24B 23B 22B 21B 20B 19B 18B 17B 16B 15B 14B 13B 12B 11B 10B 9B 8B 7B 6B 5B 4B 3B 2B 1B 24A 23A 22A 21A 20A 19A 18A 17A 16A 15A 14A 13A 12A 11A 10A 9A 8A 7A 6A 5A 4A 3A 2A 1A Figure 5: Pinout for J2 (Amp 536511-3) 9 http://www.national.com DAC14135 Evaluation Board Schematic http://www.national.com 10 DAC14135 Evaluation Board Layout DAC14135PCASM Layer 1 DAC14135PCASM Layer 2 DAC14135PCASM Layer 3 DAC14135PCASM Layer 4 11 http://www.national.com DAC14135 14-bit, 135MSPS D/A Converter DAC14135 Physical Dimensions Symbol Min Max A – 1.10 A1 0.05 0.15 A2 0.80 1.05 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 D 12.40 12.60 E E1 e L L1 R1 Notes 2 8.1 BSC 6.00 6.20 2 0.50 BSC 0.50 0.75 1.00 REF 0.127 Notes: 1. All dimensions are in millimeters. 2. Dimensions D and E1 do not include mold protrusion. Allowable protrusion is 0.20mm per side. Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, a) are intended for surgical implant into the body, or b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. N National Semiconductor Corporation National Semiconductor Europe National Semiconductor Hong Kong Ltd. National Semiconductor Japan Ltd. 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 Fax: (+49) 0-180-530 85 86 E-mail: europe.support.nsc.com Deutsch Tel: (+49) 0-180-530 85 85 English Tel: (+49) 0-180-532 78 32 Francais Tel: (+49) 0-180-532 93 58 Italiano Tel: (+49) 0-180-534 16 80 2501 Miramar Tower 1-23 Kimberley Road Tsimshatsui, Kowloon Hong Kong Tel: (852) 2737-1600 Fax: (852) 2736-9960 Tel: 81-043-299-2309 Fax: 81-043-299-2408 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. http://www.national.com 12 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications. TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, TI will not be responsible for any failure to meet such requirements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Audio www.ti.com/audio Communications and Telecom www.ti.com/communications Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps DLP® Products www.dlp.com Energy and Lighting www.ti.com/energy DSP dsp.ti.com Industrial www.ti.com/industrial Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical Interface interface.ti.com Security www.ti.com/security Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive Microcontrollers microcontroller.ti.com Video and Imaging RFID www.ti-rfid.com OMAP Mobile Processors www.ti.com/omap Wireless Connectivity www.ti.com/wirelessconnectivity TI E2E Community Home Page www.ti.com/video e2e.ti.com Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2011, Texas Instruments Incorporated