DAC3154
DAC3164
www.ti.com
SLAS960 – MAY 2013
Dual 12-/10-Bit 500 MSPS Digital-to-Analog Converters
Check for Samples: DAC3154 , DAC3164
FEATURES
APPLICATIONS
•
•
•
1
2
•
•
•
•
•
•
•
•
•
Dual Channel
Resolution
– DAC3154: 10-Bit
– DAC3164: 12-Bit
Maximum Sample Rate: 500 MSPS
Pin Compatible Family with DAC3174 and
DAC3151/DAC3161/DAC3171
Input Interface:
– 12-/10-Bit Wide LVDS Inputs
– Internal FIFO
Chip to Chip Synchronization
Power Dissipation: 460mW
Spectral Performance at 20 MHz IF
– SNR: 62 dBFS for DAC3154, 72 dBFS for
DAC3164
– SFDR: 76 dBc for DAC3154, 77 dBc for
DAC3164
Current Sourcing DACs
Compliance Range: –0.5V to 1V
Package: 64 Pin QFN (9x9mm)
•
•
•
•
Multi-Carrier, Multi-Mode Cellular
Infrastructure Base Stations
Radar
Signal Intelligence
Software-Defined Radio
Test and Measurement Instrumentation
DESCRIPTION
The DAC3154/DAC3164 are dual channel 10-/12-bit,
pin-compatible family of 500 MSPS digital-to-analog
converters (DAC). The DAC3154/DAC3164 use a 10/12-bit wide LVDS digital bus with an input FIFO.
FIFO input and output pointers can be synchronized
across multiple devices for precise signal
synchronization. The DAC outputs are current
sourcing and terminate to GND with a compliance
range of –0.5 to 1V. DAC3154/ DAC3164 are pin
compatible with the dual-channel, 14-bit, 500 MSPS
digital-to-analog converters DAC3174, and the singlechannel, 14-/12-10-bit, digital-to-analog converters
DAC3171/DAC3161/DAC3151.
The devices are available in a QFN-64 PowerPAD™
package is specified over the full industrial
temperature range (–40°C to 85°C).
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
DAC3154
DAC3164
SLAS960 – MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
VDDA18
VFUSE
DIGVDD18
CLKVDD18
BLOCK DIAGRAMS
DACCLKP
Clock Distribution
LVPECL
1.2 V
Reference
DACCLKN
DATACLKN
Programmable
Delay
DACA
Gain
LVDS
100
DATA9P
QMC
A-offset
DATA9N
8 Sample FIFO
De-interleave
Pattern Test
IOUTAN
IOUTBP
10-b
DACB
10
LVDS
IOUTBN
100
QMC
B-offset
DACB
Gain
DATA0N
LVDS
VDDA33
100
SYNCP
IOUTAP
10-b
DACA
10
DATA0P
BIASJ
LVDS
100
DATACLKP
EXTIO
SYNCN
Optional Input
Used for multi-DAC sync
ALIGNP
Control Interface
LVPECL
TESTMODE
ALARM
SLEEP
RESETB
TXENABLE
SCLK
SDENB
SDIO
SDO
IOVDD
GND
ALIGNN
Figure 1. DAC3154
2
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DAC3154
DAC3164
VFUSE
DIGVDD18
VDDA18
SLAS960 – MAY 2013
CLKVDD18
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DACCLKP
Clock Distribution
LVPECL
1.2 V
Reference
DACCLKN
DATACLKN
Programmable
Delay
DACA
Gain
LVDS
100
DATA11P
QMC
A-offset
DATA11N
8 Sample FIFO
De-interleave
Pattern Test
IOUTAN
IOUTBP
12-b
DACB
12
LVDS
IOUTBN
100
QMC
B-offset
DACB
Gain
DATA0N
LVDS
VDDA33
100
SYNCP
IOUTAP
12-b
DACA
12
DATA0P
BIASJ
LVDS
100
DATACLKP
EXTIO
SYNCN
Optional Input
Used for multi-DAC sync
ALIGNP
Control Interface
LVPECL
TESTMODE
ALARM
SLEEP
RESETB
TXENABLE
SCLK
SDENB
SDIO
SDO
IOVDD
GND
ALIGNN
Figure 2. DAC3164
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DAC3164
SLAS960 – MAY 2013
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VDDA18
NC
NC
IOUTAP
IOUTAN
VDDA33
EXTIO
BIASJ
VDDA33
VDDA33
IOUTBN
IOUTBP
NC
NC
VDDA18
SLEEP
PINOUT – DAC3154
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DACCLKP
1
48
TXENABLE
DACCLKN
2
47
ALARM
CLKVDD18
3
46
SDO
ALIGNP
4
45
IOVDD
ALIGNN
5
44
SDIO
SYNCP
6
43
SCLK
SYNCN
7
42
SDENB
VFUSE
8
41
RESETB
(MSB) D9P
9
40
NC
D9N
10
39
NC
D8P
11
38
NC
D8N
12
37
NC
D7P
13
36
NC
D7N
14
35
NC
34
NC
33
NC
26
DATACLKP
DATACLKN
D2P
27
28
29
30
31
32
D0N
25
(LSB) D0P
24
D1N
23
D1P
22
DIGVDD18
21
D2N
20
D3N
19
D3P
18
DIGVDD18
17
D4N
16
D4P
D6N
D5N
15
GND PAD (backside)
D5P
D6P
DAC3154
PIN ASSIGNMENT TABLE – DAC3154
PIN
NAME
NO.
I/O
DESCRIPTION
CONTROL/SERIAL
SCLK
43
SDENB
42
SDIO
44
I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register XYZ), the SDIO pin in
an input only. Internal Pull-down.
SDO
46
O
Uni-directional serial interface data in 4 pin mode (register XYZ). The SDO pin is tri-stated in 3-pin
interface mode (default). Internal Pulldown.
RESETB
41
I
Serial interface reset input. Active low. Initialized internal registers during high to low transition.
Assynchronous. Internal pull-up.
ALARM
47
O
CMOS output for ALARM condition.
TXENABLE
48
I
Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled.
When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored. Internal
pull-down.
SLEEP
49
I
Puts device in sleep, active high. Internal pull-down.
4
I
Serial interface clock. Internal pull-down.
I
Serial interface clock. Internal pull-up.
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DAC3164
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SLAS960 – MAY 2013
PIN ASSIGNMENT TABLE – DAC3154 (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
I
LVDS input data bits for both channels. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two data
transfers per DATACKP/N clock cycle.
DATA INTERFACE
DATA[9:0]P/N
9/1019/20
22/23
26/2731/32
The data format is interleaved with channel A (rising edge) and channel B falling edge.
In the default mode (reverse bus not enabled):
DATA9P/N is most significant data bit (MSB)
DATA0P/N is most significant data bit (LSB)
DATACLKP/N
24/25
I
DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge in
multiplexed output mode.
SYNCP/N
6/7
I
Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising edge
of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N.
ALIGNP/N
4/5
I
LVPECL FIFO output syncrhonization. This positive/negative pair is captured with the rising edge of
DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it can
be left unconnected.
1/2
I
LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
IOUTAP/N
61/60
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full
scale current source and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input
results in a 0 mA current source and the least positive voltage on the IOUTAP pin.
IOUTBP/N
53/54
O
B-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full
scale current source and the most positive voltage on the IOUTBP pin. Similarly, a 0xFFFF data input
results in a 0 mA current source and the least positive voltage on the IOUTBP pin.
OUTPUT/CLOCK
DACCLKP/N
REFERENCE
EXTIO
58
I/O Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling
capacitor to GND when used as reference output.
BIASJ
57
O
Full-scale output current bias. For 20 mA full-scale output current, connect a 960 Ω resistor to GND.
IOVDD
45
I
Supply voltage for CMOS IO’s. 1.8V – 3.3V.
CLKVDD18
3
I
1.8V clock supply
DIGVDD18
21, 28
I
1.8V digital supply. Also supplies LVDS receivers.
VDDA18
50, 64
I
Analog 1.8V supply
VDDA33
55, 56,
59
I
Analog 3.3V supply
VFUSE
8
I
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DVDD pins for normal operation.
POWER SUPPLY
NC
33-40,
51, 52,
62, 63
Not used. These pins can be left open or tied to GROUND in actual application use.
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DAC3164
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VDDA18
NC
NC
IOUTAP
IOUTAN
VDDA33
EXTIO
BIASJ
VDDA33
VDDA33
IOUTBN
IOUTBP
NC
NC
VDDA18
SLEEP
PINOUT – DAC3164
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DACCLKP
1
48
TXENABLE
DACCLKN
2
47
ALARM
CLKVDD18
3
46
SDO
ALIGNP
4
45
IOVDD
ALIGNN
5
44
SDIO
SYNCP
6
43
SCLK
SYNCN
7
42
SDENB
VFUSE
8
41
RESETB
(MSB) D11P
9
40
NC
D11N
10
39
NC
D10P
11
38
NC
D10N
12
37
NC
D9P
13
36
D0N
D9N
14
35
D0P (LSB)
34
D1N
33
D1P
26
DATACLKP
DATACLKN
D4P
27
28
29
30
31
32
D2N
25
D2P
24
D3N
23
D3P
22
DIGVDD18
21
D4N
20
D5N
19
D5P
18
DIGVDD18
17
D6N
16
D6P
D8N
D7N
15
GND PAD (backside)
D7P
D8P
DAC3164
PIN ASSIGNMENT TABLE – DAC3164
PIN
NAME
NO.
I/O
DESCRIPTION
CONTROL/SERIAL
SCLK
43
SDENB
42
SDIO
44
I/O Bi-directional serial data in 3 pin mode (default). In 4-pin interface mode (register XYZ), the SDIO pin
in an input only. Internal Pull-down.
SDO
46
O
Uni-directional serial interface data in 4 pin mode (register XYZ). The SDO pin is tri-stated in 3-pin
interface mode (default). Internal Pulldown.
RESETB
41
I
Serial interface reset input. Active low. Initialized internal registers during high to low transition.
Assynchronous. Internal pull-up.
ALARM
47
O
CMOS output for ALARM condition.
TXENABLE
48
I
Transmit enable active high input. TXENABLE must be high for the DATA to the DAC to be enabled.
When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored.
Internal pull-down.
SLEEP
49
I
Puts device in sleep, active high. Internal pull-down.
6
I
Serial interface clock. Internal pull-down.
I
Serial interface clock. Internal pull-up.
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DAC3164
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SLAS960 – MAY 2013
PIN ASSIGNMENT TABLE – DAC3164 (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
DATA INTERFACE
DATA[11:0]P/N
9/1019/20
22/23,
26-2735/36
I
LVDS input data bits for both channels. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two
data transfers per DATACKP/N clock cycle.
The data format is interleaved with channel A (rising edge) and channel B falling edge.
In the default mode (reverse bus not enabled):
DATA11P/N is most significant data bit (MSB)
DATA0P/N is most significant data bit (LSB)
DATACLK[:0]P/N
24/25
I
DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge
in multiplexed output mode.
SYNCP/N
6/7
I
Reset the FIFO or to be used as a syncing source. These two functions are captured with the rising
edge of DATACLKP/N. The signal captured by the falling edge of DATACLKP/N.
ALIGNP/N
24/25
I
LVPECL FIFO output syncrhonization. This positive/negative pair is captured with the rising edge of
DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it
can be left unconnected.
1/2
I
LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
IOUTAP/N
61/60
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
full scale current source and the most positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data
input results in a 0 mA current source and the least positive voltage on the IOUTA1 pin. The IOUTA2
pin is the complement of IOUTA1.
IOUTBP/N
53/54
O
B-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
full scale current source and the most positive voltage on the IOUTB1 pin. Similarly, a 0xFFFF data
input results in a 0 mA current source and the least positive voltage on the IOUTB1 pin. The IOUTB2
pin is the complement of IOUTB1.
OUTPUT/CLOCK
DACCLKP/N
REFERENCE
EXTIO
58
I/O Used as external reference input when internal reference is disabled. Requires a 0.1 µF decoupling
capacitor to GND when used as reference output.
BIASJ
57
O
Full-scale output current bias. For 20 mA full-scale output current, connect a 960 Ω resistor to GND.
IOVDD
45
I
Supply voltage for CMOS IO’s. 1.8V – 3.3V.
CLKVDD18
3
I
1.8V clock supply
DIGVDD18
21, 28
I
1.8V digital supply. Also supplies LVDS receivers.
VDDA18
50, 64
I
Analog 1.8V supply
VDDA33
55, 56,
59
I
Analog 3.3V supply
VFUSE
8
I
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DVDD pins for normal operation.
POWER SUPPLY
NC
37, 38,
39, 40,
51, 52
62, 63
Not used. These pins can be left open or tied to GROUND in actual application use.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
ECO PLAN
DAC3154
QFN-64
RGC
DAC3164
(1)
–40°C to 85°C
GREEN (RoHS
and no Sb/Br)
ORDERING
NUMBER
TRANSPORT
MEDIA
QUANTITY
DAC3154IRGCT
250
DAC3154IRGCR
2000
DAC3164IRGC25
Tape and Reel
25
DAC3164IRGCT
250
DAC3164IRGCR
2000
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
Supply voltage
VDDA33 to GND
–0.5 to 4
VDDA18 to GND
–0.5 to 2.3
CLKVDD18 to GND
–0.5 to 2.3
IOVDD to GND
Terminal voltage
range
UNIT
V
–0.5 to 4
DIGVDD18 to GND
–0.5 to 2.3
CLKVDD18 to DIGVDD18
–0.5 to 0.5
VDDA18 to DIGVDD18
–0.5 to 0.5
D[11..0]P, D[11..0]N, DATACLKP, DATACLKN, SYNCP, SYNCN to GND
–0.5 to DIGVDD18 + 0.5
DACCLKP, DACCLKN, ALIGNP, ALIGNN
–0.5 to CLKVDD18 + 0.5
TXENABLE, ALARM, SDO, SDIO, SCLK, SDENB, RESETB to GND
IOUTAP, IOUTAN, IOUTBP, IOUTBN to GND
EXTIO, BIASJ to GND
V
–0.5 to IOVDD + 0.5
–0.7 to 1.4
–0.5 to VDDA33 + 0.5
Storage temperature range
–65 to 150
°C
ESD, Human Body Model
2
kV
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC (1)
DAC3174
QFN (64 PIN)
θJA
Junction-to-ambient thermal resistance
23.0
θJCtop
Junction-to-case (top) thermal resistance
7.6
θJB
Junction-to-board thermal resistance
2.8
ψJT
Junction-to-top characterization parameter
0.1
ψJB
Junction-to-board characterization parameter
2.8
θJCbot
Junction-to-case (bottom) thermal resistance
0.2
(1)
8
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLAS960 – MAY 2013
ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, DAC sample rate = 500MSPS, 50% clock
duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUTFS = 20mA (unless otherwise noted).
PARAMETER
TEST CONDITIONS
Resolution
DAC3154
MIN
TYP
DAC3164
MAX
10
MIN
TYP
UNIT
MAX
12
Bits
DC ACCURACY
DNL Differential nonlinearity
INL Integral nonlinearity
1 LSB = IOUTFS/210 for
DAC3154; 1 LSB = IOUTFS/212
for DAC3164
±0.04
±0.2
±0.15
±0.5
±0.4
±0.4
LSB
%FSR
LSB
ANALOG OUTPUTS
Coarse gain linearity
Offset error
Gain error
Mid code offset
0.01
0.01
With external reference
±2
±2
With internal reference
±2
±2
Gain mismatch
With internal reference
Minimum full scale output current
Maximum full scale output current
Nominal full-scale current,
IOUTFS = 16xIBAIS current
Output compliance range
IOUTFS = 20 mA
-2
2
Output capacitance
2
2
2
20
20
-0.5
Output resistance
-2
%FSR
-0.5
%FSR
mA
1
V
300
300
kΩ
5
5
pF
REFERENCE OUTPUT
VREF
Reference output voltage
1.14
Reference output current
1.2
1.26
1.14
100
1.2
1.26
V
100
nA
REFERENCE INPUT
VEXTIO Input voltage range
External reference mode
0.1
Input resistance
1.2
1.25
0.1
1.2
1.25
V
1
1
MΩ
Small signal bandwidth
500
500
kHz
Input capacitance
100
100
pF
±1
±1
ppm of
FSR/°C
With external reference
±15
±15
With internal reference
±30
±30
±8
±8
TEMPERATURE COEFFICIENTS
Offset drift
Gain drift
Reference voltage drift
ppm /°C
POWER SUPPLY
DIGVDD18, VFUSE, VDDA18,
CLKVDD18
1.71
1.8
1.71
1.8
1.89
V
VDDA33
3.15
3.3
3.15
3.3
3.45
V
3.45
V
IOVDD
Sets CMOS IO voltage levels.
Nominal 1.8V, 2.5V or 3.3V
1.71
1.71
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ELECTRICAL CHARACTERISTICS – DC SPECIFICATIONS (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, DAC sample rate = 500MSPS, 50% clock
duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUTFS = 20mA (unless otherwise noted).
PARAMETER
TEST CONDITIONS
DAC3154
MIN
DAC3164
TYP
MAX
52
49
MIN
UNIT
TYP
MAX
59
52
59
mA
67
49
57
mA
115
130
115
130
mA
0.002
0.015
0.002
0.015
mA
464
530
464
530
mW
POWER CONSUMPTION
IVDDA33
3.3V Analog supply current
ICLKVDD18 1.8V Clock supply current
IDIGVDD18
1.8V Digital supply current
(DIGVDD18 and VFUSE)
IIOVDD
1.8V IO Supply current
Pdis
Total power dissipation
IVDDA33
3.3V Analog supply current
ICLKVDD18 1.8V Clock supply current
MODE 1
fDAC = 491.52 MSPS,
QMC on,
IF = 20 MHz
MODE 2
fDAC = 320 MSPS,
QMC on,
IF = 20 MHz
51
51
mA
38
38
mA
87
87
mA
IDIGVDD18
1.8V Digital supply current
(DIGVDD18 and VFUSE)
IIOVDD
1.8V IO Supply current
0.002
0.002
mA
Pdis
Total power dissipation
396
396
mW
IVDDA33
3.3V Analog supply current
2.6
2.6
mA
43
43
mA
110
110
mA
ICLKVDD18 1.8V Clock supply current
MODE 3
Sleep mode,
fDAC = 491.52 MSPS,
DAC in sleep mode
IDIGVDD18
1.8V Digital supply current
(DIGVDD18 and VFUSE)
IIOVDD
1.8V IO Supply current
0.003
0.003
mA
Pdis
Total power dissipation
284
284
mW
IVDDA33
3.3V Analog supply current
1.6
4
1.6
4
mA
1.8
4
1.8
4
mA
3
mA
0.015
mA
26
mW
ICLKVDD18 1.8V Clock supply current
IDIGVDD18
1.8V Digital supply current
(DIGVDD18 and VFUSE)
IIOVDD
1.8V IO Supply current
Pdis
Total power dissipation
PSRR
Power supply rejection ratio
T
Operating temperature
10
MODE 4
Power-down mode,
no clock,
DAC in sleep mode
1.7
0.003
10
DC tested
0.015
0.003
26
10
–0.4
0.4
-0.4
0.4 %/FSR/V
–40
85
-40
85
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°C
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SLAS960 – MAY 2013
ELECTRICAL CHARACTERISTICS – AC SPECIFICATIONS
Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T MAX = 85°C, DAC sample rate = 500MSPS, 50%
clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise
noted).
PARAMETER
TEST CONDITIONS
DAC3154
MIN
TYP MAX
DAC3164
MIN
UNIT
TYP MAX
ANALOG OUTPUT
fDAC
Maximum sample rate
ts(DAC)
Output settling time to
0.1%
500
Transition: Code 0x0000 to 0x3FFF
tPD
Output propagation delay
Does not include digital latency
tr(IOUT)
tf(IOUT)
500
MSPS
11
11
ns
2
2
ns
Output rise time 10% to
90%
200
200
ps
Output fall time 90% to
10%
200
200
ps
Length of delay from DAC input pins to DATA at
output pins. In normal operation mode including the
latency of FIFO.
26
26
µs
fDAC = 500 MSPS, fout = 10.1 MHz
81
82
fDAC = 500 MSPS, fout = 20.1 MHz
76
77
fDAC = 500 MSPS, fout = 70.1 MHz
69
70
fDAC = 500 MSPS, fout = 10.1 ±0.5 MHz
82
83
fDAC = 500 MSPS, fout = 20.1 ±0.5 MHz
81
82
fDAC = 500 MSPS, fout = 70.1 ±0.5 MHz
73.5
74
Digital Latency
AC PERFORMANCE
SFDR
IMD3
Spurious free dynamic
range
Intermodulation distortion
fDAC = 500 MSPS, fout = 150.1 ±0.5 MHz
NSD
ACLR
Noise spectral density
61
61
fDAC = 500 MSPS, fout = 10.1 MHz
147
158
fDAC = 500 MSPS, fout = 20.1 MHz
146
156
fDAC = 500 MSPS, fout = 70.1 MHz
146
153
69
77
68
73
90
90
fDAC = 491.52 MSPS, fout = 30.72 MHz,
Adjacent channel leakage WCDMA TM1
ratio
f AC = 491.52 MSPS, fout = 153.6 MHz,
WCDMA TM1
Channel isolation
fDAC = 500 MSPS,
fout = 20 MHz
dBc
dBc
dBc/Hz
dBc
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dBc
11
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DAC3164
SLAS960 – MAY 2013
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ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS
Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T MAX = 85°C, DAC sample rate = 500MSPS, 50%
clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise
noted).
PARAMETERS
TEST CONDITIONS
DAC3154
MIN
TYP
DAC3164
MAX
MIN
TYP
MAX
UNIT
CMOS DIGITAL INPUTS (RESETB, SDENB, SCLK, SDIO, TXENABLE)
0.6x
IOVDD
0.6x
IOVDD
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
–40
40
IIL
Low-level input current
–40
40
V
0.25×
IOVDD
IOVDD = 3.3 V, 2.5 V
or 1.8 V
0.25×
IOVDD
V
-40
40
μA
-40
40
μA
DIGITAL OUTPUTS – CMOS INTERFACE (SDOUT, SDIO)
VOH
High-level output voltage
VOL
Low-level output voltage
IOVDD = 3.3 V, 2.5 V,
or 1.8 V
0.85×
IOVDD
0.85×
IOVDD
V
0.125×
IOVDD
0.125×
IOVDD
V
SERIAL PORT TIMING
ts(SENDB)
Setup time, SDENB to rising edge of
SCLK
20
20
ns
ts(SDIO)
Setup time, SDIO to rising edge of SCLK
10
10
ns
th(SDIO)
Hold time, SDIO from rising edge of SCLK
5
5
ns
t(SCLK)
Period of SCLK
100
100
ns
t(SCLKH)
High time of SCLK
40
40
ns
t(SCLKL)
Low time of SCLK
40
40
ns
td(DATA)
Data output delay after falling edge of
SCLK
TRESET
Minimum RESTB pulsewidth
10
10
ns
LVDS INTERFACE (D[x..0]P/N, DA[x..0]P/N , DB[x..0]P/N , DA_CLKP/N, DB_CLKP/N, DATACLKP/N, SYNCP/N, ALIGNP/N)
VA,B+
Logic high differential input voltage
threshold
VA,B–
Logic low differential input voltage
threshold
VCOM
Input Common Mode Range
1.0
1.2
2.0
1.0
1.2
2.0
ZT
Internal termination
85
110
135
85
110
135
CL
LVDS input capacitance
12
175
175
mV
-175
2
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–175
2
mV
V
Ω
pF
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SLAS960 – MAY 2013
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS (continued)
Typical values at T A = 25°C, full temperature range is T MIN = –40°C to T MAX = 85°C, DAC sample rate = 500MSPS, 50%
clock duty cycle, VDDA33/IOVDD = 3.3V, VDDA18/CLKVDD18/DIGVDD18 = 1.8V, IOUT FS = 20mA (unless otherwise
noted).
PARAMETERS
TEST CONDITIONS
DAC3154
MIN
TYP
DAC3164
MAX
MIN
TYP
MAX
UNIT
LVDS INPUT TIMING: SINGLE BUS SINGLE CLOCK MODE
config3 Setting
ts(DATA)
Setup
time
D[x..0] valid to DATACLK rising or
falling edge
datadly
clkdly
0
0
-20
-20
0
1
-120
-120
0
2
-220
-220
0
3
-310
-310
0
4
-390
-390
0
5
-480
-480
0
6
-560
-560
0
7
-630
-630
1
0
70
70
2
0
150
150
3
0
230
230
4
0
330
330
5
0
430
430
6
0
530
530
7
0
620
620
ps
congfig3 Setting
th(DATA)
Hold
time
D[x..0] valid to DATACLK rising or
falling edge
datadly
clkdly
0
0
310
310
0
1
390
390
0
2
480
480
0
3
560
560
0
4
650
650
0
5
740
740
0
6
850
850
0
7
930
930
1
0
200
200
2
0
100
100
3
0
20
20
4
0
-60
-60
5
0
-140
-140
6
0
-220
-220
7
0
-290
-290
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13
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SLAS960 – MAY 2013
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TYPICAL CHARACTERISTICS
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA fullscale output current (unless otherwise noted).
0.2
0.05
0.15
0.04
0.03
0.02
0.05
DNL (LSB)
INL (LSB)
0.1
0
−0.05
0
−0.01
−0.02
−0.1
−0.03
−0.15
−0.2
0.01
−0.04
0
200
400
600
Code
800
−0.05
1000
0
Figure 3. DAC3154 Integral Nonlinearity
1000
G004
0dBFS
−6dBFS
−12dBFS
80
70
70
60
50
60
50
40
40
30
30
20
20
0
50
100
150
Output Frequency (dB)
200
10
250
0
50
G005
Figure 5. DAC3154 SFDR vs Output Frequency Over Input
Scale
100
150
Output Frequency (dB)
200
250
G006
Figure 6. DAC3154 Second-Order Harmonic Distortion vs
Output Frequency Over Input Scale
100
100
0dBFS
−6dBFS
−12dBFS
90
80
80
SFDR (dBc)
60
50
40
70
60
50
30
40
20
30
0
50
100
150
Output Frequency (dB)
200
fDAC = 200 MSPS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
90
70
HD3 (dBc)
800
90
HD2 (dBc)
SFDR (dBc)
80
250
20
0
G007
Figure 7. DAC3154 Third-Order Harmonic Distortion vs
Output Frequency Over Input Scale
14
600
Code
100
0dBFS
−6dBFS
−12dBFS
90
10
400
Figure 4. DAC3154 Differential Nonlinearity
100
10
200
G003
50
100
150
Output Frequency (MHz)
200
250
G008
Figure 8. DAC3154 SFDR vs Output Frequency Over fDAC
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SLAS960 – MAY 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA fullscale output current (unless otherwise noted).
100
100
0dBFS
−6dBFS
−12dBFS
90
80
70
IMD3 (dBc)
IMD3 (dBc)
80
60
50
40
60
50
40
20
30
0
50
100
150
Output Frequency (dB)
200
20
250
50
100
150
Output Frequency (MHz)
G010
fDAC = 200 MSPS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
160
150
NSD (dBc/Hz)
150
140
130
140
130
120
120
110
110
0
50
100
150
Output Frequency (dB)
200
100
250
0
100
Output Frequency (MHz)
G011
Figure 11. DAC3154 NSD vs Output Frequency Over Input
Scale
200
250
G012
Figure 12. DAC3154 NSD vs Output Frequency Over fDAC
−50
−50
Adjacent channel
Alternate channel
−60
ACLR (dBc)
−60
ACLR (dBc)
250
170
0dBFS
−6dBFS
−12dBFS
160
−70
−80
−90
−70
−80
−90
fDAC = 500 MSPS
−100
200
Figure 10. DAC3154 IMD3 vs Output Frequency Over fDAC
170
100
0
G009
Figure 9. DAC3154 IMD3 vs Output Frequency Over Input
Scale
NSD (dBc/Hz)
70
30
10
fDAC = 200 MSPS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
90
0
50
fDAC = 500 MSPS
100
150
Output Frequency (MHz)
200
250
−100
0
G013
Figure 13. DAC3154 ACLR (Adjacent Channel) vs Output
Frequency
50
100
150
Output Frequency (MHz)
200
250
G012
Figure 14. DAC3154 ACLR (Alternate Channel) vs Output
Frequency
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA fullscale output current (unless otherwise noted).
10
10
fDAC = 491. 52MSPS
fout = 20 MHz
−10
−10
−20
−20
−30
−40
−50
−30
−40
−50
−60
−60
−70
−70
−80
−80
−90
10
50
90
130
170
Frequency (MHz)
210
−90
250
−10
130
170
Frequency (MHz)
210
250
G016
fDAC = 500 MSPS
fout = 70 MHz
Tone spacing = 1 MHz
0
−10
−20
Power (dBm)
−20
−30
−40
−50
−60
−30
−40
−50
−60
−70
−70
−80
−80
−90
−90
−100
−100
15
17
19
21
Frequency (MHz)
23
25
-20 dBm
* Att
5 dB
* RBW
30 kHz
* VBW
300 kHz
* SWT
2 s
65
67
69
71
Frequency (MHz)
G017
Figure 17. DAC3154 Two-Tone Spectral Plot (IF = 20MHz)
73
75
G018
Figure 18. DAC3154 Two-Tone Spectral Plot (IF = 70MHz)
Ref
-10 dBm
* Att
5 dB
* RBW
30 kHz
* VBW
300 kHz
* SWT
2 s
-20
-30
A
-40
A
-30
-40
-50
1 RM *
1 RM *
-60
CLRWR
-50
-60
-70
-70
-80
NOR
-90
3DB
-110
Center
NOR
-80
-90
-100
70 MHz
Standard:
4.08 MHz/
W-CDMA
3GPP
FWD
Adjacent
Span
40.8 MHz
Tx
Channel
3DB
-100
Center
70 MHz
1.55 MHz/
Channel
Lower
Upper
Channels
Ch1
(Ref)
-18.62 dBm
Ch2
-18.64 dBm
Ch3
-18.72 dBm
Ch4
-18.70 dBm
Total
Alternate
Lower
Upper
-61.24 dB
-61.34 dB
Channel
Adjacent
Span
W-CDMA
Bandwidth
Tx
3.84
MHz
3.84
MHz
5
MHz
Channel
Bandwidth
Spacing
3GPP
15.5 MHz
FWD
Power
-10.64 dBm
Lower
Upper
-69.11 dB
-69.15 dB
-61.11 dB
-61.39 dB
-12.65 dBm
Figure 19. DAC3154 ACPR Four-Carrier
WCDMA Test Mode 1
16
90
10
fDAC = 500 MSPS
fout = 20 MHz
Tone spacing = 1 MHz
0
Power (dBm)
50
Figure 16. DAC3154 Single-Tone Spectral Plot (IF = 70MHz)
10
CLRWR
10
G011
Figure 15. DAC3154 Single-Tone Spectral Plot (IF = 20MHz)
Ref
fDAC = 491. 52MSPS
fout = 70 MHz
0
Power (dBm)
Power (dBm)
0
Figure 20. DAC3154 ACPR Single-Carrier
WCDMA Test Mode 1
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SLAS960 – MAY 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA fullscale output current (unless otherwise noted).
Ref
* Att
-10 dBm
5 dB
* RBW
30 kHz
* VBW
300 kHz
* SWT
2 s
Ref
A
-30
* RBW
30 kHz
* VBW
300 kHz
* SWT
2 s
A
-30
-40
-40
1 RM *
1 RM *
CLRWR
-50
-50
-60
-60
-70
-70
NOR
-80
NOR
-80
-90
-90
70 MHz
2.92827419 MHz/
Channel
E-UTRA/LTE
Bandwidth
Adjacent
Span
9.015
MHz
9.015
MHz
10
MHz
Channel
Bandwidth
Spacing
Center
29.2827419 MHz
Tx
Square
Power
-12.33 dBm
Lower
Upper
-64.00 dB
-64.09 dB
3DB
-100
3DB
-100
Center
Tx
5 dB
-20
-20
CLRWR
* Att
-10 dBm
70 MHz
5.855034538 MHz/
Channel
E-UTRA/LTE
Bandwidth
Adjacent
18.015
MHz
18.015
MHz
20
MHz
Channel
Bandwidth
Spacing
Figure 21. DAC3154 ACPR LTE 10-MHz FDD E-TM 1.1
Span
58.55034538 MHz
Square
Power
-11.14 dBm
Lower
Upper
-61.93 dB
-62.21 dB
Figure 22. DAC3154 ACPR LTE 20-MHz FDD E-TM 1.1
600
Power (mW)
500
400
300
200
QMC on
100
200
300
400
500
fDAC (MSPS)
G023
Figure 23. DAC3154 Power Consumption vs fDAC
0.4
0.2
0.3
0.15
0.2
0.1
DNL (LSB)
INL (LSB)
0.1
0
−0.1
−0.2
−0.3
0
−0.05
−0.1
−0.4
−0.15
−0.5
−0.6
0.05
0
500
1000
1500
2000 2500
Code
3000
3500
4000
−0.2
0
500
G024
Figure 24. DAC3164 Integral Nonlinearity
1000
1500
2000 2500
Code
3000
3500
4000
G025
Figure 25. DAC3164 Differential Nonlinearity
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA fullscale output current (unless otherwise noted).
100
100
0dBFS
−6dBFS
−12dBFS
90
80
70
70
HD2 (dBc)
SFDR (dBc)
80
60
50
30
30
20
20
0
50
100
150
Output Frequency (dB)
200
10
250
200
250
G027
80
SFDR (dBc)
60
50
40
70
60
50
30
40
20
30
0
50
100
150
Output Frequency (dB)
200
fDAC = 200 MSPS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
90
70
HD3 (dBc)
100
150
Output Frequency (dB)
100
80
20
250
0
50
G028
Figure 28. DAC3164 Third-Order Harmonic Distortion vs
Output Frequency Over Input Scale
100
150
Output Frequency (MHz)
200
250
G029
Figure 29. DAC3164 SFDR vs Output Frequency Over fDAC
100
100
0dBFS
−6dBFS
−12dBFS
90
80
80
IMD3 (dBc)
60
50
40
70
60
50
30
40
20
30
0
50
100
150
Output Frequency (dB)
200
fDAC = 200 MSPS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
90
70
10
50
Figure 27. DAC3164 Second-Order Harmonic Distortion vs
Output Frequency Over Input Scale
0dBFS
−6dBFS
−12dBFS
90
10
0
G026
100
IMD3 (dBc)
50
40
Figure 26. DAC3164 SFDR vs Output Frequency Over Input
Scale
250
20
0
G030
Figure 30. DAC3164 IMD3 vs Output Frequency Over Input
Scale
18
60
40
10
0dBFS
−6dBFS
−12dBFS
90
50
100
150
Output Frequency (MHz)
200
250
G031
Figure 31. DAC3164 IMD3 vs Output Frequency Over fDAC
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SLAS960 – MAY 2013
TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA fullscale output current (unless otherwise noted).
180
180
0dBFS
−6dBFS
−12dBFS
170
160
NSD (dBc/Hz)
NSD (dBc/Hz)
160
150
140
150
140
130
130
120
120
110
fDAC = 200 MSPS
fDAC = 300 MSPS
fDAC = 400 MSPS
fDAC = 500 MSPS
170
0
50
100
150
Output Frequency (dB)
200
110
250
0
100
Output Frequency (MHz)
G032
Figure 32. DAC3164 NSD vs Output Frequency Over Input
Scale
Alternate channel
−60
ACLR (dBc)
ACLR (dBc)
−60
−70
−80
−90
−70
−80
−90
fDAC = 500 MSPS
0
50
fDAC = 500 MSPS
100
150
Output Frequency (MHz)
200
−100
250
0
50
G034
Figure 34. DAC3164 ACLR (Adjacent Channel) vs Output
Frequency
100
150
Output Frequency (MHz)
200
250
G035
Figure 35. DAC3164 ACLR (Alternate Channel) vs Output
Frequency
10
10
fDAC = 491. 52MSPS
fout = 20 MHz
0
−10
−10
−20
−20
−30
−40
−50
−30
−40
−50
−60
−60
−70
−70
−80
−80
10
50
90
130
170
Frequency (MHz)
210
fDAC = 491. 52MSPS
fout = 70 MHz
0
Power (dBm)
Power (dBm)
G033
−50
Adjacent channel
−90
250
Figure 33. DAC3164 NSD vs Output Frequency Over fDAC
−50
−100
200
250
−90
10
G036
Figure 36. DAC3164 Single-Tone Spectral Plot (IF = 20MHz)
50
90
130
170
Frequency (MHz)
210
250
G037
Figure 37. DAC3164 Single-Tone Spectral Plot (IF = 70MHz)
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA fullscale output current (unless otherwise noted).
10
10
fDAC = 500 MSPS
fout = 20 MHz
Tone spacing = 1 MHz
0
−10
−10
−20
Power (dBm)
Power (dBm)
−20
−30
−40
−50
−60
−40
−50
−60
−70
−80
−80
−90
−90
−100
−100
15
17
19
21
Frequency (MHz)
23
25
-10 dBm
* Att
5 dB
* RBW
30 kHz
* VBW
300 kHz
* SWT
2 s
65
Ref
73
75
G039
-10 dBm
* Att
5 dB
* RBW
30 kHz
* VBW
300 kHz
* SWT
2 s
-20
A
-30
A
-30
-40
-40
1 RM *
1 RM *
-50
CLRWR
-60
-70
NOR
-80
NOR
-80
-90
-90
3DB
-100
Center
70 MHz
Standard:
Tx
-50
-60
-70
4.08 MHz/
W-CDMA
3GPP
Span
Adjacent
FWD
Lower
Upper
Channels
Ch1
-18.70 dBm
(Ref)
Ch2
-18.69 dBm
Ch3
-18.77 dBm
Ch4
-18.75 dBm
Total
3DB
-100
40.8 MHz
Center
Channel
Tx
70 MHz
Ref
Adjacent
W-CDMA
Lower
Upper
3.84
MHz
3.84
MHz
5
MHz
Channel
Spacing
Channel
Span
Channel
Bandwidth
Alternate
3GPP
15.5 MHz
FWD
Power
-10.70 dBm
Lower
Upper
-77.84 dB
-77.14 dB
-70.86 dB
-70.84 dB
-12.71 dBm
* Att
-20 dBm
5 dB
* RBW
30 kHz
* VBW
300 kHz
* SWT
2 s
Figure 41. DAC3164 ACPR Single-Carrier
WCDMA Test Mode 1
Ref
* Att
-20 dBm
5 dB
* RBW
30 kHz
* VBW
300 kHz
* SWT
2 s
-30
-30
A
-40
A
-40
-50
-50
1 RM *
1 RM *
CLRWR
-60
-60
-70
-70
-80
-80
NOR
-90
3DB
-110
Center
NOR
-90
-100
-100
Tx
1.55 MHz/
Bandwidth
-70.74 dB
-70.87 dB
Figure 40. DAC3164 ACPR Four-Carrier
WCDMA Test Mode 1
70 MHz
2.92827419 MHz/
Channel
Bandwidth
Adjacent
Bandwidth
Spacing
Span
E-UTRA/LTE
9.015
MHz
9.015
MHz
10
MHz
Channel
29.2827419 MHz
Square
Power
-12.37 dBm
Lower
Upper
-73.67 dB
-73.46 dB
Figure 42. DAC3164 ACPR LTE 10-MHz FDD E-TM 1.1
20
69
71
Frequency (MHz)
Figure 39. DAC3164 Two-Tone Spectral Plot (IF = 70MHz)
-20
CLRWR
67
G038
Figure 38. DAC3164 Two-Tone Spectral Plot (IF = 20MHz)
CLRWR
−30
−70
Ref
fDAC = 500 MSPS
fout = 70 MHz
Tone spacing = 1 MHz
0
3DB
-110
Center
Tx
70 MHz
5.855034538 MHz/
Channel
Bandwidth
Adjacent
E-UTRA/LTE
18.015
MHz
Channel
Bandwidth
Spacing
Span
18.015
MHz
20
MHz
58.55034538 MHz
Square
Power
-11.20 dBm
Lower
Upper
-70.91 dB
-70.66 dB
Figure 43. DAC3164 ACPR LTE 20-MHz FDD E-TM 1.1
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TYPICAL CHARACTERISTICS (continued)
All plots are at 25°C, nominal supply voltages, fDAC = 500MSPS, 50% clock duty cycle, 0-dBFS input signal and 20mA fullscale output current (unless otherwise noted).
600
Power (mW)
500
400
300
200
QMC on
100
200
300
400
500
fDAC (MSPS)
G044
Figure 44. DAC3164 Power Consumption vs fDAC
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DEFINITION OF SPECIFICATIONS
Adjacent Carrier Leakage Ratio (ACLR): Defined as the ratio in decible relative to the carrier (dBc) between
the measured power within the channel and that of its adjacent channel.
Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the
ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current.
Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSB
change in the digital input code.
Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the
value at ambient (25°C) to values over the full operating temperature range.
Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output
current and the ideal full-scale output current.
Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output,
determined by a straight line drawn from zero scale to full scale.
Intermodulation Distortion (IMD3): The two-tone IMD3 is defined as the ratio (in dBc) of the 3rd-order
intermodulation distortion product to either fundamental output tone.
Offset Drift: Defined as the maximum change in DC offset, in terms of ppm of full-scale range (FSR) per °C,
from the value at ambient (25°C) to values over the full operating temperature range.
Offset Error: Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output
current and the ideal mid-scale output current.
Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the
current-output DAC. Exceeding this limit may result reduced reliability of the device or adversely affecting
distortion performance.
Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsius
from value at ambient (25°C) to values over the full operating temperature range.
Spurious Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the
output signal and the peak spurious signal.
Signal to Noise Ratio (SNR): Defined as the ratio of the RMS value of the fundamental output signal to the
RMS sum of all other spectral components below the Nyquist frequency, including noise, but excluding the first
six harmonics and dc.
TIMING DIAGRAMS
D[9:0]P/N
A3[9:0]
B3[9:0]
ts(DATA)
A4[9:0]
B4[9:0]
th(DATA)
A5[9:0]
B5[9:0]
ts(DATA)
A6[9:0]
B6[9:0]
A7[9:0]
B7[9:0]
th(DATA)
DATACLKP/N
(DDR)
ts(DATA)
SYNCP/N
th(DATA)
Resets write pointer to position 0
Figure 45. DAC3154 Input Timing Diagram for Dual Channel DDR Mode
22
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D[9:0]P/N
A3[9:0]
A4[9:0]
ts(DATA)
A5[9:0]
A6[9:0]
A7[9:0]
A8[9:0]
A9[9:0]
A10[9:0]
A11[9:0]
th(DATA)
DATACLKP/N
(SDR)
ts(DATA)
SYNCP/N
th(DATA)
Resets write pointer to position 0
Figure 46. DAC3154 Input Timing Diagram for Single Channel SDR Mode
D[11:0]P/N
A3[11:0] B3[11:0] A4[11:0] B4[11:0] A5[11:0] B5[11:0] A6[11:0] B6[11:0] A7[11:0] B7[11:0]
ts(DATA)
th(DATA)
ts(DATA)
th(DATA)
DATACLKP/N
(DDR)
ts(DATA)
SYNCP/N
th(DATA)
Resets write pointer to position 0
Figure 47. DAC3164 Input Timing Diagram for Dual Channel DDR Mode
D[11:0]P/N
A3[11:0] A4[11:0] A5[11:0] A6[11:0] A7[11:0] A8[11:0] A9[11:0] A10[11:0] A11[11:0]
ts(DATA)
th(DATA)
DATACLKP/N
(SDR)
ts(DATA)
SYNCP/N
th(DATA)
Resets write pointer to position 0
Figure 48. DAC3164 Input Timing Diagram for Single Channel SDR Mode
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DATA INPUT FORMATS
Table 1. DAC3154 Dual Channel DDR Mode
BITS
DIFFERENTIAL PAIR (P/N)
DATACLK RISING EDGE
DATACLK FALLING EDGE
D9
A9
B9
D8
A8
B8
D7
A7
B7
D6
A6
B6
D5
A5
B5
D4
A4
B4
D3
A3
B3
D2
A2
B2
D1
A1
B1
D0
A0
B0
SYNC
FIFO Write Reset
–
Table 2. DAC3154 Single Channel SDR Mode
BITS
DIFFERENTIAL PAIR (P/N)
DATACLK RISING EDGE
D9
A9
D8
A8
D7
A7
D6
A6
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
D0
A0
SYNC
FIFO Write Reset
DATACLK FALLING EDGE
–
Table 3. DAC3164 Dual Channel DDR Mode
BITS
24
DIFFERENTIAL PAIR (P/N)
DATACLK RISING EDGE
DATACLK FALLING EDGE
D11
A11
B11
D10
A10
B10
D9
A9
B9
D8
A8
B8
D7
A7
B7
D6
A6
B6
D5
A5
B5
D4
A4
B4
D3
A3
B3
D2
A2
B2
D1
A1
B1
D0
A0
B0
SYNC
FIFO Write Reset
–
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Table 4. DAC3164 Single Channel DDR Mode
BITS
DIFFERENTIAL PAIR (P/N)
DATACLK RISING EDGE
D11
A11
D10
A10
D9
A9
D8
A8
D7
A7
D6
A6
D5
A5
D4
A4
D3
A3
D2
A2
D1
A1
D0
A0
SYNC
FIFO Write Reset
DATACLK FALLING EDGE
–
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SERIAL INTERFACE DESCRIPTION
The serial port of the DAC3154/DAC3164 is a flexible serial interface which communicates with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of DAC3154/DAC3164. It is compatible with most synchronous transfer formats and can be
configured as a 3 or 4 pin interface by sif4_ena in register config0, bit9. In both configurations, SCLK is the serial
interface input clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for
both data in and data out. For 4 pin configuration, SDIO is data in only and SDO is data out only. Data is input
into the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.
Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low. The first frame byte
is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit
address to be accessed. Table 5 indicates the function of each bit in the instruction cycle and is followed by a
detailed description of each bit. The data transfer cycle consists of two bytes.
Table 5. Instruction byte of the Serial interface
MSB
Bit
Description
LSB
7
R/W
6
A6
5
A5
4
A4
3
A3
2
A2
1
A1
0
A0
R/W
Identifies the following data transfer cycle as a read or write operation. A high indicates a read
operation from DAC3154/DAC3164 and a low indicates a write operation to DAC3154/DAC3164.
[A6 : A0]
Identifies the address of the register to be accessed during the read or write operation.
Figure 49 shows the serial interface timing diagram for a DAC3154/DAC3164 write operation. SCLK is the serial
interface clock input to DAC3154/DAC3164. Serial data enable SDENB is an active low input to
DAC3154/DAC3164. SDIO is serial data in. Input data to DAC3154/DAC3164 is clocked on the rising edges of
SCLK.
Instruction Cycle
Data Transfer Cycle
SDENB
SCLK
SDIO
rwb
A6
A5
A4
A3
A2
tS (SDENB)
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t SCLK
SDENB
SCLK
SDIO
tS(SDIO) tH(SDIO)
Figure 49. Serial Interface Write Timing Diagram
Figure 50 shows the serial interface timing diagram for a DAC3154/DAC3164 read operation. SCLK is the serial
interface clock input to DAC3154/DAC3164. Serial data enable SDENB is an active low input to
DAC3154/DAC3164. SDIO is serial data in during the instruction cycle. In 3 pin configuration, SDIO is data out
from the DAC3154/DAC3164 during the data transfer cycle, while SDO is in a high-impedance state. In 4 pin
configuration, both SDIO and SDO are data out from the DAC3154/DAC3164 during the data transfer cycle. At
the end of the data transfer, SDIO and SDO will output low on the final falling edge of SCLK until the rising edge
of SDENB when they will 3-state.
26
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Instruction Cycle
Data Transfer Cycle
SDENB
SCLK
SDIO
rwb
A6
A5
A4
A3
A2
A1
SDO
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDENB
SCLK
SDIO
SDO
Data n
Data n-1
td (Data)
Figure 50. Serial Interface Read Timing Diagram
REGISTER DESCRIPTIONS
In the SIF interface there are four types of registers:
NORMAL:
The NORMAL register type allows data to be written and read from. All 16-bits of the data are
registered at the same time. There is no synchronizing with an internal clock thus all register
writes are asynchronous with respect to internal clocks. There are three subtypes of NORMAL:
AUTOSYNC:
A NORMAL register that causes a sync to be generated after the write is
finished. These are most commonly used in things like offsets and phaseadd
where there is a word or block setup that extends across multiple registers
and all of the registers need to be programmed before any take effect on the
circuit. For example, the phaseadd is two registers long. It wouldn’t serve the
user to have the first write 16 of the 32 bits cause a change in the frequency,
so the design allows all the registers to be written and then when that last
one for this block is finished, an autosync is generated for the mixer telling it
to grab all the new SIF values. This will occur on a mixer clock cycle so that
no meta-stability errors occur.
No RESET Value: These are NORMAL registers, but for one reason or another reset value can
not be guaranteed. This could be because the register has some read_only
bits or some internal logic partially controls the bit values. An example is the
SIF_CONFIG6 register. The bits come from the temperature sensor and the
fuses. Depending on which fuses are blown and what the die temp is the
reset value will be different.
FUSE controlled:
READ_ONLY:
While this isn’t a type of register, you may see this description in the area
describing the default value for the register. What is means is that fuses will
change the default value and the value shown in the document is for when
no fuses are blown.
Registers that are internal wires ANDed with the address bus then connected to the SIF
output data bus.
WRITE_TO_CLEAR: These registers are just like NORMAL registers with one exception. They can be written
and read, however, when the internal logic asynchronously sets a bit high in one of
these registers, that bit stays high until it is written to ‘0’. This way interrupts will be
captured and stay constant until cleared by the user.
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Table 6. Register Map
(MSB)
Bit 15
Name
Address
Default
Bit 14
config0
0x00
0x44FC
qmc_
offset_ena
dual_ ena
config1
0x01
0x600E
iotest_ena
bsideclk_e
na
config2
0x02
0x3FFF
config3
0x03
0x0000
config4
0x04
0x0000
config5
0x05
0x0000
config6
0x06
0x0084(D
AC3164)
0x0088(D
AC3154)
config7
0x07
0xFFFF
config8
0x08
0x4000
reserved
config9
0x09
0x8000
fifo_offset (2:0)
config10
0x0A
0xF080
Bit 13
Bit 12
chipwidth (1:0)
fullword_i
nterface_
ena
64cnt_ena
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
reserved
twos
sif4_ena
reserve
d
fifo_ ena
alarm_
out_ena
alarm_
out_pol
alignrx_en
a
syncrx_en
a
lvdsdataclk_
ena
reserved
synconly_en
a
dacclkgon
e_ ena
dataclkgone
_ena
collision_ena
reserve
d
daca_
compliment
dacb_
complime
nt
sif_sync
sif_
sync_ena
alarm_
2away_en
a
alarm_1awa
y_ena
alarm_coll
ision _ena
reserved
reserved
lvdsdata_ena (13:0)
datadlya (2:0)
clkdlya (2:0)
datadlyb (2:0)
reserved
alarm_fro
m_
zerochka
clkdlyb (2:0)
extref_ena
reserved
dual_ena
iotest_results (13:0)
alarm_fro
m_
zerochkb
alarms_from_fifoa (2:0)
alarms_from_fifob (2:0)
alarm_dacclk
_ gone
alarm_dat
aclk_
gone
clock_gon
e
tempdata (7:0)
alarm_fro
m_ iotesta
alarm_fro
m_ iotestb
reserved
fuse_cntl (5:0)
reserved
alarms_mask (15:0)
qmc_offseta (12:0)
qmc_offsetb (12:0)
coarse_dac (3:0)
fuse_
sleep
reserved
reserved
reserved
tsense_
sleep
clkrecv_ena
sleepa
config11
0x0B
0x1111
config12
0x0C
0x3A7A
reserved
iotest_pattern0 (13:0)
config13
0x0D
0x36B6
reserved
iotest_pattern1 (13:0)
config14
0x0E
0x2AEA
reserved
iotest_pattern2 (13:0)
config15
0x0F
0x0545
reserved
iotest_pattern3 (13:0)
config16
0x10
0x1A1A
reserved
iotest_pattern4 (13:0)
config17
0x11
0x1616
reserved
iotest_pattern5 (13:0)
config18
0x12
0x2AAA
reserved
iotest_pattern6 (13:0)
config19
0x13
0x06C6
reserved
iotest_pattern7 (13:0)
config20
0x14
0x0000
config21
0x15
0xFFFF
sleepcntl (15:0)
config22
0x16
0x0000
fa002_data(15:0)
config23
0x17
0x0000
fa002_data(31:16)
config24
0x18
0x0000
fa002_data(47:32)
config25
0x19
0x0000
config127
0x7F
0x0044
28
(LSB)
Bit 0
Bit 11
sifdac_
ena
reserved
sleepb
reserved
reserved
reserved
reserved
sifdac (13:0)
fa002_data(63:48)
reserved
reserved
reserved
reserved
reserved
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titest_vol
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Register name: config0 – Address: 0x00, Default: 0x44FC
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config0
0x00
15
qmc_offset_ena
Enable the offset function when asserted.
0
14
dual_ena
Utilizes both DACs when asserted.
1
FUSE
controlled
13:12
chipwidth
Programmable bits for setting the input interface width.
00: all 14 bits are used. NOTE: not applicable to
DAC3154/DAC3164.
01: upper 12 bits are used 10: upper 10 bits are used
11: upper 10 bits are used
00
11
reserved
reserved
0
10
twos
When asserted, this bit tells the chip to presume 2’s
complement data is arriving at the input. Otherwise offset
binary is presumed.
1
9
sif4_ena
When asserted the SIF interface becomes a 4 pin interface.
This bit has a lower priority than the dieid_ena bit.
0
8
reserved
reserved
0
7
fifo_ena
When asserted, the FIFO is absorbing the difference between 1
INPUT clock and DAC clock. If it is not asserted then the
FIFO buffering is bypassed but the reversing of bits and
handling of offset binary input is still available. NOTE: When
the FIFO is bypassed the DACCCLK and DATACLK must
be aligned or there may be timing errors; and, it is not
recommended for actual application use.
6
alarm_out_ena
When asserted the pin alarm becomes an output instead of a
tri-stated pin.
1
5
alarm_out_pol
This bit changes the polarity of the ALARM signal.
(0=negative logic, 1=positive logic)
1
4
alignrx_ena
When asserted the ALIGN pin receiver is powered up. NOTE: 1
It is recommended to clear this bit when ALIGNP/N are
not used.
3
syncrx_ena
When asserted the SYNC pin receiver is powered up. NOTE:
It is recommended to clear this bit when SYNCP/N are
not used.
1
2
lvdsdataclk_ena
When asserted the DATACLK pin receiver is powered up.
1
1
reserved
reserved
0
0
synconly_ena
When asserted the chip is put into the SYNC ONLY mode
where the SYNC pin is used as the sync input for both the
front and back of the FIFO.
0
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Register name: config1 – Address: 0x01, Default: 0x600E
Register
Name
Addr
(Hex)
Bit
Name
Function
Default
Value
config1
0x01
15
iotest_ena
Turns on the io-testing circuitry when asserted. This is the circuitry
that will compare a 8 sample input pattern to SIF programmed
registers to make sure the data coming into the chip meets
setup/hold requirements. If this bit is a ‘0’ then the clock to this
circuitry is turned off for power savings. NOTE: Sample 0 should
be aligned with the rising edge of SYNC.
0
14
bsideclk_ena
When asserted the input clock for the B side datapath is enabled.
Otherwise the IO TEST and the FIFO on the B side of the design
will not get a clock.
1
13
reserved
reserved.
1
12
64cnt_ena
This enables the resetting of the alarms after 64 good samples with 0
the goal of removing unnecessary errors. For instance on a lab
board, when checking the setup/hold through IO TEST, there may
initially be errors, but once the test is up and running everything
works. Setting this bit removes the need for a SIF write to clear the
alarm register.
11
dacclkgone_ena
This allows the DACCLK gone signal from the clock monitor to be
used to shut the output off.
0
10
dataclkgone_end
This allows the DATACLK gone signal from the clock monitor to be
used to shut the output off.
0
9
collision_ena
This allows the collision alarm from the FIFO to shut the output off
0
8
reserved
reserved.
0
7
daca_compliment
When asserted the output to the DACA is complimented. This
allows the user of the chip to effectively change the + and –
designations of the DAC output pins.
0
6
dacb_compliment
When asserted the output to the DACB is complimented. This
allows the user of the chip to effectively change the + and –
designations of the DAC output pins.
0
5
sif_sync
This is the SIF_SYNC signal. Whatever is programmed into this bit
will be used as the chip sync when SIF_SYNC mode is enabled.
Design is sensitive to rising edges so programming from 0->1 is
when the sync pulse is generated. 1->0 has no effect.
0
4
sif_sync_ena
When asserted enable SIF_SYNC mode.
0
3
alarm_2away_ena
When asserted alarms from the FIFO that represent the pointers
being 2 away are enabled
1
2
alarm_1away_ena
When asserted alarms from the FIFO that represent the pointers
being 1 away are enabled
1
1
alarm_collision_ena
When asserted the collision of FIFO pointers causes an alarm to be 1
generated
0
reserved
reserved
0
Register name: config2 – Address: 0x02, Default: 0x3FFF
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config2
0x02
15
reserved
reserved
0
14
reserved
reserved
0
13:0
lvdsdata_ena
These 14 bits are individual enables for the 14 input pin receivers.
NOTE: It is recommended to clear bit (1:0) for the 12-bit
DAC3164, and clear bit (3:0) for the 10-bit DAC3154.
0x3FFF
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Register name: config3 – Address: 0x03, Default: 0x0000
Register
Name
Addr
(Hex)
Bit
Name
Function
config3
0x03
15:13
datadlya
Controls the delay of the A data inputs through the LVDS receivers. 000
0= no additional delay and each LSB adds a nominal 80ps.
12:10
clkdlya
Controls the delay of the A data clock input through the LVDS
receivers. 0= no additional delay and each LSB adds a nominal
80ps.
9:7
datadlyb
Controls the delay of the B data inputs through the LVDS receivers. 000
0= no additional delay and each LSB adds a nominal 80ps.
6:4
clkdlyb
Controls the delay of the B data clock input through the LVDS
receivers. 0= no additional delay and each LSB adds a nominal
80ps.
000
3
extref_ena
Enable external reference for the DAC when set.
0
2:1
reserved
reserved
00
0
dual_clock_ena
When asserted it tells the LVDS input circuit that there are two
individual data clocks. NOTE: must be in SIF_SYNC mode, and
not applicable to DAC3154/DAC3164.
0
Default Value
000
Register name: config4 – Address: 0x04, Default: 0x0000
Register
Name
Addr
(Hex)
Bit
Name
Function
Default
Value
config4
WRITE TO
CLEAR/
No RESET
value
0x04
15:14
reserved
reserved
00
13:0
iotest_ results
The values of these bits tell which bit in the input word failed during the
io-test pattern comparison. Bit 13 corresponds to the MSB input.
0x0000
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Register name: config5 – Address: 0x05, Default: 0x0000
Register
Name
Addr
(Hex)
Bit
Name
Function
config5
WRITE TO
CLEAR
0x05
15
alarm_from_ zerochka
When this bit is asserted the FIFO A write pointer has an all zeros
pattern in it. Since this pointer is a shift register, all zeros will cause
the input point to be stuck until the next sync. The result could be a
repeated 8T pattern at the output if the mixer is off and no syncs
occur. Check for this error will tell the user that another sync is
necessary to restart the FIFO write pointer.
0
14
alarm_from_ zerochkb
When this bit is asserted the FIFO B write pointer has an all zeros
pattern in it. Since this pointer is a shift register, all zeros will cause
the input point to be stuck until the next sync. The result could be a
repeated 8T pattern at the output if the mixer is off and no syncs
occur. Check for this error will tell the user that another sync is
necessary to restart the FIFO write pointer.
0
13:11
alarms_from_ fifoa
These bits report the FIFO A pointer status.
000: All fine
001: Pointers are 2 away
01X: Pointers are 1 away
1XX: FIFO Pointer collision
000
10:8
alarms_from_ fifob
These bits report the FIFO B pointer status.
000: All fine
001: Pointers are 2 away
01X: Pointers are 1 away
1XX: FIFO Pointer collision
0
7
alarm_dacclk_ gone
Bit gets asserted when the DACCLK has been stopped long for
enough cycles to be caught. The number of cycles varies with
interpolation.
0
6
alarm_dataclk_ gone
Bit gets asserted when the DATACLK has been stopped long for
enough cycles to be caught. The number of cycles varies with
interpolation.
0
5
clock_gone
This bit gets set when either alarm_dacclk_gone or
alarm_dataclk_gone are asserted. It controls the output of the
CDRV_SER block. When high, the CDRV_SER block will output
“0x8000” for each output connected to a DAC. The bit must be
written to ‘0’ for CDRV_SER outputs to resume normal operation.
0
4
alarm_from_ iotesta
This is asserted when the input data pattern does not match the
pattern in the iotest_pattern registers.
0
3
alarm_from_ iotestb
This is asserted when the input data pattern does not match the
pattern in the iotest_pattern registers.
0
2
reserved
reserved
0
1
reserved
reserved
0
0
reserved
reserved
0
32
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Default
Value
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Register name: config6 – Address: 0x06, Default: 0x0084 (DAC3164); 0x0088 (DAC3154)
Register
Name
Addr
(Hex)
Bit
Name
Function
Default
Value
config6
No RESET
Value
0x06
15:8
tempdata
This the output from the chip temperature sensor.
NOTE: when reading these bits the SIF interface must be exteremly
slow, 1MHz range.
0x00
7:2
fuse_cntl
These are the values of the blown fuses and are used to determine the
available functionality in the chip.
NOTE: These bits are READ_ONLY and allow the user to check
what features have been disabled in the device.
bit5 = 1: Force full word interface.
bit4 = 1: reserved
bit3 = 1: reserved
bit2 = 1: Forces Single DAC Mode. Note: This does not force the
channel B in sleep mode. In order to do so, user needs to program
the sleepb SPI bit (config10, bit 5) to "1".
bit1:0 : Forces a different bits size.
“00” 14bit.
“01” 12bit
“10” 10bit
“11” 10bit
0x21 for
DAC3164;
0x22 for
DAC3154
1
reserved
reserved
0
0
reserved
reserved
0
Register name: config7 – Address: 0x07, Default: 0xFFFF
Register
Name
Addr
(Hex)
Bit
Name
Function
Default
Value
config7
0x07
15:0
alarms_ mask
Each bit is used to mask an alarm. Assertion masks the alarm: bit15 =
alarm_mask_zerochka
bit14 = alarm_mask_zerochkb
bit13 = alarm_mask_fifoa_collision
bit12 = alarm_mask_fifoa_1away
bit11 = alarm_mask_fifoa_2away
bit10 = alarm_mask_fifob_collision
bit9 = alarm_mask_fifob_1away
bit8 = alarm_mask_fifob_2away
bit7 = alarm_mask_dacclk_gone
bit6 = alarm_mask_dataclk_gone
bit5 = Masks the signal which turns off the DAC output when a clock or
collision occurs. This bit has no effect on the PAD_ALARM output.
bit4 = alarm_mask_iotesta
bit3 = alarm_mask_iotestb
bit2 =
bit1 =
bit0 =
0xFFFF
Register name: config8 – Address: 0x08, Default: 0x4000
Register
Name
Addr
(Hex)
Bit
Name
Function
Default
Value
config8
0x08
15:13
reserved
reserved
010
12:0
qmc_ offseta
The DAC A offset correction. The offset is measured in DAC LSBs.
0x0000
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Register name: config9 – Address: 0x09, Default: 0x8000
Register
Name
Addr
(Hex)
Bit
Name
Function
Default
Value
config9
AUTO
SYNC
0x09
15:13
fifo_ offset
This is the starting point for the READ_POINTER in the FIFO block.
The READ_POINTER is set to this location when a sync occurs on the
DACCLK side of the FIFO.
100
12:0
qmc_ offsetb
The DAC B offset correction. The offset is measured in DAC LSBs.
NOTE: Writing this register causes an autosync to be generated in
the QMOFFSET block.
0x0000
Register name: config10 – Address: 0x0A, Default: 0xF080
Register
Name
Addr
(Hex)
Bit
Name
Function
Default
Value
Config10
0x0A
15:12
coarse_ dac
Scales the output current is 16 equal steps.
1111
VrefIO
Rbias
´ (mem_coarse_daca + 1)
11
fuse_ sleep
Put the fuses to sleep when set high.
0
10
reserved
reserved
0
9
reserved
reserved
0
8
tsense_ sleep
When asserted the temperature sensor is put to sleep.
0
7
clkrecv_ena
Turn on the DAC CLOCK receiver block when asserted.
1
6
sleepa
When asserted DACA is put to sleep.
0
5
sleepb
When asserted DACB is put to sleep. Note: This bit needs to be
programmed to "1" for single DAC mode.
0
4:0
reserved
reserved
00000
Register name: config11 – Address: 0x0B, Default: 0x1111
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config11
0x0B
15:12
reserved
reserved
0001
11:8
reserved
reserved
0001
7:4
reserved
reserved
0001
3:0
reserved
reserved
0001
Register name: config12 – Address: 0x0C, Default: 0x3A7A
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config12
0x0C
15:14
reserved
reserved
00
13:0
iotest_ pattern0
This is dataword0 in the IO test pattern. It is used with the seven
other words to test the input data. NOTE: This word should be
aligned with the rising edge of SYNC when testing the IO
interface.
0x3A7A
Register name: config13 – Address: 0x0D, Default: 0x36B6
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config13
0x0D
15:14
reserved
reserved
00
13:0
iotest_ pattern1
This is dataword1 in the IO test pattern. It is used with the seven
other words to test the input data.
0x36B6
34
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Register name: config14 – Address: 0x0E, Default: 0x2AEA
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config14
0x0E
15:14
reserved
reserved
00
13:0
iotest_ pattern2
This is dataword2 in the IO test pattern. It is used with the seven
other words to test the input data.
0x2AEA
Register name: config15 – Address: 0x0F, Default: 0x0545
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config15
0x0F
15:14
reserved
reserved
00
13:0
iotest_ pattern3
This is dataword3 in the IO test pattern. It is used with the seven
other words to test the input data.
0x0545
Register name: config16 – Address: 0x10, Default: 0x1A1A
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config16
0x10
15:14
reserved
reserved
00
13:0
iotest_ pattern4
This is dataword4 in the IO test pattern. It is used with the seven
other words to test the input data.
0x1A1A
Register name: config17 – Address: 0x11, Default: 0x1616
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config17
0x11
15:14
reserved
reserved
00
13:0
iotest_ pattern5
This is dataword5 in the IO test pattern. It is used with the seven
other words to test the input data.
0x1616
Register name: config18 – Address: 0x12, Default: 0x2AAA
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config18
0x12
15:14
reserved
reserved
00
13:0
iotest_ pattern5
This is datawor6 in the IO test pattern. It is used with the seven
other words to test the input data.
0x2AAA
Register name: config19 – Address: 0x13, Default: 0x06C6
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config19
0x13
15:14
reserved
reserved
00
13:0
iotest_ pattern7
This is dataword7 in the IO test pattern. It is used with the seven
other words to test the input data.
0x06C6
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Register name: config20– Address: 0x14, Default: 0x0000
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config20
0x14
15
sifdac_ ena
When asserted the DAC output is set to the value in sifdac. This
can be used for trim setting and other static tests.
0
14
reserved
reserved
0
13:0
sifdac
This is the value that is sent to the DACs when sifdac_ena is
asserted.
0x0000
Register name: config21– Address: 0x15, Default: 0xFFFF
Register
Name
Addr
(Hex)
Bit
Name
Function
Default Value
config21
0x15
15:0
sleepcntl
This controls what blocks get sent a SLEEP signal when the
PAD_SLEEP pin is asserted. Programming a ‘1’ in a bit will pass
the SLEEP signal to the appropriate block.
0xFFFF
bit15 = DAC A
bit14 = DAC B
bit13 = FUSE Sleep
bit12 = Temperature Sensor
bit11 = Clock Receiver
bit10 = LVDS DATA Receivers
bit9 = LVDS SYNC Receiver
bit8 = PECL ALIGN Receiver
bit7 = LVDS DATACLK Receiver
bit6 =
bit5 =
bit4 =
bit3 =
bit2 =
bit1 =
bit0 =
Register name: config22– Address: 0x16
Register
Name
Addr
(Hex)
Bit
Name
Function
config22
READ
ONLY
0x16
15:0
fa002_ data(15:0)
Lower 16bits of the DIE ID word
Default Value
Register name: config23– Address: 0x17
Register
Name
Addr
(Hex)
Bit
Name
Function
config23
READ
ONLY
0x17
15:0
fa002_ data(31:16)
Lower middle 16bits of the DIE ID word
Default Value
Register name: config24– Address: 0x18, Default
Register
Name
Addr
(Hex)
Bit
Name
Function
config24
READ
ONLY
0x18
15:0
fa002_ data(47:32)
Upper middle 16bits of the DIE ID word
36
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Default Value
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Register name: config25– Address: 0x19
Register
Name
Addr
(Hex)
Bit
Name
Function
config25
READ
ONLY
0x19
15:0
fa002_ data(63:48)
Upper 16bits of the DIE ID word
Default Value
Register name: config127– Address: 0x7F, Default: 0x0045
Register
Name
Addr
(Hex)
Bit
Name
Function
Default
Value
config127
READ
ONLY/No
RESET
Value
0x7F
15:14
reserved
reserved
00
13:12
reserved
reserved
00
11:10
reserved
reserved
00
9:8
reserved
reserved
00
7
reserved
reserved
0
6
titest_voh
A fixed ‘1’ that can be used to test the Voh at the SIF output.
1
5
titest_vol
A fixed ‘0’ that can be used to test the Vol at the SIF output.
0
4:3
vendorid
Fixed to "01".
01
2:0
versionid
Chip version.
001
Synchronization Modes
There are three modes of syncing included in the DAC3154/DAC3164.
•
•
•
NORMAL Dual Sync – The SYNC pin is used to align the input side of the FIFO (write pointers) with the A(0)
sample. The ALIGN pin is used to reset the output side of the FIFO (read pointers) to the offset value.
Multiple chip alignment can be accomplished with this kind of syncing.
SYNC ONLY – In this mode only the SYNC pin is used to sync both the read and write pointers of the FIFO.
There is an asynchornized handoff between the DATACLK and DACCLK when using this mode, therefore it is
impossible to accurately align multiple chips closer than 2 or 3T.
SIF_SYNC – When neither SYNC nor ALIGN are used, a programmable SYNC pulse can be used to sync
the design. However, the same issues as SYNC ONLY apply. There is an asynchornized handoff between
the serial clock domain and the two sides of the FIFO. Because of the asynchronous nature of the SIF_SYNC
it is impossible to align the sync up with any sample at the input.
Note: When ALIGNP/N are not used, it is recommended to clear the alignrx_ena register (config1, bit 4),
and tie ALIGNP to DIGVDD18 and ALIGNN to GROUND. When SYNCP/N are not used, it is recommended
to clear register syncrx_ena (config0, bit3), and the unused SYNCP/N pins can be left open or tied to
GROUND.
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Alarm Monitoring
DAC3154/DAC3164 includes flexible alarm monitoring that can be used to alert a possible malfunction scenario.
All alarm events can be accessed either through the SIP registers and/or through the ALARM pin. Once an alarm
is set, the corresponding alarm bit in register config5 must be reset through the serial interface to allow further
testing. The set of alarms includes the following conditions:
Zero check alarm
• Alarm_from_zerochk. Occurs when the FIFO write pointer has an all zeros pattern. Since the write pointer is a
shift register, all zeros will cause the input point to be stuck until the next sync event. When this happens a
sync to the FIFO block is required.
FIFO alarms
• alarm_from_fifo. Occurs when there is a collision in the FIFO pointers or a collision event is close.
• alarm_fifo_2away. Pointers are within two addresses of each other.
• alarm_fifo_1away. Pointers are within one address of each other.
• alarm_fifo_collision. Pointers are equal to each other.
Clock alarms
• clock_gone. Occurs when either the DACCLK or DATACLOCK have been stopped.
• alarm_dacclk_gone. Occurs when the DACCLK has been stopped.
• alarm_dataclk_gone. Occurs when the DATACLK has been stopped.
Pattern checker alarm
• alarm_from_iotest. Occurs when the input data pattern does not match the pattern key.
To prevent unexpected DAC outputs from propagating into the transmit channel chain, DAC3154, DAC3164
includes a feature that disables the outputs when a catastrophic alarm occurs. The catastrophic alarms include
FIFO pointer collision, the loss DACCLK or the loss of DATACLK. When any of these alarms occur the internal
TXenable signal is driven low, causing a zeroing of the data going to the DAC in
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