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DAC3282
SLAS646C – DECEMBER 2009 – REVISED MAY 2015
DAC3282 16-Bit, 625 MSPS, 2x Interpolating, Dual-Channel Digital-to-Analog Converter
(DAC)
1 Features
3 Description
•
•
The DAC3282 is a dual-channel 16-bit 625 MSPS
digital-to-analog converter (DAC) with an 8-bit LVDS
input data bus with on-chip termination, optional 2x
interpolation filter, and internal voltage reference. The
DAC3282 offers superior linearity, noise and crosstalk
performance.
1
•
•
•
•
•
•
•
•
•
•
•
Dual, 16-Bit, 625 MSPS DACs
8-Bit Input LVDS Data Bus
– Byte-Wide Interleaved Data Load
– 8 Sample Input FIFO
– Optional Data Pattern Checker
Multi-DAC Synchronization
Optional 2x Interpolation Filter
Zero-IF Sinc Correction Filter
Fs/2 and ± Fs/4 Coarse Mixer
Digital Offset Adjustment for LO Correction
Temperature Sensor
3- or 4-Wire Serial Control Interface
On Chip 1.2-V reference
Differential Scalable Output: 2 to 20 mA
Low Power: 950 mW at 625 MSPS, 845 mW at
500 MHz, Full Operating Conditions
Space Saving Package: 48-pin 7×7mm VQFN
Input data can be interpolated by 2x through an onchip interpolating FIR filter with over 85 dB of stopband attenuation. Multiple DAC3282 devices can be
fully synchronized.
The DAC3282 allows either a complex or real output.
An optional coarse mixer in complex mode provides
frequency upconversion and the dual DAC output
produces a complex Hilbert Transform pair. The
digital offset correction feature allows optimization of
LO feed-through of an external quadrature modulator
performing the final single sideband RF upconversion.
The DAC3282 is characterized for operation over the
entire industrial temperature range of –40°C to 85°C
and is available in a 48-pin 7×7mm VQFN package.
2 Applications
•
•
•
•
Device Information(1)
Cellular Base Stations
Diversity Transmit
Wideband Communications
Digital Synthesis
PART NUMBER
DAC3282
PACKAGE
VQFN (48)
BODY SIZE (NOM)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DACVDD18
VFUSE
DIGVDD18
CLKVDD18
Simplified Schematic
DACCLKP
Clock Distribution
LVPECL
1.2 V
Reference
DACCLKN
A
offset
DATACLKN
FIR4
x
sin(x)
D0N
Coarse Mixer
Fs/4, -Fs/4, Fs/2
5 taps
59 taps
x
sin(x)
16-b
DAC
16-b
DAC
x2
LVDS
B
offset
Frame Strobe
100
FRAMEP
16
x2
Programmable Delay
(0-15T)
100
LVDS
16
8 Sample FIFO
Pattern
Test
De-interleave
D7N
D0P
A
gain
FIR0
LVDS
100
D7P
BIASJ
LVDS
100
DATACLKP
EXTIO
IOUTA1
IOUTA2
IOUTB1
IOUTB2
B
gain
FRAMEN
OSTRP
Temp
Sensor
RESETB
TXENABLE
SCLK
SDIO
SDENB
ALARM_SDO
AVDD33
GND
Control Interface
LVPECL
OSTRN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC3282
SLAS646C – DECEMBER 2009 – REVISED MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
4
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings ............................................................ 6
Recommended Operating Conditions....................... 6
Thermal Information ................................................. 7
Electrical Characteristics – DC Specifications ......... 7
Electrical Characteristics – AC Specifications .......... 9
Electrical Characteristics – Digital Specifications ... 10
Timing Characteristics ........................................... 11
Typical Characteristics ............................................ 12
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 27
7.5 Programming .......................................................... 30
7.6 Register Maps ........................................................ 32
8
Application and Implementation ........................ 45
8.1 Application Information............................................ 45
8.2 Typical Application ................................................. 51
9
Power Supply Recommendations...................... 53
9.1 Power-up Sequence................................................ 53
10 Layout................................................................... 54
10.1 Layout Guidelines ................................................. 54
10.2 Layout Example .................................................... 55
11 Device and Documentation Support ................. 56
11.1
11.2
11.3
11.4
11.5
Device Support......................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
56
57
57
57
57
12 Mechanical, Packaging, and Orderable
Information ........................................................... 57
4 Revision History
Changes from Revision B (May 2012) to Revision C
Page
•
Changed data sheet global format to include Device Information and ESD Rating tables, Feature Description
section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations
section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable
Information section ................................................................................................................................................................ 1
•
Added design parameters for application example .............................................................................................................. 51
Changes from Revision A (February 2010) to Revision B
Page
•
Added to Description of the PIN FUNCTIONS table pin no.31, FROM: Bi-directional in 3-pin....(default). TO: Bidirectional in 3-pin....(default) and 4-pin mode. ..................................................................................................................... 5
•
Changed FIFO block diagram Figure 24 ............................................................................................................................. 17
•
Added 4th & 5th paragraphs to the INPUT FIFO section, under Figure 24. ........................................................................ 17
•
Changed Figure 25 .............................................................................................................................................................. 18
•
Added "CONFIG19 multi_sync_sel" to FIFO MODES OF OPERATION section ................................................................ 19
•
Changed Mode descriptions in FIFO Operation Modes, Table 1, from "Enabled" to "Single Sync Source" and added
new FIFO Mode, "Dual Sync Sources"................................................................................................................................. 19
•
Changed the "DATA PATTERN CHECKER" section text for clarification............................................................................ 19
•
Changed from "SDIO is data in only" to "SDIO is bidirectional" in SERIAL INTERFACE section first paragraph, ............. 30
•
Changed FROM: "In 4 pin.....cycle(s)." TO: "In 4 pin configuration, both ALARM_SDO and SDIO are data out from
DAC3282." in paragraph under Figure 32.. .......................................................................................................................... 31
•
Changed Bit 5 function to: Allows the FRAME input to reset the FIFO write pointer when asserted. AND changed Bit
4 first sentence to: "Allows the FRAME or OSTR signal to reset the FIFO read pointer when asserted." in CONFIG0
Register description ............................................................................................................................................................. 33
•
Changed CONFIG3 Register table from: "CONFIG1, 0x01 to CONFIG3, 0x03" and in Bit 4:2 Function From: "When
the FIFO......read pointer." TO: "This is the default FIFO read pointer position after the FIFO read pointer has been
synchronized." ..................................................................................................................................................................... 34
•
Changed CONFIG7 register table, BIt 6 Function description "This alarm indicates......more detail."................................. 36
2
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SLAS646C – DECEMBER 2009 – REVISED MAY 2015
•
Added text string to CONFIG18 Register table, Bit 1 Function description for clarification. ................................................ 39
•
Moved the MULTI-DEVICE SYNCHRONIZATION section to follow "Bypass Mode" section.............................................. 45
•
Changed the illustration for Figure 74. ................................................................................................................................. 45
•
Changed the illustration for Figure 76 ................................................................................................................................. 47
•
Changed the POWER-UP-SEQUENCE section for clarification. ......................................................................................... 53
•
Deleted SNR definition and added: Noise Spectral....Nyquist zone. ................................................................................... 56
Changes from Original (December 2009) to Revision A
Page
•
Deleted FIFO_OSTRP and FIFO_OSTRN descriptions from Pin Functions table. N/A for this device. ................................ 5
•
Changed Default from 0x41 to 0x43 for Register name VERSION31 in Table 8 Register Map .......................................... 32
•
Changed Default address from 0x41 to 0x43 for Register name:VERSION31; and Default Value for Bit 5:0 from
000001 to 000011................................................................................................................................................................. 44
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DAC3282
SLAS646C – DECEMBER 2009 – REVISED MAY 2015
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5 Pin Configuration and Functions
AVDD33
IOUTB1
IOUTB2
AVDD33
EXTIO
BIASJ
AVDD33
VFUSE
AVDD33
IOUTA2
IOUTA1
AVDD33
48
47
46
45
44
43
42
41
40
39
38
37
RGZ Package
48-Pin VQFN with Thermal Pad
Top View
CLKVDD18
1
36
RESETB
DACVDD18
2
35
DACVDD18
DACCLKP
3
34
ALARM_SDO
DACCLKN
4
33
SDENB
GND
5
32
SCLK
OSTRP
6
31
SDIO
30
TXENABLE
29
DIGVDD18
DAC3282
RGZ Package
48-QFN 7x7mm
(Top View )
24
23
D2P
D2N
22
D1P
D3N
25
21
12
D3P
D6N
20
D1N
FRAMEN
26
19
11
FRAMEP
D6P
18
D0P
DATACLKN
27
17
10
DATACLKP
D7N
16
D0N
D4N
28
15
9
D4P
D7P
14
8
D5N
DIGVDD18
13
7
D5P
OSTRN
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
37, 40, 42,
45, 48
I
Analog supply voltage. (3.3 V)
ALARM_SDO
34
O
1.8V CMOS output for ALARM condition. The ALARM output functionality is defined through the
CONFIG6 register. Default polarity is active low, but can be changed to active high via CONFIG0
alarm_pol control bit. Optionally, it can be used as the uni-directional data output in 4-pin serial
interface mode (CONFIG 23 sif4_ena = ‘1’).
BIASJ
43
O
Full-scale output current bias. For 20mA full-scale output current, connect a 960 Ω resistor to GND.
CLKVDD18
1
I
Internal clock buffer supply voltage. (1.8 V)
It is recommended to isolate this supply from DACVDD18 and DIGVDD18.
AVDD33
D[7..0]P
9, 11, 13,
15, 21, 23,
25, 27
I
LVDS positive input data bits 0 through 7. Each positive/negative LVDS pair has an internal 100 Ω
termination resistor. Data format relative to DATACLKP/N clock is Double Data Rate (DDR) with two
data transfers per DATACKP/N clock cycle. Dual channel 16-bit data is transferred byte-wide on this
single 8-bit data bus using FRAMEP/N as a frame strobe indicator.
D7P is most significant data bit (MSB) – pin 9
D0P is least significant data bit (LSB) – pin 27
The order of the bus can be reversed via CONFIG19 rev bit.
4
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
LVDS negative input data bits 0 through 15. (See D[7:0]P description above)
10, 12, 14,
16, 22, 24,
26, 28
I
DACCLKP
3
I
Positive external LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18/2.
DACCLKN
4
I
Complementary external LVPECL clock input for DAC core. (see the DACCLKP description)
DACVDD18
2, 35
I
DAC core supply voltage. (1.8 V)
It is recommended to isolate this supply from CLKVDD18 and DIGVDD18.
DATACLKP
17
I
LVDS positive input data clock. This positive/negative pair has an internal 100 Ω termination resistor.
Input data D[7:0]P/N is latched on both edges of DATACLKP/N (Double Data Rate) with two data
transfers input per DATACLKP/N clock cycle.
DATACLKN
18
I
LVDS negative input data clock. (See DATACLKP description)
DIGVDD18
8, 29
I
Digital supply voltage. (1.8V)
It is recommended to isolate this supply from CLKVDD18 and DACVDD18.
EXTIO
44
I/O
FRAMEP
19
I
LVDS frame indicator positive input. This positive/negative pair has an internal 100 Ω termination
resistor. This signal is captured with the rising edge of DATACLKP/N and used to indicate the
beginning of the frame. It is also used as a reset signal by the FIFO. The FRAMEP/N signal should
be edge-aligned with D[7:0]P/N.
FRAMEN
20
I
LVDS frame indicator negative input. (See the FRAMEN description)
5,
Thermal
Pad
I
Pin 5 and the Thermal Pad located on the bottom of the QFN package is ground for all supplies.
IOUTA1
38
O
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
full scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data
input results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin.
IOUTA2
39
O
A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the
IOUTA1 described above. An input data value of 0x0000 results in a 0 mA sink and the most positive
voltage on the IOUTA2 pin.
IOUTB1
47
O
B-Channel DAC current output. Refer to IOUTA1 description above.
IOUTB2
46
O
B-Channel DAC complementary current output. Refer to IOUTA2 description above.
OSTRP
6
I
LVPECL output strobe positive input. This positive/negative pair is captured with the rising edge of
DACCLKP/N. It is used to reset the clock dividers and for multiple DAC synchronization. If unused it
can be left floating.
OSTRN
7
I
LVPECL output strobe negative input. (See the OSTRP description)
RESETB
36
I
1.8V CMOS active low input for chip RESET. Internal pull-up.
SCLK
32
I
1.8V CMOS serial interface clock. Internal pull-down.
SDENB
33
I
1.8V CMOS active low serial data enable, always an input to the DAC3282. Internal pull-up.
SDIO
31
I/O
TXENABLE
30
I
1.8V CMOS active high input. TXENABLE must be high for the DATA to the DAC to be enabled.
When TXENABLE is low, the digital logic section is forced to all 0, and any input data is ignored.
Internal pull-down.
VFUSE
41
I
Digital supply voltage. (1.8V) This supply pin is also used for factory fuse programming. Connect to
DACVDD18 pins for normal operation.
D[7..0]N
GND
D7N is most significant data bit (MSB) – pin 10
D0N is least significant data bit (LSB) – pin 28
Used as external reference input when internal reference is disabled through CONFIG25 extref_ena
= ‘1’. Used as internal reference output when CONFIG25 extref_ena = ‘0’ (default). Requires a 0.1
μF decoupling capacitor to AGND when used as reference output.
1.8V CMOS serial interface data. Bi-directional in 3-pin mode (default) and 4-pin mode. Internal pulldown.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply
voltage
(1)
MIN
MAX
DACVDD18 (2)
–0.5
2.3
DIGVDD18 (2)
–0.5
2.3
CLKVDD18 (2)
–0.5
2.3
VFUSE (2)
–0.5
2.3
AVDD33 (2)
–0.5
4
CLKVDD18 to DIGVDD18
–0.5
0.5
–0.5
0.5
DACVDD18 to DIGVDD18
D[7..0]P ,D[7..0]N, DATACLKP,DATACLKN, FRAMEP, FRAMEN
Terminal
voltage
(2)
UNIT
V
–0.5
DIGVDD18 + 0.5
DACCLKP, DACCLKN, OSTRP, OSTRN (2)
–0.5
CLKVDD18 + 0.5
ALARM_SDO, SDIO, SCLK, SDENB, RESETB, TXENABLE (2)
–0.5
DIGVDD18 + 0.5
IOUTA1/B1, IOUTA2/B2 (2)
–1.0
AVDD33 + 0.5
–0.5
AVDD33 + 0.5
EXTIO, BIASJ
(2)
V
Peak input current (any input)
20
mA
Peak total input current (all inputs)
–30
mA
TA
Operating free-air temperature, DAC3282
–40
85
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured with respect to GND.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Voltage
6
MIN
NOM
MAX
1.8-V DAC core supply voltage, DACDVDD18
1.7
1.8
1.9
V
1.8-V digital supply voltage, DIGVDD18
1.7
1.8
1.9
V
1.8-V internal clock buffer supply voltage, CLKVDD18
1.7
1.8
1.9
V
3.3-V analog supply voltage, AVDD33
3.0
3.3
3.6
V
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6.4 Thermal Information
DAC3282
THERMAL METRIC (1)
RGZ (VQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
26.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
12.2
°C/W
RθJB
Junction-to-board thermal resistance
3.7
°C/W
ψJT
Junction-to-top characterization parameter
0.2
°C/W
ψJB
Junction-to-board characterization parameter
3.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics – DC Specifications (1)
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Resolution
MIN
TYP
MAX
UNIT
16
Bits
DC ACCURACY
DNL
Differential nonlinearity
INL
Integral nonlinearity
1 LSB = IOUTFS/216
±2
LSB
±4
LSB
ANALOG OUTPUT
Coarse gain linearity
Offset error
Mid code offset
With external reference
Gain error
With internal reference
Gain mismatch
With internal reference
Minimum full scale output current
Maximum full scale output current
Nominal full-scale current, IOUTFS =
16 × IBIAS current.
Output compliance range (2)
IOUTFS = 20 mA
±0.04
LSB
0.01
%FSR
±2
%FSR
±2
–2
%FSR
2
%FSR
2
mA
20
AVDD
–0.5V
Output resistance
Output capacitance
AVDD
+0.5V
V
300
kΩ
5
pF
REFERENCE OUTPUT
VREF
Reference output voltage
Reference output current
1.14
(3)
1.2
1.26
V
100
nA
REFERENCE INPUT
VEXTIO
Input voltage range
Input resistance
External Reference Mode
0.1
1.2
1.25
V
1
MΩ
Small signal bandwidth
472
kHz
Input capacitance
100
pF
±1
ppm of
FSR/°C
TEMPERATURE COEFFICIENTS
Offset drift
Gain drift
With external reference
±15
With internal reference
±30
ppm of
FSR/°C
±8
ppm/°C
Reference voltage drift
(1)
(2)
(3)
Measured differential across IOUTA1 and IOUTA2 or IOUTB1 and IOUTB2 with 25 Ω each to AVDD.
The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,
resulting in reduced reliability of the DAC3282 device. The upper limit of the output compliance is determined by the load resistors and
full-scale output current. Exceeding the upper limit adversely affects distortion performance and integral nonlinearity.
Use an external buffer amplifier with high impedance input to drive any external load.
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Electrical Characteristics – DC Specifications(1) (continued)
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AVDD33
3.0
3.3
3.6
V
DACVDD18, DIGVDD18,
CLKVDD18
1.7
1.8
1.9
V
POWER SUPPLY
I(AVDD33)
Analog supply current
96
mA
I(DIGVDD18)
Digital supply current
268
mA
74
mA
10
mA
2
mA
3
mA
0.5
mA
1
mA
I(DACVDD18) DAC supply current
I(CLKVDD18)
Clock supply current
I(AVDD33)
Power down mode analog supply
current
I(DIGVDD18)
Power down mode digital supply
current
I(DACVDD18)
Power down mode DAC supply
current
I(CLKVDD18)
Power down mode clock supply
current
P
Power Dissipation
PSRR
Power Supply Rejection Ratio
T
Operating Range
8
Mode 1(below)
Mode 4 (below)
Mode 1: fDAC = 625MSPS, 2x
interpolation, mixer on,
Digital Offset Control on
950
Mode 2: fDAC = 491.52MSPS, 2x
interpolation, Zero-IF
Correction Filter on, mixer off, Digital
Offset Control on
845
mW
Mode 3: Sleep Mode, fDAC =
625MSPS, 2X interpolation, mixer
on,
DAC in sleep mode:
CONFIG24 sleepa, sleepb set to 1
575
mW
Mode 4: Power-Down mode, No
clock, static data pattern, DAC in
power-down mode:
CONFIG23 clkpath_sleep_a,
clkpath_sleepb set to 1
CONFIG24 clkrecv_sleep, sleepa,
sleepb set to 1
15
mW
DC tested
–0.4
–40
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25
1100
mW
0.4
%/FSR/V
85
°C
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6.6 Electrical Characteristics – AC Specifications
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
ANALOG OUTPUT
fDAC
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
Maximum output update rate
Digital Latency
1x Interpolation
312.5
2x Interpolation
625
MSPS
No interpolation, FIFO off, Offset off,
Inverse sinc off
38
2x Interpolation
59
Zero-IF Sinc Correction Filter
16
FIFO
8
Offset
4
DAC clock
cycles
AC PERFORMANCE (2)
SFDR
IMD3
NSD
fDAC = 625 MSPS, fOUT = 10.1 MHz
2x Interp, DAC A+B on
83
fDAC = 625 MSPS, fOUT = 20.1 MHz
2x Interp, DAC A+B on
78
fDAC = 625 MSPS, fOUT = 70.1 MHz
2x Interp, DAC A+B on
64
fDAC = 625 MSPS, fOUT = 30 ± 0.5
MHz 2x Interp, DAC A+B on
82
Third-order two-tone intermodulation fDAC = 625 MSPS, fOUT = 50 ± 0.5
distortion Each tone at –6 dBFS
MHz 2x Interp, DAC A+B on
80
Spurious Free Dynamic Range
SFDR (0 to fDAC/2) Tone at 0 dBFS
Noise Spectral Density Single Tone
at 0 dBm
Adjacent Channel Leakage Ratio,
Single Carrier
WCDMA (3)
Alternate Channel Leakage Ratio,
Single Carrier
Channel Isolation
(1)
(2)
(3)
fDAC = 625 MSPS, fOUT = 150 ± 0.5
MHz 2x Interp, DAC A+B on,
69
fDAC = 625 MSPS, fOUT = 10.1 MHz
2x Interp, DAC A+B on
161
fDAC = 625 MSPS, fOUT = 150.1 MHz
2x Interp, DAC A+B on
150
dBc
dBc
dBc/Hz
fDAC = 491.52 MSPS, fOUT= 30.72
MHz 2x Interp, DAC A+B on
81
fDAC = 491.52 MSPS, fOUT = 153.6
MHz 2x Interp, DAC A+B on
76
fDAC = 491.52 MSPS, fOUT = 30.72
MHz 2x Interp, DAC A+B on
84
dBc
fDAC = 491.52 MSPS, fOUT = 153.6
MHz 2x Interp, DAC A+B on
77
dBc
fDAC = 625 MSPS, fOUT = 10 MHz
84
dBc
dBc
Measured single ended into 50 Ω load.
4:1 transformer output termination, 50 Ω doubly terminated load.
Single carrier, W-CDMA with 3.84 MHz BW, 5-MHz spacing, centered at IF, PAR = 12dB. TESTMODEL 1, 10 ms
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6.7 Electrical Characteristics – Digital Specifications
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MAX
UNIT
Byte-wide DDR format
DATACLK frequency = 625 MHz
312.5
MSPS
1x Interpolation
1250
2x Interpolation
1250
LVDS INTERFACE: D[7:0]P/N, DATACLKP/N, FRAMEP/N
MIN
TYP
(1)
fDATA
Input data rate
fBUS
Byte-wide LVDS data transfer rate
VA,B+
Logic high differential input voltage
threshold
175
400
mV
VA,B–
Logic low differential input voltage
threshold
–175
–400
mV
VCOM
Input Common Mode
1.0
1.2
2.0
V
ZT
Internal termination
85
110
135
Ω
CL
LVDS Input capacitance
2
MSPS
pF
CLOCK INPUT (DACCLKP/N)
Duty cycle
Differential voltage
40%
(2)
0.4
60%
1.0
DACCLKP/N Input Frequency
V
625
MHz
fDACCLK /
(8 x interp)
MHz
OUTPUT STROBE (OSTRP/N)
fOSTR
Frequency
fOSTR = fDACCLK / (n × 8 × Interp)
where n is any positive integer
fDACCLK is DACCLK frequency in
MHz
Duty cycle
40%
Differential voltage
0.4
60%
1.0
V
CMOS INTERFACE: ALARM_SDO, SDIO, SCLK, SDENB, RESETB, TXENABLE
VIH
High-level input voltage
VIL
Low-level input voltage
0.54
V
IIH
High-level input current
–40
40
μA
IIL
Low-level input current
–40
40
μA
CI
CMOS Input capacitance
VOH
VOL
(1)
(2)
10
1.25
V
2
pF
SDO, SDIO
Iload = –100 μA
DIGVDD18 –0.2
V
SDO, SDIO
Iload = –2 mA
0.8 x DIGVDD18
V
SDO, SDIO
Iload = 100 μA
0.2
V
SDO, SDIO
Iload = 2 mA
0.5
V
See LVDS INPUTS section for terminology.
Driving the clock input with a differential voltage lower than 1 V will result in degraded performance.
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6.8 Timing Characteristics
over recommended operating free-air temperature range, nominal supplies, IOUTFS = 20 mA (unless otherwise noted)
PARAMETER
ANALOG OUTPUT
ts(DAC)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
Output settling time to 0.1%
Transition: Code 0x0000 to 0xFFFF
10.4
ns
tpd
Output propagation delay
DAC outputs are updated on the
falling edge of DAC clock. Does not
include Digital Latency (see below).
2
ns
tr(IOUT)
Output rise time 10% to 90%
220
ps
tf(IOUT)
Output fall time 90% to 10%
220
PS
DAC Wake-up Time
IOUT current settling to 1% of
IOUTFS. Measured from SDENB
rising edge; Register CONFIG24,
toggle sleepa from 1 to 0
90
μs
DAC Sleep Time
IOUT current settling to less than
1% of IOUTFS. Measured from
SDENB rising edge; Register
CONFIG24, toggle sleepa from 0 to
1.
90
μs
Power-up
time
TIMING LVDS INPUTS: DATACLKP/N, double edge latching – See Figure 25
ts(DATA)
Setup time, D[7:0]P/N and
FRAMEP/N, valid to either edge of
DATACLKP/N
FRAMEP/N latched on rising edge
of DATACLKP/N only
0
ps
th(DATA)
Hold time, D[7:0]P/N and
FRAMEP/N, valid after either edge
of DATACLKP/N
FRAMEP/N latched on rising edge
of DATACLKP/N only
400
ps
t(FRAME)
FRAMEP/N pulse width
fDATACLK is DATACLK frequency in
MHz
1/2fDATACL
ns
t_align
Maximum offset between
DATACLKP/N and DACCLKP/N
rising edges
K
FIFO Bypass Mode only
fDACCLK is DACCLK frequency in
MHz
1/2fDACCLK
–0.55
ns
TIMING OSTRP/N Input: DACCLKP/N rising edge latching
ts(OSTR)
Setup time, OSTRP/N valid to rising
edge of DACCLKP/N
200
ps
th(OSTR)
Hold time, OSTRP/N valid after
rising edge of DACCLKP/N
200
ps
SERIAL PORT TIMING – See Figure 40 and Figure 41
ts(SDENB)
Setup time, SDENB to rising edge of
SCLK
20
ns
ts(SDIO)
Setup time, SDIO valid to rising
edge of SCLK
10
ns
th(SDIO)
Hold time, SDIO valid to rising edge
of SCLK
5
ns
t(SCLK)
Period of SCLK
1
μs
All other registers
100
ns
Register CONFIG5 read
(temperature sensor read)
0.4
μs
All other registers
40
ns
Register CONFIG5 read
(temperature sensor read)
0.4
μs
All other registers
40
ns
t(SCLKH)
High time of SCLK
Register CONFIG5 read
(temperature sensor read)
t(SCLKL)
Low time of SCLK
td(Data)
Data output delay after falling edge
of SCLK
10
ns
tRESET
Minimum RESETB pulsewidth
25
ns
(1)
Measured single ended into 50 Ω load.
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6.9 Typical Characteristics
5
5
DNL
4
4
3
3
2
2
Error - LSB
Error - LSB
INL
1
0
-1
1
0
-1
-2
-2
-3
-3
-4
-4
-5
-5
0
10000 20000 30000 40000 50000 60000 70000
Code
0
Figure 1. Integral Non-Linearity
Figure 2. Differential Non-Linearity
90
fDAC = 625 MSPS, 2x Interpolation,
IOUTFS = 20 mA
85
SFDR - Spurious Free Dynamic Range - dBc
SFDR - Spurious Free Dynamic Range - dBc
90
80
75
0 dBFS
-6 dBFS
70
65
60
-12 dBFS
55
50
0
50
100
150
200
fOUT - Output Frequency - MHz
fDAC = 312.5 MSPS, 0 dBFS,
IOUTFS = 20 mA
85
80
75
1x Interpolation
70
65
60
2x Interpolation
55
50
250
0
Figure 3. SFDR vs Input Scale
SFDR - Spurious Free Dynamic Range - dBc
SFDR - Spurious Free Dynamic Range - dBc
40
60
80
100
fOUT - Output Frequency - MHz
120
90
2x interpolation, 0 dBFS,
IOUTS = 20 mA
75
fDAC = 200 MSPS
70
65
fDAC = 400 MSPS
60
fDAC = 600 MSPS
55
50
20
Figure 4. SFDR vs Interpolation
80
fDAC = 625 MSPS, 2x interpolation,
0 dBFS
85
80
75
2 mA
70
10 mA
65
20 mA
60
55
50
0
50
100
150
200
fOUT - Output Frequency - MHz
250
0
Figure 5. SFDR vs fDAC
12
10000 20000 30000 40000 50000 60000 70000
Code
50
100
150
200
fOUT - Output Frequency - MHz
250
Figure 6. SFDR vs IOUTFS
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Typical Characteristics (continued)
10
10
2x Interpolation, 0 dBFS,
fDAC = 625 MSPS,
fOUT = 10 MHz
0
-10
-10
-20
-20
Power - dBm
Power - dBm
2x Interpolation, 0 dBFS,
fDAC = 625 MSPS,
fOUT = 100 MHz
0
-30
-40
-50
-30
-40
-50
-60
-60
-70
-70
-80
-80
-90
0
50
100
150
200
f - Frequency - MHz
250
-90
300
0
100
150
200
f - Frequency - MHz
250
300
Figure 8. Single Tone Spectral Plot
Figure 7. Single Tone Spectral Plot
95
90
50
90
fDAC = 625 MSPS, 2x Interpolation,
Tones at fOUT ± 0.5 MHz,
IOUTFS = 20 mA
fDAC = 312.5 MSPS,
Tones at fOUT ± 0.5 MHz,
0 dBFS, IOUTFS = 20 mA
85
85
-6 dBFS
2x Interpolation
IMD3 - dBc
IMD3 - dBc
80
-12 dBFS
75
70
80
75
1x Interpolation
0 dBFS
65
60
70
55
50
0
65
50
100
150
200
fOUT - Output Frequency - MHz
0
250
20
40
60
80
100
fOUT - Output Frequency - MHz
120
Figure 10. IMD3 vs Interpolation
Figure 9. IMD3 vs Input Scale
100
90
95
85
fDAC = 200 MSPS
10 mA
90
80
85
fDAC = 400 MSPS
2 mA
IMD3 - dBc
IMD3 - dBc
75
70
fDAC = 600 MSPS
65
80
75
70
20 mA
65
60
50
60
2x Interpolation,
Tones at fOUT ± 0.5 MHz,
0 dBFS, IOUTS = 20 mA
55
0
50
100
150
200
fOUT - Output Frequency - MHz
55
250
50
0
Figure 11. IMD3 vs fDAC
fDAC = 625 MSPS, 2x Interpolation,
Tones at fOUT ± 0.5 MHz, 0 dBFS
50
100
150
200
fOUT - Output Frequency - MHz
250
Figure 12. IMD3 vs IOUTFS
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Typical Characteristics (continued)
170
170
fDAC = 625 MSPS, 2x Interpolation,
IOUTFS = 20 mA
165
fDAC = 312.5 MSPS, 0 dBFS,
IOUTFS = 20 mA
165
160
160
NSD - dBc/Hz
NSD - dBc/Hz
0 dBFS
155
-6 dBFS
150
145
-12 dBFS
2x Interpolation
155
1x Interpolation
150
140
145
135
130
0
50
100
150
200
fOUT - Output Frequency - MHz
140
250
0
20
Figure 13. NSD vs Input Scale
170
2x Interpolation, 0 dBFS,
IOUTS = 20 mA
165
fDAC = 625 MSPS,
2x Interpolation 0 dBFS
165
160
160
155
20 mA
155
fDAC = 600 MSPS
10 mA
150
150
145
145
fDAC = 200 MSPS
2 mA
fDAC = 400 MSPS
140
140
135
135
130
0
50
100
150
200
fOUT - Output Frequency - MHz
250
130
0
50
100
150
200
fOUT - Output Frequency - MHz
Figure 15. NSD vs fDAC
250
Figure 16. NSD vs IOUTFS
90
80
fDAC = 491.52 MSPS, 2x Interpolation
IOUTFS = 20 mA
fDAC = 491.52 MSPS, 2x Interpolation,
IOUTFS = 20 mA
Aternate, 0 dBFS
75
85
Alternate 0 dBFS
ACLR, 0 dBFS
Adjacent 0 dBFS
80
ACLR - dBc
ACLR - dBc
120
Figure 14. NSD vs Interpolation
170
NSD - dBc/Hz
40
60
80
100
fOUT - Output Frequency - MHz
75
Alternate, -6 dBFS
70
ACLR -6 dBFS
65
Adjacent -6 dBFS
70
65
0
Alternate -6 dBFS
50
100
150
200
fOUT - Output Frequency - MHz
60
250
Figure 17. Single Carrier WCDMA ACLR vs Input Scale
14
55
0
50
100
150
200
fOUT - Output Frequency - MHz
250
Figure 18. Four Carrier WCDMA ACLR vs Input Scale
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Typical Characteristics (continued)
300
1000
900
250
2x+coarse_mix
2x+invsinc
200
DVDD18 - mA
800
Power - mW
2x+coarse_mix
2x
700
1x+invsinc
600
2x+invsinc
2x
150
1x+invsinc
100
1x
1x
500
50
400
0
50
100
150
200
250
fDATA - MSPS
300
0
0
350
Figure 19. Power vs fDATA
20
90
18
80
16
CLKVDD18 - mA
DACVDD - mA
150
200
250
fDATA - MSPS
300
350
14
Coarse_mix on
60
50
40
100
Figure 20. DVDD18 vs fDATA
100
70
50
Coarse_mix off
12
10
8
30
6
20
4
10
2
0
0
0
100
200
300
400
fDAC - MSPS
500
0
600
100
200
300
400
fDAC - MSPS
500
600
Figure 22. CLKVDD18 vs fDAC
Figure 21. DACVDD18 vs fDAC
120
100
AVDD33 - mA
80
60
40
20
0
0
100
200
300
400
fDAC - MSPS
500
600
Figure 23. AVDD33 vs fDAC
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7 Detailed Description
7.1 Overview
The DAC3282 is a dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with an 8-bit LVDS input
data bus with on-chip termination, optional 2x-4x interpolation filters, digital IQ compensation and internal voltage
reference. Input data can be interpolated by 2x or 4x through on-chip interpolating FIR filters with over 85 dB of
stop-band attenuation. Multiple DAC3282 devices can be fully synchronized. The DAC3282 allows either a
complex or real output. An optional coarse mixer in complex mode provides frequency upconversion and the dual
DAC output produces a complex Hilbert Transform pair. The digital IQ compensation feature allows optimization
of phase, gain and offset to maximize sideband rejection and minimize LO feed-through of an external
quadrature modulator performing the final single sideband RF up-conversion.
DACVDD18
VFUSE
DIGVDD18
CLKVDD18
7.2 Functional Block Diagram
DACCLKP
Clock Distribution
LVPECL
1.2 V
Reference
DACCLKN
A
offset
DATACLKN
FIR4
D0N
59 taps
x
sin(x)
16
Coarse Mixer
Fs/4, -Fs/4, Fs/2
5 taps
16-b
DAC
16-b
DAC
x2
LVDS
B
offset
Frame Strobe
100
FRAMEP
x2
Programmable Delay
(0-15T)
x
sin(x)
100
LVDS
16
8 Sample FIFO
Pattern
Test
De-interleave
D7N
D0P
A
gain
FIR0
LVDS
100
D7P
BIASJ
LVDS
100
DATACLKP
EXTIO
IOUTA1
IOUTA2
IOUTB1
IOUTB2
B
gain
FRAMEN
OSTRP
Temp
Sensor
RESETB
TXENABLE
SCLK
SDENB
SDIO
ALARM_SDO
AVDD33
GND
Control Interface
LVPECL
OSTRN
7.3 Feature Description
7.3.1 Input FIFO
The DAC3282 includes a 2-channel, 16-bits wide and 8-samples deep input FIFO which acts as an elastic buffer.
The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC data
rate clock such as the ones resulting from clock-to-data variations from the data source.
Figure 24 shows the block diagram of the FIFO.
16
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Feature Description (continued)
Clock Handoff
Input Side
Clocked by DATACLK
Two DATACLK cycles to capture
2x 16-bit of I-data and Q-data
Data[15:8] 8-bit
Data[7:0] 8-bit
Frame Align
Q-data, 16-bit
32-bit
0
Sample 0
I0 [15:0], Q0 [15:0]
0
1
Sample 1
I1 [15:0], Q1 [15:0]
1
2
Sample 2
I2 [15:0], Q2 [15:0]
2
3
Sample 3
I3 [15:0], Q3 [15:0]
3
4
Sample 4
I4 [15:0], Q4 [15:0]
4
5
Sample 5
I5 [15:0], Q5 [15:0]
5
6
Sample 6
I6 [15:0], Q6 [15:0]
6
7
Sample 7
I7 [15:0], Q7 [15:0]
7
Write Pointer Reset
FRAME
32-bit
0…7
Read Pointer
I-data, 16-bit
0…7
Write Pointer
Initial
Position
D[7:0]
Output Side
Clocked by FIFO Out Clock
(DACCLK/Interpolation Factor)
FIFO:
2 x 16-bits wide
8-samples deep
16-bit
FIFO I Output
FIFO Q Output
16-bit
Initial
Position
Read Pointer Reset
fifo_offset(2:0)
S
M
multi_sync_ena
OSTR
fifo_reset_ena
S (Single Sync Source Mode). Reset handoff from input side to output side.
M (Dual Sync Sources Mode). OSTR resets read pointer. Multi-DAC synchronization
Figure 24. DAC3282 FIFO Block Diagram
Data is written to the device 8-bits at a time on the rising and falling edges of DATACLK. In order to form a
complete 32-bit wide sample (16-bit I-data and 16-bit Q-data) two DATACLK periods are required as shown in
Figure 25. Each 32-bit wide sample is written into the FIFO at the address indicated by the write pointer.
Similarly, data from the FIFO is read by the FIFO Out Clock 32-bits at a time from the address indicated by the
read pointer. The FIFO Out Clock is generated internally from the DACCLK signal and its rate is equal to
DACCLK/Interpolation. Each time a FIFO write or FIFO read is done the corresponding pointer moves to the next
address.
The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown in
Figure 24. This offset gives optimal margin within the FIFO. The default read pointer location can be set to
another value using fifo_offset(2:0) in register CONFIG3. Under normal conditions data is written-to and readfrom the FIFO at the same rate and consequently the write and read pointer gap remains constant. If the FIFO
write and read rates are different, the corresponding pointers will be cycling at different speeds which could result
in pointer collision. Under this condition the FIFO attempts to read and write data from the same address at the
same time which will result in errors and thus must be avoided.
The FRAME signal besides acting as a frame indicator can also used to reset the FIFO pointers to their initial
location. Unlike Data, the FRAME signal is latched only on the rising edges of DATACLK. When a rising edge
occurs on FRAME, the pointers will return to their original position. The write pointer is always set back to
position 0 upon reset. The read pointer reset position is determined by fifo_offset (address 4 by default).
Similarly, the read pointer sync source is selected by multi_sync_sel (CONFIG19). Either the FRAME or OSTR
signal can be set to reset the read pointer. If FRAME is used to reset the read pointer, the FIFO Out Clock will
recapture the FRAME signal to reset the read pointer. This clock domain transfer (DATACLK to FIFO Out Clock)
results in phase ambiguity of the reset signal. This limits the precise control of the output timing and makes full
synchronization of multiple devices difficult.
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Feature Description (continued)
To alleviate this, the device offers the alternative of resetting the FIFO read pointer independently of the write
pointer by using the OSTR signal. The OSTR signal is sampled by DACCLK and must satisfy the timing
requirements in the specification table. In order to minimize the skew it is recommended to use the same clock
distribution device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the
DAC3282 devices in the system. Swapping the polarity of the DACCLK output with respect to the OSTR output
establishes proper phase relationship.
The FIFO pointers reset procedure can be done periodically or only once during initialization as the pointers
automatically return to the initial position when the FIFO has been filled. To reset the FIFO periodically, it is
necessary to have FRAME and OSTR signals to repeat at multiple of 8 FIFO samples. To disable FIFO reset, set
fifo_reset_ena and multi_sync_ena (CONFIG0) to 0.
The frequency limitation for the FRAME signal is the following
fSYNC = fDATACLK/(n x 16) where n = 1, 2,...
The frequency limitation for the OSTR signal is the following:
fOSTR = fDAC/(n x interpolation x 8) where n = 1, 2, ...
The frequencies above are at maximum when n = 1. This is when FRAME and OSTR have a rising edge
transition every 8 FIFO samples. The occurrence can be made less frequent by setting n > 1, for example, every
n x 8 FIFO samples.
LVDS Pairs (Data Source)
D[7:0]P/N
Q3[15:8]
Q3[7:0]
I4[15:8]
Q4[15:8]
Q4[7:0]
I5[15:8]
I5[7:0]
Q5[15:8]
Q5[7:0]
I6[15:8]
I6[7:0]
Q6[15:8]
Q6[7:0]
I7[15:8]
I7[7:0]
Q7[15:8]
Write sample 4 to FIFO (32-bits)
Write I4[7:0] (8-bits) to Write Q4[7:0] (8-bits) to
DAC on falling edge
DAC on falling edge
ts(DATA )
ts(DATA )
DATACLKP /N
(DDR)
th(DATA )
Write I4[15:8] (8-bits) to Write Q4[15:8] (8-bits) to
DAC on rising edge
DAC on rising edge
ts(DATA )
FRAMEP/N
LVPECL Pairs
(Clock Source)
I4[7:0]
th(DATA )
th(DATA )
Resets write pointer to position 0
DACCLKP/N
2 x interpolation
ts(OSTR)
OSTRP/N
(optionally internal
sync from write reset)
th(OSTR )
Resets read pointer to position
set by fifo_offset (4 by default)
Figure 25. FIFO Write Description
7.3.2 FIFO Alarms
The FIFO only operates correctly when the write and read pointers are positioned properly. If either pointer over
or under runs the other, samples will be duplicated or skipped. To prevent this, register CONFIG7 can be used to
track three FIFO related alarms:
• alarm_fifo_2away. Occurs when the pointers are within two addresses of each other.
• alarm_fifo_1away. Occurs when the pointers are within one address of each other.
• alarm_fifo_collision. Occurs when the pointers are equal to each other.
These three alarm events are generated asynchronously with respect to the clocks and can be accessed either
through CONFIG7 or through the ALARM_SDO pin.
18
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Feature Description (continued)
7.3.3 FIFO Modes of Operation
The DAC3282 input FIFO can be completely bypassed through registers config0 and config19. The register
configuration for each mode is described in Table 1.
Register
Control Bits
CONFIG0
fifo_ena, fifo_reset_ena, multi_sync_ena
CONFIG19
multi_sync_sel
Table 1. FIFO Operation Modes
config0 FIFO Bits
FIFO Mode
Config19
fifo_ena
fifo_reset_ena
multi_sync_ena
multi_sync_sel
Dual Sync Sources
1
1
1
0
Single Sync Source
1
1
1
1
Bypass
0
X
X
X
7.3.4 Dual Sync Sources Mode
This is the recommended mode of operation for those applications that require precise control of the output
timing. In Dual Sync Sources mode, the FIFO write and read pointers are reset independently. The FIFO write
pointer is reset using the LVDS FRAME signal, and the FIFO read pointer is reset using the LVPECL OSTR
signal. This allows LVPECL OSTR signal to control the phase of the output for either a single chip or multiple
chips. Multiple devices can be fully synchronized in this mode.
7.3.5 Single Sync Source Mode
In Single Sync Source mode, the FIFO write and read pointers are reset from the same LVDS FRAME signal.
This mode has a possibility of up to 2 DAC clocks offset between the outputs of multiple devices (the DAC
outputs of the same device maintain the phase phase). Applications requiring exact output timing control will
need Dual Sync Sources mode instead of Single Sync Source Mode. A rising edge for FIFO and clock divider
sync is recommended. Periodic sync signal is not recommended due to non-deterministic latency of the sync
signal through the clock domain transfer.
7.3.6 Bypass Mode
In FIFO bypass mode, the FIFO block is not used. As a result the input data is handed off from the DATACLK to
the DACCLK domain without any compensation. In this mode the relationship between DATACLK and DACCLK
t(align) is critical and used as a synchronizing mechanism for the internal logic. Due to the t(align) constraint it is
highly recommended that a clock synchronizer such as Texas Instruments' CDCM7005 or CDCE62005 is used
to provide both clock inputs. In bypass mode the pointers have no effect on the data path or handoff.
7.3.7 Data Pattern Checker
The DAC3282 incorporates a simple pattern checker test in order to determine errors in the data interface. The
main cause of failure is setup/hold timing issues. The test mode is enabled by asserting iotest_ena in register
config1. In test mode the analog outputs are deactivated regardless of the state of TXENABLE.
The data pattern key used for the test is 8 words long and is specified by the contents of iotest_pattern[0:7] in
registers config9 through config16. The data pattern key can be modified by changing the contents of these
registers.
The first word in the test frame is determined by a rising edge transition in FRAME. At this transition, the pattern0
word should be input to the data pins. Patterns 1 through 7 should follow sequentially on each edge of DATACLK
(rising and falling). The sequence should be repeated until the pattern checker test is disabled by setting
iotest_ena back to “0”. It is not necessary to have a rising FRAME edge aligned with every pattern0 word, just
the first one to mark the beginning of the series.
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Start cycle again with optional rising edge of FRAME
D[7:0]P/N
Pattern 0 Pattern 1 Pattern 2 Pattern 3 Pattern 4 Pattern 5 Pattern 6 Pattern 7
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
DATACLKP/N (DDR)
FRAMEP/N
Figure 26. IO Pattern Checker Data Transmission Format
The test mode determines if the 8-bit LVDS data D[7:0]P/N of all the patterns were received correctly by
comparing the received data against the data pattern key. If any of the 8-bit data D[7:0]P/N were received
incorrectly, the corresponding bits in iotest_results(7:0) in register config8 will be set to “1” to indicate bit error
location. Furthermore, the error condition will trigger the alarm_from_iotest bit in register config7 to indicate a
general error in the data interface. When data pattern checker mode is enabled, this alarm in register config7, bit
3 is the only valid alarm. Other alarms in register config7 are not valid and can be disregarded.
For instance, pattern0 is programmed to the default of 0x7A. If the received Pattern 0 is 0x7B, then bit 0 in
iotest_results(7:0) will be set to “1” to indicate an error in bit 0 location. The alarm_from_iotest will also be set to
“1” to report the data transfer error. The user can then narrow down the error from the bit location information
and implement the fix accordingly.
The alarms can be cleared by writing 0x00 to iotest_results(7:0) and “0” to alarm_from_iotest through the serial
interface. The serial interface will read back 0s if there are no errors or if the errors are cleared. The
corresponding alarm bit will remain a “1” if the errors remain.
It is recommended to enable the pattern checker and then run the pattern sequence for 100 or more complete
cycles before clearing the iotest_results(7:0) and alarm_from_iotest. This will eliminate the possibility of false
alarms generated during the setup sequence.
20
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8-Bit
0
Pattern 0
Bit-by-Bit Compare
0
1
Pattern 1
Bit-by-Bit Compare
1
2
Pattern 2
Bit-by-Bit Compare
3
Pattern 3
Bit-by-Bit Compare
4
Pattern 4
Bit-by-Bit Compare
5
Pattern 5
Bit-by-Bit Compare
6
Pattern 6
Bit-by-Bit Compare
8-Bit
FRAME
LVDS
Drivers Only one
Data
Format
edge needed
Pattern 0 ... 7
D[7:0]
8-Bit
DATACLK
7
Pattern 7
Bit-by-Bit Compare
2
3
iotest_pattern0
iotest_pattern1
iotest_pattern2
8-Bit
Input
iotest_results[7]
iotest_pattern3
iotest_pattern4
4
iotest_pattern5
5
iotest_pattern6
6
iotest_pattern7
7
8-Bit
Input
Bit 7
Results
•
•
•
8-Bit
Input
•
•
•
•
•
•
alarm_from_iotest
iotest_results[0]
All Bits
Results
Bit 0
Results
Go back to 0 after cycle or new
rising edge on FRAME
Figure 27. DAC3282 Pattern Check Block Diagram
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7.3.8 FIR Filters
The DAC3282 has two FIR filters, a 2x interpolation FIR (FIR0) and a non-interpolating FIR (FIR4) that
compensates for the sinc droop of the DAC on zero-IF applications. The correction filter is placed before the
interpolating filter and can only be used with both FIRs enabled.
Figure 28 shows the magnitude spectrum response for FIR0, a 59-tap interpolating half-band filter. The transition
band is from 0.4 to 0.6 × fIN (the input data rate for the FIR filter) with < 0.002dB of pass-band ripple and > 85 dB
stop-band attenuation. Figure 29 shows the transition band region from 0.36 to 0.46 × fIN. Up to 0.45 × fIN there is
less than 0.5 dB of attenuation.
20
0.1
0
0
-20
Magnitude - dB
Magnitude - dB
-0.1
-40
-60
-80
-100
-0.2
-0.3
-0.4
-120
-0.5
-140
-160
0
0.1
0.2 0.3
0.4 0.5 0.6
f/fin
0.7
0.8 0.9
1
0.36 0.37 0.38 0.39 0.4 0.41 0.42 0.43 0.44 0.45 0.46
f/fin
Figure 28. Magnitude Spectrum for FIR0
Figure 29. FIR0 Transition Band
4
0.5
3
0.4
0.3
FIR4
2
0.2
0
Corrected
-1
-2
Magnitude - dB
Magnitude - dB
FIR4
1
0.1
Corrected
0
-0.1
-0.2
Sin(x)/x
Sin(x)/x
-0.3
-3
-4
0
-0.4
0.05 0.1 0.15 0.2 0.25 0.3 0.35
fOUT/fDAC
0.4 0.45 0.5
Figure 30. Magnitude Spectrum for Zero-IF Sinc
Correction Filter up to 0.5 × fDAC
22
-0.5
0
0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2
fOUT/fDAC
Figure 31. Correction Range of Zero-IF Sinc
Correction Filter 0 to 0.2 × fDAC
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The DAC sample and hold operation results in the well known sin(x)/x or sinc(x) frequency response shown in
Figure 30 (red line). The DAC3282 has a 5-tap inverse sinc filter (FIR4) placed before the 2x interpolation filter to
compensate for this effect up to 0.2 × fDAC. The inverse sinc filter runs at the input data rate and is operational
only if the 2x interpolation filter is enabled as well, correspondingly the rate of this filter is always half of the DAC
update rate. As a result, the filter cannot completely flatten the frequency response of the sample and hold output
as shown in Figure 30.
Figure 31 shows the magnitude spectrum for FIR4 over the correction range. The inverse sinc filter response
(Figure 31, black line) has approximately the opposite frequency response to sin(x)/x between 0 to 0.2 x fDAC,
resulting in the corrected response in Figure 31 (blue line). Between 0 to 0.2 × fDAC, the inverse sinc filter
compensates for the sample and hold roll-off with less than 0.04-dB error.
The filter taps for all digital filters are listed in Table 2.
Table 2. FIR Filter Coefficients
FIR0
2x Interpolating Half-Band Filter
FIR4
Non-Interpolating Zero-IF
Sinc Correction Filter
59 Taps
5 Taps
4
4
1
0
0
–5
–12
–12
0
0
–5
28
28
1
0
0
–58
–58
0
0
108
108
0
0
–188
–188
0
0
308
308
0
0
–483
–483
0
0
734
734
0
0
–1091
–1091
0
0
1607
1607
0
0
–2392
–2392
0
0
3732
3732
0
0
–6681
–6681
0
0
20768
20768
32768
(1)
264
(1)
(1)
Center taps are highlighted in BOLD.
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The zero-IF sinc filter has a gain > 1 at all frequencies. Therefore, the input data must be reduced from full scale
to prevent saturation in the filter. The amount of back-off required depends on the signal frequency, and is set
such that at the signal frequencies the combination of the input signal and filter response is less than 1 (0 dB).
For example, if the signal input to FIR4 is at 0.1 × fDAC, the response of FIR4 is 0.1 dB, and the signal must be
backed off from full scale by 0.1 dB to avoid saturation.
Note that the loss of signal amplitude may result in lower SNR due to decrease in signal amplitude.
7.3.9 Coarse Mixer
The DAC3282 has a coarse mixer block capable of shifting the input signal spectrum by the fixed mixing
frequencies fS/2 or ±fS/4. The coarse mixing function is built into the interpolation filter and thus FIR0 must be
enabled to use it.
Treating channels A and B as a complex vector of the form I(t) + j Q(t), where I(t) = A(t) and Q(t) = B(t), the
outputs of the coarse mixer, AOUT(t) and BOUT(t) are equivalent to:
A OUT (t) = A(t)cos(2p fCMIX t) - B(t)sin(2p fCMIX t)
(1)
BOUT (t) = A(t)sin(2p fCMIX t) + B(t)cos(2p fCMIX t)
(2)
where fCMIX is the fixed mixing frequency selected by mixer_func(1:0). For fS/2, +fS/4 and –fS/4 the above
operations result in the simple mixing sequences shown in Table 3.
Table 3. Coarse Mixer Sequences
Mode
24
mixer_func(1:0)
Mixing Sequence
Normal
(Low Pass, No Mixing)
00
AOUT = { +A, +A , +A, +A }
BOUT = { +B, +B , +B, +B }
fS/2
01
AOUT = { +A, –A , +A, –A }
BOUT = { +B, –B , +B, –B }
+fS/4
10
AOUT = { +A, –B , –A, +B }
BOUT = { +B, +A , –B, –A }
–fS/4
11
AOUT = { +A, +B , –A, –B }
BOUT = { +B, –A , –B, +A }
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(x2 Bypass)
FIR 0
x2
B Data In
A Data Out
Coarse Mixer
x2
A Data In
B Data Out
Block Diagram
A Mix In
0
A Mix Out
1
0 1
1 -1
1
B Mix In
B Mix Out
0
0 1
1 -1
mixer_func(1:0)
Mix Sequencer
Figure 32. Coarse Mixers Block Diagram
The coarse mixer in the DAC3282 treats the A and B inputs as complex input data and for most mixing
frequencies produces a complex output. Only when the mixing frequency is set to fS/2 the A and B channels can
be maintained isolated as shown in Table 3. In this case the two channels are upconverted as independent
signals. By setting the mixer to fS/2 the FIR0 outputs are inverted thus behaving as a high-pass filter.
Table 4. Dual-Channel Real Upconversion Options
(1)
FIR Mode
Input Frequency (1)
Output Frequency (1)
Signal Bandwidth (1)
Spectrum Inverted?
Low pass
0.0 to 0.4 x fDATA
0.0 to 0.4 x fDATA
0.4 x fDATA
No
High pass
0.0 to 0.4 x fDATA
0.6 to 1.0 x fDATA
0.4 x fDATA
Yes
fDATA is the input data rate of each channel after de-interleaving.
7.3.10 Digital Offset Control
The qmc_offseta(12:0) and qmc_offsetb(12:0) values in registers CONFIG20 through CONFIG23 can be used to
independently adjust the A and B path DC offsets. Both offset values are in represented in 2s-complement format
with a range from –4096 to 4095.
Note that a write to register CONFIG20 is required to load the values of all four qmc_offset registers (CONFIG20CONFIG23) into the offset block simultaneously. When updating the offset values CONFIG20 should be written
last. Programming any of the other three registers will not affect the offset setting.
The offset value adds a digital offset to the digital data before digital-to-analog conversion. Since the offset is
added directly to the data it may be necessary to back off the signal to prevent saturation. Both data and offset
values are LSB aligned.
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qmc_offseta
{-4096 , -4095, … , 4095}
13
16
S
A Data In
16
S
B Data In
13
16
A Data Out
16
B Data Out
qmc_offsetb
{-4096 , -4095, … , 4095}
Figure 33. Digital Offset Block Diagram
7.3.11 Temperature Sensor
The DAC3282 incorporates a temperature sensor block which monitors the temperature by measuring the
voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive-approximation
(SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement
value representing the temperature in degrees Celsius.
The sampling is controlled by the serial interface signals SDENB and SCLK. If the temperature sensor is enabled
(tsense_ena = 1 in register CONFIG24) a conversion takes place each time the serial port is written or read. The
data is only read and sent out by the digital block when the temperature sensor is read in register CONFIG5. The
conversion uses the first eight clocks of the serial clock as the capture and conversion clock, the data is valid on
the falling eighth SCLK. The data is then clocked out of the chip on the rising edge of the ninth SCLK. No other
clocks to the chip are necessary for the temperature sensor operation. As a result the temperature sensor is
enabled even when the device is in sleep mode.
In order for the process described above to operate properly, the serial port read from CONFIG5 must be done
with an SCLK period of at least 1 µs. If this is not satisfied the temperature sensor accuracy is greatly reduced.
7.3.12 Sleep Modes
The DAC3282 features independent sleep control of each DAC (sleepa and sleepb), their corresponding clock
path (clkpath_sleep_a and clkpath_sleep_b) as well as the clock input receiver of the device (clkrecv_sleep). The
sleep control of each of these components is done through the SIF interface and is enabled by setting a 1 to the
corresponding sleep register.
Complete power down of the device is set by setting all of these components to sleep. Under this mode the
supply power consumption is reduced to 15mW. Power-up time in this case will be in the milliseconds range.
Alternatively for those applications were power-up and power-down times are critical it is recommended to only
set the DACs to sleep through the sleepa and sleepb registers. In this case both the sleep and wake-up times
are only 90µs.
7.3.13 Reference Operation
The DAC3282 uses a bandgap reference and control amplifier for biasing the full-scale output current. The fullscale output current is set by applying an external resistor RBIAS to pin BIASJ. The bias current IBIAS through
resistor RBIAS is defined by the on-chip bandgap reference voltage and control amplifier. The default full-scale
output current equals 16 times this bias current and can thus be expressed as:
IOUTFS = 16 × IBIAS = 16 × VEXTIO / RBIAS
Each DAC has a 4-bit independent coarse gain control via coarse_daca(3:0) and coarse_dacb (3:0) in the
CONFIG4 register. Using gain control, the IOUTFS can be expressed as:
IOUTAFS = (DACA_gain + 1) × IBIAS = (DACA_gain + 1) × VEXTIO / RBIAS
IOUTBFS = (DACB_gain + 1) × IBIAS = (DACB_gain + 1) × VEXTIO / RBIAS
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Where VEXTIO is the voltage at terminal EXTIO. The bandgap reference voltage delivers an accurate voltage of
1.2V. This reference is active when extref_ena = ‘0’ in CONFIG25. An external decoupling capacitor CEXT of 0.1
μF should be connected externally to terminal EXTIO for compensation. The bandgap reference can additionally
be used for external reference operation. In that case, an external buffer with high impedance input should be
applied in order to limit the bandgap load current to a maximum of 100 nA. The internal reference can be
disabled and overridden by an external reference by setting the CONFIG25 extref_ena control bit. Capacitor CEXT
may hence be omitted. Terminal EXTIO thus serves as either input or output node.
The full-scale output current can be adjusted from 20 mA down to 2 mA by varying resistor RBIAS or changing the
externally applied reference voltage. The internal control amplifier has a wide input range, supporting the fullscale output current range of 20 dB.
7.4 Device Functional Modes
7.4.1 Data Interface
The DAC3282 has a single 8-bit LVDS bus that accepts dual, 16-bit data input in byte-wide format. Data into the
DAC3282 is formatted according to the diagram shown in Figure 34 where index 0 is the data LSB and index 15
is the data MSB. The data is sampled by DATACLK, a double data rate (DDR) clock.
The FRAME signal is required to indicate the beginning of a frame. The frame signal can be either a pulse or a
periodic signal where the frame period corresponds to 8 samples. The pulse-width (t(FRAME)) needs to be at least
equal to ½ the DATACLK period. FRAME is sampled by a rising edge in DATACLK.
The setup and hold requirements listed in the specifications tables must be met to ensure proper sampling.
SAMPLE 0
I0
[15:8]
D[7:0]P/N
I0
[7:0]
Q0
[15:8]
SAMPLE 1
Q0
[7:0]
I1
[15:8]
I1
[7:0]
Q1
[15:8]
Q1
[7:0]
t(FRAME)
FRAMEP/N
DATACLKP /N
(DDR)
Figure 34. Byte-Wide Data Transmission Format
7.4.2 LVPECL Inputs
Figure 35 shows an equivalent circuit for the DAC input clock (DACCLKP/N) and the FIFO output strobe clock
(OSTRP/N).
CLKVDD
333 W
DACCLKP
OSTRP
2 kW
Note: Input common mode level is
approximately 2/3*CLKVDD18,
or 1.2V nominal.
2 kW
DACCLKN
OSTRN
666 W
GND
Figure 35. DACCLKP/N and OSTRP/N Equivalent Input Circuit
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Device Functional Modes (continued)
Figure 36 shows the preferred configuration for driving the CLKIN/CLKINC input clock with a differential
ECL/PECL source.
0.1 mF
CLKIN
Differential +
ECL
or
(LV)PECL
source
-
CAC
100 W
CLKINC
0.1 mF
150 W
RT
150 W
Figure 36. Preferred Clock Input Configuration With a Differential ECL/PECL Clock Source
7.4.3 LVDS Inputs
The D[7:0]P/N, DATACLKP/N and FRAMEP/N LVDS pairs have the input configuration shown in Figure 37.
Figure 38 shows the typical input levels and common-move voltage used to drive these inputs.
To Adjacent
LVDS Input
50
D[7:0]P,
DATACLKP ,
FRAMEP
100pF
Total
D[7:0]N,
DATACLKN ,
FRAMEN
LVDS
Receiver
50
Ref Note (1)
To Adjacent
LVDS Input
Note (1): RCENTER node common
to the D[7:0] P/N, DATACLKP / N and
FRAMEP/N receiver inputs
Figure 37. D[7:0]P/N, DATACLKP/N and FRAMEP/N LVDS Input Configuration
Example
D[7:0]P,
DATACLKP ,
FRAMEP
LVDS
Receiver
100
VA,B
VCOM =
(VA+VB)/2
DAC3282
VA
1.40V
VB
1.00V
VA,B
400mV
0V
VA
VB
D[7:0]N,
DATACLKN ,
FRAMEN
-400mV
GND
Logical Bit
Equivalent
1
0
Figure 38. LVDS Data (D[7:0]P/N, DATACLKP/N, FRAMEP/N Pairs) Input Levels
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Table 5. Example LVDS Data Input Levels
Applied Voltages
Resulting Differential
Voltage
Resulting
Common-Mode
Voltage
VCOM
VA
VB
VA,B
1.4 V
1.0 V
400 mV
1.0 V
1.4 V
–400 mV
1.2 V
0.8 V
400 mV
0.8 V
1.2 V
–400 mV
Logical Bit Binary
Equivalent
1
1.2 V
0
1
1.0 V
0
7.4.4 CMOS Digital Inputs
Figure 39 shows a schematic of the equivalent CMOS digital inputs of the DAC3282. SDIO, SCLK and
TXENABLE have pull-down resistors while SDENB and RESETB have pull-up resistors internal to the DAC3282.
See the specification table for logic thresholds. The pull-up and pull-down circuitry is approximately equivalent to
100kΩ.
DIGVDD 18
DIGVDD 18
internal
digital in
SDIO
SCLK
TXENABLE
internal
digital in
SDENB
RESETB
GND
GND
Figure 39. CMOS/TTL Digital Equivalent Input
7.4.5 DAC Transfer Function
The CMOS DAC’s consist of a segmented array of NMOS current sinks, capable of sinking a full-scale output
current up to 20 mA. Differential current switches direct the current to either one of the complementary output
nodes IOUT1 or IOUT2. (DACA = IOUTA1 or IOUTA2 and DACB = IOUTB1 or IOUTB2.) Complementary output
currents enable differential operation, thus canceling out common mode noise sources (digital feed-through, onchip and PCB noise), dc offsets, even order distortion components, and increasing signal output power by a
factor of two.
The full-scale output current is set using external resistor RBIAS in combination with an on-chip bandgap voltage
reference source (+1.2V) and control amplifier. Current IBIAS through resistor RBIAS is mirrored internally to
provide a maximum full-scale output current equal to 16 times IBIAS.
The relation between IOUT1 and IOUT2 can be expressed as:
IOUT1 = – IOUTFS – IOUT2
We will denote current flowing into a node as – current and current flowing out of a node as + current. Since the
output stage is a current sink the current can only flow from AVDD into the IOUT1 and IOUT2 pins. The output
current flow in each pin driving a resistive load can be expressed as:
IOUT1 = IOUTFS × (65535 – CODE) / 65536
IOUT2 = IOUTFS × CODE / 65536
where CODE is the decimal representation of the DAC data input word.
For the case where IOUT1 and IOUT2 drive resistor loads RL directly, this translates into single ended voltages
at IOUT1 and IOUT2:
VOUT1 = AVDD – | IOUT1 | × RL
VOUT2 = AVDD – | IOUT2 | × RL
Assuming that the data is full scale (65536 in offset binary notation) and the RL is 25 Ω, the differential voltage
between pins IOUT1 and IOUT2 can be expressed as:
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VOUT1 = AVDD – | –0mA | × 25 Ω = 3.3 V
VOUT2 = AVDD – | –20mA | × 25 Ω = 2.8 V
VDIFF = VOUT1 – VOUT2 = 0.5V
Note that care should be taken not to exceed the compliance voltages at node IOUT1 and IOUT2, which would
lead to increased signal distortion.
7.5 Programming
7.5.1 Serial Interface
The serial port of the DAC3282 is a flexible serial interface which communicates with industry standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of DAC3282. It is compatible with most synchronous transfer formats and can be configured as
a 3 or 4 pin interface by sif4_ena in register CONFIG23. In both configurations, SCLK is the serial interface input
clock and SDENB is serial interface enable. For 3 pin configuration, SDIO is a bidirectional pin for both data in
and data out. For 4 pin configuration, SDIO is bidirectional and ALARM_SDO is data out only. Data is input into
the device with the rising edge of SCLK. Data is output from the device on the falling edge of SCLK.
Each read/write operation is framed by signal SDENB (Serial Data Enable Bar) asserted low for 2 to 5 bytes,
depending on the data length to be transferred (1–4 bytes). The first frame byte is the instruction cycle which
identifies the following data transfer cycle as read or write, how many bytes to transfer, and what address to
transfer the data. Table 6 indicates the function of each bit in the instruction cycle and is followed by a detailed
description of each bit. Frame bytes 2 to 5 comprise the data transfer cycle.
Table 6. Instruction Byte of the Serial Interface
MSB
LSB
Bit
7
6
5
4
3
2
1
0
Description
R/W
N1
N0
A4
A3
A2
A1
A0
R/W
Identifies the following data transfer cycle as a read or write operation. A high indicates a read
operation from DAC3282 and a low indicates a write operation to DAC3282.
[N1 : N0]
Identifies the number of data bytes to be transferred per Table 7. Data is transferred MSB first.
Table 7. Number of Transferred Bytes Within One
Communication Frame
[A4 : A0]
N1
N0
Description
0
0
Transfer 1 Byte
0
1
Transfer 2 Bytes
1
0
Transfer 3 Bytes
1
1
Transfer 4 Bytes
Identifies the address of the register to be accessed during the read or write operation. For multibyte transfers, this address is the starting address. Note that the address is written to the
DAC3282 MSB first and counts down for each byte.
Figure 40 shows the serial interface timing diagram for a DAC3282 write operation. SCLK is the serial interface
clock input to DAC3282. Serial data enable SDENB is an active low input to DAC3282. SDIO is serial data in.
Input data to DAC3282 is clocked on the rising edges of SCLK.
30
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Instruction Cycle
Data Transfer Cycle
SDENB
SCLK
SDIO
rwb
N1
N0
-
A3
A2
A1
tS(SDENB)
A0
D7
D6
D5
D4
D3
D2
D1
D0
tSCLK
SDENB
SCLK
SDIO
tSCLKH
tS( SDIO) tH(SDIO)
tSCLKL
Figure 40. Serial Interface Write Timing Diagram
Figure 41 shows the serial interface timing diagram for a DAC3282 read operation. SCLK is the serial interface
clock input to DAC3282. Serial data enable SDENB is an active low input to DAC3282. SDIO is serial data in
during the instruction cycle. In 3 pin configuration, SDIO is data out from DAC3282 during the data transfer
cycle(s), while ALARM_SDO is in a high-impedance state. In 4 pin configuration, both ALARM_SDO and SDIO
are data out from DAC3282. At the end of the data transfer, ALARM_SDO will output low on the final falling edge
of SCLK until the rising edge of SDENB when it will 3-state.
Instruction Cycle
Data Transfer Cycle
SDENB
SCLK
SDIO
rwb
N1
N0
-
A3
A2
ALARM_
SDO
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
3-pin interface
D7
D6
D5
D4
D3
D2
D1
D0
4-pin interface
SDENB
SCLK
SDIO or
ALARM_SDO
Data n
Data n-1
td (Data)
Figure 41. Serial Interface Read Timing Diagram
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7.6 Register Maps
Table 8. Register Descriptions
Name
Address
Default
(MSB)
Bit 7
CONFIG0
0x00
0x70
qmc_offset_ena
fifo_ena
fifo_reset_ena
multi_sync_ena
alarm_out_ena
alarm_pol
CONFIG1
0x01
0x11
unused
unused
unused
fir_ena
fir4_ena
iotest_ena
CONFIG2
0x02
0x00
unused
unused
unused
unused
CONFIG3
0x03
0x10
64cnt_ena
unused
unused
CONFIG4
0x04
0XFF
CONFIG5
0x05
N/A
CONFIG6
0x06
0x00
unused
CONFIG7
0x07
0x00
unused
CONFIG8
0x08
0x00
iotest_results(7:0)
CONFIG9
0x09
0x7A
iotest_pattern0(7:0)
CONFIG10
0x0A
0xB6
iotest_pattern1(7:0)
CONFIG11
0x0B
0xEA
iotest_pattern2(7:0)
CONFIG12
0x0C
0x45
iotest_pattern3(7:0)
CONFIG13
0x0D
0x1A
iotest_pattern4(7:0)
CONFIG14
0x0E
0x16
iotest_pattern5(7:0)
CONFIG15
0x0F
0xAA
iotest_pattern6(7:0)
CONFIG16
0x10
0xC6
CONFIG17
0x11
0x00
CONFIG18
0x12
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
mixer_func(1:0)
unused
twos
output_delay(3:0)
alarm_
2away_ena
fifo_offset(2:0)
coarse_daca(3:0)
alarm_
1away_ena
coarse_dacb(3:0)
tempdata(7:0)
alarm_mask(6:0)
alarm_from_
zerochk
alarm_fifo_
collision
reserved
alarm_from_ iotest
unused
alarm_fifo_
2away
alarm_fifo_
1away
iotest_pattern7(7:0)
reserved
0x02
reserved
reserved
reserved
aequalsb
reserved
unused
reserved
daca_
complement
unused
dacb_
complement
clkdiv_
sync_ena
unused
unused
multi_
sync_sel
rev
CONFIG19
0x13
0x00
CONFIG20
0x14
0x00
CONFIG21
0x15
0x00
CONFIG22
0x16
0x00
qmc_offseta(12:8)
unused
unused
unused
CONFIG23
0x17
0x00
qmc_offsetb(12:8)
sif4_ena
clkpath_
sleep_a
clkpath_
sleep_b
CONFIG24
0x18
0x83
sleepa
reserved
reserved
CONFIG25
0x19
0x00
extref_ena
reserved
reserved
CONFIG26
0x1A
0x00
CONFIG27
0x1B
0x00
reserved
CONFIG28
0x1C
0x00
reserved
CONFIG29
0x1D
0x00
reserved
CONFIG30
0x1E
0x00
VERSION31
0x1F
0x43
32
bequalsa
reserved
qmc_offseta(7:0)
qmc_offsetb(7:0)
tsense_ena
clkrecv_sleep
unused
reserved
sleepb
reserved
unused
unused
unused
unused
unused
reserved
reserved
deviceid(1:0)
version(5:0)
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7.6.1 CONFIG0 (address = 0x00) [reset = 0x70]
Figure 42. CONFIG0
7
qmc_offset_ena
R/W
6
fifoin_ena
R/W
5
fifo_reset_ena
R/W
4
multi_sync_ena
R/W
3
alarm_out_ena
R/W
2
alarm_pol
R/W
1
0
mixer_func
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. CONFIG0 Field Descriptions
Bit
Field
Type
Reset
Description
7
qmc_offset_ena
R/W
0
When asserted the DAC offset correction is enabled.
6
fifo_ena
R/W
1
When asserted the FIFO is enabled. When the FIFO is bypassed
DACCCLKP/N and DATACLKP/N must be aligned to within t_align.
5
fifo_reset_ena
R/W
1
Allows the FRAME input to reset the FIFO write pointer when asserted
4
multi_sync_ena
R/W
1
Allows the FRAME or OSTR signal to reset the FIFO read pointer when
asserted. This selection is determined by multi_sync_sel in register CONFIG19.
3
alarm_out_ena
R/W
0
When asserted the ALARM_SDO pin becomes an output. The functionality of
this pin is controlled by the CONFIG6 alarm_mask setting.
2
alarm_pol
R/W
0
This bit changes the polarity of the ALARM signal. (0=negative logic, 1=positive
logic)
1:0
mixer_func
R/W
00
Controls the function of the mixer block.
Mode
mixer_func(1:0)
Normal
00
High Pass (Fs/2)
01
Fs/4
10
–Fs/4
11
7.6.2 CONFIG1 (address = 0x01) [reset = 0x11]
Figure 43. CONFIG1
7
Unused
R/W
6
Unused
R/W
5
Unused
R/W
4
fir_ena
R/W
3
fir4_ena
R/W
2
iotest_ena
R/W
1
Unused
R/W
0
twos
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. CONFIG1 Field Descriptions
Bit
Field
Type
Reset
Description
7
Unused
R/W
0
Reserved for factory use
6
Unused
R/W
0
Reserved for factory use.
5
Unused
R/W
0
Reserved for factory use
4
fir_ena
R/W
1
When asserted the chip does 2X interpolation of the data.
3
fir4_ena
R/W
0
When asserted, the zero-IF sinc correction filter is enabled. This filter cannot
be used unless fir_ena is asserted.
2
iotest_ena
R/W
0
When asserted enables the data pattern checker operation.
1
Unused
R/W
0
Reserved for factory use.
0
twos
R/W
1
When asserted the inputs are expected to be in 2's complement format. When
de-asserted the input format is expected to be offset-binary.
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7.6.3 CONFIG2 (address = 0x02) [reset = 0x00]
Figure 44. CONFIG2
7
Unused
R/W
6
Unused
R/W
5
Unused
R/W
4
Unused
R/W
3
2
1
0
R/W
R/W
output_delay
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. CONFIG2 Field Descriptions
Bit
Field
Type
Reset
Description
7
Unused
R/W
0
Reserved for factory use.
6
Unused
R/W
0
Reserved for factory use.
5
Unused
R/W
0
Reserved for factory use.
4
Unused
R/W
0
Reserved for factory use.
output_delay
R/W
0000
Delays the output to the DACs from 0 to 15 DAC clock cycles.
3:0
7.6.4 CONFIG3 (address = 0x03) [reset = 0x10]
Figure 45. CONFIG3
7
64cnt_ena
R/W
6
Unused
R/W
5
Unused
R/W
4
3
fifo_offset
R/W
R/W
2
1
alarm_2away_ena
R/W
R/W
0
alarm_1away_ena
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. CONFIG3 Field Descriptions
Bit
Field
Type
Reset
Description
7
64cnt_ena
R/W
0
This enables resetting the alarms after 64 good samples with the
goal of removing unnecessary errors. For instance, when checking
setup/hold through the pattern checker test, there may initially be
errors. Setting this bit removes the need for a SIF write to clear the
alarm register.
6
Unused
R/W
0
Reserved for factory use.
5
Unused
R/W
0
Reserved for factory use.
fifo_offset
R/W
100
This is the default FIFO read pointer position after the FIFO read
pointer has been synced. With this value the initial difference
between write and read pointers can be controlled. This may be
helpful in controlling the delay through the device.
1
alarm_2away_ena
R/W
0
When asserted alarms from the FIFO that represent the write and
read pointers being 2 away are enabled.
0
alarm_1away_ena
R/W
0
When asserted alarms from the FIFO that represent the write and
read pointers being 1 away are enabled.
4:2
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7.6.5 CONFIG4 (address = 0x04) [reset = 0xFF]
Figure 46. CONFIG4
7
6
5
4
3
2
coarse_daca
R/W
R/W
1
0
R/W
R/W
coarse_dach
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. CONFIG4 Field Descriptions
Bit
Field
Type
Reset
Description
7:4
coarse_daca
R/W
1111
Scales the DACA output current in 16 equal steps.
VEXTIO
´ (coarse_daca/b + 1)
Rbias
3:0
coarse_dach
R/W
1111
Scales the DACB output current in 16 equal steps.
7.6.6 CONFIG5 (address = 0x05) READ ONLY
Figure 47. CONFIG5
7
6
5
4
3
2
1
0
R
R
R
R
tempdata
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. CONFIG5 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
tempdata
R
N/A
This is the output from the chip temperature sensor. The value
of this register in two’s complement format represents the
temperature in degrees Celsius. This register must be read
with a minimum SCLK period of 1µs. (Read Only)
7.6.7 CONFIG6 (address =0x06) [reset = 0x00]
Figure 48. CONFIG6
7
Unused
R/W
6
5
4
R/W
R/W
R/W
3
alarm_mask
R/W
2
1
0
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. CONFIG6 Field Descriptions
Bit
7
6:0
Field
Type
Reset
Description
Unused
R/W
0
Reserved for factory use.
alarm_mask
R/W
0000000
These bits control the masking of the alarm outputs. This
means that the ALARM_SDO pin will not be asserted if the
appropriate bit is set. The alarm will still show up in the
CONFIG7 bits. (0=not masked, 1= masked).
alarm_mask
Masked Alarm
6
alarm_from_zerochk
5
alarm_fifo_collision
4
reserved
3
alarm_from_iotest
2
not used (expansion)
1
alarm_fifo_2away
0
alarm_fifo_1away
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7.6.8 CONFIG7 (address = 0x07) [reset = 0x00] (WRITE TO CLEAR)
Figure 49. CONFIG7
7
6
alarm_from_
zerochk
W
Unused
W
5
alarm_fifo_
collision
W
4
Reserved
W
3
alarm_from_
iotest
W
2
Unused
W
1
alarm_fifo_
2away
W
0
alarm_fifo_
1away
W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. CONFIG7 Field Descriptions
Bit
Field
Type
Reset
Description
7
Unused
W
0
Reserved for factory use.
6
alarm_from_zerochk
W
0
This alarm indicates the 8-bit FIFO write pointer address has an all
zeros patterns. Due to pointer address being a shift register, this is
not a valid address and will cause the write pointer to be stuck until
the next sync. This error is typically caused by timing error or
improper power start-up sequence. If this alarm is asserted,
resynchronization of FIFO is necessary. Refer to the Power-Up
Sequence section for more detail.
5
alarm_fifo_collision
W
0
Alarm occurs when the FIFO pointers over/under run each other.
4
Reserved
W
0
Reserved for factory use.
3
alarm_from_iotest
W
0
This is asserted when the input data pattern does not match the
pattern in the iotest_pattern registers.
2
Unused
W
0
Reserved for factory use.
1
alarm_fifo_2away
W
0
Alarm occurs with the read and write pointers of the FIFO are within
2 addresses of each other.
0
alarm_fifo_1away
W
0
Alarm occurs with the read and write pointers of the FIFO are within
1 address of each other.
7.6.9 CONFIG8 (address = 0x08) [reset = 0x00] (WRITE TO CLEAR)
Figure 50. CONFIG8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
iotest_results
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17. CONFIG8 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
iotest_results
R/W
0x00
The values of these bits tell which bit in the byte-wide LVDS bus
failed during the pattern checker test.
7.6.10 CONFIG9 (address = 0x09) [reset = 0x7A]
Figure 51. CONFIG9
7
6
5
4
R/W
R/W
R/W
3
iotest_pattern0
R/W
R/W
2
1
0
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. CONFIG9 Field Descriptions
36
Bit
Field
Type
Reset
Description
7:0
iotest_pattern0
R/W
0x7A
This is dataword0 in the IO test pattern. It is used with the seven
other words to test the input data.
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7.6.11 CONFIG10 (address = 0x0A) [reset = 0xB6]
Figure 52. CONFIG10
7
6
5
R/W
R/W
R/W
4
3
iotest_pattern1
R/W
R/W
2
1
0
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. CONFIG10 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
iotest_pattern1
R/W
0xB6
This is dataword1 in the IO test pattern. It is used with the seven
other words to test the input data.
7.6.12 CONFIG11 (address = 0x0B) [reset = 0xEA]
Figure 53. CONFIG11
7
6
5
R/W
R/W
R/W
4
3
iotest_pattern2
R/W
R/W
2
1
0
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. CONFIG11 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
iotest_pattern2
R/W
0xEA
This is dataword2 in the IO test pattern. It is used with the seven
other words to test the input data.
7.6.13 CONFIG12 (address =0x0C) [reset = 0x45]
Figure 54. CONFIG12
7
6
5
R/W
R/W
R/W
4
3
iotest_pattern3
R/W
R/W
2
1
0
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. CONFIG12 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
iotest_pattern3
R/W
0x45
This is dataword3 in the IO test pattern. It is used with the seven
other words to test the input data.
7.6.14 CONFIG13 (address =0x0D) [reset = 0x1A]
Figure 55. CONFIG13
7
6
5
R/W
R/W
R/W
4
3
iotest_pattern4
R/W
R/W
2
1
0
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. CONFIG13 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
iotest_pattern4
R/W
0x1A
This is dataword4 in the IO test pattern. It is used with the seven
other words to test the input data.
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7.6.15 CONFIG14 Register Name (address = 0x0E) [reset = 0x16]
Figure 56. CONFIG14
7
6
5
R/W
R/W
R/W
4
3
iotest_pattern5
R/W
R/W
2
1
0
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. CONFIG14 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
iotest_pattern5
R/W
0x16
This is dataword5 in the IO test pattern. It is used with the seven
other words to test the input data.
7.6.16 CONFIG15 Register Name (address = 0x0F) [reset = 0xAA]
Figure 57. CONFIG15
7
6
5
R/W
R/W
R/W
4
3
iotest_pattern6
R/W
R/W
2
1
0
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. CONFIG15 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
iotest_pattern6
R/W
0xAA
This is dataword6 in the IO test pattern. It is used with the seven
other words to test the input data.
7.6.17 CONFIG16 (address = 0x10) [reset = 0xC6]
Figure 58. CONFIG16
7
6
5
R/W
R/W
R/W
4
3
iotest_pattern7
R/W
R/W
2
1
0
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. CONFIG16 Field Descriptions
38
Bit
Field
Type
Reset
Description
7:0
iotest_pattern7
R/W
0xC6
This is dataword7 in the IO test pattern. It is used with the seven
other words to test the input data.
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7.6.18 CONFIG17 (address = 0x11) [reset = 0x00]
Figure 59. CONFIG17
7
Reserved
R/W
6
Reserved
R/W
5
Reserved
R/W
4
Reserved
R/W
3
Reserved
R/W
2
Reserved
R/W
1
Reserved
R/W
0
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. CONFIG17 Field Descriptions
Bit
Field
Type
Reset
Description
7:6
Reserved
R/W
00
Reserved for factory use.
5
Reserved
R/W
0
Reserved for factory use.
4
Reserved
R/W
0
Reserved for factory use.
3:0
Reserved
R/W
0000
Reserved for factory use.
7.6.19 CONFIG18 (address = 0x12) [reset = 0x02]
Figure 60. CONFIG18
7
6
Reserved
R/W
R/W
5
4
R/W
R/W
3
daca_complement
R/W
2
dacb_complement
R/W
1
clkdiv_sync_ena
R/W
0
Unused
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. CONFIG18 Field Descriptions
Bit
Field
Type
Reset
Description
7:5
Reserved
R/W
000
Reserved for factory use.
4
Reserved
R/W
0
Reserved for factory use.
3
dacb_complement
R/W
0
When asserted the output to the DACA is complemented. This
allows to effectively change the + and – designations of the
LVDS data lines.
2
daca_complement
R/W
0
When asserted the output to the DACB is complemented. This
allows to effectively change the + and – designations of the
LVDS data lines.
1
clkdiv_sync_ena
R/W
1
Enables the syncing of the clock divider using the OSTR signal
or the FRAME signal passed through the FIFO. This selection is
determined by multi_sync_sel in register CONFIG19. The
internal divided-down clocks are phase-aligned after syncing.
See Power-Up Sequence section for more detail.
0
Unused
R/W
0
Reserved for factory use.
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7.6.20 CONFIG19 (address = 0x13) [reset = 0x00]
Figure 61. CONFIG19
7
bequalsa
R/W
6
aequalsb
R/W
5
Reserved
R/W
4
Unused
R/W
3
Unused
R/W
2
Unused
R/W
1
multi_sync_sel
R/W
0
rev
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. CONFIG19 Field Descriptions
Bit
Field
Type
Reset
Description
7
bequalsa
R/W
0
When asserted the DACA data is driven onto DACB.
6
aequalsb
R/W
0
When asserted the DACB data is driven onto DACA.
5
Reserved
R/W
0
Reserved for factory use.
4
Unused
R/W
0
Reserved for factory use.
3
Unused
R/W
0
Reserved for factory use.
2
Unused
R/W
0
Reserved for factory use.
1
multi_sync_sel
R/W
0
Selects the signal source for multiple device and clock divider
synchronization.
0
rev
R/W
0
multi_sync_sel
Sync Source
0
OSTR
1
FRAME through FIFO handoff
Reverse the input bits for the data word. MSB becomes LSB.
7.6.21 CONFIG20 (address = 0x14) [reset = 0x00] (CAUSES AUTOSYNC)
Figure 62. CONFIG20
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
qmc_offseta
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 29. CONFIG20 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
qmc_offseta
R/W
0x00
Lower 8 bits of the DAC A offset correction. The offset is
measured in DAC LSBs. Writing this register causes an
autosync to be generated. This loads the values of all four
qmc_offset registers (CONFIG20-CONFIG23) into the offset
block at the same time. When updating the offset values
CONFIG20 should be written last. Programming any of the
other three registers will not affect the offset setting.
7.6.22 CONFIG21 (address = 0x15) [reset = 0x00]
Figure 63. CONFIG21
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
qmc_offsetb
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 30. CONFIG21 Field Descriptions
40
Bit
Field
Type
Reset
Description
7:0
qmc_offsetb
R/W
0x00
Lower 8 bits of the DAC B offset correction. The offset is
measured in DAC LSBs.
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7.6.23 CONFIG22 (address = 0x16) [reset = 0x00]
Figure 64. CONFIG22
7
6
R/W
R/W
5
qmc_offseta
R/W
4
3
R/W
R/W
2
Unused
R/W
1
Unused
R/W
0
Unused
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 31. CONFIG22 Field Descriptions
Bit
Field
Type
Reset
Description
7:3
qmc_offseta
R/W
00000
Upper 5 bits of the DAC A offset correction.
2
Unused
R/W
0
Reserved for factory use.
1
Unused
R/W
0
Reserved for factory use.
0
Unused
R/W
0
Reserved for factory use.
7.6.24 CONFIG23 (address = 0x17) [reset = 0x00]
Figure 65. CONFIG23
7
6
5
qmc_offsetb(12:8)
4
3
2
sif4_ena
R/W
R/W
R/W
R/W
R/W
R/W
1
clkpath_sleep_
a
R/W
0
clkpath_sleep_
b
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 32. CONFIG23 Field Descriptions
Bit
Field
Type
Reset
Description
7:3
qmc_offsetb(12:8)
R/W
00000
Upper 5 bits of the DAC B offset correction.
2
sif4_ena
R/W
0
When asserted the SIF interface becomes a 4 pin interface. The
ALARM_SDO pin is turned into a dedicated output for the
reading of data.
1
clkpath_sleep_a
R/W
0
When asserted puts the clock path through DAC A to sleep. This
is useful for sleeping individual DACs. Even if the DAC is asleep
the clock needs to pass through it for the logic to work.
However, if the chip is being put into a power down mode, then
all parts of the DAC can be turned off.
0
clkpath_sleep_b
R/W
0
When asserted puts the clock path through DAC B to sleep.
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7.6.25 CONFIG24 (address = 0x18) [reset = 0x83]
Figure 66. CONFIG24
7
tsense_ena
R/W
6
clkrecv_sleep
R/W
5
Unused
R/W
4
Reserved
R/W
3
sleepb
R/W
2
sleepa
R/W
1
Reserved
R/W
0
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 33. CONFIG24 Field Descriptions
Bit
Field
Type
Reset
Description
7
tsense_ena
R/W
1
Turns on the temperature sensor when asserted.
6
clkrecv_sleep
R/W
0
When asserted the clock input receiver gets put into sleep
mode. This also affects the OSTR receiver.
5
Unused
R/W
0
Reserved for factory use.
4
Reserved
R/W
0
Reserved for factory use.
3
sleepb
R/W
0
When asserted DACB is put into sleep mode.
2
sleepa
R/W
0
When asserted DACA is put into sleep mode.
1
Reserved
R/W
1
Reserved for factory use.
0
Reserved
R/W
1
Reserved for factory use.
7.6.26 CONFIG25 (address = 0x19) [reset = 0x00]
Figure 67. CONFIG25
7
6
R/W
R/W
5
Reserved
R/W
4
3
R/W
R/W
2
extref_ena
R/W
1
Reserved
R/W
0
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 34. CONFIG25 Field Descriptions
Bit
Field
Type
Reset
Description
7:3
Reserved
R/W
00000
Reserved for factory use.
2
extref_ena
R/W
0
Allows the device to use an external reference or the internal
reference. (0=internal, 1=external)
1
Reserved
R/W
0
Reserved for factory use.
0
Reserved
R/W
0
Reserved for factory use.
7.6.27 CONFIG26 (address = 0x1A) [reset = 0x00]
Figure 68. CONFIG26
7
Reserved
R/W
6
Reserved
R/W
5
Reserved
R/W
4
Reserved
R/W
3
Unused
R/W
2
R/W
1
Reserved
R/W
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 35. CONFIG26 Field Descriptions
Bit
Field
Type
Reset
Description
7
Reserved
R/W
0
Reserved for factory use.
6
Reserved
R/W
0
Reserved for factory use.
5
Reserved
R/W
0
Reserved for factory use.
5
Reserved
R/W
0
Reserved for factory use.
3
Unused
R/W
0
Reserved for factory use.
Reserved
R/W
000
Reserved for factory use.
2:0
42
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7.6.28 CONFIG27 (address =0x1B) [reset = 0x00]
Figure 69. CONFIG27
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
Reserved
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 36. CONFIG27 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R/W
0x00
Reserved for factory use.
7.6.29 CONFIG28 (address = 0x1C) [reset = 0x00]
Figure 70. CONFIG28
7
6
5
R/W
R/W
R/W
4
Reserved
R/W
3
2
1
0
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 37. CONFIG28 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R/W
0x00
Reserved for factory use.
7.6.30 CONFIG29 (address = 0x1D) [reset = 0x00]
Figure 71. CONFIG29
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
Reserved
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 38. CONFIG29 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R/W
0x00
Reserved for factory use.
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7.6.31 CONFIG30 (address = 0x1E) [reset = 0x00]
Figure 72. CONFIG30
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
2
1
0
R
R
R
Reserved
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 39. CONFIG30 Field Descriptions
Bit
Field
Type
Reset
Description
7:0
Reserved
R/W
0x00
Reserved for factory use.
7.6.32 VERSION31 (address = 0x1F) [reset = 0x43] (READ ONLY)
Figure 73. VERSION31
7
6
5
4
3
deviceid
R
version
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 40. VERSION31 Field Descriptions
44
Bit
Field
Type
Reset
Description
7:0
deviceid(1:0)
R
01
Returns ‘01’ for DAC3282. (Read Only)
5:0
version(5:0)
R
000011
A hardwired register that contains the version of the chip. (Read
Only)
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DAC3282 is appropriate for a variety of transmitter applications including complex I/Q direct conversion, upconversion using an intermediate frequency (IF) and diversity applications.
8.1.1 Multi-device Synchronization
In various applications, such as multi antenna systems where the various transmit channels information is
correlated, it is required that multiple DAC devices are completely synchronized such that their outputs are phase
aligned. The DAC3282 architecture supports this mode of operation.
8.1.1.1 Multi-device Synchronization: Dual Sync Sources Mode
For single or multi-device synchronization it is important that delay differences in the data are absorbed by the
device so that latency through the device remains the same. Furthermore, to guarantee that the outputs from
each DAC are phase aligned it is necessary that data is read from the FIFO of each device simultaneously. In
the DAC3282 this is accomplished by operating the multiple devices in Dual Sync Sources mode. In this mode
the additional OSTR signal is required by each DAC3282 to be synchronized.
Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into the
multiple DAC devices can experience different delays due to variations in the digital source output paths or board
level wiring. These different delays can be effectively absorbed by the DAC3282 FIFO so that all outputs are
phase aligned correctly.
DACCLKP/N
OSTRP/N
D[7:0]P/N
FPGA
DAC3282/3 DAC1
FRAMEP/N
LVPECL Outputs
PLL/
DLL
LVDS Interface
Clock Generator
delay 1
DATACLKP/N
Variable delays due to variations in the
FPGA(s) output paths or board level wiring
or temperature/voltage deltas
Outputs are
phase aligned
D[7:0]P/N
LVPECL Outputs
FRAMEP/N
delay 2
DATACLKP/N
DAC3282/3 DAC2
OSTRP/N
DACCLKP/N
Figure 74. Synchronization System in Dual Sync Sources Mode with PLL Bypassed
For correct operation both OSTR and DACCLK must be generated from the same clock domain. The OSTR
signal is sampled by DACCLK and must satisfy the timing requirements in the specifications table. If the clock
generator does not have the ability to delay the DACCLK to meet the OSTR timing requirement, the polarity of
the DACCLK outputs can be swapped with respect to the OSTR ones to create 180 degree phase delay of the
DACCLK. This may help establish proper setup and hold time requirement of the OSTR signal.
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Application Information (continued)
LVPECL Pairs
(DAC3282/3 1)
Careful board layout planning must be done to ensure that the DACCLK and OSTR signals are distributed from
device to device with the lowest skew possible as this will affect the synchronization process. In order to
minimize the skew across devices it is recommended to use the same clock distribution device to provide the
DACCLK and OSTR signals to all the DAC devices in the system.
DACCLKP/N(1)
ts(OSTR)
th(OSTR)
tSKEW ~ 0
LVPECL Pairs
(DAC3282/3 2)
OSTRP/N(1)
DACCLKP/N(2)
ts(OSTR)
th(OSTR)
OSTRP/N(2)
Figure 75. Timing Diagram for LVPECL Synchronization Signals
The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the
DAC3282 devices have a DACCLK and OSTR signal and must be carried out on each device.
1. Start-up the device as described in the power-up sequence. Set the DAC3282 in Dual Sync Sources mode
and select OSTR as the FIFO output pointer sync source and clock divider sync source (multi_sync_sel in
register config19).
2. Sync the clock divider and FIFO pointers.
3. Verify there are no FIFO alarms either through register config7 or through the ALARM_SDO pin.
After these steps all the DAC3282 outputs will be synchronized.
8.1.1.2 Multi-device Operation: Single Sync Source Mode
In Single Sync Source mode, the FIFO write and read pointers are reset from the same FRAME source.
Although the FIFO in this mode can still absorb the data delay differences due to variations in the digital source
output paths or board level wiring, it is impossible to guarantee data will be read from the FIFO of different
devices simultaneously thus preventing exact phase alignment.
The FIFO read pointer reset is handoff between the two clock domains (DATACLK and FIFO OUT CLOCK) by
simply re-sampling the write pointer reset. Since the two clocks are asynchronous there is a small but distinct
possibility of a meta-stablility during the pointer handoff. This meta-stability can cause the outputs of the multiple
devices to slip by up to 2 DAC clock cycles.
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Application Information (continued)
DACCLKP/N
D[7:0]P/N
FPGA
DAC3282/3 DAC1
FRAMEP/N
LVPECL Output
LVDS Interface
Clock Generator
delay 1
DATACLKP/N
PLL/
DLL
0 to 2
DAC Clock cycles
Variable delays due to variations in the
FPGA(s) output paths or board level wiring
or temperature/voltage deltas
D[7:0]P/N
LVPECL Output
FRAMEP/N
delay 2
DATACLKP/N
DAC3282/3 DAC2
DACCLKP/N
Figure 76. Multi-Device Operation in Single Sync Source Mode
8.1.2 Analog Current Outputs
Figure 77 shows a simplified schematic of the current source array output with corresponding switches.
Differential switches direct the current of each individual NMOS current source to either the positive output node
IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by the stack of
the current sources and differential switches, and is typically >300 kΩ in parallel with an output capacitance of 5
pF.
The external output resistors are referred to an external ground. The minimum output compliance at nodes
IOUT1 and IOUT2 is limited to AVDD – 0.5 V, determined by the CMOS process. Beyond this value, transistor
breakdown may occur resulting in reduced reliability of the DAC3282 device. The maximum output compliance
voltage at nodes IOUT1 and IOUT2 equals AVDD + 0.5 V. Exceeding the minimum output compliance voltage
adversely affects distortion performance and integral non-linearity. The optimum distortion performance for a
single-ended or differential output is achieved when the maximum full-scale signal at IOUT1 and IOUT2 does not
exceed 0.5 V.
AVDD
RLOAD
RLOAD
IOUT1
IOUT2
S(1)
S(N)
S(2)
S(1)C
S(2)C
S(N)C
...
Figure 77. Equivalent Analog Current Output
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Application Information (continued)
The DAC3282 can be easily configured to drive a doubly terminated 50 Ω cable using a properly selected RF
transformer. Figure 78 and Figure 79 show the 50 Ω doubly terminated transformer configuration with 1:1 and 4:1
impedance ratio, respectively. Note that the center tap of the primary input of the transformer has to be
connected to AVDD to enable a DC current flow. Applying a 20 mA full-scale output current would lead to a 0.5
Vpp for a 1:1 transformer and a 1 Vpp output for a 4:1 transformer. The low dc-impedance between IOUT1 or
IOUT2 and the transformer center tap sets the center of the ac-signal at AVDD, so the 1 Vpp output for the 4:1
transformer results in an output between AVDD + 0.5 V and AVDD – 0.5 V.
AVDD
3.3 V
50 W
1:1
IOUT 1
RLOAD
50 W
100 W
IOUT 2
50 W
AVDD 3.3 V
Figure 78. Driving a Doubly Terminated 50 Ω Cable Using a 1:1 Impedance Ratio Transformer
AVDD
3.3 V
100 W
4 :1
IOUT 1
RLOAD
50 W
IOUT 2
100 W
AVDD 3.3 V
Figure 79. Driving a Doubly Terminated 50 Ω Cable Using a 4:1 Impedance Ratio Transformer
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Application Information (continued)
8.1.3 Passive Interface to Analog Quadrature Modulators
A common application in communication systems is to interface the DAC to an IQ modulator like the TRF3703
family of modulators from Texas Instruments. The input of the modulator is generally of high impedance and
requires a specific common-mode voltage. A simple resistive network can be used to maintain 50Ω load
impedance for the DAC3282 and also provide the necessary common-mode voltages for both the DAC and the
modulator.
Vin ~ Varies
Vout ~ 2.8 to 3.8 V
I1
Signal Conditioning
IOUTA1
IOUTA2
IOUTB1
IOUTB2
I2
S
Q1
RF
Q2
Quadrature modulator
Figure 80. DAC to Analog Quadrature Modulator Interface
The DAC3282 has a maximum 20mA full-scale output and a voltage compliance range of AVDD ± 0.5 V. The
TRF3703 IQ modulator family can be operated at three common-mode voltages: 1.5V, 1.7V, and 3.3V.
Figure 81 shows the recommended passive network to interface the DAC3282 to the TRF3703-17 which has a
common mode voltage of 1.7V. The network generates the 3.3V common mode required by the DAC output and
1.7V at the modulator input, while still maintaining 50Ω load for the DAC.
V1
R1
I
I
R2
R3
DAC3282
TRF3703-17
V2
R3
R2
/I
/I
R1
V1
Figure 81. DAC3282 to TRF3703-17 Interface
If V1 is set to 5V and V2 is set to -5V, the corresponding resistor values are R1 = 57Ω, R2 = 80Ω, and R3 =
336Ω. The loss developed through R2 is about -1.86 dB. In the case where there is no –5V supply available and
V2 is set to 0V, the resistor values are R1 = 66Ω, R2 = 101Ω, and R3 = 107Ω. The loss with these values is
–5.76dB.
Figure 82 shows the recommended network for interfacing with the TRF3703-33 which requires a common mode
of 3.3V. This is the simplest interface as there is no voltage shift. Because there is no voltage shift there isn't any
loss in the network. With V1 = 5V and V2 = 0V, the resistor values are R1 = 66Ω and R3 = 208Ω.
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Application Information (continued)
V1
R1
I
I
R3
DAC3282
TRF3703-33
V2
R3
/I
/I
R1
V1
Figure 82. DAC3282 to TRF3703-33 Interface
In most applications a baseband filter is required between the DAC and the modulator to eliminate the DAC
images. This filter can be placed after the common-mode biasing network. For the DAC to modulator network
shown in Figure 83, R2 and the filter load R4 need to be considered into the DAC impedance. The filter has to be
designed for the source impedance created by the resistor combination of R3 // (R2+R1). The effective
impedance seen by the DAC is affected by the filter termination resistor resulting in R1 // (R2+R3 // (R4/2)).
V1
R1
R2
I
R3
Filter
V2
DAC3282
R4
TRF3703
R3
R2
/I
R1
V1
Figure 83. DAC3282 to Modulator Interface with Filter
Factoring in R4 into the DAC load, a typical interface to the TRF3703-17 with V1 = 5V and V2 = 0V results in the
following values: R1 = 72Ω, R2 = 116Ω, R3 = 124Ω and R4 = 150Ω. This implies that the filter needs to be
designed for 75Ω input and output impedance (single-ended impedance). The common mode levels for the DAC
and modulator are maintained at 3.3V and 1.7V and the DAC load is 50Ω. The added load of the filter
termination causes the signal to be attenuated by –10.8 dB.
A filter can be implemented in a similar manner to interface with the TRF3703-33. In this case it is much simpler
to balance the loads and common mode voltages due to the absence of R2. An added benefit is that there is no
loss in this network. With V1 = 5V and V2 = 0V the network can be designed such that R1 = 115Ω, R3 = 681Ω,
and R4 = 200Ω. This results in a filter impedance of R1 // R2=100Ω, and a DAC load of R1 // R3 // (R4/2) which
is equal to 50Ω. R4 is a differential resistor and does not affect the common mode level created by R1 and R3.
The common-mode voltage is set at 3.3 V for a full-scale current of 20mA.
For more information on how to interface the DAC3282 to an analog quadrature modulator please refer to the
application reports Passive Terminations for Current Output DACs (SLAA399) and Design of Differential Filters
for High-Speed Signal Chains (SLWA053).
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8.2 Typical Application
5V
Byte-Wide
Data
100
DATACLKP /N
100
Optional
Filter Network
FRAMEP/N
DAC-A
CMIX
100
I-FIR
D0P/N
Q-FIR
100
QISINC
D7P/N
IISINC
DAC3282 DAC
FIFO & Demux
LVDS Data Interface
FPGA
DAC-B
RF OUT
DACCLKP/N
100
0
100
90
PLL/
DLL
Div
2/4/8
VCO
NDivider
VCTRL_IN
Loop
Filter
PFD
RDiv
/1
/2
Div
Clock Divider/
Distribution
CDCE62005
Clock Generator with VCO
PFD/CP
CPOUT
TRF3720
AQM with PLL/VCO
Loop
Filter
Div
10 MHz
OSC
Figure 84. System Diagram of Direct Conversion Radio
8.2.1 Design Requirements
For this design example of a direct conversion transmitter, use the parameters in Table 41.
Table 41. Design Parameters
PARAMETER
VALUE
Channel Type
4x W-CDMA Carriers, each with 3.84 MHz bandwidth
(20 MHz total bandwidth)
Input Data Rate
307.2 MSPS
Interpolation
2
NCO Frequency
Bypassed
Output IF
None (Complex baseband)
DAC Conversion Rate (DACCLK frequency)
614.4 MSPS
8.2.2 Detailed Design Procedure
Refer to Figure 84 for an example Direct Conversion Radio. The DAC3282 receives an interleaved complex I/Q
baseband input data stream and increases the sample rate through interpolation by a factor of 2 or 4. By
performing digital interpolation on the input data, undesired images of the original signal can be push out of the
band of interest and more easily suppressed with analog filters.
For a Zero IF (ZIF) frequency plan, complex mixing of the baseband signal is not required. Alternatively, for a
Complex IF frequency plan the input data can be pre-placed at an IF within the bandwidth limitations of the
interpolation filters. In addition, complex mixing is available using the coarse mixer block to up-convert the signal.
The output of both DAC channels is used to produce a Hilbert transform pair and can be expressed as:
AOUT(t) = A(t)cos(ωct) – B(t)sin(ωct) = m(t)
(3)
BOUT(t) = A(t)sin(ωct) + B(t)cos(ωct) = mh(t)
(4)
where m(t) and mh(t) connote a Hilbert transform pair and ωc is the mixer frequency. The complex output is input
to an analog quadrature modulator (AQM) such as the Texas Instruments TRF3720 for a single side-band (SSB)
up conversion to RF. A passive (resistor only) interface to the AQM with an optional LC filter network is
recommended. The TRF3720 includes a VCO/PLL to generate the LO frequency. Upper single-sideband
upconversion is achieved at the output of the analog quadrature modulator, whose output is expressed as:
RF(t) = A(t)cos(ωc + ωLO)t – B(t)sin(ωc + ωLO)t
(5)
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Flexibility is provided to the user by allowing for the selection of negative mixing frequency to produce a lowersideband upconversion. Note that the process of complex mixing translates the signal frequency from 0Hz
means that the analog quadrature modulator IQ imbalance produces a sideband that falls outside the signal of
interest. DC offset error in DAC and AQM signal path may produce LO feed-through at the RF output which may
fall in the band of interest. To suppress the LO feed-through, the DAC3282 provides a digital offset correction
capability for both DAC-A and DAC-B paths. In addition phase and gain imbalances in the DAC and AQM result
in a lower-sideband product. The DAC3282 offers gain and phase correction capabilities to minimize the
sideband product.
The complex IF architecture has several advantages over the real IF architecture:
• Uncalibrated side-band suppression ~ 35dBc compared to 0dBc for real IF architecture.
• Direct DAC to AQM interface – no amplifiers required
• DAC 2nd Nyquist zone image is offset fDAC compared with fDAC– 2 x IF for a real IF architecture, reducing the
need for filtering at the DAC output.
• Uncalibrated LO feed through for AQM is ~ 35 dBc and calibration can reduce or completely remove the LO
feed through.
8.2.3 Application Performance Curves
* R BW 30 kH z
* RBW 30 kHz
* VBW 300 kHz
* V BW 30 0 k Hz
Re f - 13 d B m
* At t
15 d B
* S WT 10 s
Ref -14.4 dBm
- 20
CL RW R
10 dB
-30
A
- 40
-40
- 50
-50
A
1 RM *
-60
CLRWR
-70
- 60
- 70
- 80
-80
- 90
-90
N OR
- 10 0
- 11 0
NOR
-100
-110
- 12 0
- 13 0
-120
-130
Ce nt e r 7 0 M Hz
2 MH z/
Tx Channel
Bandwidth
3.84 MHz
Adjacent Channel
Bandwidth
Spacing
3.84 MHz
5 MHz
S pa n 2 0 M Hz
W-CDMA 3GPP FWD
Power
Lower
Upper
Center 153.6 MHz
EXT
-7.62 dBm
-78.89 dB
-78.83 dB
2 MHz/
Tx Channel
Bandwidth
3.84 MHz
Adjacent Channel
Bandwidth
Spacing
3.84 MHz
5 MHz
Ref -19.7 dBm
* SWT 10 s
-40
A
-50
1 RM * -60
CLRWR -70
1 RM * -60
CLRWR -70
-80
-80
* SWT 10 s
A
-90
-90
-100
-100
NOR
NOR
-110
-110
-120
-120
-130
-130
Center 70 MHz
3.5 MHz/
Standard: W-CDMA 3GPP FWD
52
10 dB
-40
-50
Ch1(Ref)
Ch2
Ch3
Ch4
Total
Figure 87.
* Att
-30
-30
Tx Channels
EXT
-8.89 dBm
-76.86 dB
-76.18 dB
* RBW 30 kHz
* VBW 300 kHz
* RBW 30 kHz
* VBW 300 kHz
10 dB
Power
Lower
Upper
Figure 86. Single Carrier W-CDMA Test Model 1,
fOUT = 153.6 MHz
Figure 85. Single Carrier W-CDMA Test Model 1, fOUT = 70
MHz
* Att
Span 20 MHz
W-CDMA 3GPP FWD
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 153.6 MHz
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 70 MHz
Ref -18 dBm
* SWT 10 s
-20
- 30
1 RM *
* Att
Span 35 MHz
Adjacent Channel
Lower
Upper
Center 153.6 MHz
EXT
-74.09 dB
-74.14 dB
-14.16 dBm
2x Interpolation, 0 dBFS,
-14.20 dBm
fDAC = 491.52 MSPS,
-14.34 dBm
fOUT = 70 MHz
-14.39 dBm
-8.25 dBm
Four Carrier W-CDMA Test Model 1, fOUT = 70
MHz
3.5 MHz/
Tx Channels
Ch1(Ref)
Ch2
Ch3
Ch4
-15.80
-15.92
-16.08
-16.21
Span 35 MHz
Adjacent Channel
Standard: W-CDMA 3GPP FWD
dBm
dBm
dBm
dBm
Lower
Upper
EXT
-70.59 dB
-69.18 dB
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 153.6 MHz
Total
-9.98 dBm
Figure 88. Four Carrier W-CDMA Test Model 1, fOUT = 153.6
MHz
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* RBW 30 kHz
* VBW 300 kHz
Ref -17.3 dBm
* Att
10 dB
* SWT 10 s
Ref -18.3 dBm
-20
-30
* Att
10 dB
-30
A
-40
-40
-50
-50
1 RM * -60
CLRWR
-70
1 RM * -60
CLRWR -70
-80
-80
A
-90
-90
-100
NOR
-100
-110
-110
-120
-120
NOR
-130
-130
Center 70 MHz
Tx Channel
Bandwidth
Adjacent Channel
Bandwidth
Spacing
3.5 MHz/
Span 35 MHz
Center 153.6 MHz
EXT
10 MHz
Power
Lower
Upper
10 MHz
10 MHz
-8.39 dBm
-74.18 dB
-70.40 dB
3.5 MHz/
Tx Channel
Bandwidth
10 MHz
Adjacent Channel
Bandwidth
Spacing
10 MHz
10 MHz
EXT
Power
Lower
Upper
-9.49 dBm
-71.66 dB
-69.13 dB
Figure 90. 10MHz Single Carrier LTE, fOUT = 153.6 MHz
Figure 89. 10MHz Single Carrier LTE, fOUT = 70 MHz
* RBW 30 kHz
* RBW 30 kHz
* VBW 300 kHz
* VBW 300 kHz
Ref -18.8 dBm
Span 35 MHz
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 153.6 MHz
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 70 MHz
* Att
15 dB
Ref -18 dBm
* SWT 10 s
-30
* Att
10 dB
* SWT 10 s
-30
-40
A
-40
-50
-50
1 RM * -60
-70
1 RM * -60
CLRWR
-70
-80
-80
CLRWR
* RBW 30 kHz
* VBW 300 kHz
* SWT 10 s
-90
A
-90
-100
NOR
-100
-110
-110
-120
-120
-130
NOR
-130
Center 70 MHz
Tx Channel
Bandwidth
Adjacent Channel
Bandwidth
Spacing
6.5 MHz/
Span 65 MHz
Center 153.6 MHz
EXT
20 MHz
20 MHz
20 MHz
Power
Lower
Upper
-7.17 dBm
-65.69 dB
-67.79 dB
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 70 MHz
Figure 91. 20MHz Single Carrier LTE, fOUT = 70 MHz
6.5 MHz/
Tx Channel
Bandwidth
20 MHz
Adjacent Channel
Bandwidth
Spacing
20 MHz
20 MHz
Span 65 MHz
EXT
Power
Lower
Upper
-8.23 dBm
-65.14 dB
-64.96 dB
2x Interpolation, 0 dBFS,
fDAC = 491.52 MSPS,
fOUT = 153.6 MHz
Figure 92. 20MHz Single Carrier LTE, fOUT = 153.6 MHz
9 Power Supply Recommendations
9.1 Power-up Sequence
The following startup sequence is recommended to power-up the DAC3282:
1. Set TXENABLE low.
2. Supply all 1.8V voltages (DACVDD, DIGVDD, CLKVDD and VFUSE) and all 3.3V voltages (AVDD). The
1.8V and 3.3V supplies can be powered up simultaneously or in any order. There are no specific
requirements on the ramp rate for the supplies.
3. Provide all LVPECL inputs: DACCLKP/N and the optional OSTRP/N. These inputs can also be provided after
the SIF register programming.
4. Toggle the RESETB pin for a minimum of 25ns active low pulse width.
5. Program all the SIF registers.
6. FIFO configuration needed for synchronization:
(a) Program fifo_reset_ena (config0, bit) to enable FRAMEP/N as the FIFO input pointer sync source.
(b) Program multi_sync_ena (config0, bit) to enable syncing of the FIFO output pointer.
(c) Program multi_sync_sel (config19, bit) to select the FIFO output pointer and clock divider sync
source
7. Clock divider configuration needed for synchronization:
(a) Program clkdiv_sync_ena (config18, bit) to “1” to enable clock divider sync.
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Power-up Sequence (continued)
8. Provide all LVDS inputs (D[7:0]P/N, DATACLKP/N, and FRAMEP/N) simultaneously. Synchronize the FIFO
and clock divider by providing the pulse or periodic signals needed.
(a) For Single Sync Source Mode where FRAMEP/N is used to sync the FIFO, a single rising edge for FIFO,
FIFO data formatter, and clock divider sync is recommended. Periodic sync signal is not recommended
due to the non-deterministic latency of the sync signal through the clock domain transfer.
(b) For Dual Sync Sources Mode, both single pulse or periodic sync signals can be used.
9. FIFO and clock divider configurations after all the sync signals have provided the initial sync pulses needed
for synchronization:
(a) For Single Sync Source Mode where the clock divider sync source is FRAMEP/N, clock divider syncing
may be disabled after DAC3282 initialization and before the data transmission by setting
clkdiv_sync_ena (config18, bit) to “0”. This is to prevent accidental syncing of the clock divider when
sending FRAMEP/N pulse to other digital blocks.
(b) For Dual Sync Sources Mode, where the clock divider sync source is from the OSTRP/N, the clock
divider syncing may be enabled at all time.
(c) Optionally, to prevent accidental syncing of the FIFO, disable FIFO syncing by setting fifo_reset_ena and
multi_sync_ena to “0” after the FIFO input and output pointers are initialized. If the FIFO sync remains
enabled after initialization, the FRAMEP/N pulse must occur in ways to not disturb the FIFO operation.
Refer to the Input FIFO section for detail.
10. Enable transmit of data by asserting the TXENABLE pin.
11. At all time, if any of the clocks (i.e. DATACLK or DACCLK) is lost or FIFO collision alarm is detected, a
complete resynchronization of the DAC is necessary. Please set TXENABLE low and repeat step 6 through
10. Program the FIFO configuration and clock divider configuration per step 6 and 7 appropriately to accept
the new sync pulse or pulses for the synchronization.
10 Layout
10.1 Layout Guidelines
The design of the PCB is critical to achieve the full performance of the DAC3282 device. Defining the PCB
stackup should be the first step in the board design. Experience has shown that at least 6 layers are required to
adequately route all required signals to and from the device. Each signal routing layer must have an adjacent
solid ground plane to control signal return paths to have minimal loop areas and to achieve controlled
impedances for microstrip and stripline routing. Power planes must also have adjacent solid ground planes to
control supply return paths. Minimizing the spacing between supply and ground planes improves performance by
increasing the distributed decoupling.
Although the DAC3282 device consists of both analog and digital circuitry, TI highly recommends solid ground
planes that encompass the device and its input and output signal paths. TI does not recommend split ground
planes that divide the analog and digital portions of the device. Split ground planes may improve performance if a
nearby, noisy, digital device is corrupting the ground reference of the analog signal path. When split ground
planes are employed, one must carefully control the supply return paths and keep the paths on top of their
respective ground reference planes.
Quality analog output signals and input conversion clock signal path layout is required for full dynamic
performance. Symmetry of the differential signal paths and discrete components in the path is mandatory and
symmetrical shunt-oriented components should have a common grounding via. The high frequency requirements
of the analog output and clock signal paths necessitate using differential routing with controlled impedances and
minimizing signal path stubs (including vias) when possible.
Coupling onto or between the clock and output signal paths should be avoided using any isolation techniques
available including distance isolation, orientation planning to prevent field coupling of components like inductors
and transformers, and providing well coupled reference planes. Via stitching around the clock signal path and the
input analog signal path provides a quiet ground reference for the critical signal paths and reduces noise
coupling onto these paths. Sensitive signal traces must not cross other signal traces or power routing on
adjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces should cross at
90 ° angles to minimize crosstalk.
54
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Layout Guidelines (continued)
The substrate (dielectric) material requirements of the PCB are largely influenced by the speed and length of the
high speed serial lanes. Affordable and common FR4 varieties are adequate in most cases.
Coupling of ambient signals into the signal path is reduced by providing quiet, close reference planes and by
maintaining signal path symmetry to ensure the coupled noise is common-mode. Faraday caging may be used in
very noisy environments and high dynamic range applications to isolate the signal path.
10.2 Layout Example
100 W
100 W
100 W Matched Length
Differential Microstrip Traces
0.1uF
0.1uF
0.1uF
0.01uF
Symmetric Output
Signal Path
0.01uF
0.1uF
0W
953 W
7W
0.1uF
0.01uF
0.01uF
0.1uF
0.1uF
Figure 93. Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Definition Of Specifications
Adjacent Carrier Leakage Ratio
(ACLR)
Defined for a 3.84 Mcps 3GPP W-CDMA input signal measured in a 3.84
MHz bandwidth at a 5MHz offset from the carrier with a 12 dB peak-toaverage ratio.
Analog and Digital Power Supply
Rejection Ratio (APSSR, DPSSR)
Defined as the percentage error in the ratio of the delta IOUT and delta
supply voltage normalized with respect to the ideal IOUT current.
Differential Nonlinearity (DNL)
Defined as the variation in analog output associated with an ideal 1 LSB
change in the digital input code.
Gain Drift
Defined as the maximum change in gain, in terms of ppm of full-scale
range (FSR) per °C, from the value at ambient (25°C) to values over the
full operating temperature range.
Gain Error
Defined as the percentage error (in FSR%) for the ratio between the
measured full-scale output current and the ideal full-scale output current.
Integral Nonlinearity (INL)
Defined as the maximum deviation of the actual analog output from the
ideal output, determined by a straight line drawn from zero scale to full
scale.
Intermodulation Distortion
(IMD3, IMD)
The two-tone IMD3 is defined as the ratio (in dBc) of the 3rd-order
intermodulation distortion product to either fundamental output tone.
Noise Spectral Density (NSD)
Defined as the difference of power (in dBc) between the output tone
signal power and the noise floor of 1Hz bandwidth within the first Nyquist
zone.
Offset Drift
Defined as the maximum change in DC offset, in terms of ppm of fullscale range (FSR) per °C, from the value at ambient (25°C) to values
over the full operating temperature range.
Offset Error
Defined as the percentage error (in FSR%) for the ratio between the
measured mid-scale output current and the ideal mid-scale output current.
Output Compliance Range
Defined as the minimum and maximum allowable voltage at the output of
the current-output DAC. Exceeding this limit may result reduced reliability
of the device or adversely affecting distortion performance.
Reference Voltage Drift
Defined as the maximum change of the reference voltage in ppm per °C
from value at ambient (25°C) to values over the full operating temperature
range.
Spurious Free Dynamic Range
(SFDR)
Defined as the difference (in dBc) between the peak amplitude of the
output signal and the peak spurious signal.
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11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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23-Apr-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC3282IRGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
DAC3282I
DAC3282IRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green NIPDAU | NIPDAUAG
Level-3-260C-168 HR
-40 to 85
DAC3282I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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