Product
Folder
Order
Now
Technical
Documents
Support &
Community
Tools &
Software
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
DAC38RF8x Dual-Channel, Differential-Output, 14-Bit, 9-GSPS, RF-Sampling DAC With
JESD204B Interface, On-Chip PLL and Wide-Band Interpolation
1 Features
•
1
•
•
•
•
•
14-Bit resolution, 9-GSPS DAC with multimode
operation
– 16-Bit, Dual-channel data mode
– Max input rate: 2.5-GSPS
– Wideband digital up-converter
– Interpolation:
1,2,4,6,8,10,12,16,18,20,24x
– 12-Bit, Dual-channel data mode
– Max input rate: 3.33-GSPS
– Wideband digital Up-converter
– Interpolation: 1,2,24x
– 8-Bit, Single-channel data mode
– Max input rate: 9-GSPS
JESD204B interface
– Subclass 1 for multichip synchronization
– DAC38RF89: Maximum lane rate: 12.5 Gbps
– DAC38RF82: Maximum lane rate: 12.8 Gbps
Differential output
– Supports DC coupling
– RF Full-scale output power (with 2:1 balun):
3 dBm at 2.14 GHz
Internal PLL and VCO with bypass
– DAC38RF82: fC(VCO) = 5.9 or 8.9 GHz
– DAC38RF89: fC(VCO) = 5 or 7.5 GHz
Power supplies: -1.8 V, 1.0 V, 1.8 V
Package: 10 x 10 mm BGA, 0.8 mm pitch,
144-balls
In dual channel operation, the input interface is
capable of data rates up to 3.33 GSPS at 12-bits and
2.5 GSPS at 16-bits resolution without interpolation.
When used as a complex baseband transmitter with
interpolation modes from 2x to 24x, the DAC38RF82
or DAC38RF89 is capable of synthesizing wideband
signals up to 2 GHz bandwidth with 16-bit input
resolution and 2.66 GHz bandwidth with 12-bit input
resolution.
The 8-bit mode allows an input at the full 9 GSPS
maximum DAC sample rate and can synthesize
wideband signals from 0 to 4.5 GHz.
An optional low jitter PLL/VCO simplifies the DAC
clock generation by allowing use of a lower frequency
reference clock. DAC38RF82 and DAC38RF89
support different VCO frequency ranges, summarized
in Device Comparison Table.
Device Information(1)
PART NUMBER
DAC38RF82
DAC38RF89
PACKAGE
FCBGA (144)
BODY SIZE (NOM)
10.0 mm x 10.0 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
32x6 MHz 256-QAM Carriers
2 Applications
•
•
•
•
•
Arbitrary waveform generators
Radar and electronic warfare
Communications test equipment
Direct RF synthesis for DOCSIS 3.0/3.1
Microwave backhaul
3 Description
The DAC38RF82 and DAC38RF89 are high
performance, wide bandwidth RF-sampling digital-toanalog (DACs) that are capable of dual channel input
data rate up to 3.33 GSPS or single-channel
operation with 8-bits up to 9-GSPS. The devices have
a low power JESD204B Interface with up to 8 lanes,
with a maximum bit rate of 12.5 Gbps (DAC38RF89)
and 12.8 Gbps (DAC38RF82).
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
1
1
1
2
6
6
9
Absolute Maximum Ratings ...................................... 9
ESD Ratings.............................................................. 9
Recommended Operating Conditions....................... 9
Thermal Information ................................................ 10
Electrical Characteristics - DC Specifications ......... 10
Electrical Characteristics - Digital Specifications .... 12
Electrical Characteristics - AC Specifications ......... 15
PLL/VCO Electrical Characteristics ........................ 18
Timing Requirements .............................................. 19
Typical Characteristics .......................................... 20
Detailed Description ............................................ 25
8.1 Overview ................................................................. 25
8.2 Functional Block Diagrams ..................................... 25
8.3 Feature Description................................................. 27
8.4 Device Functional Modes........................................ 64
8.5 Register Maps ........................................................ 68
9
Application and Implementation ...................... 130
9.1 Application Information.......................................... 130
9.2 Typical Application ............................................... 131
10 Power Supply Recommendations ................... 135
10.1 Power Supply Sequencing .................................. 136
11 Layout................................................................. 136
11.1 Layout Guidelines ............................................... 136
11.2 Layout Example .................................................. 138
12 Device and Documentation Support ............... 139
12.1 Related Links ......................................................
12.2 Receiving Notification of Documentation
Updates..................................................................
12.3 Support Resources .............................................
12.4 Trademarks .........................................................
12.5 Electrostatic Discharge Caution ..........................
12.6 Glossary ..............................................................
139
139
139
139
139
139
13 Mechanical, Packaging, and Orderable
Information ......................................................... 139
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2017) to Revision D
Page
•
Changed Feature From: Maximum lane rate: 12.5 Gbps To: DAC38RF89: Maximum lane rate: 12.5 Gbps ....................... 1
•
Changed Feature From: Maximum lane rate: 12.5 Gbps To: DAC38RF82: Maximum lane rate: 12.8 Gbps ....................... 1
•
Changed From: maximum bit rate of 12.5 Gbpss To: maximum bit rate of 12.5 Gbps (DAC38RF89) and 12.8 Gbps
(DAC38RF82) the Description ................................................................................................................................................ 1
•
Added note to TJ in the Absolute Maximum Ratings.............................................................................................................. 9
•
Changed the fSerDes MAX value From: 12.5 Gbps To: 12.8 Gbps for DAC38RF82.............................................................. 12
•
Changed From: maximum bit rate of 12.5 Gbps. To: maximum bit rate of 12.5 Gbps (DAC38RF89) and 12.8 Gbps
(DAC38RF82) in the Overview ............................................................................................................................................. 25
•
Changed from: SerDes lane is 12.5 Gbps To: SerDes lane is 12.5 Gbps (DAC38RF89) and 12.8 Gbps
(DAC38RF82) in SerDes Rate ............................................................................................................................................. 28
•
Deleted JESD204B Subclass 0 Support .............................................................................................................................. 42
•
Added Writing to Reserved Bits............................................................................................................................................ 68
•
Changed 0x04 and 0x05 From: 0x0000 To: variable in Table 47 ....................................................................................... 68
•
Added Note 1 to Table 47 ................................................................................................................................................... 68
•
Changed 0x7F From: 0x0008 To: 0x0009 in Table 47 ........................................................................................................ 68
•
Changed 0x0D From: 0x8300 To: 0x8000 in Table 47 ....................................................................................................... 68
•
Changed 0x0F From: 0x1F83 To: 0xFFFF in Table 47 ....................................................................................................... 68
•
Changed 0x32 and 0x33 From: 0x0800 To: 0x0400 in Table 47 ........................................................................................ 69
•
Changed 0x23 From: 0x03F3 To: 0xFFFF in Table 47 ....................................................................................................... 70
•
Changed 0x3B From: 0x0002 To: 0x1802 in Table 47 ....................................................................................................... 70
•
Changed From: [reset = 0x0000] To: [reset = variable] in SERDES Loss of Signal Detection Alarms Register
(address = 0x04) [reset = variable]....................................................................................................................................... 74
•
Changed From: [reset = 0x0000] To: [reset = variable] in SERDES Loss of Signal Detection Alarms Register
(address = 0x04) [reset = variable]....................................................................................................................................... 75
2
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Revision History (continued)
•
Changed From: [reset = 0x0008] To: [reset = 0x0009] in Vendor ID and Chip Version Register (address = 0x7F)
[reset = 0x0009].................................................................................................................................................................... 78
•
Changed From: [reset = 0x1300] To: [reset = 0x8000] in JESD FIFO Control Register (address = 0x0D)[reset =
0x8000] ................................................................................................................................................................................. 81
•
Changed From: [reset = 0x0000] To: [reset = 0x0400] in Gain for path AB Register (address = 0x32) [reset = 0x0400] .. 95
•
Changed From: [reset = 0x0000] To: [reset = 0x0400] in Gain for path CD Register (address = 0x33) [reset = 0x0400] .. 95
•
Changed all bits From R To R/W in Figure 94 .................................................................................................................... 96
•
Changed all bits From R To R/W in Figure 95 .................................................................................................................... 97
•
Changed the Description of Bit 3:1 in Table 91 ................................................................................................................... 97
•
Changed Bit 1 From: MIN_LATENCY_ENA To: Reserved in Table 97 ............................................................................ 101
•
Changed the title of Figure 110 To: JESD Crossbar Configuration 2 Register (JESD_CROSSBAR2) ............................. 106
•
Changed the title of Figure 111 To: JESD Alarms for Lane 0 Register (JESD_ALM_L2) ................................................. 107
•
Changed the title of Figure 111 To: JESD Alarms for Lane 5 Register (JESD_ALM_L5) ................................................. 112
•
Changed From: [reset = 0xF000] To: [reset = 0xFC03] in Clock Configuration Register (address = 0x0A) [reset =
0xFC03] .............................................................................................................................................................................. 116
•
Changed From: [reset = 0x8000] To: [reset = 0x2002] in Divided Output Clock Configuration Register (address =
0x0C) [reset = 0x2002] ....................................................................................................................................................... 117
•
Added Note 1 to Table 120 ............................................................................................................................................... 118
•
Changed the description of Bit 1 From: TBD To: Enables SPI SYSREF for Internal SYSREF Generator in Table 120 .. 118
•
Added Note 1 to Table 121 ............................................................................................................................................... 118
•
Added Note 1 to Table 122 ............................................................................................................................................... 119
•
Changed From: [reset = 0x0002] To: [reset = 0x1802] in Serdes Clock Configuration Register (address = 0x3B)
[reset = 0x1802].................................................................................................................................................................. 126
•
Changed the reset value of Bit 14:11 From: 0x0 To: 0111 in Table 131 ........................................................................... 126
•
Changed Bit 4:2 From: BUSWIDTH To: Reserved in Table 134 ....................................................................................... 128
Changes from Revision B (August 2017) to Revision C
Page
•
Changed the tr NOM value from 50 ns To 50 ps in the Anaolog Output of the Timing Requirements table ....................... 19
•
Changed the tf NOM value from 50 ns To 50 ps in the Anaolog Output of the Timing Requirements table ....................... 19
•
Changed the MPY values in Table 4.................................................................................................................................... 29
•
Changed The title From: SerDes PLL Modes Selection To: SerDes PLL Multiplier (MPY) Values in in Table 4 ................ 29
•
Added section: Digital Quadrature Modulator....................................................................................................................... 55
•
Added section: Low Power Coarse Resolution Mixing Modes ............................................................................................. 56
•
Added cross reference to MPY values in Table 132 ......................................................................................................... 126
•
Changed the enable/disable description for bit [15:13] of Table 134 ................................................................................ 128
Changes from Revision A (April 2017) to Revision B
Page
•
Deleted Changed Feature From: Interpolation: 1,2,4,24x To: Interpolation: 1,2,24x ............................................................. 1
•
Changed the ALARM pin From: alarm_out_pol To: alm_out_pol in the Pin Functions table................................................. 7
•
Changed the Description of pins A3, A4, A7, A6, A9, A10, A12, E12, F11, F7, G6, H5, H7, J6, J11 in the Pin
Functions table ....................................................................................................................................................................... 7
•
Changed description of TXENABLE pin in the PIN Functions table ...................................................................................... 8
•
Changed the MAX value of VEE18N rail From: 0.5 V To 0.3 V in the Absolute Maximum Ratings table ............................. 9
•
Added "Supply Voltage Range" to the Recommended Operating Conditions table .............................................................. 9
•
Changed DNL typical value From: ±0.5 to ±3 LSB in Electrical Characteristics - DC Specifications table ......................... 10
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
3
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
•
Changed INL typical value From: ±1 To: ±4 LSB in Electrical Characteristics - DC Specifications table............................ 10
•
Added "Reference voltage drift" to the Electrical Characteristics - DC Specifications table ................................................ 10
•
Changed Power Dissipation Test Condition From: MODE 5: dual channel, 8-bit input mode, 2x Interpolation To:
MODE 5: dual channel, 8-bit input mode, 1x Interpolation in the Electrical Characteristics - DC Specifications ................ 11
•
Changed the ILOAD values to negative for CMOS interface parameter, low-level output voltage, in the Electrical
Characteristics - Digital Specifications table......................................................................................................................... 12
•
Added 0 dBFS to the condition statement for the Electrical Characteristics - AC Specifications table ............................... 15
•
Added MIN and TYP value to maximum DAC sample rate for DAC38RF89 only in the Electrical Characteristics - AC
Specifications table............................................................................................................................................................... 15
•
Added NSD values for DAC38RF82 with on-chip PLL enabled to Electrical Characteristics - AC Specifications table...... 17
•
Changed the Isolation values in the TEST CONDITIONS, TYP value From: 74 dBc To: 82 dBc and 56 dBc To 73
dBc in the Electrical Characteristics - AC Specifications table............................................................................................. 17
•
Added Figure 16 ................................................................................................................................................................... 21
•
Added MPY value for 16.5x in the Table 4........................................................................................................................... 29
•
Changed input rate max and fdac max for 6x interpolation mode in Table 9 ..................................................................... 32
•
Changed input data rate From: 6666 MSPS To: 3333 MSPS for LMFSHd=41380, 2x interpolation in Table 9 ................ 33
•
Changed Table 12, JESD204B frame format for LMFSHd=84111 ..................................................................................... 33
•
Changed Table 14, JESD204B frame format for LMFSHd=44210 ...................................................................................... 34
•
Changed Table 16, JESD204B frame format for LMFSHd = 24410 .................................................................................... 34
•
Changed Table 17, JESD204B frame format for LMFSHd = 44210 .................................................................................... 34
•
Changed Table 18, JESD204B frame format for LMFSHd = 88210 .................................................................................... 35
•
Changed Table 19, JESD204B frame format for LMFSHd = 24410 .................................................................................... 35
•
Changed Table 20, JESD204B frame format for LMFSHd=48410 ...................................................................................... 35
•
Changed Table 21, JESD204B frame format for LMFSHd = 24310 .................................................................................... 35
•
Changed Table 22, JESD204B frame format for LMFSHd = 48310 .................................................................................... 35
•
Changed Table 23, JESD204B frame format for LMFSHd = 81180 .................................................................................... 36
•
Changed Table 24, JESD204B frame format for LMFSHd = 41380 .................................................................................... 36
•
Changed Table 26, JESD204B frame format for LMFSHd = 41121 .................................................................................... 37
•
Added Table 27, JESD204B frame format for LMFSHd = 41121 ........................................................................................ 38
•
Changed Table 38 ................................................................................................................................................................ 49
•
Changed register field programming values for LMFSHd=24410, 41380, 41121 and 24310 in the Register
Programming for JESD and Interpolation Mode table.......................................................................................................... 54
•
Changed the bit positions of N_M1 register field From: 12-8 To: 4-0 in the Table 42 table ................................................ 55
•
Changed the bit positions of N_M1’ (NPRIME_M1) register field From: 4-0 To: 12-0 in the Table 42 table ....................... 55
•
Changed the description of DAC PLL alarm in Alarm Monitoring ........................................................................................ 60
•
Changed from BIST_ENA to Reserved in Table 61 ............................................................................................................ 80
•
Changed from BIST_ZERO to Reserved in Table 61 ......................................................................................................... 80
•
Changed the description of OUTSUM_SEL field in Table 69 ............................................................................................. 86
•
Changed the Description of Bit 11 From "dummy data generation" to "distortion enhancement" in Table 116 ............... 116
•
Changed the junction temp and loop filter voltage range for PLL tuning in Figure 142 ..................................................... 130
4
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Changes from Original (February 2017) to Revision A
Page
•
Corrected the NSD values for -9dBFS in Electrical Characteristics - AC Specifications table ........................................... 17
•
Added PLL/VCO characteristics table to PLL/VCO Electrical Characteristics ..................................................................... 18
•
Added JESD204B clock phase register setting to Table 41 ................................................................................................ 54
•
Removed descriptions for CLKJESD_DIV register from Table 41 ...................................................................................... 54
•
Added JESD204B clock phase register setting to Table 42 ................................................................................................ 54
•
Added information about the DAC output total current for various full scale current settings in DAC Fullscale Output
Current ................................................................................................................................................................................. 62
•
Changed Bit 0 of Table 128 From: Enables the GSM PLL To: Reserved.......................................................................... 123
•
Changed Table 130 ........................................................................................................................................................... 125
•
Changed description of SERDES_REFCLK_DIV register field in Table 131 .................................................................... 126
•
Changed Bit 12:11, 6:5 and 4:2 of Table 134 ................................................................................................................... 128
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
5
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
5 Device Comparison Table
PART NUMBER
ANALOG OUTPUT TYPE
VCO0 CENTER FREQUENCY
VCO1 CENTER FREQUENCY
DAC38RF82
Differential
5.9 GHz
8.9 GHz
DAC38RF89
Differential
5 GHz
7.5 GHz
6 Pin Configuration and Functions
AAV Package
144-Pin (FCBGA)
Top View
A
B
C
D
E
F
G
12
DACCLKSE
VSSCLK
AGND
VOUT2+
VOUT2-
AGND
11
VSSCLK
VSSCLK
AGND
AGND
AGND
VDDA1
VDDA18
VEE18N
VEE18N
VSSCLK
VDDAVCO18VDDAVCO18 VSSCLK
H
J
K
L
M
AGND
VOUT1-
VOUT1+
AGND
VDDA18
VDDA1
AGND
AGND
AGND
VDDL2_1
VDDL2_1
VSSCLK
VEE18N
VEE18N
SDIO
VDDCLK1
VDDCLK1
VSSCLK
RESET
SCLK
SDO
VDDOUT18 VDDOUT18
10
DACCLK+ VDDAPLL18
EXTIO
9
DACCLK- VDDAPLL18
RBIAS
8
VSSCLK
VSSCLK
ATEST
VDDPLL1
VDDPLL1
VSSCLK
VDDL1_1
VDDL1_1
VSSCLK
ALARM
SLEEP
SDEN
7
CLKTX+
VDDTX18
SYNC1+
VDDDIG1
DGND
VDDE1
DGND
VDDE1
DGND
GPI0
GPO0
GPI1
6
CLKTX-
VDDTX1
SYNC1-
DGND
VDDDIG1
DGND
VDDE1
DGND
VDDE1
TXENABLE
GPO1
DGND
5
VDDDIG1
VDDDIG1
VDDDIG1
VDDDIG1
VDDDIG1
VDDDIG1
VDDDIG1
VDDIO18
TRST
TMS
DGND
RX3+
4
SYSREF-
VDDS18
SYNC0+
VSENSE
VDDDIG1
VDDDIG1
VDDDIG1
TDI
TDO
TCLK
DGND
RX3-
3
SYSREF+
VDDS18
SYNC0-
IFORCE
VDDDIG1
AMUX1
AMUX0
VDDT1
VDDT1
TESTMODE
DGND
RX2-
2
DGND
DGND
DGND
DGND
DGND
DGND
DGND
VDDR18
VDDR18
DGND
DGND
RX2+
1
RX7+
RX7-
RX6-
RX6+
RX5+
RX5-
RX4-
RX4+
RX0+
RX0-
RX1-
RX1+
Not to scale
6
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
C11, C12, D11, E11,
F12, J12, K11, L11,
M11, M12
AGND
–
Analog ground.
K8
ALARM
O
CMOS output for ALARM condition. Default polarity is active low, but can be changed to active high via
RESET_CONFIG alm_out_pol control bit..
G3
AMUX0
O
Analog test pin for SerDes, Lane 0 to Lane 3. Can be left floating.
F3
AMUX1
O
Analog test pin for SerDes, Lane 4 to Lane 7. Can be left floating.
C8
ATEST
O
Analog test pin for DAC, references and PLL. Can be left floating.
A7
CLKTX+
O
Divided output clock, internal 100 Ω differential termination, self-biased, positive terminal.
A6
CLKTX-
O
Divided output clock, internal 100 Ω differential termination, self-biased, negative terminal.
A10
DACCLK+
I
Device clock, internal 100 Ω differential termination, self-biased, positive terminal.
A9
DACCLK-
I
Device clock, internal 100 Ω differential termination, self-biased, negative terminal.
A12
DACCLKSE
I
Single ended device clock optional input. Can be left floating if not used, internal 50 Ω termination.
A2, B2, C2, D2, D6, E2,
E7, F2, F6, G2, G7, H6,
J7, K2, L2, L3, L4, L5,
M6
DGND
-
Digital ground.
C10
EXTIO
I/O
Requires a 0.1 μF decoupling capacitor to AGND.
K7
GPI0
-
Factory use only. User should GND.
M7
GPI1
-
Factory use only. User should GND.
L7
GPO0
O
Used for CMOS SYNC0\ signal.
L6
GPO1
O
Used for CMOS SYNC1\ signal.
D3
IFORCE
O
Test pin for on chip parametrics. Can be left floating.
C9
RBIAS
O
Full-scale output current bias. Change the full-scale output current through DACFS in register DACFS
(8.5.72). Expected to be 3.6 kΩ to GND for 40 mA full scale output.
K9
RESET
I
Active low input for chip RESET, which resets all the programming registers to their default state. Internal
pull-up.
J1
RX0+
I
CML SerDes interface lane 0 input, positive
K1
RX0-
I
CML SerDes interface lane 0 input, negative
M1
RX1+
I
CML SerDes interface lane 1 input, positive
L1
RX1-
I
CML SerDes interface lane 1 input, negative
M2
RX2+
I
CML SerDes interface lane 2 input, positive
M3
RX2-
I
CML SerDes interface lane 2 input, negative
M5
RX3+
I
CML SerDes interface lane 3 input, positive
M4
RX3-
I
CML SerDes interface lane 3 input, negative
H1
RX4+
I
CML SerDes interface lane 4 input, positive
G1
RX4-
I
CML SerDes interface lane 4 input, negative
E1
RX5+
I
CML SerDes interface lane 5 input, positive
F1
RX5-
I
CML SerDes interface lane 5 input, negative
D1
RX6+
I
CML SerDes interface lane 6 input, positive
C1
RX6-
I
CML SerDes interface lane 6 input, negative
A1
RX7+
I
CML SerDes interface lane 7 input, positive
B1
RX7-
I
CML SerDes interface lane 7 input, negative
L9
SCLK
I
Serial interface clock. Internal pull-down.
M8
SDEN
I
Active low serial data enable, always an input to the DAC38RFxx. Internal pull-up.
M10
SDIO
I/O
Serial interface data. Bi-directional in 3-pin mode (default) and uni-directional input 4-pin mode. Internal
pull-down.
M9
SDO
O
Uni-directional serial interface data output in 4-pin mode. The SDO pin is tri-stated in 3-pin interface
mode (default).
L8
SLEEP
I
Active high asynchronous hardware power-down input. Internal pull-down.
C4
SYNC0+
O
Synchronization request to transmitter for JESD204B link 0, LVDS positive output.
C3
SYNC0-
O
Synchronization request to transmitter for JESD204B link 0, LVDS negative output.
C7
SYNC1+
O
Synchronization request to transmitter for JESD204B link 1, LVDS positive output.
C6
SYNC1-
O
Synchronization request to transmitter for JESD204B link 1, LVDS negative output.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
7
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Pin Functions (continued)
PIN
DESCRIPTION
NAME
A3
SYSREF+
I
LVPECL SYSREF positive input, internal 100 Ω differential termination, self biased. This
positive/negative pair is captured with the rising edge of DACCLKP/N. It is used for multiple DAC
synchronization.
A4
SYSREF-
I
LVPECL SYSREF negative input, self biased, internal 100 Ω differential termination. (See the SYSREF+
description)
K4
TCLK
I
JTAG test clock. Internal pull-down
H4
TDI
I
JTAG test data in. Internal pull-up
J4
TDO
O
JTAG test data out. Internal pull-up
K3
TESTMODE
-
This pin is used for factory testing.
Recommended to connect to ground for normal operation.
K5
TMS
I
JTAG test mode select. Internal pull-up
J5
TRST
I
JTAG test reset. Internal pull-up. Must be connected to ground if not used
K6
TXENABLE
I
Transmit enable active high input. Internal pull-down.
This pin is ORed with spi_txenable bit in JESD_FIFO register to enable analog output data transmission.
To enable analog output data transmission, pull CMOS TXENABLE pin to high.
To disable analog output, pull CMOS TXENABLE pin to low. The DAC output is forced to midscale.
F11, J11
VDDA1
I
Analog 1 V supply voltage. Must be separated from VDDDIG1 supply for best performance.
G11, H11
VDDA18
I
Analog 1.8 V supply voltage. (1.8 V)
D8, E8
VDDPLL1
I
Analog 1 V supply for PLL.
B9, B10
VDDAPLL18
I
PLL analog supply voltage. (1.8 V)
D9, E9
VDDAVCO18
I
Analog supply voltage for VCO (1.8 V)
G9, H9
VDDCLK1
I
Internal clock buffer supply voltage (1 V).
It is recommended to isolate this supply from VDDDIG1 and VDDA1.
G8, H8
VDDL1_1
I
DAC core supply voltage. (1 V)
G10, H10
VDDL2_1
I
DAC core supply voltage. (1 V)
A5, B5, C5, D5, D7, E3,
E4, E5, E6, F4, F5, G4,
G5
VDDDIG1
I
Digital supply voltage. (1 V).
It is recommended to isolate this supply from VDDCLK1 and VDDA1.
VDDE1
I
Digital Encoder supply voltage (1 V).
Must be separated from VDDDIG1 supply
VDDIO18
I
Supply voltage for all digital I/O and CMOS I/O. (1.8 V)
VDDOUT18
I
DAC output supply. (1.8 V)
H2, J2
VDDR18
I
Supply voltage for SerDes. (1.8 V)
B3, B4
VDDS18
I
Supply voltage for LVDS SYNC0+/- and SYNC1+/- (1.8 V)
H3, J3
VDDT1
I
Supply voltage for SerDes termination. (1 V)
B6
VDDTX1
I
Supply voltage for divided clock output. (1 V)
B7
VDDTX18
I
Supply voltage for divided clock output . (1.8 V)
D10, E10, K10, L10
VEE18N
I
Analog supply voltage. (-1.8 V)
L12
VOUT1+
O
DAC channel 1 output.
K12
VOUT1-
O
DAC channel 1 complementary output.
D12
VOUT2+
O
DAC channel 2 output.
E12
VOUT2-
O
DAC channel 2 complementary output.
D4
VSENSE
O
Test pin for on chip parametrics. Can be left floating.
A8, A11, B8, B11, B12,
F8, F9, F10, J8, J9, J10
VSSCLK
-
Clock ground.
F7, H7, G6, J6
H5
G12, H12
8
I/O
NO.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
Supply Voltage Range (2)
MIN
MAX
UNIT
VDDDAC1, VDDDIG1, VDDL1_1, VDDL2_1,
VDDCLK1, VDDT1, VDDCLK1, VDDTX1, VDDE1
–0.3
1.3
V
VDDR18, VDDIO18, VDDS18, VDDAPLL18,
VDDAREF18, VDDAOUT18, VDDA18,
VDDAVCO18, VDDTX18
–0.3
2.45
V
VEE18N
–2
0.3
V
–0.3
0.3
V
RX[0..7]+/-
–0.5
VDDDIG1 + 0.5 V
V
SDEN, SCLK, SDIO, SDO, TXENABLE, ALARM,
RESET, SLEEP, TMS, TCLK, TDI, TDO, TRST,
TESTMODE, GPI0, GPI1, GPO0, GPO1
–0.5
VDDIO + 0.5 V
V
CLKOUT+/-
–0.5
VDDTX18 + 0.5 V
V
DACCLK+/-, SYSREF+/-, DACCLKSE
–0.5
VDDCLK1 + 0.5 V
V
SYNC0+/-, SYNC1+/-
–0.5
VDDS18 + 0.5 V
V
IOUT1+/-, IOUT2+/-
–0.5
VDDAOUT18 + 0.5 V
V
RBIAS, EXTIO, ATEST
–0.5
VDDAOUT18 + 0.5 V
V
IFORCE, VSENSE
–0.5
VDDDIG1 + 0.5 V
V
AMUX1, AMUX0
–0.5
VDDT1 + 0.5 V
V
20
mA
Voltage between AGND and DGND
Pin Voltage Range (2)
Peak input current (any input)
Peak total input current (all inputs)
–30
mA
Junction temperature TJ (3)
150
°C
Operating free-air temperature, TA
–40
85
°C
Storage temperature, Tstg
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured with respect to AGND or DGND.
Maximum junction temperature is de-rated to 105°C when operating serdes lane rate above 12.5 Gbps
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
TJ
TA
Maximum rated operating junction temperature (1)
125
Recommended free-air temperature
–40
Supply Voltage Range
MAX
UNIT
105
°C
°C
85
VDDA18, VDDAPLL18, VDDS18,
VDDIO18, VDDR18, VDDAPLL18,
VDDOUT18, VDDAVCO18
1.71
1.8
1.89
VDDDIG1 VDDA1, VDDT1, VDDAPLL1,
VDDCLK1, VDDL1_1, VDDL2_1,
VDDTX1, VDDE1
0.95
1
1.05
–1.89
–1.8
–1.71
VEE18N
(1)
NOM
Recommended operating temperature
°C
V
Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
9
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
7.4 Thermal Information
THERMAL METRIC
DAC38RF82
DAC38RF89
(1)
UNIT
AAV (FCBGA)
144 PINS
RθJA
Junction-to-ambient thermal resistance
25
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
1.0
°C/W
RθJB
Junction-to-board thermal resistance
7.7
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
7.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics - DC Specifications
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
Digital Input Resolution
8-bit Input Mode
8
12-bit Input Mode
12
16-bit Input Mode
16
DAC Core Resolution
bits
14
bits
DNL Differential nonlinearity
±3
LSB
INL Integral nonlinearity
±4
LSB
Gain Error
±2
%FSR
Analog Output
Full scale output current
P(OUTFS)
10
2:1 transformer coupled into 50 Ω- load.
Transformer (TCM2-452X-2+) loss not deembedded
2.1 GHz output frequency
Full scale output power
Output Compliance Range
30
40
3
1.3
mA
dBm
2.3
V
Output capacitance
Single ended to ground
1.5
pF
Output resistance
Differential
100
ohms
Reference Output: EXTIO
VREF
Reference output voltage
0.9
V
Reference output current
100
nA
±8
ppm/°C
Reference voltage drift
Power Supply Current and consumption
1 V Digital supplies: VDDDIG1
1 V Analog supplies: VDDA1 VDDACLK1
VDDTX1 VDDAPLL1 VDDT1 VDDE1
1.8 V Supplies: VDDA18 VDDOUT18
VDDAVCO18 VDDAPLL18 VDDR18
VDDIO18 VDDS18 VDDTX18
MODE 1: dual channel, 12-bit input mode, 2x
Interpolation, Sin(x)/x enabled, fDAC = 6 GHz,
CLKTX Disabled
-1.8 V Supply: VEE18N
PDIS
Power Dissipation
1 V Digital supplies: VDDDIG1
1 V Analog supplies: VDDA1 VDDACLK1
VDDTX1 VDDAPLL1 VDDT1 VDDE1
1.8 V Supplies: VDDA18 VDDOUT18
VDDAVCO18 VDDAPLL18 VDDR18
VDDIO18 VDDS18 VDDTX18
MODE 2: dual channel, 16-bit input mode, 2x
Interpolation, Sin(x)/x enabled, fDAC = 5 GHz,
CLKTX Disabled
-1.8 V Supply: VEE18N
PDIS
10
Power Dissipation
Submit Documentation Feedback
815
1300
mA
1144
1250
mA
218
270
mA
159
180
mA
2638
3360
mW
798
mA
1026
mA
222
mA
159
mA
2510
mW
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Electrical Characteristics - DC Specifications (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted.
PARAMETER
TEST CONDITIONS
1V Digital supplies: VDDDIG1
1 V Analog supplies: VDDA1 VDDACLK1
VDDTX1 VDDAPLL1 VDDT1 VDDE1
1.8 V Supplies: VDDA18 VDDOUT18
VDDAVCO18 VDDAPLL18 VDDR18
VDDIO18 VDDS18 VDDTX18
MODE 3: dual channel, 12-bit input mode, 2x
Interpolation, Sin(x)/x enabled, fDAC = 3 GHz,
CLKTX Disabled
-1.8V Supply: VEE18N
PDIS
Power Dissipation
1 V Digital supplies: VDDDIG1
1 V Analog supplies: VDDA1 VDDACLK1
VDDTX1 VDDAPLL1 VDDT1 VDDE1
1.8 V Supplies: VDDA18 VDDOUT18
VDDAVCO18 VDDAPLL18 VDDR18
VDDIO18 VDDS18 VDDTX18
MODE 4: dual channel, 16-bit input mode, 2x
Interpolation, Sin(x)/x enabled, fDAC = 2.5
GHz, CLKTX Disabled
-1.8 V Supply: VEE18N
PDIS
Power Dissipation
1 V Digital supplies: VDDDIG1
1 V Analog supplies: VDDA1 VDDACLK1
VDDTX1 VDDAPLL1 VDDT1 VDDE1
1.8 V Supplies: VDDA18 VDDOUT18
VDDAVCO18 VDDAPLL18 VDDR18
VDDIO18 VDDS18 VDDTX18
MODE 5: dual channel, 8-bit input mode, 1x
Interpolation, Sin(x)/x enabled, fDAC = 9 GHz,
CLKTX Disabled
-1.8 V Supply: VEE18N
PDIS
Power Dissipation
TYP
MAX
UNIT
500
mA
751
mA
218
mA
159
mA
1930
mW
517
mA
708
mA
222
mA
159
mA
1911
mW
624
mA
1469
mA
218
mA
159
mA
2772
mW
1 V Digital supplies: VDDDIG1
63
568
mA
1 V Analog supplies: VDDA1 VDDACLK1
VDDTX1 VDDAPLL1 VDDT1 VDDE1
18
105
mA
47
51
mA
1.8 V Supplies: VDDA18 VDDOUT18
VDDAVCO18 VDDAPLL18 VDDR18
VDDIO18 VDDS18 VDDTX18
MODE 6: Power down mode, no clock, DAC
in sleep, SerDes in sleep, CLKTX Disabled
-1.8 V Supply: VEE18N
PDIS
MIN
Power Dissipation
VDDTX1
VDDTX18
23
28
mA
208
815
mW
fDAC = 8847 MSPS, Clock Out Divider Enabled
25
mA
fDAC = 5898 MSPS, Clock Out Divider Enabled
19
mA
Clock Out Enabled
16
mA
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
11
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
7.6 Electrical Characteristics - Digital Specifications
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, external differential clock mode at 9
GSPS, 12x Interpolation, fOUT = 2.14 GHz, I(OUTFS) = 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1200
mV
CML SerDes Inputs: RX[7:0]+/VDIFF
Receiver input amplitude
VCOM
Input Common Mode Voltage
ZDDIFF
Internal differential termination
50
TERM = 111
600
TERM = 001
700
TERM = 100
0
TERM = 101
fSerDes
250
85
SerDes bit rate
mV
115
Ω
DAC38RF89
0.78125
100
12.5
Gbps
DAC38RF82
0.78125
12.8
Gbps
9
GHz
2000
mV
Differential Clock Inputs: SYSREF±, DACCLK±
fDACCLK
DACCLK input frequency
VCOM
Input common mode voltage
0.1
0.5
VI(DPP)
Differential input peak-to-peak voltage
800
ZT
Internal termination
100
Ω
CL
Input capacitance
2
pF
Duty cycle (DACCLK only
40%
V
60%
LVDS Output: SYNC0±, SYNC1±
VCOM
Output common mode voltage
1.2
V
ZT
Internal termination
100
Ω
VOD
Differential output voltage swing
500
mV
1300
mV
CML Output: DIVCLKOUT±
VOD
CML OUTPUT: CLKTX+/-
CMOS Interface: SDEN, SCLK, SDIO, SDO, TXENABLE, ALARM, RESET, SLEEP, TMS, TCLK, TDI, TDO, TRST, TESTMODE, SYNCSE1,
SYNCSE2
VIH
High-level input voltage
VIL
Low-level input voltage
IIH
High-level input current
IIL
Low-level input current
CI
CMOS input capacitance
0.7 x
VDDIO
V
–40
40
µA
–40
40
µA
High-level output voltage
Low-level output voltage
pF
VDDIO –
0.2
V
0.8 x
VDDIO
ILOAD = –2 mA
VOL
0.3 x
VDDIO
2
ILOAD = –100 µA
VOH
V
ILOAD = 100 µA
0.2
ILOAD = 2 mA
0.5
V
Latency
RX SerDes Digital Delay
full rate, RATE = “00”
34
half rate, RATE = “01”
29
quarter rate, RATE = “10”
26.5
eighth rate, RATE = “11”
26.25
SerDes output to JED204B elastic buffer
input latency
12
Submit Documentation Feedback
21 -39
UI
JESD
clock
cycles
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Electrical Characteristics - Digital Specifications (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, external differential clock mode at 9
GSPS, 12x Interpolation, fOUT = 2.14 GHz, I(OUTFS) = 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise noted.
PARAMETER
TEST CONDITIONS
Digital Latency: JESD Buffer to DAC Output
MIN
TYP
LMFSHD = 41121 or 82121, 1x Interpolation
269
LMFSHD = 41121 or 82121, 2x Interpolation
417
LMFSHD = 41121 or 82121, 4x Interpolation
717
LMFSHD = 41380 or 82380, 1x Interpolation
293
LMFSHD = 41380 or 82380, 2x Interpolation
465
LMFSHD = 81180, 1x Interpolation
289
LMFSHD = 82121, 6x Interpolation
269
LMFSHD = 82121, 8x Interpolation
1120
LMFSHD = 82121, 12x Interpolation
1602
LMFSHD = 82121, 16x Interpolation
2091
LMFSHD = 42111 or 84111, 6x Interpolation
817
LMFSHD = 42111 or 84111, 8x Interpolation
1057
LMFSHD = 42111 or 84111, 10x
Interpolation
1184
LMFSHD = 42111 or 84111, 12x
Interpolation
1532
LMFSHD = 42111 or 84111, 16x
Interpolation
1997
LMFSHD = 42111 or 84111, 18x
Interpolation
2142
LMFSHD = 42111 or 84111, 24x
Interpolation
2941
LMFSHD = 22210 or 44210, 8x Interpolation
1020
LMFSHD = 22210 or 44210, 12x
Interpolation
1473
LMFSHD = 22210 or 44210, 16x
Interpolation
1917
LMFSHD = 22210 or 44210, 18x
Interpolation
2050
LMFSHD = 22210 or 44210, 20x
Interpolation
2275
LMFSHD = 22210 or 44210, 24x
Interpolation
2821
LMFSHD = 12410 or 24410, 16x
Interpolation
1912
LMFSHD = 12410 or 24410, 24x
Interpolation
2786
LMFSHD = 44210 or 88210, 8x Interpolation
1317
LMFSHD = 44210 or 88210, 16x
Interpolation
1709
LMFSHD = 44210 or 88210, 24x
Interpolation
2509
LMFSHD = 24410 or 48410, 16x
Interpolation
1672
LMFSHD = 24410 or 48410, 24x
Interpolation
1593
Product Folder Links: DAC38RF82 DAC38RF89
UNIT
DAC clock
cycles
916
LMFSHD = 44210 or 88210, 12x
Interpolation
Copyright © 2017–2020, Texas Instruments Incorporated
MAX
Submit Documentation Feedback
13
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Electrical Characteristics - Digital Specifications (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, external differential clock mode at 9
GSPS, 12x Interpolation, fOUT = 2.14 GHz, I(OUTFS) = 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
13
LMFSHD = 41121 or 82121, 2x Interpolation
9
LMFSHD = 41121 or 82121, 4x Interpolation
6
LMFSHD = 41380 or 82380, 1x Interpolation
15
LMFSHD = 41380 or 82380, 2x Interpolation
10
LMFSHD = 81180, 1x Interpolation
6
LMFSHD = 82121, 6x Interpolation
5
LMFSHD = 82121, 8x Interpolation
5
LMFSHD = 82121, 12x Interpolation
5
LMFSHD = 82121, 16x Interpolation
SYSREF TO JESD LMFC RESET
14
Submit Documentation Feedback
TYP
LMFSHD = 41121 or 82121, 1x Interpolation
MAX
UNIT
5
LMFSHD = 42111 or 84111, 6x Interpolation
16
LMFSHD = 42111 or 84111, 8x Interpolation
16
LMFSHD = 42111 or 84111, 10x
Interpolation
15
LMFSHD = 42111 or 84111, 12x
Interpolation
15
LMFSHD = 42111 or 84111, 16x
Interpolation
13
LMFSHD = 42111 or 84111, 18x
Interpolation
15
LMFSHD = 42111 or 84111, 24x
Interpolation
15
LMFSHD = 22210 or 44210, 8x Interpolation
8
LMFSHD = 22210 or 44210, 12x
Interpolation
7
LMFSHD = 22210 or 44210, 16x
Interpolation
6
LMFSHD = 22210 or 44210, 18x
Interpolation
7
LMFSHD = 22210 or 44210, 20x
Interpolation
5
LMFSHD = 22210 or 44210, 24x
Interpolation
4
LMFSHD = 12410 or 24410, 16x
Interpolation
9
LMFSHD = 12410 or 24410, 24x
Interpolation
7
LMFSHD = 44210 or 88210, 8x Interpolation
29
LMFSHD = 44210 or 88210, 12x
Interpolation
27
LMFSHD = 44210 or 88210, 16x
Interpolation
26
LMFSHD = 44210 or 88210, 24x
Interpolation
25
LMFSHD = 24410 or 48410, 16x
Interpolation
8
LMFSHD = 24410 or 48410, 24x
Interpolation
6
JESD
clock
cycles
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
7.7 Electrical Characteristics - AC Specifications
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, external differential clock mode at 9
GSPS, 12x Interpolation, 0 dBFS, fOUT = 2.14 GHz, I(OUTFS) = 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise
noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Analog Output
fDAC
Maximum DAC sample rate
DAC38RF82 only
9
DAC38RF89 only
8.4
9
GSPS
AC Performance - CW
SFDR
SFDR
SFDR
HD2
Spurious Free Dynamic Range 0 –
fDAC/2
Spurious Free Dynamic Range within
500 MHz fOUT ± 250 MHz
Spurious Free Dynamic Range
excluding HD2, HD3 and CMP2 0 –
fDAC/2
2nd Order Harmonic
fCLK = 6 GHz , fOUT = 501 MHz
63
fCLK = 6 GHz , fOUT = 951 MHz
62
fCLK = 6 GHz , fOUT = 1851 MHz
58
fCLK = 6 GHz , fOUT = 2651 MHz
57
fCLK = 9 GHz , fOUT = 501 MHz
62
fCLK = 9 GHz , fOUT = 951 MHz
61
fCLK = 9 GHz , fOUT = 1851 MHz
61
fCLK = 9 GHz , fOUT = 2651 MHz
54
fCLK = 9 GHz , fOUT = 3651 MHz
51
fCLK = 6 GHz , fOUT = 501 MHz
97
fCLK = 6 GHz , fOUT = 951 MHz
93
fCLK = 6 GHz , fOUT = 1851 MHz
88
fCLK = 6 GHz , fOUT = 2651 MHz
77
fCLK = 9 GHz , fOUT = 501 MHz
94
fCLK = 9 GHz , fOUT = 951 MHz
90
fCLK = 9 GHz , fOUT = 1851 MHz
85
fCLK = 9 GHz , fOUT = 2651 MHz
82
fCLK = 9 GHz , fOUT = 3651 MHz
79
fCLK = 6 GHz , fOUT = 501 MHz
72
fCLK = 6 GHz , fOUT = 951 MHz
71
fCLK = 6 GHz , fOUT = 1851 MHz
74
fCLK = 6 GHz , fOUT = 2651 MHz
71
fCLK = 9 GHz , fOUT = 501 MHz
69
fCLK = 9 GHz , fOUT = 951 MHz
69
fCLK = 9 GHz , fOUT = 1851 MHz
72
fCLK = 9 GHz , fOUT = 2651 MHz
71
fCLK = 9 GHz , fOUT = 3651 MHz
67
fCLK = 6 GHz , fOUT = 501 MHz
72
fCLK = 6 GHz , fOUT = 951 MHz
65
fCLK = 6 GHz , fOUT = 1851 MHz
57
fCLK = 6 GHz , fOUT = 2651 MHz
57
fCLK = 9 GHz , fOUT = 501 MHz
71
fCLK = 9 GHz , fOUT = 951 MHz
65
fCLK = 9 GHz , fOUT = 1851 MHz
62
fCLK = 9 GHz , fOUT = 2651 MHz
54
fCLK = 9 GHz , fOUT = 3651 MHz
51
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
dBc
dBc
dBc
dBc
15
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Electrical Characteristics - AC Specifications (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, external differential clock mode at 9
GSPS, 12x Interpolation, 0 dBFS, fOUT = 2.14 GHz, I(OUTFS) = 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise
noted.
PARAMETER
HD3
CMP2
CMP4+
IMD3
16
TEST CONDITIONS
3rd Order Harmonic
Fs/2 clock mixing product (Fs/2 – fOUT)
Fs/N (N = 4, 8, 16) clock mixing product
(fOUT ± Fs/N)
Third-order two-tone intermodulation
distortion
Submit Documentation Feedback
MIN
TYP
MAX
fCLK = 6 GHz , fOUT = 501 MHz
63
fCLK = 6 GHz , fOUT = 951 MHz
62
fCLK = 6 GHz , fOUT = 1851 MHz
71
fCLK = 6 GHz , fOUT = 2651 MHz
69
fCLK = 9 GHz , fOUT = 501 MHz
62
fCLK = 9 GHz , fOUT = 951 MHz
61
fCLK = 9 GHz , fOUT = 1851 MHz
66
fCLK = 9 GHz , fOUT = 2651 MHz
65
fCLK = 9 GHz , fOUT = 3651 MHz
67
fCLK = 6 GHz , fOUT = 501 MHz
85
fCLK = 6 GHz , fOUT = 951 MHz
85
fCLK = 6 GHz , fOUT = 1851 MHz
82
fCLK = 6 GHz , fOUT = 2651 MHz
79
fCLK = 9 GHz , fOUT = 501 MHz
78
fCLK = 9 GHz , fOUT = 951 MHz
76
fCLK = 9 GHz , fOUT = 1851 MHz
73
fCLK = 9 GHz , fOUT = 2651 MHz
74
fCLK = 9 GHz , fOUT = 3651 MHz
68
fCLK = 6 GHz , fOUT = 501 MHz
92
fCLK = 6 GHz , fOUT = 951 MHz
87
fCLK = 6 GHz , fOUT = 1851 MHz
81
fCLK = 6 GHz , fOUT = 2651 MHz
78
fCLK = 9 GHz , fOUT = 501 MHz
95
fCLK = 9 GHz , fOUT = 951 MHz
89
fCLK = 9 GHz , fOUT = 1851 MHz
84
fCLK = 9 GHz , fOUT = 2651 MHz
79
fCLK = 9 GHz , fOUT = 3651 MHz
74
fCLK = 6 GHz , fOUT = 501 ± 5 MHz, –6 dBFS each tone
80
fCLK = 6 GHz , fOUT = 951 ± 5 MHz, –6 dBFS each tone
76
fCLK = 6 GHz , fOUT = 1851 ± 5 MHz, –6 dBFS each
tone
73
fCLK = 6 GHz , fOUT = 2651 ± 5 MHz, –6 dBFS each
tone
72
fCLK = 9 GHz , fOUT = 501 ± 5 MHz, –6 dBFS each tone
80
fCLK = 9 GHz , fOUT = 951 ± 5 MHz, –6 dBFS each tone
75
fCLK = 9 GHz , fOUT = 1851 ± 5 MHz, –6 dBFS each
tone
70
fCLK = 9 GHz , fOUT = 2651 ± 5 MHz, –6 dBFS each
tone
70
fCLK = 9 GHz , fOUT = 3651 ± 5 MHz, –6 dBFS each
tone
68
UNIT
dBc
dBc
dBc
dBc
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Electrical Characteristics - AC Specifications (continued)
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, external differential clock mode at 9
GSPS, 12x Interpolation, 0 dBFS, fOUT = 2.14 GHz, I(OUTFS) = 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise
noted.
PARAMETER
Noise Spectral Density > 50 MHz
offset (1)
NSD
NSD
(on-chip
PLL)
Isolation
(1)
TEST CONDITIONS
Noise Spectral Density > 50 MHz offset
On-chip PLL enabled
Isolation between DAC A and DAC B
analog output
MIN
TYP
MAX
fCLK = 6 GHz , fOUT = 501 MHz
–170
fCLK = 6 GHz , fOUT = 951 MHz
–163
fCLK = 6 GHz , fOUT = 1851 MHz
–157
fCLK = 6 GHz , fOUT = 2651 MHz
–155
fCLK = 9 GHz , fOUT = 501 MHz
–172
fCLK = 9 GHz , fOUT = 951 MHz
–166
fCLK = 9 GHz , fOUT = 1851 MHz
–157
fCLK = 9 GHz , fOUT = 2651 MHz
–156
fCLK = 9 GHz , fOUT = 3651 MHz
–153
fCLK = 6 GHz , fOUT = 501 MHz, –9 dBFS
–172
fCLK = 6 GHz , fOUT = 951 MHz, –9 dBFS
–164
fCLK = 6 GHz , fOUT = 1851 MHz, –9 dBFS
–162
fCLK = 9 GHz , fOUT = 2651 MHz, –9 dBFS
–162
fCLK = 9 GHz , fOUT = 3651 MHz, –9 dBFS
–159
fCLK = 5 GHz , fOUT = 501 MHz
–172
fCLK = 5 GHz , fOUT = 951 MHz
–166
fCLK = 5 GHz , fOUT = 1851 MHz
–157
fCLK = 7.5 GHz , fOUT = 501 MHz
–173
fCLK = 7.5 GHz , fOUT = 951 MHz
–167
fCLK = 7.5 GHz , fOUT = 1851 MHz
–159
fCLK = 7.5 GHz , fOUT = 2651 MHz
–155
fCLK = 7.5 GHz , fOUT = 3651 MHz
–151
fCLK = 5 GHz , fOUT = 501 MHz, –9 dBFS
–169
fCLK = 5 GHz , fOUT = 951 MHz, –9 dBFS
–167
fCLK = 5 GHz , fOUT = 1851 MHz, –9 dBFS
–162
fCLK = 7.5 GHz , fOUT = 2651 MHz, –9 dBFS
–162
fCLK = 7.5 GHz , fOUT = 3651 MHz, –9 dBFS
–157
fOUT = 1856 MHz
82
fOUT = 3105 MHz
73
UNIT
dBFS/Hz
dBFS/Hz
dBc
Also valid for on-chip PLL enabled in DAC38RF82
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
17
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
7.8 PLL/VCO Electrical Characteristics
Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, internal PLL/VCO clock mode, 12x
Interpolation, fOUT = 1.8 GHz, I(OUTFS) = 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise noted.
PARAMETER
TEST CONDITIONS
DAC38RF82
MIN
TYP
DAC38RF89
MAX
MIN
TYP
UNIT
MAX
PLL/VCO
fref
Reference clock
frequency
100
fVCO
/4
100
fVCO
/4
MHz
fPFD
Frequency of phase &
frequency detector
100
500
100
500
MHz
fvcoL
Low VCO operating
frequency
5240
6720
4500
5600
MHz
fvcoH
High VCO operating
frequency
7960
9000
6600
8400
MHz
fBW
Loop filter bandwidth
500
500
KHz
Low VCO Phase Noise
600 KHz
Frequ
ency
Offset
1.2 MHz
1.8 MHz
-123
fvco = 6 GHz,CP=5, fPFD = 500 MHz,
measured at output frequency = 1.8 GHz
6.0 MHz
-132
-135
-146
600 KHz
Frequ
ency
Offset
1.2 MHz
1.8 MHz
-123
dBc/Hz
-132
fvco = 5 GHz,CP=5, fPFD = 312.5 MHz,
measured at output frequency = 1.8 GHz
-136
6.0 MHz
-147
High VCO Phase Noise
600 kHz
Frequ
ency
Offset
1.2 MHz
1.8 MHz
-123
fvco = 9 GHz, CP=5, fPFD = 500 MHz,
measured at output frequency = 1.8 GHz
6.0 MHz
-131
-135
-148
600 kHz
Frequ
ency
Offset
1.2 MHz
1.8 MHz
-124
-132
fvco = 7.5 GHz, CP=5, fPFD = 468.75 MHz,
measured at output frequency = 1.8 GHz
-136
6.0 MHz
18
Submit Documentation Feedback
dBc/Hz
-148
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
7.9 Timing Requirements
MIN
NOM
MAX
UNIT
Digital Input Timing Specifications
Timing: SYSREF+/ts(SYSREF)
Setup time, SYSREF+/- valid to rising
edge of DACCLK+/-
SYSREF Capture assist disabled
50
ps
th(SYSREF)
Hold time, SYSREF+/- valid after rising
edge of DACCLK+/-
SYSREF Capture assist disabled
50
ps
Timing: Serial Port
ts(/SDEN)
Setup time, SDEN to rising edge of SCLK
20
ns
ts(SDIO)
Setup time, SDIO valid to rising edge of SCLK
10
ns
th(SDIO)
Hold time, SDIO valid after rising edge of SCLK
5
ns
t(SCLK)
Period of SCLK
td(Data)
tRESET
temperature sensor read
1
µs
100
ns
Data output delay after falling edge of SCLK
25
ns
Minimum RESET pulse width
25
ns
All other registers
Analog Output
ts(DAC)
Output settling time to 0.1%
1
ns
tr
Output rise time 10% to 90%
50
ps
tf
Output fall time 90% to 10%
50
ps
250
ps
Latency
RX SerDes AnalogDelay
DAC wake-up time
IOUT current settling to 1% of IOUTFS
from deep sleep
90
µs
DAC sleep time
IOUT current settling to less than 1% of
IOUTFS in deep sleep
90
µs
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
19
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
7.10 Typical Characteristics
Unless otherwise noted, all plots are at TA = 25°C, nominal supply voltages, fDAC = 8847.36MSPS, 12x interpolation, 0dBFS
digital input, 40 mA full scale output current , LMFSHd = 84111 and PLL is disabled.
180
180
-12dBFS
-9dBFS
-6dBFS
0dBFS
174
168
168
162
NSD (dBc/Hz)
NSD (dBc/Hz)
162
156
150
144
144
138
132
126
126
1000
1500
2000 2500 3000 3500
Output Frequency (MHz)
4000
120
500
4500
1500
2000 2500 3000 3500
Output Frequency (MHz)
4000
4500
D011
Figure 2. NSD vs Output Frequency Over Output Current
IoutFS
180
80
174
75
168
70
-12dBFS
-6dBFS
0dBFS
HD2 (dBc)
65
156
150
144
5 GHz VCO (DAC38RF89)
7.5GHz VCO (DAC38RF89)
6 GHz VCO (DAC38RF82)
9 GHz VCO (DAC38RF82)
9 GHz External clock
138
132
126
120
500
1000
D005
162
NSD (dBc/Hz)
150
132
Figure 1. NSD vs Output Frequency Over Input Scale
1000
1500
2000 2500 3000 3500
Output Frequency (MHz)
4000
60
55
50
45
40
35
500
4500
1000
1500
D012
Figure 3. NSD vs Output Frequency Over Clocking Option
2000 2500 3000 3500
Output Frequency (MHz)
4000
4500
D002
Figure 4. HD2 vs Output Frequency Over Input Scale
80
90
Iout=10mA
Iout=20mA
Iout=30mA
Iout=40mA
75
70
5 GHz VCO (DAC38RF89)
7.5GHz VCO (DAC38RF89)
6 GHz VCO (DAC38RF82)
9 GHz VCO (DAC38RF82)
9 GHz External clock
85
80
75
HD2 (dBc)
65
HD2 (dBc)
156
138
120
500
Iout=40mA
Iout=30mA
Iout=20mA
Iout=10mA
174
60
55
50
70
65
60
55
50
45
45
40
35
500
40
1000
1500
2000 2500 3000 3500
Output Frequency (MHz)
4000
4500
Submit Documentation Feedback
1000
1500
D010
Figure 5. HD2 vs Output Frequency Over Output Current
IoutFS
20
35
500
2000 2500 3000 3500
Output Frequency (MHz)
4000
4500
D012
Figure 6. HD2 vs Output Frequency Over Clocking Option
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Typical Characteristics (continued)
Unless otherwise noted, all plots are at TA = 25°C, nominal supply voltages, fDAC = 8847.36MSPS, 12x interpolation, 0dBFS
digital input, 40 mA full scale output current , LMFSHd = 84111 and PLL is disabled.
105
100
95
90
85
80
75
70
65
60
55
50
45
40
35
500
80
75
70
HD3 (dBc)
HD3 (dBc)
65
60
55
50
-12dBFS
-6dBFS
0dBFS
45
40
35
500
1000
1500
2000 2500 3000 3500
Output Frequency (MHz)
4000
4500
75
70
70
65
65
SFDR (dBc)
HD3 (dBc)
80
75
60
55
5 GHz VCO (DAC38RF89)
7.5GHz VCO (DAC38RF89)
6 GHz VCO (DAC38RF82)
9 GHz VCO (DAC38RF82)
9 GHz External clock
40
35
500
1000
1500
2000 2500 3000 3500
Output Frequency (MHz)
4000
2000 2500 3000 3500
Output Frequency (MHz)
4000
4500
D024
-12dBFS
-6dBFS
0dBFS
60
55
50
45
40
35
500
4500
1000
1500
D012
Figure 9. HD3 vs Output Frequency Over Clocking Option
2000 2500 3000 3500
Output Frequency (MHz)
4000
4500
D001
Figure 10. SFDR vs Output Frequency Over Input Scale
80
90
Iout=10mA
Iout=20mA
Iout=30mA
Iout=40mA
75
70
5 GHz VCO (DAC38RF89)
7.5GHz VCO (DAC38RF89)
6 GHz VCO (DAC38RF82)
9 GHz VCO (DAC38RF82)
9 GHz External clock
85
80
75
65
SFDR (dBc)
SFDR (dBc)
1500
Figure 8. HD3 vs Output Frequency Over Output Current
IoutFS
80
45
1000
D004
Figure 7. HD3 vs Output Frequency Over Input Scale
50
Iout=10mA
Iout=20mA
Iout=30mA
Iout=40mA
60
55
50
70
65
60
55
50
45
45
40
35
500
40
1000
1500
2000 2500 3000 3500
Output Frequency (MHz)
4000
4500
35
500
1000
1500
D008
Figure 11. SFDR vs Output Frequency Over Output Current
IoutFS
2000 2500 3000 3500
Output Frequency (MHz)
4000
4500
D012
Figure 12. SFDR vs Output Frequency Over Clocking Option
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
21
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Typical Characteristics (continued)
80
80
75
75
70
70
65
65
IMD3 (dBc)
IMD3 (dBc)
Unless otherwise noted, all plots are at TA = 25°C, nominal supply voltages, fDAC = 8847.36MSPS, 12x interpolation, 0dBFS
digital input, 40 mA full scale output current , LMFSHd = 84111 and PLL is disabled.
60
55
50
40
35
500
60
55
50
-18dBFS
-12dBFS
-6dBFS
0dBFS
45
1000
1500
5 GHz VCO (DAC38RF89)
7.5GHz VCO (DAC38RF89)
6 GHz VCO (DAC38RF82)
9 GHz VCO (DAC38RF82)
9 GHz External clock
45
40
2000 2500 3000 3500
Output Frequency (MHz)
4000
35
500
4500
1000
1500
D006
2000 2500 3000 3500
Output Frequency (MHz)
4000
4500
D012
-18 dBFS digital backoff
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
90
DAC A to B
DAC B to A
86
82
78
74
70
66
62
58
54
0
500
1000 1500 2000 2500 3000 3500 4000 4500
Output Frequency (MHz)
D000
Figure 15. Power vs Output Frequency
22
Figure 14. IMD3 vs Output Frequency Over Clocking Option
Isolation (dBc)
Output Power (dBm)
Figure 13. IMD3 vs Output Frequency Over Input Scale
Submit Documentation Feedback
50
500
1000
1500
2000 2500 3000 3500
Output Frequency (MHz)
4000
4500
D002
Figure 16. Isolation vs Output Frequency
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Typical Characteristics (continued)
Unless otherwise noted, all plots are at TA = 25°C, nominal supply voltages, fDAC = 8847.36MSPS, 12x interpolation, 0dBFS
digital input, 40 mA full scale output current , LMFSHd = 84111 and PLL is disabled.
-60
-80
CP=2
CP=3
CP=4
CP=5
CP=6
CP=7
CP=8
CP=9
CP=10
CP=11
CP=12
CP=13
CP=14
CP=15
-100
-120
-100
Phase Noise (dBc)
Phase Noise (dBc)
-80
CP=1
CP=2
CP=3
CP=4
CP=5
CP=6
CP=7
CP=8
CP=9
CP=10
CP=11
CP=12
CP=13
CP=14
CP=15
-120
-140
-140
-160
1000
10000
100000
1000000
Freq offset (Hz)
VCO frequency = 8.85 GHz
1E+7
-160
1000
5E+7
Measured at 1.8 GHz
1E+7
5E+7
D003
Measured at 1.8 GHz
Figure 18. DAC38RF89 VCO1 Phase Noise vs Offset
Frequency Over Charge pump current
-90
-90
div4
div3
div2
-100
div4
div3
div2
-100
-110
Phase Noise (dBc)
-110
Phase Noise (dBc)
100000
1000000
Freq offset (Hz)
VCO frequency = 7.5 GHz
Figure 17. DAC38RF82 VCO1 Phase Noise vs Offset
Frequency Over Charge pump current
-120
-130
-120
-130
-140
-140
-150
-150
-160
1000
10000
D027
10000
100000
1000000
Freq offset (Hz)
1E+7
5E+7
-160
1000
10000
D028
VCO frequency = 8.85 GHz
100000
1000000
Freq offset (Hz)
1E+7
5E+7
D004
VCO frequency = 7.5 GHz
Figure 19. DAC38RF82 VCO1 Output Clock Phase Noise vs
Offset frequency Over Divider Ratio
Figure 20. DAC38RF89 VCO1 Output Clock Phase Noise vs
Offset frequency Over Divider Ratio
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
23
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Typical Characteristics (continued)
Unless otherwise noted, all plots are at TA = 25°C, nominal supply voltages, fDAC = 8847.36MSPS, 12x interpolation, 0dBFS
digital input, 40 mA full scale output current , LMFSHd = 84111 and PLL is disabled.
-80
-80
CP=1
CP=2
CP=3
CP=4
CP=5
CP=6
CP=7
CP=8
CP=9
CP=10
CP=11
CP=12
CP=13
CP=14
CP=15
-120
-100
Phase Noise (dBc)
Phase Noise (dBc)
-100
-140
-160
1000
CP=1
CP=2
CP=3
CP=4
CP=5
CP=6
CP=7
CP=8
CP=9
CP=10
CP=11
CP=12
CP=13
CP=14
CP=15
-120
-140
10000
100000
1000000
Freq offset (Hz)
VCO frequency = 5.9 GHz
1E+7
-160
1000
5E+7
10000
D029
Measured at 1.8 GHz
100000
1000000
Freq offset (Hz)
VCO frequency = 5.0 GHz
Figure 21. DAC38RF82 VCO0 Phase Noise vs Offset
Frequency Over Charge Pump Current
1E+7
D001
Measured at 1.8 GHz
Figure 22. DAC38RF89 VCO0 Phase Noise vs Offset
Frequency Over Charge Pump Current
-100
-100
div4
div3
div2
-110
-110
-120
-120
Phase Noise (dBc)
Phase Noise (dBc)
div4
div3
div2
-130
-140
-150
-160
1000
-130
-140
-150
10000
100000
1000000
Freq offset (Hz)
1E+7
5E+7
10000
100000
1000000
Freq offset (Hz)
1E+7
5E+7
D030
VCO frequency = 5 GHz
Figure 23. DAC38RF82 VCO0 Output clock Phase Noise vs
Offset Frequency Over Divider Ratio
Submit Documentation Feedback
-160
1000
D030
VCO frequency = 5.9 GHz
24
5E+7
Figure 24. DAC38RF89 VCO0 Output clock Phase Noise vs
Offset Frequency Over Divider Ratio
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8 Detailed Description
8.1 Overview
The DAC38RF82 and DAC38RF89 are high performance, wide bandwidth RF-sampling digital-to-analog (DACs)
that are capable of dual channel input data rate up to 3.33 GSPS or single-channel operation with 8-bits up to 9GSPS. The devices have a low power JESD204B Interface with up to 8 lanes, with a maximum bit rate of 12.5
Gbps (DAC38RF89) and 12.8 Gbps (DAC38RF82). In dual channel operation, the input interface is capable of
data rates up to 3.33 GSPS at 12-bits and 2.5 GSPS at 16-bits resolution without interpolation. When used as a
complex baseband transmitter with interpolation modes from 2x to 24x, the DAC38RF82 (or DAC38RF89) is
capable of synthesizing wideband signals up to 2 GHz bandwidth with 16-bit input resolution and 2.66 GHz
bandwidth with 12-bit input resolution. The 8-bit mode allows an input at the full 9 GSPS maximum DAC sample
rate and can synthesize wideband signals from 0 to 4.5 GHz. An optional low jitter PLL/VCO simplifies the DAC
clock generation by allowing use of a lower frequency reference clock. DAC38RF82 and DAC38RF89 support
different VCO frequency ranges, summarized in Device Comparison Table.
DACCLK+
Low Jitter
PLL
DACCLK±
DACCLKSE
VDDL2_1
VDDL1_1
VDDA1
VDDE1
VDDDIG1
VDDAVCO18
VDDAPLL1
VDDAPLL18
VDDCLK1
8.2 Functional Block Diagrams
CLKTX+
Divider
/2, /3, /4
Clock
Distribution
CLKTX±
VDDTX1
Multi-band DUC Channel 2 (multi-DUC2)
SYSREF+
SYSREF±
I
RX[4..7]+
Q
14-b
100 W
DAC
x
sin(x)
I
RX[4..7]±
VDDTX18
DACB
Gain
NCO 3
VOUT2+
VOUT2±
Q
JESD Interface
SYNC2\+
SYNC2\±
VDDT1
VDDR18
NCO 4
0.9 V
Ref
NCO 1
EXTIO
RBIAS
TESTMODE
I
RX[0..3]+
Q
RX[0..3]±
I
SYNC1\+
Q
14-b
100 W
DAC
x
sin(x)
VDDS18
VEE18N
DACA
Gain
NCO 2
SYNC1\±
VOUT1+
VOUT1±
VDDA18
Multi-band DUC Channel 1 (multi-DUC1)
ATEST
AMUX0/1
Temp
Sensor
TRST\
TMS
TDI
GPI1
GPI0
GPO1
GPO0
TESTMODE
ALARM
SLEEP
RESETB
TXENABLE
SCLK
SDENB
SDO
SDIO
GND
VDDIO18
JTAG
TCLK
Control Interface
VSENSE
TDO
IFORCE
Figure 25. 12-, 16-Bit Input Mode Block Diagram
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
25
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
DACCLK+
Low Jitter
PLL
DACCLK-
VDDL2_1
VDDL1_1
VDDA1
VDDDIG1
VDDAVCO18
VDDAPLL1
VDDAPLL18
VDDCLK1
Functional Block Diagrams (continued)
CLKTX+
Divider
/2, /3, /4
Clock
Distribution
CLKTXVDDTX1
DACCLKSE
VDDTX18
SYSREF+
SYSREFRX[4..7]+
DACA
Gain
JESD Interface
RX[4..7]SYNC2\+
SYNC2\VDDT1
VDDR18
14-b
DAC
x
sin(x)
8
RX[0..3]+
100:
VOUT1+
VOUT1-
0.9 V
Ref
RX[0..3]SYNC1\+
EXTIO
RBIAS
TESTMODE
VEE18N
SYNC1\VDDA18
VDDS18
ATEST
AMUX0/1
Temp
Sensor
TRST\
TMS
TCLK
GPI1
GPI0
GPO1
GPO0
TESTMODE
ALARM
SLEEP
RESETB
TXENABLE
SCLK
SDENB
SDIO
SDO
VDDIO18
GND
JTAG
TDI
Control Interface
VSENSE
TDO
IFORCE
Copyright © 2016, Texas Instruments Incorporated
Figure 26. 8-Bit Input Mode Block Diagram
26
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.3 Feature Description
8.3.1 SerDes Inputs
The DAC38RF82 (or DAC38RF89) RX [0..7]+/- differential inputs are each internally terminated to a common
point via 50 Ω, as shown in Figure 27.
RXP
0.7V
50O
TERM
=001
50pF
TERM
=100
TERM
=101
Level
Shift
To
Equalizer
&
Samplers
50O
0.25V
RXN
Figure 27. Serial Lane Input Termination
Common mode termination is via a 50 pF capacitor to GND. The common mode voltage and termination of the
differential signal can be controlled in a number of ways to suit a variety of applications via field TERM in register
SRDS_CFG2 (8.5.87), as described in Table 1.
NOTE
AC coupling is recommended for JESD204B compliance.
Table 1. Receiver Termination Selection
TERM
EFFECT
000
Reserved
001
Common point set to 0.7 V. This configuration is for AC coupled systems. The transmitter has no effect on the
receiver common mode, which is set to optimize the input sensitivity of the receiver. Note: this mode is not
compatible with JESD204B.
01x
Reserved
100
Common point set to GND. This configuration is for applications that require a 0 V common mode.
101
Common point set to 0.25 V. This configuration is for applications that require a low common mode.
110
Reserved
111
Common point floating. This configuration is for DC coupled systems in which the common mode voltage is set by
the attached transmit link partner to 0 and 0.6 V. Note: this mode is not compatible with JESD204B
Input data is sampled by the differential sensing amplifier using clocks derived from the clock recovery algorithm.
The polarity of RX+ and RX- can be inverted by setting the bit of the corresponding lane in field INVPAIR in
register SRDS_POL (8.5.88) to “1”. This can potentially simplify PCB layout and improve signal integrity by
avoiding the need to swap over the differential signal traces.
Due to processing effects, the devices in the RX+ and RX- differential sense amplifiers will not be perfectly
matched and there will be some offset in switching threshold. The DAC38RF82 (or DAC38RF89) contains
circuitry to detect and correct for this offset. This feature can be enabled by setting ENOC in register
SRDS_CFG1 (8.5.86) to “1”. It is anticipated that most users will enable this feature.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
27
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.3.2 SerDes Rate
The DAC38RF82 (or DAC38RF89) has eight configurable JESD204B serial lanes. The highest speed of each
SerDes lane is 12.5 Gbps (DAC38RF89) and 12.8 Gbps (DAC38RF82). Because the primary operating
frequency of the SerDes is determined by its reference clock and PLL multiplication factor, there is a limit on the
lowest SerDes rate supported. To support lower speed application, each receiver should be configured to
operate at half, quarter or eighth of the full rate via field RATE in register SRDS_CFG2 (8.5.87). Refer to Table 2
for details.
Table 2. Lane Rate Selection
RATE
EFFECT
00
Full rate. Four data samples taken per SerDes PLL output clock cycle.
01
Half rate. Two data samples taken per SerDes PLL output clock cycle.
10
Quarter rate. One data samples taken per SerDes PLL output clock cycle.
11
Eighth rate. One data samples taken every two SerDes PLL output clock cycles.
8.3.3 SerDes PLL
The DAC38RF82 (or DAC38RF89) has two integrated PLLs, one PLL is to provide the clocking of DAC, refer to
the DAC PLL section; the other PLL is to provide the clocking for the high speed SerDes. The reference
frequency of the SerDes PLL can be in the range of 100-800 MHz nominal, and 300-800 MHz optimal. The
reference frequency is derived from DACCLK divided down by the value in field SerDes_REFCLK_DIV in register
SRDS_CLK_CFG (8.5.84), as shown in Figure 28. Field SerDes_CLK_SEL in register SRDS_CLK_CFG (8.5.84)
determines if the DACCLK input or DAC PLL output is used as the source of the SerDes PLL reference. If the
DACCLK input is used, a pre-divider set by field SerDes_REFCLK_PREDIV in register SRDS_CLK_CFG
(8.5.84) should be used to reduce the frequency of the DACCLK.
SERDES_REFCLK_PREDIV
Predivider
0
DACCLK+
divider
0
SERDES
PLL
REFCLK
DACCLKDAC PLL
DACCLKSE
1
1
SERDES_REFCLK_DIV
SERDES_REFCLK_SEL
SEL_EXTCLK_DIFFSE
Figure 28. Reference Clock of SerDes PLL
During normal operation, the clock generated by PLL is 4-25 times the reference frequency, according to the
multiply factor selected via the field MPY] in register SRDS_PLL_CFG (8.5.85). In order to select the appropriate
multiply factor and reference clock frequency, it is first necessary to determine the required PLL output clock
frequency. The relationship between the PLL output clock frequency and the lane rate is determined by field
RATE in register SRDS_CFG2 (8.5.87) is shown in Table 3. Having computed the PLL output frequency, the
reference frequency can be obtained by dividing this by the multiply factor specified via MPY.
28
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Table 3. Relationship Between Lane Rate and SerDes PLL Output Frequency
RATE
LINE RATE
PLL OUTPUT FREQUENCY
00
x Gbps
0.25x GHz
01
x Gbps
0.5x GHz
10
x Gbps
1x GHz
11
x Gbps
2x GHz
Table 4. SerDes PLL Multiplier (MPY) Values
MPY
EFFECT
0x10
4x
0x14
5x
0x18
6x
0x20
8x
0x21
8.25x
0x28
10x
0x30
12x
0x32
12.5x
0x3C
15x
0x40
16x
0x42
16.5x
0x50
20x
0x58
22x
0x64
25x
Other codes
Reserved
The wide range of multiply factors combined with the different rate modes means it is often possible to achieve a
given line rate from multiple different reference frequencies. The configuration which utilizes the highest
reference frequency achievable is always preferable.
The SerDes PLL VCO must be in the nominal range of 1.5625 - 3.125 GHz. It is necessary to adjust the loop
filter depending on the operating frequency of the VCO. If the PLL output frequency is below 2.17 GHz, VRANGE
in register SRDS_PLL_CFG (8.5.84) should be set high.
Performance of the integrated PLL can be optimized according to the jitter characteristics of the reference clock
by setting the appropriate loop bandwidth via field LB in register SRDS_PLL_CFG (8.5.84). The loop bandwidth
is obtained by dividing the reference frequency by BWSCALE, where the BWSCALE is a function of both LB and
PLL output frequency as shown in Table 5.
Table 5. SerDes PLL Loop Bandwidth Selection
LB
EFFECT
BWSCALE vs PLL OUTPUT FREQUENCY
3.125 GHz
2.17 GHz
1.5625 GHz
16
00
Medium loop bandwidth
13
14
01
Ultra high loop bandwidth
7
8
8
10
Low loop bandwidth
21
23
30
11
High loop bandwidth
10
11
14
An approximate loop bandwidth of 8 – 30 MHz is suitable and recommended for most systems where the
reference clock is via low jitter clock input buffer. For systems where the reference clock is via a low jitter input
cell, but of low quality, an approximate loop bandwidth of less than 8 MHz may offer better performance. For
systems where the reference clock is cleaned via an ultra-low jitter LC-based cleaner PLL, a high loop bandwidth
up to 60 MHz is more appropriate. Note that the use of ultra-high loop bandwidth setting is not recommended for
PLL multiply factor of less than 8.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
29
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
A free running clock output is available when field ENDIVCLK in register SRDS_PLL_CFG (8.5.85) is set high. It
runs at a fixed divided-by-80 of the PLL output frequency and can be output on the ALARM pin by setting field
DTEST to “0001” (lanes 0 – 3) or “0010” (lanes 4 – 7) in register DTEST (8.5.76).
8.3.4 SerDes Equalizer
All channels of the DAC38RF82 (or DAC38RF89) incorporate an adaptive equalizer, which can compensate for
channel insertion loss by attenuating the low frequency components with respect to the high frequency
components of the signal, thereby reducing inter-symbol interference. Figure 29 shows the response of the
equalizer, which can be expressed in terms of the amount of low frequency gain and the frequency up to which
this gain is applied (i.e., the frequency of the ’zero’). Above the zero frequency, the gain increases at 6 dB/octave
until it reaches the high frequency gain.
dB
Gain
6
-6.3
108
Log10MHz
414
Frequency
Figure 29. Equalizer Frequency Response
The equalizer can be configured via fields EQ and EQHLD in register SRDS_CFG1 (8.5.86). Table 6 and Table 7
summarize the options. When enabled, the receiver equalization logic analyzes data patterns and transition times
to determine whether the low frequency gain should be increased or decreased. The decision logic is
implemented as a voting algorithm with a relatively long analysis interval. The slow time constant that results
reduces the probability of incorrect decisions but allows the equalizer to compensate for the relatively stable
response of the channel. The lock time for the adaptive equalizer is data dependent, and so it is not possible to
specify a generally applicable absolute limit. However, assuming random data, the maximum lock time will be
6x106 divided by the CDR activity level. For field CDR in register SRDS_CFG1 (8.5.86) = 110, the activity level
is 1.5 x 106 UI.
When EQ[2] = 0, finer control of gain boost is available using the EQBOOST IEEE1500 tuning chain field, as
shown in Table 6.
Table 6. Receiver Equalization Configuration
EQ
EFFECT
00
No equalization. The equalizer provides a flat response at the maximum gain. This setting may be
appropriate if jitter at the receiver occurs predominantly as a result of crosstalk rather than
frequency dependent loss.
01
Fully adaptive equalization. The zero position is determined by the selected operating rate, and the
low frequency gain of the equalizer is determined algorithmically by analyzing the data patterns and
transition positions in the received data. This setting should be used for most applications.
10
Precursor equalization analysis. The data patterns and transition positions in the received data are
analyzed to determine whether the transmit link partner is applying more or less precursor
equalization than necessary.
11
Postcursor equalization analysis. The data patterns and transition positions in the received data are
analyzed to determine whether the transmit link partner is applying more or less post-cursor
equalization than necessary.
[1-0]
30
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Table 6. Receiver Equalization Configuration (continued)
EQ
[2]
EFFECT
0
Default
1
Boost. Equalizer gain boosted by 6 dB, with a 20% reduction in bandwidth, and an increase of
5mW power consumption. May improve performance over long links.
Table 7. Receiver Equalizer Hold
EQHOLD
EFFECT
0
Equalizer adaption enabled. The equalizer adaption and analysis algorithm is enabled. This should be the default
state.
1
Equalizer adaption held. The equalizer is held in its current state. Additionally, the adaption and analysis algorithm
is reset.
Table 8. Relationship Between Lane Rate and SerDes PLL Output Frequency
EQBOOST
GAIN BOOST (dB)
BANDWIDTH CHANGE (%)
POWER INCREASE (mW)
00
0
0
0
01
2
-30
0
01
4
10
5
11
6
-20
5
When EQ is set to 010 or 011, the equalizer is reconfigured to provide analytical data about the amount of pre
and post cursor equalization respectively present in the received signal. This can in turn be used to adjust the
equalization settings of the transmitting link partner, where a suitable mechanism for communicating this data
back to the transmitter exists. Status information is provided by setting field DTEST in register DTEST (8.5.76) to
“0111” for EQOVER and “0110” for EQUNDER. The procedure is as follows:
1. Enable the equalizer by setting fields EQHLD low and EQ to “001” (register SRDS_CFG1 8.5.86). Allow
sufficient time for the equalizer to adapt;
2. Set EQHLD to 1 to lock the equalizer and reset the adaption algorithm. This also causes both EQOVER and
EQUNDER to become low;
3. Wait at least 48 UI, and proportionately longer if the CDR activity is less than 100%, to ensure the 1 on
EQHLD is sampled and acted upon;
4. Set EQ to “010” or “011”, and EQHLD to 0. The equalization characteristics of the received signal are
analysed (the equalizer response will continue to be locked);
5. Wait at least 150×103 UI to allow time for the analysis to occur, proportionately longer if the CDR activity is
less than 100%;
6. Examine EQOVER and EQUNDER for results of analysis
– If EQOVER is high, it indicates the signal is over equalized;
– If EQUNDER is high, it indicates the signal is under equalized;
7. Set EQHLD to 1;
8. Repeat items 3–7 if required;
9. Set EQ to “001”, and EQHLD to 0 to exit analysis mode and return to normal adaptive equalization.
NOTE
When changing EQ from one non-zero value to another, EQHLD must already be 1. If this
is not the case, there is a chance the equalizer could be reset by a transitory input state
(i.e., if EQ is momentarily 000). EQHLD can be set to 0 at the same time as EQ is
changed.
As the equalizer adaption algorithm is designed to equalize the post cursor, EQOVER or
EQUNDER will only be set during post cursor analysis if the amount of post cursor
equalization required is more or less than the adaptive equalizer can provide.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
31
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.3.5 JESD204B Descrambler
The descrambler is a 16-bit parallel self-synchronous descrambler based on the polynomial 1 + x14 + x15. From
the JESD204B specification, the scrambling/descrambling process only occurs on the user data, not on the code
group synchronization or the ILA sequence. Each multi-DUC has a separate descrambler that can be enabled
independently. The descrambler is enabled by field SCR in the multi-DUC paged register JESD_N_HD_SCR
(8.5.49).
8.3.6 JESD204B Frame Assembly
The DAC38RF82 (or DAC38RF89) may be programmed as a single or dual DAC device, with one JESD RX
block designated for each DAC. The two JESD RX blocks can be programmed to operate as two separate links
or as a single link.
The JESD204B defines the following parameters:
• L is the number of lanes
• M is the number of I or Q streams per device (2 = 1 IQ pair, 4 = 2 IQ pairs, 8 = 4 IQ pairs)
• F is the number of octets per frame clock period
• S is the number of samples per frame
• HD is the High-Density bit which controls whether a sample may be divided over more lanes
• N = NPRIME is the number of bits per sample (12 or 16 - bits)
Fields K and L are found in multi-DUC paged register JESD_K_L (8.5.46), M and S in multi-DUC paged register
JESD_M_S (8.5.48), and N, NPRIME and HD in multi-DUC paged register JESD_N_HD_SCR (8.5.49).
Table 9 lists the available JESD204B formats, interpolation rates and sample rate limits for the DAC38RF82 (or
DAC38RF89). The ranges are limited by the SerDes PLL VCO frequency range, the SerDes PLL reference clock
range, the maximum SerDes line rate, and the maximum DAC sample frequency. Table 10 through Table 27 lists
the frame formats for each mode. In the frame format tables, i CH (N) [x:y] and q CH (N) [x:y] are bits x through y
of the I and Q samples at time N of DUC channel CH. If [x..y] is not listed, the full sample is assumed. For
example, i0(0)[15:8] are bits 15 – 8 of the I sample at time 0, and q(1) is the full Q sample at time 1.
Table 9. JESD204B Formats for DAC38RF82 and DAC38RF89
L-M-F-S-Hd
1 TX
82121
42111
22210
12410
32
L-M-F-S-Hd
2 TX
NA
84111
44210
24410
Frame Format
1 TX: Table 10
1 TX: Table 11
2 TX: Table 12
1 TX: Table 13
2 TX: Table 14
1 TX: Table 15
2 TX: Table 16
Submit Documentation Feedback
Input
Resolution
IQ pairs per
DAC
Interp
Input rate
max (MSPS)
fDAC Max
(MSPS)
16
1
6
1500
9000
16
1
8
1125
9000
16
1
12
750
9000
16
1
16
562.5
9000
16
1
6
1250
7500
16
1
8
1125
9000
16
1
10
900
9000
16
1
12
750
9000
16
1
16
562.5
9000
16
1
18
500
9000
16
1
24
375
9000
16
1
8
625
5000
16
1
12
625
7500
16
1
16
562.5
9000
16
1
18
500
9000
16
1
20
450
9000
16
1
24
375
9000
16
1
16
312.5
5000
16
1
24
312.5
7500
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Table 9. JESD204B Formats for DAC38RF82 and DAC38RF89 (continued)
L-M-F-S-Hd
1 TX
Frame Format
Input
Resolution
IQ pairs per
DAC
Interp
Input rate
max (MSPS)
fDAC Max
(MSPS)
16
16
2
8
625
5000
2
12
625
7500
16
2
16
562.5
9000
16
2
24
375
9000
16
2
16
312.5
5000
16
2
24
312.5
7500
88210
1 TX: Table 17
2 TX: Table 18
24410
48410
1 TX: Table 19
2 TX: Table 20
24310
48310
1 TX: Table 21
2 TX: Table 22
12
2
24
375
9000
81180
NA
1 TX: Table 23
8
real input
1
9000
9000
1
3333
3333
2
3333
6666
1
2500
2500
2
2500
5000
4
2250
9000
44210
41380
82380
41121
(1)
L-M-F-S-Hd
2 TX
82121
1 TX: Table 24
2 TX: Table 25
1 TX: Table 26
2 TX: Table 27
real input (1)
12
real input (1)
16
Can also be used as I-Q pair per 2 DACs. See description in Wideband DUC (wide-DUC)
Table 10. JESD204B Frame Format for LMFSHd = 82121
# un bits
4
8
# en bits
5
10
Nibble
1
2
lane RX0
i0[15:8]
lane RX1
i0[7:0]
lane RX2
i1[15:8]
lane RX3
i1[7:0]
lane RX4
q0[15:8]
lane RX5
q0[7:0]
lane RX6
q1[15:8]
lane RX7
q1[7:0]
Table 11. JESD204B Frame Format for LMFSHd = 42111
# un bits
4
8
# en bits
5
10
Nibble
1
lane RX0
2
i0[15:8]
lane RX1
i0[7:0]
lane RX2
q0[15:8]
lane RX3
q0[7:0]
Table 12. JESD204B Frame Format for LMFSHd = 84111
(1)
(2)
# un bits
4
8
# en bits
5
10
Nibble
1
2
lane RX0
A-i0[15:8] (1)
lane RX1
A-i0[7:0] (2)
DAC A, I sample 0, MSB byte
DAC A, I sample 0, LSB byte
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
33
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Table 12. JESD204B Frame Format for LMFSHd = 84111 (continued)
lane RX2
A-q0[15:8]
lane RX3
A-q0[7:0]
lane RX4
B-i0[15:8]
lane RX5
B-i0[7:0]
lane RX6
B-q0[15:8]
lane RX7
B-q0[7:0]
Table 13. JESD204B Frame Format for LMFSHd = 22210
# un bits
4
8
12
16
# en bits
5
10
15
20
Nibble
1
2
3
4
lane RX0
i0
lane RX1
q0
Table 14. JESD204B Frame Format for LMFSHd = 44210
# un bits
4
8
12
16
# en bits
5
10
15
20
Nibble
1
2
3
4
lane RX0
(1)
A-i0
(1)
lane RX1
A-q0
lane RX2
B-i0
lane RX3
B-q0
DAC A, I sample 0
Table 15. JESD204B Frame Format for LMFSHd = 12410
# un bits
4
8
12
16
20
24
28
32
# en bits
5
10
15
20
25
30
35
40
Nibble
1
2
3
4
5
6
7
8
lane RX0
i0
q0
Table 16. JESD204B Frame Format for LMFSHd = 24410
# un bits
4
8
12
16
20
24
28
32
# en bits
5
10
15
20
25
30
35
40
Nibble
1
2
3
4
5
6
7
8
lane RX0
A-i0
lane RX1
(1)
(1)
A-q0
B-i0
B-q0
DAC A, I sample 0
Table 17. JESD204B Frame Format for LMFSHd = 44210
(1)
(2)
34
# un bits
4
8
12
16
# en bits
5
10
15
20
Nibble
1
2
3
4
lane RX0
A1-i0 (1)
lane RX1
A1-q0 (2)
lane RX2
A2-i0
DAC A, MultiDUC 1, I sample 0
DAC A, MultiDUC 2, I sample 0
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Table 17. JESD204B Frame Format for LMFSHd = 44210 (continued)
lane RX3
A2-q0
Table 18. JESD204B Frame Format for LMFSHd = 88210
(1)
# un bits
4
8
12
16
# en bits
5
10
15
20
Nibble
1
2
3
4
lane RX0
A1-i0 (1)
lane RX1
A1-q0
lane RX2
A2-i0
lane RX3
A2-q0
lane RX4
B1-i0
lane RX5
B1-q0
lane RX6
B2-i0
lane RX7
B1-q0
DAC A, MultiDUC 1, I sample 0
Table 19. JESD204B Frame Format for LMFSHd = 24410
# un bits
4
8
12
16
20
24
28
32
# en bits
5
10
15
20
25
30
35
40
Nibble
1
2
3
4
5
6
7
8
lane RX0
A1-i0 (1)
A1-q0
lane RX1
A2-i0
A2-q0
(1)
DAC A, MultiDUC 1, I sample 0
Table 20. JESD204B Frame Format for LMFSHd = 48410
# un bits
4
8
12
16
20
24
28
32
# en bits
5
10
15
20
25
30
35
40
Nibble
1
2
3
4
5
6
7
8
lane RX0
A1-i0 (1)
A1-q0
lane RX1
A2-i0
A2-q0
lane RX2
B1-i0
B1-q0
lane RX3
B2-i0
B2-q0
(1)
DAC A, MultiDUC 1, I sample 0
Table 21. JESD204B Frame Format for LMFSHd = 24310
(1)
# un bits
4
8
12
16
20
24
# en bits
5
10
15
20
25
30
Nibble
1
2
3
4
5
6
lane RX0
A1-i0 (1)
A1-q0
lane RX1
A2-i0
A2-q0
DAC A, MultiDUC 1, I sample 0
Table 22. JESD204B Frame Format for LMFSHd = 48310
# un bits
4
8
12
16
20
24
# en bits
5
10
15
20
25
30
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
35
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Table 22. JESD204B Frame Format for LMFSHd = 48310 (continued)
Nibble
(1)
1
2
3
4
5
lane RX0
A1-i0 (1)
A1-q0
lane RX1
A2-i0
A2-q0
lane RX2
B1-i0
B1-q0
lane RX3
B2-i0
B2-q0
6
DAC A, MultiDUC 1, I sample 0
Table 23. JESD204B Frame Format for LMFSHd = 81180
# un bits
4
8
# en bits
5
10
Nibble
1
lane RX0
(1)
2
A0
(1)
lane RX1
A1
lane RX2
A2
lane RX3
A3
lane RX4
A4
lane RX5
A5
lane RX6
A6
lane RX7
A7
DAC A, sample 0
Table 24. JESD204B Frame Format for LMFSHd = 41380
# un bits
4
8
12
16
20
24
# en bits
5
10
15
20
25
30
Nibble
1
2
3
4
5
6
lane 0
(1)
A-0
(1)
A-1
lane 1
A-2
A-3
lane 2
A-4
A-5
lane 3
A-6
A-7
DAC A, sample 0
Table 25. JESD204B Frame Format for LMFSHd = 82380
36
# un bits
4
8
12
16
20
24
# en bits
5
10
15
20
25
30
Nibble
1
2
3
4
5
6
lane 0
i(0)
i(1)
lane 1
i(2)
i(3)
lane 2
i(4)
i(5)
lane 3
i(6)
i(7)
lane 4
q(0)
q(1)
lane 5
q(2)
q(3)
lane 6
q(4)
q(5)
lane 7
q(6)
q(7)
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Table 26. JESD204B Frame Format for LMFSHd = 41121
(1)
(2)
# un bits
4
8
# en bits
5
10
Nibble
1
2
lane 0
A-0[15:8] (1)
lane 1
A-0[7:0] (2)
lane 2
A-1[15:8]
lane 3
A-1[7:0]
DAC A, sample 0, MSB byte
DAC A, sample 0, LSB byte
Table 27. JESD204B Frame Format for LMFSHd = 82121
(1)
(2)
# un bits
4
8
# en bits
5
10
Nibble
1
2
lane RX0
A-0[15:8] (1)
lane RX1
A-0[7:0] (2)
lane RX2
A-1[15:8]
lane RX3
A-1[7:0]
lane RX4
B-0[15:8]
lane RX5
B-0[7:0]
lane RX6
B-1[15:8]
lane RX7
B-1[7:0]
DAC A, sample 0, MSB byte
DAC A, sample 0, LSB byte
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
37
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.3.7 SYNC Interface
The DAC38RF82 (or DAC38RF89) JESD204B interface has two differential SYNC outputs called SYNC0 and
SYNC1 to support one or two links. Alternatively, GPO0 and GPO1 can be used to output SYNC as a singleended CMOS level. Each of the differential or CMOS outputs is enabled by a 2-bit register (fields GPO0_SEL,
GPO1_SEL, SYNC0B_SEL, SYNC1B_SEL in register IO_CONFIG 8.5.2), with bit 0 enabling multi-DUC1 SYNC
and bit 1 enabling multi-DUC2 SYNC. If both are enabled, the SYNC\ signals are OR’ed.
The SYNC signal can be asserted low by the receiver either to make a synchronization request to
initialize/reinitialize the link or to report an error to the transmitter. Synchronization requests must have a
minimum duration of five frames plus nine octets rounded up to the nearest whole number of frames. To report
an error, the SYNC signal is asserted for exactly two frames. The transmitter interprets any negative edge of its
SYNC input as an error and any SYNC assertion lasting four frames or longer as a synchronization request. See
the following sections in the standard for more details.
• 7.6.3 Errors requiring re-initialization
• 7.6.4 Error reporting via SYNC interface
• 8.4 SYNC signal decoding
8.3.8 Single or Dual Link Configuration
The DAC38RF82 (or DAC38RF89) JESD204B interface can be configures with one or two links. The advantage
of using two links, one for each DAC, is that one link can be re-established without affecting the other link and
DAC.
The configuration for each mode of operation are:
1. Dual DAC, dual link
a. Program fields OCTETPATH0_SEL to OCTETPATH7_SEL in multi-DUC paged registers
JESD_CROSSBAR1 (8.5.57) and JESD_CROSSBAR2 (8.5.58) so that each multi-DUC will pick data off
of the appropriate SerDes lane.
b. Appropriate bits in field LANE_ENA in multi-DUC paged register JESD_LN_EN (8.5.45) must be set for
each multi-DUC enable the lanes used.
c. Field ONE_DAC_ONLY in register RESET_CONFIG (8.5.1) should be ‘0’ (default).
2. Dual DAC, single link
a. Program OCTETPATH0_SEL to OCTETPATH7_SEL in multi-DUC paged registers JESD_CROSSBAR1
(8.5.57) and JESD_CROSSBAR2 (8.5.58) so that each multi-DUC will pick data off the appropriate
SerDes lane.
b. Appropriate bits in field LANE_ENA in multi-DUC paged register JESD_LN_EN (8.5.45) must be set for
each multi-DUC enable the lanes used.
c. Set field ONE_LINK_ONLY to ‘1’ to configure TXENABLE output.
3. Single DAC, single link
a. Set Field ONE_DAC_ONLY in register RESET_CONFIG (8.5.1) to ‘1’ to gate clocks to unused multiDUC2 for power savings.
b. ONE_LINK_ONLY bit does not matter in this case.
8.3.9 Multi-Device Synchronization
In many applications, such as multi antenna systems where the various transmit channels information is
correlated, it is required that the latency across the link is deterministic and multiple DAC devices are completely
synchronized such that their outputs are phase aligned. The DAC38RF82 (or DAC38RF89) achieves the
deterministic latency using SYSREF (JESD204B Subclass 1).
SYSREF is generated from the same clock domain as DACCLK. After having resynchronized its local multiframe
clock (LMFC) to SYSREF, the DAC will request a link re-initialization via SYNC interface. Processing of the
signal on the SYSREF input can be enabled and disabled via the SPI interface.
The SYSREF capture circuit and the timing requirements relative to device clock are described in SYSREF
Capture Circuit.
38
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.3.10 SYSREF Capture Circuit
The JESD204B standard for Device Subclass 1 introduces a SYSREF signal that can be used as a global timing
reference to align the phase of the internal local multiframe clock (LMFC) and frame clock across multiple
devices. This allows the system to achieve deterministic latency and align data samples across several data
converters. The SYSREF signal accomplishes this goal by identifying a device clock edge for each chip that can
be used as an alignment reference. In particular, the LMFC and frame clock align to the device clock edge upon
which the SYSREF transition from “0” to “1” is sampled. SYSREF may be periodic, one-shot, or “gapped”
periodic and its period must be a multiple of the LMFC period.
Figure 30. SYSREF Signal Timing
With high-speed device clocks, the phase of the SYSREF signals relative to the device clock must meet the
setup/hold time requirements of each individual device clock. Historically, this has been done by controlling the
board-level routing delay and/or employing commercial clock distribution capable of generating device clocks and
SYSREF signals with programmable delays and with the option of splitting SYSREF into multiple SYSREFS,
each with its own fine-tuned delay. Since the DAC38RF82 (or DAC38RF89) supports device clock frequencies
up to 9 GHz, a SYSREF capture circuit is includes in the DAC38RF82 (or DAC38RF89) that allows a relaxation
in meeting the device clock setup and hold.
The SYSREF capture circuit provides:
• tolerance to manufacturing and environmental variations in SYSREF phase
• immunity to sampling errors due to setup/hold/meta-stability
• information about phase of SYSREF relative to DAC clock inside the data converter
• software compensation for phase misalignment due to PCB design errors
The concepts behind the SYSREF capture scheme are illustrated in Figure 31.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
39
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Figure 31. SYSREF Capture Strategy and Phase Tolerance Windows
To understand Figure 31, to begin with we’ll ignore the SYSREF phase tolerance windows in the lower portion of
the figure and focus on the blue clock waveform at the top of the figure. This waveform represents the device
clock input to a particular DAC chip. The green arrows, labeled “R” and “F”, correspond to the rising and falling
edges of this clock (ignoring for the moment the additional arrows labeled “ER” and "EF”). While previous
devices with lower device clocks captured SYSREF only on the rising edge of the device clock, the new scheme
samples SYSREF on the falling edge as well, which provides more flexibility when optimizing the setup and hold
time of the SYSREF capture path. Moreover, each time a rising SYSREF edge is captured, the chip remembers
the clock phase during which the event occurred, and the system designer can later read back the phase
information to observe the SYSREF timing relative to the device clock at the internal capture point. If SYSREF
transitions close to the rising or falling clock edge sampling points the capture flop setup and hold time may not
be met and the observed phase may be unreliable and subject to meta-stability phenomenon.
To reduce the sensitivity to setup/hold/meta-stability concerns an “early” version of the device clock is generated
within the DAC and additional SYSREF samples are taken at the “early falling” and “early rising” edges of the
clock (labeled “EF” and “ER”, respectively, in Figure 31). The resulting set of four samples is used to narrow
down the timing of the rising SYSREF edge to one of four possible clock phases. If the rising SYSREF transition
takes place between the “EF” and “F” samples, then SYSREF is said to occur in phase θ1. Similarly, if it takes
place between the “F” and “ER” samples, then it is said to occur in phase θ2. If SYSREF transitions between the
“ER” and “R” samples, then it is said to occur in phase θ3. And, finally, if the SYSREF rising edge event happens
between the “R” and “EF” samples, then it is said to occur in phase θ4. As mentioned before, the chip
remembers all observed SYSREF phases and the user can later read them back. Since the delay between
“early” and “on time” versions of the clock is intentionally chosen to be larger than the setup/hold/meta-stability
window, at most one of the four samples can be affected even when the SYSREF transitions right at one of the
four sampling points. Thus, the uncertainty in the observed SYSREF timing is limited to adjacent phases, and
with twice as many sampling phases the resolution of the timing information is improved by a factor of two.
Referring to the lower portion of Figure 31, the user can now see how this information regarding the observed
SYSREF phases is used to devise a reliable SYSREF capture methodology with a high degree of tolerance to
manufacturing and environmental variations in SYSREF phase. Based on the SYSREF phases observed for a
particular DAC chip during system characterization, the system designer can select one of four so-called “phase
tolerance window” options (denoted “’00”, “01”, “10”, and “11”) to maximize immunity to manufacturing and
environmental variations. For example, consider the default phase tolerance window labeled “window=00” in the
figure. If, during characterization, the system designer observes (by reading back the recorded phase
observations) that the rising SYSREF edge nominally occurs in either θ1 or θ2 or both (i.e. θ12) then he would
40
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
program that particular DAC chip to use phase tolerance window “00”. This mapping is indicated in the figure
with the label “θ1|θ12|θ2: window=00”. Having programmed the device to use window “00”, all future SYSREF
events that occur in θ1 or θ2 would trigger the LMFC and frame clock to be aligned using the following rising
clock edge as the alignment reference (as indicated by the red arrow pointing to rising clock edge “R” and
labeled “Window=00/01 alignment edge”).
The full extent of each phase tolerance window is indicated in the figure using “box and whisker” plots. For the
“window=00” example, the “box” portion of the plot indicates that the phase tolerance window is centered on θ12
(to be precise on the boundary between θ1 and θ2) and the “whisker” portion indicates that even if the rising
edge of SYSREF occurs as early as the preceding θ4 or as late as the following θ3 it still results in LMFC and
frame clock alignment to the same rising clock edge indicated by the red arrow labeled “Window=00/01
alignment edge”. When programmed for phase tolerance window “00”, the DAC chip is tolerant to variations in
the SYSREF timing ranging from a rising SYSREF edge that occurs just after one rising edge of clock to just
before the next rising edge of the clock. The qualifying phrases “just after” and “just before” are used here to
indicate that the SYSREF transition must occur far enough away from the rising edges of the clock to avoid
setup/hold violations and prevent the device from concluding that the SYSREF transition has crossed out off the
phase tolerance window when in fact it has not. The tolerance range for window “00” is from rising clock edge to
rising clock edge and is indicated in the figure by the green text labeled “tolerance = R↔R”.
Following the above example, if characterization reveals SYSREF timing centered on θ23 then phase tolerance
window “01” (with tolerance for SYSREF rising edge events from EF to EF) should be chosen. Notice that this
option is tolerant even to rising SYSREF edges that occur after the rising device clock edge (i.e. in θ4) and will
treat them just as if they had occurred in one of the earlier three phases, aligning to the same rising device clock
edge indicated by the red arrow labeled “Window=00/01 Alignment Edge”. This allows the system designer to
tolerate PCB design errors and/or environmental and manufacturing variations – achieving his intended
alignment without having to make physical changes to the board to adjust the SYSREF timing.
Similarly, if characterization indicates that SYSREF timing is centered on θ34 or θ41 then phase tolerance
window “10” or “11” can be selected, resulting in tolerance for “F↔F” or “ER↔ER” SYSREF timing, respectively.
Note, however, that in these two cases the alignment reference edge is by default taken to be the subsequent
rising edge of the device clock. Since this may not be the desired behavior, the DAC38RF82 (or DAC38RF89)
allows the user to program in an optional alignment offset of θ1 if the default offset of 0 does not achieve the
desired alignment. This feature is illustrated in Figure 32 where the user can see that by setting the alignment
offset to -1, phase tolerance windows “10” and “11” can be made to trigger alignment to the earlier rising device
clock edge used by windows “00” and “01”. Alternatively, the window “00” and “01” alignment edge can be
pushed one cycle later by setting their alignment offset to +1.
Figure 32. Optional SYSREF Alignment Offset
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
41
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Several important controls related to SYSREF alignment and capture timing are contained in register
SYSR_CAPTURE (8.5.78). For example, as mentioned before, the device is capable of monitoring the observed
phases of the rising SYSREF edge events; however, in order to avoid unwanted noise coupling from the
SYSREF circuits into the DAC output, the SYSREF monitoring circuits are disabled by default. Field
SYSR_STATUS_ENA enables SYSREF status monitoring. Field SYSR_PHASE_WDW contains the the phase
tolerance window selected for normal operation, which is optimized during characterization. Field
SYSR_ALIGN_DLY contains the control that allows the system designer to optionally offset the SYSREF
alignment event by ±1 device clock cycles. Field SYSR_STATUS_ENA enables the SYSREF capture alignment
accumulation and will generate alarms when enabled. Writing a “1” to field SYSR_ALIGN_SYNC clears the
accumulated SYSREF alignment statistics. The SYSREF alignment block can be bypassed completely by field
SYSREF_BYPASS_ALIGN, in which case SYSREF is latched by the rising edge of DACCLK.
When field SYSR_STATUS_ENA is high the device records the phase associated with each SYSREF event for
use in characterizing the SYSREF capture timing and selecting an appropriate phase tolerance window. The
phase data is available in two forms. First, each of the four phases has a corresponding “sticky” alarm flag
indicating which phases have been observed since the last time the register was cleared. In addition, the device
also accumulates statistics on the relative number of occurrences of each phase spanning multiple SYSREF
events using saturating 8-bit counters. These accumulated real-time SYSREF statistics allow us to account for
time-varying effects during characterization such as potential timing differences between the 1st and Nth edges
in a “gapped” SYSREF pulse train. The counters are fields PHASE1_CNT and PHASE2_CNT in register
SYSREF12_CNT (8.5.10), PHASE3_CNT and PHASE4_CNT in register SYSREF34_CNT (8.5.11), and
ALIGN_TO_R1_CNT and ALIGN_TO_R3_CNT in register SYSREF_ALIGN_R (8.5.9).
The accumulated SYSREF statistics can be cleared by writing ‘1’ to SYSR_ALIGN_SYNC. This sync signal
affects only the SYSREF statistics monitors and does not cause a sync of any other portions of the design.
Before collecting phase statistics, the user must first enable the SYSREF status monitoring logic by setting the
SYSR_STATUS_ENA bit. The user must then generate a repeating SYSREF input before using
SYSR_ALIGN_SYNC to clear the statistic counters. This is necessary to flush invalid data out of the status
pipeline.
The “sticky” alarm flags indicating which of the four phases have been observed since the last
SYSR_ALIGN_SYNC write of ‘1’ are fields ALM_SYSRPHASE1 to ALM_SYSRPHASE4 and are contained in the
ALM_SYSREF_DET register (8.5.6).
42
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.3.11 SerDes Test Modes through Serial Programming
The DAC38RF82 (or DAC38RF89) supports a number of basic pattern generation and verification of SerDes via
the serial interface. Three pseudo random bit stream (PRBS) sequences are available, along with an alternating
0/1 pattern and a 20-bit user-defined sequence. The 27 - 1, 231 - 1 or 223 – 1 sequences implemented can often
be found programmed into standard test equipment, such as a Bit Error Rate Tester (BERT). Pattern generation
and verification selection is via field TESTPATT in register SRDS_CFG1 (8.5.86), as shown in Table 28.
Table 28. SerDes Test Pattern Selection
TESTPATT
EFFECT
000
Test mode disabled.
001
Alternating 0/1 Pattern. An alternating 0/1 pattern with a period of 2 UI.
010
Verify 27 - 1 PRBS. Uses a 7-bit LFSR with feedback polynomial x7 + x6 + 1.
011
Verify 223 - 1 PRBS. Uses an ITU O.150 conformant 23-bit LFSR with feedback polynomial x23 + x18 + 1.
100
Verify 231 - 1 PRBS. Uses an ITU O.150 conformant 31-bit LFSR with feedback polynomial x31 + x28 + 1.
101
User-defined 20-bit pattern. Uses the USR PATT IEEE1500 Tuning instruction field to specify the pattern. The default
value is 0x66666.
11x
Reserved.
Pattern verification compares the output of the serial to parallel converter with an expected pattern. When there
is a mismatch, the TESTFAIL bit is driven high, which can be programmed to come out the ALARM terminal by
setting field DTEST in register DTEST (8.5.76) to “0011”.
8.3.12 SerDes Test Modes through IEEE 1500 Programming
DAC38RF82 (or DAC38RF89) also provide a number of advanced diagnostic capabilities controlled by the IEEE
1500 interface. These are:
• Accumulation of pattern verification errors;
• The ability to map out the width and height of the receive eye, known as Eye Scan;
• Rreal-time monitoring of internal voltages and currents;
The SerDes blocks support the following IEEE1500 instructions:
Table 29. IEEE1500 Instruction for SerDes Receivers
INSTRUCTION
OPCODE
DESCRIPTION
ws_bypass
0x00
Bypass. Selects a 1-bit bypass data register. Use when accessing other macros on the same
IEEE1500 scan chain.
ws_cfg
0x35
Configuration. Write protection options for other instructions.
ws_core
0x30
Core. Fields also accessible via dedicated core-side ports.
ws_tuning
0x31
Tuning. Fields for fine tuning macro performance.
ws_debug
0x32
Debug. Fields for advanced control, manufacturing test, silicon characterization and debug.
ws_unshadowed
0x34
Unshadowed. Fields for silicon characterization.
ws_char
0x33
Char. Fields used for eye scan.
The data for each SerDes instruction is formed by chaining together sub-components called head, body (receiver
or transmitter) and tail. DAC38RF82 (or DAC38RF89) uses two SerDes receiver blocks R0 and R1, each of
which contains 4 receive lanes (channels), the data for each IEEE1500 instruction is formed by chaining {head,
receive lane 0, receive lane 1, receive lane 2, receive lane 3, tail}. A description of bits in head, body and tail for
each instruction is given as follows:
NOTE
All multi-bit signals in each chain are packed with bits reversed e.g. mpy[7:0] in ws_core
head subchain is packed as {retime, enpll, mpy[0:7], vrange, lb[0:1]}. All DATA REGISTER
READS from SerDes Block R0 should read 1 bit more than the desired number of bits and
discard the first bit received on TDO e.g., to read 40-bit data from R0 block, 41 bits should
be read off from TDO and the first bit received should be discarded. Similarly, any data
written to SerDes Block R0 Data Registers should be prefixed with an extra 0.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
43
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Table 30. ws_cfg Chain
FIELD
DESCRIPTION
HEAD (STARTING FROM THE MSB OF CHAIN)
RETIME
No function.
CORE_WE
Core chain write enable.
RECEIVER (FOR EACH LANE 0, 1, 2, 3)
CORE_WE
Core chain write enable.
TUNING_WE
Tuning chain write enable.
DEBUG_WE
Reserved.
CHAR_WE
Char chain write enable.
UNSHADOWED_WE
Reserved.
TAIL (ENDING WITH THE LSB OF CHAIN)
CORE_WE
Core chain write enable.
TUNING_WE
Tuning chain write enable.
DEBUG_WE
Reserved.
RETIME
No function.
CHAIN LENGTH = 26 BITS
44
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Table 31. ws_core Chain
FIELD
DESCRIPTION
HEAD (STARTING FROM THE MSB OF CHAIN)
RETIME
No function.
ENPLL
PLL enable.
MPY[7:0]
PLL multiply.
VRANGE
VCO range.
ENDIVCLK
Enable DIVCLK output
LB[1:0]
Loop bandwidth
RECEIVER (FOR EACH LANE 0,1,2,3)
ENRX
Receiver enable.
SLEEPRX
Receiver sleep mode.
BUSWIDTH[2:0]
Bus width.
RATE[1:0]
Operating rate.
INVPAIR
Invert polarity.
TERM[2:0]
Termination.
ALIGN[1:0]
Symbol alignment.
LOS[2:0]
Loss of signal enable.
CDR[2:0]
Clock/data recovery.
EQ[2:0]
Equalizer.
EQHLD
Equalizer hold.
ENOC
Offset compensation.
LOOPBACK[1:0]
Loopback.
BSINRXP
Boundary scan initialization.
BSINRXN
Boundary scan initialization.
RESERVED
Reserved.
Testpatt[2:0]
Test pattern selection.
TESTFAIL
Test failure (real time).
LOSTDTCT
Loss of signal detected (real time).
BSRXP
Boundary scan data.
BSRXN
Boundary scan data.
OCIP
Offset compensation in progress.
EQOVER
Receiver signal over equalized.
EQUNDER
Receiver signal under equalized.
LOSTDTCT
Loss of signal detected (sticky).
SYNC
Re-alignment done, or aligned comma output
(sticky).
RETIME
No function.
TAIL (ENDING WITH THE LSB CHAIN)
CLKBYP[1:0]
Clock bypass.
SLEEPPLL
PLL sleep mode.
RESERVED
Reserved.
LOCK
PLL lock (real time).
BSINITCLK
Boundary scan initialization clock.
ENBSTX
Enable TX boundary scan.
ENBSRX
Enable RX boundary scan.
ENBSPT
RX pulse boundary scan.
RESERVED
Reserved.
NEARLOCK
PLL near to lock.
UNLOCK
PLL lock (sticky).
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
45
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Table 31. ws_core Chain (continued)
FIELD
DESCRIPTION
CFG OVR
Configuration over-ride.
RETIME
No function.
CHAIN LENGTH = 196 BITS
Table 32. ws_tuning Chain
FIELD
DESCRIPTION
HEAD (STARTING FROM THE MSB OF CHAIN)
RETIME
No function.
RECEIVER (FOR EACH LANE 0,1,2,3)
PATTERRTHR[2:0]
Resync error threshold.
PATT TIMER
PRBS timer.
RXDSEL[3:0]
Status select.
ENCOR
Enable clear-on-read for error counter.
EQZERO[4:0]
EQZ OVRi Equalizer zero.
EQZ OVR
Equalizer zero over-ride.
EQLEVEL[15:0]
EQ OVRi Equalizer gain observe or set.
EQ OVR
Equalizer over-ride.
EQBOOST[1:0]
Equalizer gain boost.
RXASEL[2:0]
Selects amux output.
TAIL (ENDING WITH THE LSB CHAIN)
ASEL[3:0]
Selects amux output.
USR PATT[19:0]
User-defined test pattern.
RETIME
No function.
CHAIN LENGTH = 174 BITS
Table 33. ws_char Chain
FIELD
DESCRIPTION
HEAD (STARTING FROM THE MSB OF CHAIN)
RETIME
No function.
RECEIVER (FOR EACH LANE 0,1,2,3)
TESTFAIL
Test failure (sticky).
ECOUNT[11:0]
Error counter.
ESWORD[7:0]
Eye scan word masking.
ES[3:0]
Eye scan.
ESPO[6:0]
Eye scan phase offset.
ES BIT SELECT[4:0]
Eye scan compare bit select.
ESVO[5:0]
Eye scan voltage offset.
ESVO OVR
Eye scan voltage offset override.
ESLEN[1:0]
Eye scan run length.
ESRUN
Eye scan run.
ESDONE
Eye scan done.
TAIL (ENDING WITH THE LSB CHAIN)
RETIME
No function.
CHAIN LENGTH = 194 BITS
46
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.3.13 Error Counter
All receive channels include a 12-bit counter for accumulating pattern verification errors. This counter is
accessible via the ECOUNT IEEE1500 Char field. It is an essential part of the eye scan capability (see the Eye
Scan section).
The counter increments once for every cycle that the TESTFAIL bit is detected. The counter does not increment
when at its maximum value (i.e., all 1s). When an IEEE1500 capture is performed, the count value is loaded into
the ECOUNT scan elements (so that it can be scanned out), and the counter is then reset, provided NCOR is set
high.
ECOUNT can be used to get a measure of the bit error rate. However, as the error rate increases, it becomes
less accurate due to limitations of the pattern verification capabilities. Specifically, the pattern verifier checks
multiple bits in parallel (as determined by the Rx bus width), and it is not possible to distinguish between 1 or
more errors.
8.3.14 Eye Scan
All receive channels provide features which facilitate mapping the received data eye or extracting a symbol
response. A number of fields accessible via the IEEE1500 Char scan chain allow the required low level data to
be gathered. The process of transforming this data into a map of the eye or a symbol response must then be
performed externally, typically in software.
The basic principle used is as follows:
• Enable dedicated eye scan input samplers, and generate an error when the value sampled differs from the
normal data sample;
• Apply a voltage offset to the dedicated eye scan input samplers, to effectively reduce their sensitivity;
• Apply a phase offset to adjust the point in the eye that the dedicated eye scan data samples are taken;
• Reset the error counter to remove any false errors accumulated as a result of the voltage or phase offset
adjustments;
• Run in this state for a period of time, periodically checking to see if any errors have occurred;
• Change voltage and/or phase offset, and repeat.
Alternatively, the algorithm can be configured to optimize the voltage offset at a specified phase offset, over a
specified time interval.
Eye scan can be used in both synchronous and asynchronous systems, while receiving normal data traffic. The
IEEE1500 Char fields used to directly control eye scan and symbol response extraction are ES, ESWORD, ES
BIT SELECT, ESLEN, ESPO, ESVO, ESVO OVR, ESRUN and ESDONE. Eye scan errors are accumulated in
ECOUNT.
The required eyescan mode is selected via the ES field, as shown in Table 34. When enabled, only data from
the bit position within the 20-bit word specified via ES BIT SELECT is analyzed. In other words, only eye scan
errors associated with data output at this bit position will accumulate in ECOUNT. The maximum legal ES BIT
SELECT is 10011.
Table 34. Eye Scan Mode Selection
ES[3:0]
EFFECT
0000
Disabled. Eye scan is disabled.
0x01
Compare. Counts mismatches between the normal sample and the eye scan sample if ES[2] = 0, and matches
otherwise.
0x10
Compare zeros. As ES = 0x01, but only analyses zeros, and ignores ones.
0x11
Compare ones. As ES = 0x01, but only analyses ones, and ignores zeroes.
0100
Count ones. Increments ECOUNT when the eye scan sample is a 1.
1x00
Average. Adjusts ESVO to the average eye opening over the time interval specified by ESLEN. Analyses zeroes when
ES[2] = 0, and ones when ES[2]= 1.
1001
1110
Outer. Adjusts ESVO to the outer eye opening (i.e. lowest voltage zero, highest voltage 1) over the time interval
specified by ESLEN. 1001 analyses zeroes, 1110 analyses ones.
1010
1101
Inner. Adjusts ESVO to the inner eye opening (i.e. highest voltage zero, lowest voltage 1) over the time interval
specified by ESLEN. 1010 analyses zeroes, 1101 analyses ones.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
47
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Table 34. Eye Scan Mode Selection (continued)
ES[3:0]
EFFECT
1x11
Timed Compare. As ES = 001x, but analyses over the time interval specified by ESLEN. Analyses zeroes when ES[2] =
0, and ones when ES[2] = 1.
When ES[3] = 0, the selected analysis runs continuously. However, when ES[3] = 1, only the number of qualified
samples specified by ESLed, as shown in Table 35. In this case, analysis is started by writing a 1 to ESRUN (it is
not necessary to set it back to 0). When analysis completes, ESDONE is set to 1.
Table 35. Eye Scan Run Length
ESLen
NUMBER OF SAMPLES ANALYZED
00
127
01
1023
10
8095
11
65535
When ESVO OVR = 1, the ESVO field determines the amount of offset voltage that is applied to the eye scan
data samplers associated with rxpi and rxni. The amount of offset is variable between 0 and 300 mV in
increments of ~10 mV, as shown Table 36. When ES[3] = 1, ESVO OVR must be 0 to allow the optimized
voltage offset to be read back via ESVO.
Table 36. Eye Scan Voltage Offset
ESVO
OFFSET (mV)
100000
-310
…
…
111110
-20
111111
-10
000000
0
000001
10
000010
20
…
…
011111
300
The phase position of the samplers associated with rxpi and rxni, is controlled to a precision of 1/32UI. When ES
is not 00, the phase position can be adjusted forwards or backwards by more than one UI using the ESPO field,
as shown in Table 37. In normal use, the range should be limited to ±0.5 UI (+15 to –16 phase steps).
Table 37. Eye Scan Phase Offset
48
ESPO
OFFSET (1/32 UI)
011111
+63
…
…
000001
+1
000000
0
111111
-1
…
…
100000
-64
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.3.15 JESD204B Pattern Test
The DAC38RF82 (or DAC38RF89) supports the following test patterns for JESD204B:
• Link layer test pattern by setting field JESD_TEST_SEQ in register JESD_LN_EN (8.5.45) and monitoring the
lane alarms (1 = fail, 0 = pass)
– Verify repeating /D.21.5/ high frequency pattern for random jitter (RJ)
– Verify repeating /K.28.5/ mixed frequency pattern for deterministic jitter (DJ)
– Verify repeating initial lane alignment (ILA) sequence
• RPAT, JSPAT or JTSPAT pattern can be verified using errors counter of 8b/10b errors produced over an
amount of time to get an estimate of BER.
• Transport layer test pattern: implements a short transport layer pattern check based on F = 1, 2, 4 or 8. The
short test pattern has a duration of one frame period and is repeated continuously for the duration of the test.
Each sample has a unique value that can be identified with the position of the sample in the user data format.
The sample values are such that correct sample values will never be decoded at the receiver if there is a
mismatch between the mapping formats being used at the transmitter and receiver devices. This can
generally be accomplished by ensuring there are no repeating sub patterns within the stream of samples
being transmitted. Refer to the JESD204B standard section 5.1.6 for more details.
The DAC38RF82 (or DAC38RF89) expects the test samples, in a frame, transmitted by an logic device as per
Table 38:
Table 38. Short Test Patterns
JESD Mode
i0
q0
i1
q1
82121
7CB8, F431
6DA9, E520
n/a
n/a
42111
7CB8
F431
n/a
n/a
22210
7CB8
F431
n/a
n/a
12410
7CB8
F431
n/a
n/a
44210
7CB8
F431
6DA9
E520
24410
7CB8
F431
6DA9
E520
41121
7CB8, F431
n/a
n/a
n/a
81180
7C00, B800, F400, 3100, 6D00,
A900, E500, 2000
n/a
n/a
n/a
24310
7CB0
F430
6DA0
E520
41380
7CB0, F430, 6DA0, E520, F870,
E960, DA50, CB40
n/a
n/a
n/a
The short test pattern has duration of one frame period and is repeated continuously for the duration of the test.
Each sample has a unique value that can be identified with the position of the sample in the user data format.
The sample values are such that correct sample values will never be decoded at the receiver if there is a
mismatch between the mapping formats being used at the transmitter and receiver devices. This can generally
be accomplished by ensuring there are no repeating sub patterns within the stream of samples being transmitted.
Following are the steps required to execute the short test functionality in DAC38RF82 (or DAC38RF89).
1. Configure other registers, make sure clocks are up and running.
2. Start driving short test patterns
3. Clear short test alarm by writing ‘0’ to field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP
(8.5.67). This is a paged register, one for each Multi-DUC.
4. Enable short test by writing a ‘1’ to field SHORTTEST_ENA in register MULTIDUC_CFG2 (8.5.14).
5. Read the short test alarm from field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP (8.5.67).
This is a paged register, one for each Multi-DUC
If the alarm read from the register is high, the short test has detected an error.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
49
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.3.16 Wideband DUC (wide-DUC)
Each DAC output in the DAC38RF82 ((or DAC38RF89)) can be supported by a wide band digital up-converter
(DUC), which is called a wide-DUC. Figure 33 shows the implementation and signal processing features of the
wide-DUC which is only available in the 2-TX modes (Table 9). For complex inputs, the in-phase (or I-channel) is
path AB of DAC A and the phase of the NCO in this path (7.5.19) must be set to 0 degrees. Similarly, the
quadrature phase (or Q-channel) is path AB of DAC B and the phase of the NCO in this path (7.5.19) must be
set to 90 degrees. The NCO frequency in both I and Q paths (7.5.20) must be set to the same value. The SPI
interface registers for the wide-DUC are addressed through paging, with page 1 supporting the I-channel and
page 2 supporting Q-channel configuration of the wide-DUC. Register PAGE_SET (8.5.8) is used to set the
pages. Both pages can be selected at the same time to program both channels of wide-DUC simultaneously.
The output of I and Q channels are added together using the output summation block (Figure 33). Bit 0 and Bit 2
of the register field OUTSUM_SEL must be set to for this to be accomplished.
PAP
I
JESD204B Interface
12/16
Multiband
summation
x
sin(x)
PAP
Gain
CMIX control
(±n x Fs/4)
Delay
CMIX control
(±n x Fs/4)
Q
PAP
Path AB
(DAC B)
xN
xN
12/16
Complex Mixer
(FMIX or CMIX)
Path AB
(DAC A)
Complex Mixer
(FMIX or CMIX)
48-bit
NCO1
cos
Input
Mux
x
sin(x)
PAP
Gain
sin
48-bit
NCO2
Copyright © 2016, Texas Instruments Incorporated
Figure 33. DAC38RF82 Wide-DUC Signal Processing Block Diagram
8.3.17 Interpolation Block
The DAC38RF82 (or DAC38RF89) provides the optional interpolation of 2x in 12-bit input mode and 2x or 4x in
16-bit input mode. In addition, 1x interpolation can be used in 8, 12 or 16-bit input modes to pass the data
directly to the DAC output. The SPI interface registers for the multi-DUCs are addressed through paging, with
page 0 supporting the I channel and page 1 supporting the Q channel. Register PAGE_SET (8.4.8) is used to set
the pages. Both pages can be selected at the same time to program both multi-DUCs simultaneously with the
same settings.
8.3.17.1 Multi-DUC input
Each interpolation block accepts data from up to 8 SerDes lanes. A crossbar switch allows any SerDes lane to
be mapped to any other SerDes lane. The crossbar switch is controlled by fields OCTETPATHx_SEL (x = [0..7])
in Registers JESD_CROSSBAR1 (8.5.57) and JESD_CROSSBAR2 (8.5.58).
50
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.3.17.2 Interpolation Filters
The digital upconverter first increases the sample rate of the IQ signal from the input sample rate to the final
DAC sample rate through a series of interpolation filters. Different sets of filters are used to achieve different
rates, as shown in Table 39. The interpolation rate is selected by field INTERP in register MULTIDUC_CFG1
(8.5.13).
Table 39. FIR filters Used for Different Interpolation Rates
FILTERS USED
Interpolation Rate
FIR0 (2x)
2
x
4
x
FIR1 (2x)
x
20
20
0
0
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
The FIR filter coefficients are shown in Table 40 The FIR filters are design with a passband BW of 0.4 x fINPUT, a
stopband attenuation of 90 dBc and ripple of < 0.001 dB. The composite frequency response for each
interpolation factor are shown in Figure 34to Figure 41.
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
0.075
0.15
0.225
0.3
f/Fdac
0.375
0.45
0
Figure 34. Composite Magnitude Response for 6x
Interpolation
0.15
20
20
0
0
-20
-20
-40
-40
-60
-80
-100
0.375
0.45
D002_8x
-60
-80
-100
-120
-120
-140
-140
-160
0.225
0.3
f/Fdac
Figure 35. Composite Magnitude Response for 8x
Interpolation
Magnitude (dB)
Magnitude (dB)
0.075
D001
-160
0
0.075
0.15
0.225
0.3
f/Fdac
0.375
0.45
0
0.075
D003
Figure 36. Composite Magnitude Response for 10x
Interpolation
0.15
0.225
0.3
f/Fdac
0.375
0.45
D004
Figure 37. Composite Magnitude Response for 12x
Interpolation
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
51
DAC38RF82, DAC38RF89
www.ti.com
20
20
0
0
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
0.075
0.15
0.225
0.3
f/Fdac
0.375
0.45
0
Figure 38. Composite Magnitude Response for 16x
Interpolation
0.15
0.225
0.3
f/Fdac
0.375
0.45
D006
Figure 39. Composite Magnitude Response for 18x
Interpolation
20
20
0
0
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
0.075
D005
-60
-80
-100
-60
-80
-100
-120
-120
-140
-140
-160
-160
0
0.075
0.15
0.225
0.3
f/Fdac
0.375
0.45
0
0.075
0.15
D007
Figure 40. Composite Magnitude Response for 20x
Interpolation
0.225
0.3
f/Fdac
0.375
0.45
D001
Figure 41. Composite Magnitude Response for 24x
Interpolation
Table 40. FIR Filter Coefficients
52
tap
FIR0
FIR1
LPFIR0_5X
FIR2
LPFIR0_3X
FIR3
LPFIR1_3X
1
6
-12
-6
29
-14
3
25
1
2
0
0
-22
0
-61
0
88
-4
3
-19
84
-51
-214
-125
-25
22
13
4
0
0
-89
0
-95
0
-576
-50
5
47
-336
-117
1209
181
150
-1764
592
6
0
0
-106
2048
681
256
-2263
-50
7
-100
1006
-18
1209
972
150
491
13
8
0
0
171
0
347
0
8139
-4
9
192
-2691
449
-214
-1475
-25
18625
1
10
0
0
745
0
-3519
0
26365
11
-342
10141
930
29
-3528
3
26365
12
0
16384
841
707
18625
13
572
10141
338
9337
8139
14
0
0
-618
19445
491
15
-914
-2691
-1892
26299
-2263
16
0
0
-3147
26299
-1764
Submit Documentation Feedback
INVSINC
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Table 40. FIR Filter Coefficients (continued)
tap
FIR0
FIR1
LPFIR0_5X
17
1409
1006
-3872
FIR2
LPFIR0_3X
19445
FIR3
LPFIR1_3X
-576
18
0
0
-3500
9337
22
19
-2119
-336
-1564
707
88
20
0
0
2121
-3528
25
21
3152
84
7336
-3519
22
0
0
13430
-1475
23
-4729
-12
19426
347
24
0
24231
972
25
7420
26904
681
26
0
26904
181
27
-13334
24231
-95
28
0
19426
-125
29
41527
13430
-61
30
65536
7336
-14
31
41527
2121
32
0
-1564
33
-13334
-3500
34
0
-3872
35
7420
-3147
36
0
-1892
37
-4729
-618
38
0
338
39
3152
841
40
0
930
41
-2119
745
42
0
449
43
1409
171
44
0
-18
45
-914
-106
46
0
-117
47
572
-89
48
0
-51
49
-342
-22
50
0
-6
51
192
52
0
53
-100
54
0
55
47
56
0
57
-19
58
0
59
6
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
INVSINC
Submit Documentation Feedback
53
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.3.17.3 JESD204B Modes, Interpolation and Clock phase Programming
Table 41 lists the register field values required for each JESD204B mode interpolation mode and clock phase.
The register field addresses are listed in Table 42.
Table 41. Register Programming for JESD and Interpolation Mode
Mode
L-M-F-S-Hd
1 TX/2TX
Register Field Programming
Interp
82121/NA
42111/84111
22210/44210
12410/24410
44210/88210
24410/48410
81180/NA
41380/82380
41121/ 82121
24310/48310
CLOCK
PHASES
(1-0)
INTERP
(4-0)
CLKJESD
_DIV
(3-0)
CLKJESD
_OUT_DI
V
(3-0)
6
11
00011
0110
0011
8
11
00100
0111
0100
12
11
00110
1010
0110
16
11
01000
1011
0111
6
10
00011
0010
0011
8
11
00100
0011
0100
10
11
00101
0101
0101
12
11
00110
0110
0110
16
11
01000
0111
0111
18
11
01001
1001
1000
24
11
01100
1010
1010
8
01
00100
0001
0100
12
10
00110
0010
0110
16
11
01000
0011
0111
18
11
01001
0100
1000
20
11
01010
0101
1001
24
11
01100
0110
1010
16
01
01000
0001
0111
24
10
01100
0010
1010
8
01
00100
0001
0100
12
10
00110
0010
0110
16
11
01000
0011
0111
24
11
01100
0110
1010
16
01
01000
0001
0111
24
10
01100
0010
1010
1
11
00000
0011
0001
1
00
00000
1100
0000
2
00
00001
1101
0001
1
01
00000
0000
0000
2
01
000001
0001
0001
4
11
00010
0011
0010
24
11
01100
0011
1010
L_M1
(4-0)
F_M1
(7-0)
M_M1
(7-0)
S_M1
(4-0)
HD
N_M1/N’_
M1
(4-0)
00111
0x00
0x01
00001
1
01111
00011
0x00
0x01
00000
1
01111
00001
0x01
0x01
00000
0
01111
00000
0x03
0x01
00000
0
01111
00011
0x01
0x03
00000
0
01111
00001
0x03
0x03
00000
0
01111
00111
0x00
0x00
00111
0
00111
00011
0x02
0x00
00111
0
01011
00011
0x00
0x00
00001
1
01111
00001
0x02
0x03
00000
0
01011
Table 42. Register Field Addresses for JESD204B Mode, Interpolation and Clock Phase Programming
Register Field Name
Register
Register Address
Bit(s)
Hyperlink
INTERP
MULTIDUC_CFG1
0x0A
12-8
8.5.13
CLKJESD_DIV
SerDes_CLK
0x25
L_M1
JESD_K_L
0x4C
4-0
8.5.47
F_M1
JESD_RBD_F
0x4B
7-0
8.5.46
JESD_M_S
0x4D
CLKJESD_OUT_DIV
M_M1
S_M1
54
15-12
Submit Documentation Feedback
11-8
15-8
4-0
8.5.28
8.5.48
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Table 42. Register Field Addresses for JESD204B Mode, Interpolation and Clock Phase
Programming (continued)
Register Field Name
Register
Register Address
Bit(s)
HD
Hyperlink
6
N_M1
JESD_N_HD_SCR
0x4E
4-0
N_M1’ (NPRIME_M1)
8.5.49
12-8
JESD_PHASE_MODE
JESD_LN_EN
0x4A
1-0
8.5.45
All registers are paged!
8.3.17.4 Digital Quadrature Modulator
Each DUC in the DAC38RF8x has digital quadrature modulator (DQM) blocks with independent Numerically
Controlled Oscillators (NCO) that converts the complex input signal to a real signal with flexible frequency
placement between 0 and fDAC/2. The NCOs are enabled by fields NCOAB_ENA and NCOCD_ENA in register
MULTIDUC_CFG2 (8.5.14). The NCOs have 48-bit frequency registers (FREQ_NCOAB (8.5.25) and
FREQ_NCOCD (8.5.26)) and 16-bit phase registers (PHASE_NCOAB (8.5.23) and PHASE_NCOCD (8.5.24))
that generate the sine and cosine terms for the complex mixing. The NCO block diagram is shown in Figure 42.
48
16
48
Frequency
Register
Accumulator
48
48
16
16
sin
Look Up
Table
16
CLK RESET
cos
16
FDAC
NCO SYNC
via
syncsel_NCO(3:0)
Phase
Register
Figure 42. NCO Block Diagram
Synchronization of the NCOs occurs by resetting the NCO accumulators to zero. The synchronization source is
selected by fields SYNCSEL_NCOAB and SYNCSEL_NCOCD in register SYNCSEL1 (8.5.29). The frequency
word in the FREQ_NCOAB and FREQ_NCOCD registers are added to the accumulators every clock cycle, fDAC.
The frequency and phase offset of the NCOs are:
fNCOAB or CD
/ AB or CD
FREQ _ NCOAB or CD u fDAC
248
2Πu
(1)
PHASE _ NCOAB or CD
216
(2)
Treating the complex channels as complex vectors of the form I + j Q, the output of the DQM is:
Output AB
^IINPUTAB u cos
2ŒINCOABW
/AB
4INPUTAB u VLQ 2ŒINCOABW
OutputCD
^IINPUTCD u cos
2ŒINCOCDW
/CD
4INPUTCD u VLQ 2ŒINCOCDW
/AB
` u 2 MIXERAB _ GAIN
/CD ` u 2
1
(3)
MIXERCD _ GAIN 1
(4)
Where t is the time since the last resetting of the NCO accumulator and the fields MIXERAB_GAIN and
MIXERCD_GAIN in register MULTIDUC_CFG2 (8.5.13) are either 0 or 1.
The maximum output amplitude of the DQM occurs if IIN(t) and QIN(t) are simultaneously full scale amplitude and
the sine and cosine arguments are equal to an integer multiple of π/4.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
55
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
With MIXERAB_GAIN or MIXERCD_GAIN = 0, the gain through the DQM is sqrt(2)/2 or -3 dB. This loss in signal
power is in most cases undesirable, and it is recommended that the gain function be used to increase the signal
by 3 dB to compensate. With MIXERAB_GAIN or MIXERCD_GAIN = 1, the gain through the DQM is sqrt(2) or
+3 dB, which can cause clipping of the signal if IIN(t) and QIN(t) are simultaneously near full scale amplitude and
should therefore be used with caution.
8.3.17.5 Low Power Coarse Resolution Mixing Modes
In addition to the NCO the DAC38RFxx also has a coarse mixer block capable of shifting the input signal
spectrum by the fixed mixing frequencies ±N x fDAC/8. Using the coarse mixer instead of the full mixers will result
in lower power consumption.
Treating the two complex channels as complex vectors of the form I(t) + j Q(t), the outputs of the coarse mixer is
equivalent to:
Output AB
IINPUTAB u cos 2ŒICMIX _ ABW
4INPUTAB u VLQ 2ŒICMIX _ ABW
(5)
OutputCD
IINPUTCD u cos 2ŒICMIX _ CDW
4INPUTCD u VLQ 2ŒICMIX _ CDW
(6)
Where fCMIX_AB and fCMIX_CD and the fixed mixing frequency selected by fields CMIX_AB or CMIX_CD in register
CMIX (8.5.21). The coarse mixer blocks are disabled by setting CMIX_AB and CMIX_CD to 0x0.
The NCO and coarse mixers can be enabled simultaneously, although this is not useful in most cases as the full
frequency range can be covered by the NCO.
8.3.17.6 Inverse Sinc Filter
The DAC38RF82 (or DAC38RF89) has a 9-tap inverse Sinc filter (INVSINC) that runs at the DAC update rate
(fDAC) that can be used to flatten the frequency response of the sample-and-hold output. The DAC sample-andhold output sets the output current and holds it constant for one DAC clock cycle until the next sample, resulting
in the well known sin(x)/x or Sinc(x) frequency response (Figure 43, red line). The inverse sinc filter response
(Figure 43, blue line) has the opposite frequency response from 0 to 0.4 x fDAC, resulting in the combined
response (Figure 43, green line). Between 0 to 0.4 x fDAC, the inverse sinc filter compensates the sample-andhold roll-off with less than 0.03 dB error.
The inverse sinc filter has a gain > 1 at all frequencies. Therefore, the signal input to INVSINC must be reduced
from full scale to prevent saturation in the filter. The amount of back-off required depends on the signal
frequency, and is set such that at the signal frequencies the combination of the input signal and filter response is
less than 1 (0 dB). For example, if the signal input to INVSINC is at 0.25 x fDAC, the response of INVSINC is 0.9
dB, and the signal must be backed off from full scale by 0.9 dB to avoid saturation. The advantage of INVSINC
having a positive gain at all frequencies is that the user is then able to optimize the back-off of the signal based
on its frequency.
The inverse sinc filters are enabled by field ISFIR_ENA in register MULTIDUC_CFG1 (8.5.13).
4
3
FIR4
Magnitude (dB)
2
1
Corrected
0
–1
–2
sin(x)/x
–3
–4
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
f/fDAC
G056
Figure 43. Composite Magnitude Spectrum for INVSINC
56
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.3.18 PA Protection Block
The DAC38RFxx incorporates an optional power amplifier protection (PAP) block to monitor when the input
signal is two large, for example when an interface error occurs, and reduces the output signal power of the DAC.
The PAP block achieves the functionality of reducing the input signal that crosses the threshold through three
main sub-blocks. These are PAP trigger generation block, PAP gain state machine and GAIN block.
The PAP block keeps track of the input signal power by maintaining a sliding window accumulation of last N
samples. N is selectable to be 32, 64 or 128 based on the setting (Table 43) of fields PAPAB_SEL_DLY in
register PAP_CFG_AB (8.5.35) and PAPCD_SEL_DLY in register PAP_CFG_CD (8.5.36). The average
amplitude of input signal is computed by dividing accumulated value by the number of samples in the delay-line
(N). The result is then compared against the threshold in fields PAPAB_THRESH in register PAP_CFG_AB
(8.5.35) and PAPCD_THRESH in register PAP_CFG_CD (8.5.36). If the threshold is violated, gain state machine
is triggered which generated gain value to ramp down the DAC output signal amplitude. After the input signal
returns to normal value, the state machine ramps up the DAC output signal amplitude.
Table 43. PAP Delay Line Selection
pap_sel_dly[1:0]
# of samples averaged
00
32
01
64
10
128
11
Reserved
The generation of the PAP trigger as explained as follows:
• The I and Q samples are treated separately – either can trigger attenuation
• In dual DUC modes, each IQ pair is treated separately and has a separate gain block
• 8 samples at the input are put through an absolute value circuit (all 2’s complement)
• Next these values are vector summed to get a 12 bit result
• Then 12 bit result is placed into the delay line and summed into the accumulator
• The accumulator is also subtracting out the delayed 12 bit word corresponding to N = 32, N = 64 or N = 128
• Finally the accumulator output is divided down by N and rounded to 13 bits. These 13 bits are compared to
the threshold in the SPI registers. A pap_trig occurs if the threshold is exceeded.
The PAP gain state machine generates the pap gain value to be applied on the output stream to reduce the
output signal amplitude. The state machine below is used to control the attenuation of the DAC output and the
gaining up of the signal again once the trigger is released.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
57
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
pap_trig=0
pap_gain=1
www.ti.com
Normal
pap_trig=1
pap_trig=1
Attenuate
Gain
wait_cnt_load_r=0
pap_trig=0
wait_cnt_load_r=1
Wait
pap_trig=1
Copyright © 2017, Texas Instruments Incorporated
Figure 44. PAP Gain State Machine
The normal operating condition for the PAP block is the NORMAL state in Figure 44. However, when the PAP
block detects an error condition it sets the pap_trig signal to ‘1’ causing a state transition from NORMAL
operation to the ATTENUATE state.
In the ATTENUTATE state the data path gain is scaled from 1.0 down to 0.0 by a programmable step amount set
by fields PAPAB_GAIN_STEP in register PAP_GAIN_AB (8.5.31) and PAPCD_GAIN_STEP in register
PAP_GAIN_CD (8.5.33). This value is always positive with the decimal place located between the MSB and
MSB-1. Unity is equal to “1000000000”. Each clock cycle (16 samples) the PAP_GAIN is stepped down by
PAPAB_GAIN_STEP and PAPCD_GAIN_STEP until the gain is 0.
After PAP_GAIN is 0, the state machine moves on to the WAIT state. Here a programmable counter counts clock
cycles to allow the condition for the pap_trig to be fixed. Fields PAPAB_WAIT in register PAP_WAIT_AB (8.5.32)
and PAPCD_WAIT in register PAP_WAIT_CD (8.5.34) are used to select the number of clock cycles (samples =
16 x PAPAB_WAIT or 16 x PAPCD_WAIT) to wait before moving to the next state. Once the WAIT counter
equals zero and pap_trig=’0’, the state machine moves on to the GAIN state. If the WAIT equals 0 but pap_trig
still equals ‘1’ then the state machine stays in the WAIT state until pap_trig =’0’.
8.3.19 Gain Block
The GAIN block also has additional output gain control through fields GAINAB in register GAINAB (8.5.39) and
GAINCD in register GAINCD (8.5.40). Similar to PAP_GAIN value, the output gain is always positive with unity
when GAINAB or GAINCD = ”010000000000”.
To reduce the power, the gain block clock has been gated whenever the pap is disabled and GAINAB or
GAINCD is set to unity.
8.3.20 Output Summation
The OUTSUM block allows addition of samples from each DUC in the multi-DUC. It is also possible to add the
output samples from the adjacent multi-DUC. Field OUTSUM_SEL in register OUTSUM (8.5.22) controls the
summation for each multi-DUC. The functionality of the block can be represented by the following equation:
58
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
OUTSUMoutput
SAME AB
SAMECD
ADJ AB
ADJCD
(7)
In order to avoid overflow, rounding operation is performed after the addition to reduce the word size back to 16bits. Exact number of bits rounded depends on the number of channels added. Table 44 shows the description of
round after the summation.
Table 44. OUTSUM Scaling and Rounding
# OF CHANNELS ADDED
# OF BITS ROUNDED
0
0, Use bits[15:0] from the result
1
Use bits[16:1] from the result and bit[0] used for rounding
2
Use bits[17:2] from the result and bits[1:0] used for rounding
3
Use bits[18:3] from the result and bit[2:0 used for rounding
4
Use bits[19:4] from the result and bit[3:0] used for rounding
8.3.21 Output Delay
The signal following output summation can be programmably delayed by 0-15 DACCLK cycles through field
OUTPUT_DELAY in register OUTSUM (8.5.20). The block takes 16 sample words (vec16) from both the A and B
paths and shifts the them to 32 sample long delay line.
8.3.22 Polarity Inversion
The signal following the output delay can be inverted by a 2’s complement conversion allowing the + and - DAC
outputs to be swapped by asserting field DAC_COMPLEMENT in register MULTIDUC_CFG1 (8.5.13).
8.3.23 Temperature Sensor
The DAC38RF82 (or DAC38RF89) incorporates a temperature sensor block which monitors the die temperature
by measuring the voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a
successive approximation (SAR) analog to digital conversion process. The result is scaled, limited and formatted
as a twos complement value representing the temperature in degrees Celsius.
The sampling is controlled by the serial interface signals SDEN and SCLK. If the temperature sensor is enabled
by writing a 0 to field TSENSE_SLEEP in register SLEEP_CONFIG (8.5.70), a conversion takes place each time
the serial port is written or read. The data is only read and sent out by the digital block when the temperature
sensor is read in field TEMPDATA in register TEMP_PLLVOLT (8.5.7). The conversion uses the first eight clocks
of the serial clock as the capture and conversion clock, the data is valid on the falling eighth SCLK. The data is
then clocked out of the chip on the rising edge of the ninth SCLK. No other clocks to the chip are necessary for
the temperature sensor operation. As a result the temperature sensor is enabled even when the device is in
sleep mode.
In order for the process described above to operate properly, the serial port read from register TEMP_PLLVOLT
must be done with an SCLK period of at least 1 μs. If this is not satisfied the temperature sensor accuracy is
greatly reduced.
8.3.24 Alarm Monitoring
The DAC38RF82 (or DAC38RF89) includes a flexible set of alarm monitoring that can be used to alert of a
possible malfunction scenario. All the alarm events can be accessed either through the SIP registers and/or
through the ALARM output. Once an alarm is set, the corresponding alarm bit must be reset through the serial
interface to allow further testing. The set of alarms includes the following conditions:
• JESD alarms
– Fields ALM_LANEx_ERR in registers JESD_ALM_Lx (x = 0-7, 8.5.59 to 8.5.66):
– multiframe alignment_error. Occurs when multiframe alignment fails
– frame alignment error. Occurs when multiframe alignment fails
– link configuration error. Occurs when there is wrong link configuration
– elastic buffer overflow. Occurs when bad RBD value is used
– elastic buffer match error. Occurs when the first non-/K/ doesn’t match the programmed data
– code synchronization error
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
59
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
•
•
•
•
www.ti.com
– 8b/10b not-in-table decode error
– 8b/10b disparity error
– Field ALM_FROM_SHORTTEST in register ALM_SYSREF_PAP (8.5.67): Occurs when the short pattern
test fails.
SerDes alarms
– Field ALM_SD_LOTDET in register ALM_SD_DET 8.5.5): Occurs when there are loss of signal detect
from SerDes lanes.
– Fields ALM_FIFOx_FLAGS in registers JESD_ALM_Lx (x = 0-7, 8.5.59 to 8.5.66):
– FIFO write error. Occurs if write request and FIFO is full.
– FIFO write full: Occurs if FIFO is full.
– FIFO read error. Occurs if read request and FIFO is empty.
– FIFO read empty: Occurs if FIFO is empty.
– Field ALM_SD0_PLL in register ALM_SYSREF_DET (8.5.6): Occurs if the PLL in the SerDes block 0
goes out of lock.
– Field ALM_SD1_PLL in register ALM_SYSREF_DET (8.5.6): Occurs if the PLL in the SerDes block 1
goes out of lock.
SYSREF alarm
– Field ALM_SYSREF_ERR in register ALM_SYSREF_PAP (8.5.67): Occurs when the SYSREF is received
at an unexpected time. If too many of these occur it will cause the JESD to go into synchronization mode
again.
DAC PLL alarm
– Field PLL_LOCK in register ALM_SYSREF_DET (8.5.6). This register field is asserted when the PLL is
unlocked. When used as an alarm output, a high signal indicates that the PLL is unlocked if the
ALM_OUT_POL bit in register RESET_CONFIG is set to 1.
PAP alarm
– Field ALM_PAP in register ALM_SYSREF_PAP (8.5.67): Occurs when the average power is above the
threshold. While any alarm_pap is asserted the attenuation for the appropriate data path is applied.
8.3.25 Differential Clock Inputs
Figure 45 shows the preferred configuration for driving the DACCLK+/- and SYSREF+/- with a differential
ECL/PECL source.
LVPCL Driver
0.01 mF
100 W
CAC
0.01 mF
240 W
240 W
Copyright © 2016, Texas Instruments Incorporated
Figure 45. Preferred Clock Input Configuration With a Differential ECL/PECL Clock Source
8.3.26 CMOS Digital Inputs
Figure 46 shows a schematic of the equivalent CMOS digital inputs of the DAC38RF82 (or DAC38RF89). SDIO,
SCLK, TCLK, SLEEP, TESTMODE and TXENABLE have internal pull-down resistors while SDEN, RESET,
TMS, TDI and TRST have internal pull-up resistors. See the Specifications table for logic thresholds. The pull-up
and pull-down circuitry is approximately equivalent to 10 kΩ.
60
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
VDDIO18
VDDIO18
10 k
SDIO
SCLK
TCLK
SLEEP
TXENABLE
TESTMODE
400
internal
digital in
SDENB
RESETB
TMS
TDI
TRSTB
400
internal
digital in
10 k
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 46. CMOS Digital Equivalent Input
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
61
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.3.27 DAC Fullscale Output Current
The DAC38RF82 (or DAC38RF89) uses a bandgap reference and control amplifier for biasing the full-scale
output current. The DAC full scale output current is set by a combination of the fixed current through the external
resistor RBIAS (connected to pin BIASJ) and current from course trim current sources:
IOUTFS
IRBIAS
Icoarsetrim
(8)
The bias current IBIAS through resistor RBIAS is defined by the on-chip bandgap reference voltage VBG (nominally
0.9 V) and control amplifier. For normal operation, it is recommended that RBIAS is set to 3.6 kΩ for a fixed
current through RBIAS of 250 µA. This current is scaled 128x internally, giving:
IRBIAS
128 u
VBG
RBIAS
128 u
0.9V
3.6 k
32 mA
(9)
The course trim current sources are configured through SPI register field DACFS in register DACFS (8.5.72), as
follows:
I coarsetrim = 2mA × DACFS - 11
(10)
From the discussion above, the DAC full scale output current can be configured from 40 mA (DACFS[3:0] =
1111) down to 10 mA (DACFS[3:0] = 0000). In addition to the full scale signal current set by SPI register DACFS
(8.5.72), an extra DC bias current is required to set the operating point of the output current sources(Table 45).
Table 45. DAC output current
(1)
DACFS ( 8.5.72)
Signal current (mA)
Total bias current (mA) (1)
0
10
1
1
12
1
2
14
2
3
16
2
4
18
3
5
20
3
6
22
4
7
24
5
8
26
5
9
28
6
10
30
6
11
32
7
12
34
7
13
36
8
14
38
8
15
40
9
The bias current per each complementary output is half the total bias current
An external decoupling capacitor CEXT of 0.1 μF should be connected externally to terminal EXTIO for
compensation. The full-scale output current can be adjusted from 40 mA down to 10 mA by varying resistor RBIAS
From 3.6 kΩ to 14.4 kΩ.
8.3.28 Current Steering DAC Architecture
The DACs in the DAC38RF82 (or DAC38RF89) consist of a segmented array of NMOS current sources, capable
of sinking a full-scale output current up to 40 mA (see Figure 47). Differential current switches direct the current
to either one of the complimentary output nodes VOUT1/2+ or VOUT1/2-. Complimentary output currents enable
differential operation, thus canceling out common mode noise sources (digital feed-through, on-chip and PCB
noise), dc offsets, even order distortion components, and increasing signal output power by a factor of four.
62
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
VDDOUT18
Zext+
Zext-
VOUT1/2+
VOUT1/2-
100 :
IOUT+
IOUT-
VDEE18N
(-1.8V)
Figure 47. Current Steering DAC Architecture for DAC38RF82 (or DAC38RF89)
Referring to Figure 47, the total output current IOUTFS is fixed, and is switched to either the + or – output by
switches S(N):
IOUTFS
IOUT +
IOUT-
(11)
Since the output stage is a current sinking architecture, it will denote current into the DAC as + current, and the
current flows IOUT+ and IOUT- into terminals VOUT1/2+ and VOUT1/2- respectively. IOUT+ and IOUT- can be
expressed as:
IOUT+
IOUT-
IOUTFS u CODE
16384
(12)
IOUTFS u 16383 CODE
16384
(13)
where CODE is the decimal representation of the 14-bit DAC core data input word. Note the signal path up to the
DAC is 16-bits and the 2 LSBs are truncated for the DAC core data input word.
8.3.29 DAC Transfer Function
The DAC38RF82 (or DAC38RF89) has a differential output and is terminated internally with a differential 100-Ω
load. The DAC38RF82 (or DAC38RF89) output compliance range is 1.3 to 2.3 V. Note that care should be taken
not to exceed the compliance voltages at node VOUT1/2+ and VOUT1/2-, which would lead to increased signal
distortion.
Referring again to Figure 47, denote the external impedance as seen by VOUT1/2+ as Zext+ and by VOUT1/2as Zext-. Note that Zext+ and Zext- should terminate to VDDOUT18 to supply the output current for the DAC.
Also, Zext+ and Zext- are ideally identical to maintain the differential balance of the output. The voltage at nodes
VOUT1/2+ and VOUT1/2- generated by the current flow through the impedance is
VOUT 1/ 2
IOUT + u 100
Zext +
u Zext +
Zext + Zext 100
IOUT - uZext u Zext +
Zext + Zext -
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
(14)
Submit Documentation Feedback
63
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
VOUT 1/ 2
IOUT - u 100
Zext u Zext +
100
Zext + Zext -
www.ti.com
IOUT + uZext +
u Zext Zext + Zext -
(15)
The DAC38RF82 (or DAC38RF89) can be easily configured to drive a doubly terminated 50-Ω cable using a
properly selected 2:1 RF transformer (Figure 48). Note that the center tap of the primary input of the transformer
has to be connected to the VDDOUT18 supply (nominally 1.8 V) to enable a DC current flow into the DAC. The
AC load impedance as seen through 2:1 transformer is 100 Ω, which is split equally into Zext+ = Zext- = 50 Ω.
The DC impedance for the transformer is a short to the center tap of the transformer, which drives the common
mode of VOUT1/2+ and VOUT1/2- to 1.8V. To calculate the peak to peak output swing VOUT1/2PP at each
node, the equations above simplify to:
VOUT 1/ 2PP
VOUT 1/ 2
VOUT 1/ 2PP
IOUTFS u 50 u
200
IOUT+ IOUTFS,IOUT
IOUTFS u
0
VOUT 1/ 2
u
IOUT- IOUTFS ,IOUT+ 0
(16)
IOUTFS u 25
(17)
With IOUTOUTFS = 40 mA, the swing becomes 1 VPP at each node. With the common mode at 1.8 V due to the
center tap, the voltage at VOUT1/2+ and VOUT1/2- varies between 1.3 and 2.3 V, which is the compliance range
of the DAC.
The differential output swing is 2x VOUT1/2PP, or 2 VPPDIFF. On the load side of the transformer, this reduces to
1.414 VPP, for a transferred load power of 7 dBm (assuming no loss).
VOUT1/2+
2:1
RLOAD
100 :
50 :
VOUT1/2VDDADAC18
(1.8V)
Figure 48. Driving a 50-Ω Load Using a 2:1 Impedance Ratio Transformer (DAC38RF82 (or DAC38RF89))
The DAC38RF82 (or DAC38RF89) can also be DC coupled. In this case, the termination voltage can be raised
above 1.8 V (for example 2.3 V) so that the common mode for the output pin is nominally 1.8 V.
8.4 Device Functional Modes
8.4.1 Clocking Modes
The DAC38RF82 (or DAC38RF89) has both a single ended clock input DACCLKSE and a differential clock input
DACCLK+/- to clock the device. The clock input is selected by field SEL_EXTCLK_DIFFSE in register
CLK_PLL_CFG (8.5.79). The DAC38RF82 (or DAC38RF89) can be clock directly with a high frequency input
clock at the DAC sample rate (PLL Bypass Mode), or an optional on-chip low-jitter phase-locked loop (PLL) can
be used to generate the high frequency DAC sample clock internally from a lower frequency reference clock
input (PLL Mode).
8.4.2 PLL Bypass Mode Programming
In PLL bypass mode a high quality clock is sourced to the DACCLK inputs. This clock is used to directly clock
the DAC38RF82 (or DAC38RF89) DAC cores. This mode gives the device best performance and is
recommended for extremely demanding applications.
The bypass mode is selected by setting the following:
1. Set field PLL_ENA in register CLK_PLL_CFG (8.5.79) to “0” to bypass the PLL circuitry.
2. Set field PLL_SLEEP in register SLEEP_CONFIG (8.5.70) to “1” to put the PLL and VCO into sleep mode.
64
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Device Functional Modes (continued)
8.4.3 Internal PLL/VCO
The DAC38RF82 (or DAC38RF89) has an internal clock generation circuit consisting of a PLL and two selectable
VCOs, as shown in Figure 49.
High VCO
yN
PFD
and
charge pump
Output
buffer
DAC
CLK
PLL_N(4-0)
Feedback
Low VCO
yM
y4
PLL_M(7-0)
Figure 49. Internal PLL/VCO Block Diagram
DAC38RF82 (or DAC38RF89) each have a low VCO (VCO0) and high VCO (VCO1), but they are tuned to
different center frequencies in each device. The VCO frequency ranges for each device are summarized in
Electrical Characteristics - Digital Specifications. The VCO is selected through field PLL_VCOSEL in register
PLL_CONFIG2 (8.5.81), with ‘0’ selecting the low VCO and a ‘1’ the high VCO. The 7 bit VCO tuning code in
field PLL_VCO in register PLL_CONFIG2 (8.5.81) is used to tune the VCO frequency from the lowest frequency
in the range to the highest frequency for the particular VCO used. For the low VCO the center VCO frequency is
achieved with PLL_VCO = 63decimal and for the high VCO the center frequency is achieved with PLL_VCO =
63decimal.
The supply current, and therefore; the analog signal amplitude in the VCO is controlled using the field
PLL_VCO_RDAC in register PLL_CONFIG1 (8.5.80). This control signal should be set 15decimal initially for 18 mA
supply current in the VCO and ~1.4 VPP single ended oscillation amplitude.
The PLL has no prescaler, so the DAC sample rate is the VCO frequency. In the PLL feedback path a fixed ÷ 4
frequency divider block receives the VCO output clock and divides its frequency by 4. The maximum operating
frequency of the phase-frequency detector (PFD) and charge pump (CP) requires this. The M (feedback) clock
divider takes the output clock signal from the fixed ÷4 block and divides it by a programmable ratio set by the 8bit field in field PLL_M_M1 in register PLL_CONFIG1 (8.5.80). The programmable division ratio range is ÷1 to
÷256, and is the value of the 8 bit unsigned binary code + 1. Although it is possible to program the M divider to
÷1, ÷2 and ÷3, these values should not be used. As stated previously the PFD and CP have a finite maximum
operating frequency, which is the VCO frequency divided by the fixed divider ratio multiplied by the minimum
allowable M divider ratio.
PFD _ CPFmax
Fvco / Fixed _ div x Mdiv min
(18)
The N (reference) divider determines the ratio between the input reference clock frequency and the PFD
operating frequency, and is set by the 5-bit field PLL_N_M1 in register CLK_PLL_CFG (8.5.79). The division ratio
range is ÷1 to ÷32, and is the value of the 5-bit unsigned binary code + 1.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
65
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Device Functional Modes (continued)
The charge pump output current amplitude is set using the 4-bit field PLL_CP_ADJ in in register PLL_CONFIG2
(8.5.81). The current amplitude is simply the digital code multiplied by the unit current amplitude of 100 µA. In a
nominal condition, with the DAC38RF82 VCO0 running at 5.898 GHz, and with the M divider set to ÷4, the PFD
will run at 368.625 MHz, and the change pump current should set to 6decimal, which gives 600 µA charge pump
output current for a good phase margin of 69 degrees. If a higher M ratio (for lower PFD frequencies) are
required the charge pump output current must be increased to maintain good loop stability and prevent excessive
peaking in the phase noise response. The charge pump output current setting PLL_CP_ADJ should be adjusted
in relation to the feedback (M) divider ratio PLL_M_M1 according to the following table to maintain a constant
phase margin of 69 degrees.
Table 46. M vs Kp for Maintaining Good Stability
M
CP_ADJ
4
6
6
9
8
12
10
15
Similarly for the DAC38RF82 VCO2 running at 8.847 GHz, and with the M divider set to ÷4, the PFD will run at
552.9375 MHz as shown above. Here the change pump current should set to 6decimal, which gives 600 µA charge
pump output current for a good phase margin of 69 degrees.
8.4.4 CLKOUT
The DAC38RF82 (or DAC38RF89) has a programmable output clock on CLKTX+/- balls that is a divided version
of the internal DAC sample clock, either with or without PLL. Two frequency dividers, either DACCLK/3 or
DACCLK/4, are available by programming field CLK_TX_DIV4 in register CLK_OUT (8.5.71). The output swing
voltage is programmable from approximately 125 to 1460 mVPP-DIFF through field CLK_TX_SWING in register
CLK_OUT (8.5.71).
Field CLK_TX_IDLE in register CLK_OUT (8.5.71) enables an idle state, in which the pins are driven to the
proper common-mode levels in order to charge the external AC coupling caps but the clock output is disabled.
The output clock circuit can be put to sleep by field CLK_TX_SLEEP in register SLEEP_CONFIG (8.5.70).
8.4.5 Serial Peripheral Interface (SPI)
The serial port of the DAC38RF82 (or DAC38RF89) is a flexible serial interface which communicates with
industry standard microprocessors and microcontrollers. The interface provides read/write access to all registers
used to define the operating modes of DAC38RF82 (or DAC38RF89). It is compatible with most synchronous
transfer formats and can be configured as a 3 or 4 terminal interface by SIF4_ENA in register IO_CONFIG
(8.5.2). In both configurations, SCLK is the serial interface input clock and SDEN is serial interface enable. For 3
terminal configuration, SDIO is a bidirectional terminal for both data in and data out. For 4 terminal configuration,
SDIO is bidirectional and SDO is data out only. Data is input into the device with the rising edge of SCLK. Data is
output from the device on the falling edge of SCLK.
The SPI registers are reset by writing a 1 to SPI_RESET in register RESET_CONFIG (8.5.1).
Each read/write operation is framed by signal SDEN (Serial Data Enable Bar) asserted low. The first frame byte
is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit
address to be accessed. Figure 50 indicates the function of each bit in the instruction cycle and is followed by a
detailed description of each bit. The data transfer cycle consists of two bytes.
Figure 50. Instruction Byte of the Serial Interface
Bit
Description
7 (MSB)
R/W
6
A6
5
A5
4
A4
3
A3
2
A2
1
A1
0
A0
R/W - Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from DAC38RF82 (or
DAC38RF89) and a low indicates a write operation to DAC38RF82 (or DAC38RF89)
A6:A0 - Identifies the address of the register to be accessed during the read or write operation.
66
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Figure 51 shows the serial interface timing diagram for a DAC38RF82 (or DAC38RF89) write operation. SCLK is
the serial interface clock input to DAC38RF82 (or DAC38RF89). Serial data enable SDEN is an active low input
to DAC38RF82 (or DAC38RF89). SDIO is serial data input. Input data to DAC38RF82 (or DAC38RF89) is
clocked on the rising edges of SCLK.
Instruction Cycle
Data Transfer Cycle
SDEN\
SCLK
SDIO
rwb
A6
A5
A4
A3
A2
tS(SDEN\)
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
tSCLK
SDEN\
SCLK
SDIO
tS(SDIO) tH(SDIO)
Figure 51. Serial Interface Write Timing Diagram
Figure 52 shows the serial interface timing diagram for a DAC38RF82 (or DAC38RF89) read operation. SCLK is
the serial interface clock input to DAC38RF82 (or DAC38RF89). Serial data enable SDEN is an active low input
to DAC38RF82 (or DAC38RF89). SDIO is serial data input during the instruction cycle. In 3 pin configuration,
SDIO is data out from the DAC38RF82 (or DAC38RF89) during the data transfer cycle, while SDO is in a highimpedance state. In 4 pin configuration, both SDIO and SDO are data out from the DAC38RF82 (or
DAC38RF89) during the data transfer cycle. At the end of the data transfer, SDIO and SDO will output low on the
final falling edge of SCLK until the rising edge of SDEN when they will 3-state.
Instruction Cycle
Data Transfer Cycle
SDEN\
SCLK
SDIO
rwb
A6
A5
A4
A3
A2
A1
A0
SDO
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDEN\
SCLK
SDIO
SDO
Data n
Data n-1
td(Data)
Figure 52. Serial Interface Read Timing Diagram
n the SIF interface there are four types of registers:
8.4.5.1 NORMAL (RW)
The NORMAL register type allows data to be written and read from. All 16-bits of the data are registered at the
same time. There is no synchronizing with an internal clock thus all register writes are asynchronous with respect
to internal clocks. There are three subtypes of NORMAL:
1. AUTOSYNC: A NORMAL register that causes a sync to be generated after the write is finished. These are
used when it is desirable to synchronize the block after writing the register or if a single field that spans
across multiple registers. For instance, the NCO requires three 16-bit register writes to set the frequency.
Upon writing the last of these registers an autosync is generated to deliver the entire field to the NCO block
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
67
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
at once, rather than in pieces after each individual register write. For a field that spans multiple registers, all
non-AUTOSYNC registers for the field must be written first before the actual AUTOSYNC register.
2. No RESET Value: These are NORMAL registers, but the reset value cannot be specified. This could be
because the register has some read only bits or some internal logic partially controls the bit values.
3. READ_ONLY (R): Registers that can only be read.
8.4.5.2 WRITE_TO_CLEAR (W0C)
These registers are just like NORMAL registers with one exception. They can be written and read, however,
when the internal logic asynchronously sets a bit high in one of these registers, that bit stays high until it is
written to ‘0’. This way interrupts will be captured and stay constant until cleared by the user.
8.4.5.3 Writing to Reserved Bits
Registers with reserved bits must have these bits written as described in the register map when writing to this
register. If a reserved bit is shown as a “1” in the reset column of the field description, whenever a write to this
register is required, “1” must be written to this bit. If the reserved bit is a “0”, a “0” would have to be written to this
location.
8.5 Register Maps
Table 47. Register Summary
Address
Reset
Acronym
Register Name
Section
General Configuration Registers (PAGE_SET[2:0] = 000)
0x00
0x5803
RESET_CONFIG
Chip Reset and Configuration
8.5.1
0x01
0x1800
IO_CONFIG
IO Configuration
8.5.2
0x02
0xFFFF
ALM_SD_MASK
Lane Signal Detect Alarm Mask
8.5.3
0x03
0xFFFF
ALM_CLK_MASK
Clock Alarms Mask
8.5.4
0x04
variable (1)
ALM_SD_DET
SERDES Loss of Signal Detection Alarms
8.5.5
0x05
variable (1)
ALM_SYSREF_DET
SYSREF Alignment Circuit Alarms
8.5.6
0x06
variable
TEMP_PLLVOLT
Temperature Sensor and PLL Loop Voltage
8.5.7
0x07-0x08
0x0000
Reserved
Reserved
0x09
0x0000
PAGE_SET
Page Set
0x0A-0x77
0x0000
Reserved
Reserved
0x78
0x0000
SYSREF_ALIGN_R
SYSERF Align to r1 and r3 Count
8.5.9
0x79
0x0000
SYSREF12_CNT
SYSREF Phase Count 1 and 2
8.5.10
8.5.11
0x7A
0x0000
SYSREF34_CNT
SYSREF Phase Count 3 and 4
0x7B-0x7E
0x0000
Reserved
Reserved
0x7F
0x0009
VENDOR_VER
Vendor ID and Chip Version
8.5.8
8.5.12
Multi-DUC Configuration Registers (PAGE_SET[0] = 1 for multi-DUC1, PAGE_SET[1] = 1 for multi-DUC2)
(1)
68
0x0A
0x02B0
MULTIDUC_CFG1
Multi-DUC Configuration (PAP, Interpolation)
0x0B
0x0000
Reserved
Reserved
8.5.13
0x0C
0x2402
MULTIDUC_CFG2
Multi-DUC Configuration (Mixers)
8.5.14
0x0D
0x8000
JESD_FIFO
JESD FIFO Control
8.5.15
0x0E
0x00FF
ALM_MASK1
Alarm Mask 1
8.5.16
0x0F
0xFFFF
ALM_MASK2
Alarm Mask 2
8.5.17
0x10
0xFFFF
ALM_MASK3
Alarm Mask 3
8.5.18
0x11
0xFFFF
ALM_MASK4
Alarm Mask 4
8.5.19
0x12
0x0000
JESD_LN_SKEW
JESD Lane Skew
8.5.20
0x13-0x16
0x0000
Reserved
Reserved
0x17
0x0000
CMIX
CMIX Configuration
0x18
0x0000
Reserved
Reserved
0x19
0x0000
OUTSUM
Output Summation and Delay
0x1A-0x1B
0x0000
Reserved
Reserved
8.5.21
8.5.22
Reflect immediately on system condition and error condition.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Register Maps (continued)
Table 47. Register Summary (continued)
Address
Reset
Acronym
Register Name
Section
0x1C
0x0000
PHASE_NCOAB
Phase offset for AB path NCO
8.5.23
0x1D
0x0000
PHASE_NCOCD
Phase offset for CD path NCO
8.5.24
0x1E-0x20
0x0000
FREQ_NCOAB
Frequency for AB path NCO
8.5.25
0x21-0x23
0x0000
FREQ_NCOCD
Frequency for CD path NCO
8.5.26
0x24
0x0010
SYSREF_CLKDIV
SYSREF Use for Clock Divider
8.5.27
0x25
0x7700
SERDES_CLK
Serdes Clock Control
8.5.28
0x26
0x0000
Reserved
Reserved
0x27
0x1144
SYNCSEL1
Sync Source Selection
8.5.29
0x28
0x0000
SYNCSEL2
Sync Source Selection
8.5.30
0x29
0x0000
PAP_GAIN_AB
PAP path AB Gain Attenuation Step
8.5.31
0x2A
0x0000
PAP_WAIT_AB
PAP path AB Wait Time at Gain = 0
8.5.32
0x2B
0x0000
PAP_GAIN_CD
PAP path CD Gain Attenuation Step
8.5.33
0x2C
0x0000
PAP_WAIT_CD
PAP path CD Wait Time at Gain = 0
8.5.34
0x2D
0x1FFF
PAP_CFG_AB
PAP path AB Configuration
8.5.35
0x2E
0x1FFF
PAP_CFG_CD
PAP path CD Configuration
8.5.36
0x2F
0x0000
SPIDAC_TEST1
Configuration for DAC SPI Constant
8.5.37
0x30
0x0000
SPIDAC_TEST2
DAC SPI Constant
8.5.38
0x31
0x0000
Reserved
Reserved
0x32
0x0400
GAINAB
Gain for path AB
8.5.39
0x33
0x0400
GAINCD
Gain for path CD
8.5.40
0x34-0x40
0x0000
Reserved
Reserved
0x41
0x0000
JESD_ERR_CNT
JESD Error Counter
0x42-0x45
0x0000
Reserved
Reserved
0x46
0x0044
JESD_ID1
JESD ID 1
8.5.42
0x47
0x190A
JESD_ID2
JESD ID 2
8.5.43
0x48
0x31C3
JESD_ID3
JESD ID 3 and Subclass
8.5.44
0x49
0x0000
Reserved
Reserved
0x4A
0x0003
JESD_LN_EN
JESD Lane Enable
8.5.45
0x4B
0x1300
JESD_RBD_F
JESD RBD Buffer and Frame Octets
8.5.46
0x4C
0x1303
JESD_K_L
JESD K and L Parameters
8.5.47
0x4D
0x0100
JESD_M_S
JESD M and S Parameters
8.5.48
0x4E
0x0F4F
JESD_N_HD_SCR
JESD N, HD and SCR Parameters
8.5.49
0x4F
0x1CC1
JESD_MATCH
JESD Character Match and Other
8.5.50
0x50
0x0000
JESD_LINK_CFG
JESD Link Configuration Data
8.5.51
0x51
0x00FF
JESD_SYNC_REQ
JESD Sync Request
8.5.52
0x52
0x00FF
JESD_ERR_OUT
JESD Error Output
8.5.53
0x53
0x0100
JESD_ILA_CFG1
JESD Configuration Value used for ILA
Check
8.5.54
0x54
0x8E60
JESD_ILA_CFG2
JESD Configuration Value used for ILA
Check
8.5.55
0x55-0x5B
0x0000
Reserved
Reserved
0x5C
0x0001
JESD_SYSR_MODE
JESD SYSREF Mode
0x5D-0x5E
0x0000
Reserved
Reserved
0x5F
0x0123
JESD_CROSSBAR1
JESD Crossbar Configuration 1
8.5.57
0x60
0x4567
JESD_CROSSBAR2
JESD Crossbar Configuration 2
8.5.58
0x61-0x63
0x0000
Reserved
Reserved
0x64
0x0000
JESD_ALM_L0
JESD Alarms for Lane 0
8.5.59
0x65
0x0000
JESD_ ALM_L1
JESD Alarms for Lane 1
8.5.60
0x66
0x0000
JESD_ ALM_L2
JESD Alarms for Lane 2
8.5.61
0x67
0x0000
JESD_ALM_L3
JESD Alarms for Lane 3
8.5.62
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
8.5.41
8.5.56
Submit Documentation Feedback
69
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Register Maps (continued)
Table 47. Register Summary (continued)
Address
Reset
Acronym
Register Name
Section
0x68
0x0000
JESD_ALM_L4
JESD Alarms for Lane 4
8.5.63
0x69
0x0000
JESD_ALM_L5
JESD Alarms for Lane 5
8.5.64
0x6A
0x0000
JESD_ALM_L6
JESD Alarms for Lane 6
8.5.65
0x6B
0x0000
JESD_ALM_L7
JESD Alarms for Lane 7
8.5.66
0x6C
0x0000
ALM_SYSREF_PAP
SYSREF and PAP Alarms
8.5.67
0x6D
0x0000
ALM_CLKDIV1
Clock Divider Alarms 1
8.5.68
0x6E-0x77
0x0000
Reserved
Reserved
Miscellaneous Configuration Registers (PAGE_SET[1:0] = 00, PAGE_SET[2] = 1)
70
0x0A
0xFC03
CLK_CONFIG
Clock Configuration
8.5.69
0x0B
0x0022
SLEEP_CONFIG
Sleep Configuration
8.5.70
0x0C
0xA002
CLK_OUT
Divided Output Clock Configuration
8.5.71
0x0D
0xF000
DACFS
DAC Fullscale Current
8.5.72
0x0E-0x0F
0x0000
Reserved
Reserved
0x10
0x0000
LCMGEN
Internal sysref generator
8.5.73
0x11
0x0000
LCMGEN_DIV
Counter for internal sysref generator
8.5.74
0x12
0x0000
LCMGEN_SPISYSREF
SPI SYSREF for internal sysref generator
8.5.75
0x13-0x1A
0x0000
Reserved
Reserved
0x1B
0x0000
DTEST
Digital Test Signals
0x1C-0x22
0x0000
Reserved
Reserved
0x23
0xFFFF
SLEEP_CNTL
Sleep Pin Control
8.5.77
0x24
0x1000
SYSR_CAPTURE
SYSREF Capture Circuit Control
8.5.78
0x25-0x30
0x0000
Reserved
Reserved
0x31
0x0200
CLK_PLL_CFG
Clock Input and PLL Configuration
8.5.79
0x32
0x0308
PLL_CONFIG1
PLL Configuration 1
8.5.80
0x33
0x4018
PLL_CONFIG2
PLL Configuration 2
8.5.81
0x34
0x0000
LVDS_CONFIG
LVDS Output Configuration
8.5.82
0x35
0x0018
PLL_FDIV
Fuse farm clock divider
8.5.83
0x36-0x3A
0x0000
Reserved
Reserved
8.5.76
0x3B
0x1802
SRDS_CLK_CFG
Serdes Clock Configuration
8.5.84
0x3C
0x8228
SRDS_PLL_CFG
Serdes PLL Configuration
8.5.85
0x3D
0x0088
SRDS_CFG1
Serdes Configuration 1
8.5.86
0x3E
0x0909
SRDS_CFG2
Serdes Configuration 2
8.5.87
0x3F
0x0000
SRDS_POL
Serdes Polarity Control
8.5.88
0x40-0x75
0x0000
Reserved
Reserved
0x76
0x0000
SYNCBOUT
JESD204B SYNCB Output
Submit Documentation Feedback
8.5.89
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.1 Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]
Figure 53. Chip Reset and Configuration Register (RESET_CONFIG)
15
0
RW
14
0
RW
13
0
RW
12
0
RW
11
0
RW
10
0
RW
9
0
RW
8
x
RW
7
0
RW
6
0
RW
5
0
RW
4
0
RW
3
0
RW
2
0
RW
1
0
RW
0
0
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 48. RESET_CONFIG Field Descriptions
Bit
Field
Type
Reset
Description
15
SPI_RESET
RW
0
This will reset all the SPI registers once programmed.
14
ALM_OUT_POL
RW
1
Changes the polarity of the alarm output.
0= active low
1= active high
13
ALM_OUT_ENA
RW
0
Turn on the alarm pin
12
SYSCLK_ENA
RW
1
Turns on the dividers for the SYSCLK to the Fusefarm
11
AUTOLOAD_TRIG
RW
1
Causes a Fuse AUTOLOAD to be executed.
10:7
Reserved
RW
0000
Reserved
6
ONE_DAC_ONLY
RW
0
When set high only the SLICE0 is available.
5
ONE_LINK_ONLY
RW
0
This needs to be set high when a single link setup is being
programmed to get the correct TXENABLE signal generation
4:2
Reserved
RW
000
Reserved
1
INIT_SLICE1
RW
1
Puts the multi-DAC2 JESD into initialization state
0
INIT_SLICE0
RW
1
Puts the multi-DAC1 JESD into initialization state
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
71
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.2 IO Configuration Register (address = 0x01) [reset = 0x1800]
Figure 54. IO Configuration Register (IO_CONFIG)
15
0
R/W
14
0
R/W
13
0
R/W
12
1
R/W
11
1
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 49. IO_CONFIG Field Descriptions
Bit
Field
Type
Reset
Description
15:14
GPO0_SEL
RW
00
Selects the JESD SYNC_N signal coming out the GPO0 pin.
Both bits can be asserted which does an oring of the SYNC_N
signals from each multi-DUC.
bit 0 = 1 then multi-DUC1 SYNC_N used
bit 1 = 1 then multi-DUC2 SYNC_N is used
13:12
SYNC0B_SEL
RW
01
Selects the JESD SYNC_N signal coming out the SYNC0B pin.
Both bits can be asserted which does an oring of the SYNC_N
signals from each multi-DUC.
bit 0 = 1 then multi-DUC1 SYNC_N used
bit 1 = 1 then multi-DUC2 SYNC_N is used
11:10
SYNC1B_SEL
RW
10
Selects the JESD SYNC_N signal coming out the SYNC1B pin.
Both bits can be asserted which does an oring of the SYNC_N
signals from each multi-DUC.
bit 0 = 1 then multi-DUC1 SYNC_N used
bit 1 = 1 then multi-DUC2 SYNC_N is used
9:8
GPO1_SEL
RW
00
Selects the JESD SYNC_N signal coming out the GPO1 pin.
Both bits can be asserted which does an oring of the SYNC_N
signals from each multi-DUC.
bit 0 = 1 then multi-DUC1 SYNC_N used
bit 1 = 1 then multi-DUC2 SYNC_N is used
7
SPI4_ENA
RW
0
When set to a '1' the chip is in 4 pin SPI interface mode.
6
Reserved
RW
0
Reserved
ATEST
RW
000000
Select the analog test points:
000000: ATEST is off (ATEST Must be off during normal
operation)
000001, 010001, 000110: VSSCLK
000010: VDDPLL1
000101: VDDCLK
000111, 001010, 010000: VDDAPLL18
001011: VDDAVCO18
001101: VDDS18
001110: VDDE1
001111, 111010, 111011, 111100: DGND
010011: VDDTX1
101001, 110001: AGND
101111, 111101, 111110, 11111: VDDDIG1
110000: VDDA18
5:0
72
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.3 Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]
Figure 55. Lane Single Detect Alarm Mask Register (ALM_SD_MASK)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 50. ALM_SD_MASK Field Descriptions
Bit
15:0
Field
Type
ALM_SD_MASK
R/W
Reset
Description
0xFFFF
Used to mask alarms
bit 15 - bit 8 : Reserved
bit7 : lane 7 loss of signal detect
bit6 : lane 6 loss of signal detect
bit5 : lane 5 loss of signal detect
bit4 : lane 4 loss of signal detect
bit3 : lane 3 loss of signal detect
bit2 : lane 2 loss of signal detect
bit1 : lane1 loss of signal detect
bit0 : lane 0 loss of signal detect
8.5.4 Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF
Figure 56. Clock Alarms Mask Register (ALM_CLK_MASK)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 51. ALM_CLK_MASK Field Descriptions
Bit
15:0
Field
Type
ALM_CLK_MASK
R/W
Reset
Description
0xFFFF
Used to mask alarms
bit 15 - bit 8 : Reserved
bit 7 : alarm_sysrefphase4
bit 6 : alarm_sysrefphase3
bit 5 : alarm_sysrefphase2
bit 4 : alarm_sysrefphase1
bit 3 : alarm_align_to_r3
bit 2 : alarm_align_to_r1
bit 1 : alarm_sd0_pll
bit 0 : alarm_sd1_pll
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
73
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.5 SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = variable]
Figure 57. SERDES Loss of Signal Detection Alarms Register (ALM_SD_DET)
15
0
W0C
14
0
W0C
13
0
W0C
12
0
W0C
11
0
W0C
10
0
W0C
9
0
W0C
8
x
W0C
7
0
W0C
6
0
W0C
5
0
W0C
4
0
W0C
3
0
W0C
2
1
W0C
1
0
W0C
0
0
W0C
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset
Table 52. ALM_SD_DET Field Descriptions
Bit
15:8
7:0
74
Field
Type
Reset
Description
Reserved
W0C
0x00
Reserved
0x00
Loss of signal detect outputs from the SERDES lanes:
bit 7 = lane7 loss of signal
bit 6 = lane6 loss of signal
bit 5 = lane5 loss of signal
bit 4 = lane4 loss of signal
bit 3 = lane3 loss of signal
bit 2 = lane2 loss of signal
bit 1 = lane1 loss of signal
bit 0 = lane0 loss of signal
ALM_SD_LOSDET
Submit Documentation Feedback
W0C
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.6 SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = variable]
Figure 58. SYSREF Alignment Circuit Alarms Register (ALM_SYSREF_DET)
15
0
W0C
14
0
W0C
13
0
W0C
12
0
W0C
11
0
W0C
10
0
W0C
9
0
W0C
8
x
W0C
7
0
W0C
6
0
W0C
5
0
W0C
4
0
W0C
3
0
W0C
2
1
W0C
1
0
W0C
0
1
W0C
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset
Table 53. ALM_SYSREF_DET Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
W0C
0000000
Reserved
8
ALM_SYSRPHASE4
W0C
0
If high the sysrefphase4 state has been observed in the
sysrefalign logic at least once since the last sysrefalign sync.
7
ALM_SYSRPHASE3
W0C
0
If high the sysrefphase3 state has been observed in the
sysrefalign logic at least once since the last sysrefalign sync.
6
ALM_SYSRPHASE2
W0C
0
If high the sysrefphase2 state has been observed in the
sysrefalign logic at least once since the last sysrefalign sync.
5
ALM_SYSRPHASE1
W0C
0
If high the sysrefphase1 state has been observed in the
sysrefalign logic at least once since the last sysrefalign sync.
4
ALM_ALIGN_TO_R3
W0C
0
If high the align_to_r3 state has been observed in the sysrefalign
logic at least once since the last sysrefalign sync. TI Internal use
only.
3
ALM_ALIGN_TO_R1
W0C
0
If high the align_to_r1 state has been observed in the sysrefalign
logic at least once since the last sysrefalign sync. TI Internal use
only.
2
ALM_SD0_PLL
W0C
0
Driven high if the PLL in the Serdes 0 block goes out of lock. A
false alarm is generated at startup when the PLL is locking. User
will have to reset this bit after start to monitor accurately.
1
ALM_SD1_PLL
W0C
0
Driven high if the PLL in the Serdes 1 block goes out of lock. A
false alarm is generated at startup when the PLL is locking. User
will have to reset this bit after start to monitor accurately.
0
PLL_LOCK
W0C
0
Asserted when PLL is unlocked.
15:9
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
75
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.7 Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]
Figure 59. Temperature Sensor and PLL Loop Voltage Register (TEMP_PLLVOLT)
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
x
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
1
R
1
1
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 54. TEMP_PLLVOLT Field Descriptions
Bit
Field
Type
Reset
Description
15:8
TEMPDATA
R
0x00
8 bits of data from the tempurature sensor
7:5
PLL_LFVOLT
R
0b000
PLL Loop filter voltage
4:0
Reserved
R
0b000
Reserved
8.5.8 Page Set Register (address = 0x09) [reset = 0x0000]
Figure 60. Page Set Register (PAGE_SET)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 55. PAGE_SET Field Descriptions
Bit
Field
15:0
76
PAGE_SET
Submit Documentation Feedback
Type
R/W
Reset
Description
0x0000
Each bit selects a page that is active. Multiple pages can be
selected at the same time. No bits asserted means that
MASTER is the only page selected.
bit 0 = page0 : multi-DUC1
bit 1 = page1 : multi-DUC2
bit 2 = page2 : DIG_MISC
bit 3-15: Reserved
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.9 SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]
Figure 61. SYSREF Align to r1 and r3 Count Register (SYSREF_ALIGN_R)
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
x
R
7
0
R
6
1
R
5
1
R
4
1
R
3
1
R
2
0
R
1
0
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 56. SYSREF_ALIGN_R Field Descriptions
Bit
Field
Type
Reset
Description
15:8
ALIGN_TO_R1_CNT
R
0x00
Part of the SYSREF Align block
7:0
ALIGN_TO_R3_CNT
R
0x00
Part of the SYSREF Align block
8.5.10 SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]
Figure 62. SYSREF Phase Count 1 and 2 Register (SYSREF12_CNT)
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
x
R
7
0
R
6
1
R
5
1
R
4
1
R
3
1
R
2
0
R
1
0
R
0
1
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 57. SYSREF12_CNT Field Descriptions
Field
Type
Reset
Description
15:8
Bit
PHASE2_CNT
R
0x00
Part of the SYSREF Align block
7:0
PHASE1_CNT
R
0x00
Part of the SYSREF Align block
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
77
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.11 SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]
Figure 63. SYSREF Phase Count 3 and 4 Register (SYSREF34_CNT)
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
x
R
7
0
R
6
1
R
5
1
R
4
1
R
3
1
R
2
0
R
1
1
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 58. SYSREF34_CNT Field Descriptions
Bit
Field
Type
Reset
Description
15:8
PHASE4_CNT
R
0x00
Part of the SYSREF Align block
7:0
PHASE3_CNT
R
0x00
Part of the SYSREF Align block
8.5.12 Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0009]
Figure 64. Vendor ID and Chip Version Register (VENDOR_VER)
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
x
R
7
0
R
6
1
R
5
1
R
4
1
R
3
1
R
2
1
R
1
1
R
0
1
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 59. VENDOR_VER Field Descriptions
78
Bit
Field
Type
Reset
Description
15
AUTOLOAD_DONE
R
0
Asserted when the Fusefarm Autoload sequence is done
14:10
EFC_ERR
R
00000
The error output from the fuse farm.
9:5
Reserved
R
00000
Reserved
4:3
VENDORID
R
01
TI identification
2:0
VERSION
R
001
Bits to determine what version of build for the chip.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.13 Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]
Figure 65. Multi-DUC Configuration (PAP, Interolation) Register (MULTIDUC_CFG1)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
1
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 60. MULTIDUC_CFG1 Field Descriptions
Bit
Field
Type
Reset
Description
15
DUAL_IQ
R/W
0
When asserted the SLICE uses both IQ paths
14
ISFIR_ENA
R/W
0
Turns on the inverse sync filter for the AB and CD paths when
programmed to 1.
13
Not used
R/W
0
Not used
12:8
INTERP
R/W
00010
Determines the interpolation amount.
00000: 1x
00001: 2x
00010: 4x
00011: 6x
00100: 8x
00101: 10x
00110: 12x
01000: 16x
01001: 18x
01010: 20x
01100: 24x
7
ALM_ZEROS_TXEN
R/W
1
When asserted any alarm that isn’t masked will mid-level the
DAC output by setting the txenable_from_dig to ‘0’
6
DAC_COMPLEMENT
R/W
0
When asserted the DAC output will be 2's complemented. This
helps with hookup at the board level.
5
ALM_ZEROS_JESD
R/W
1
When asserted any alarm that isn’t masked will zero the data
coming out of the JESD block.
4
ALM_OUT_ENA
R/W
1
When asserted the output from the selected SLICE will be
passed on to the MASTER alarm control if it is also turned on
then the alarm will be sent to the pad_alarm pin.
3
PAPA_ENA
R/W
0
Turns on the Power Amp Protection logic for path A.
2
PAPB_ENA
R/W
0
Turns on the Power Amp Protection logic for path B.
1
PAPC_ENA
R/W
0
Turns on the Power Amp Protection logic for path C.
0
PAPD_ENA
R/W
0
Turns on the Power Amp Protection logic for path D.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
79
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]
Figure 66. Multi-DUC Configuration (Mixers) Register (MULTIDUC_CFG2)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
1
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 61. MULTIDUC_CFG2 Field Descriptions
Bit
Field
Type
Reset
Description
DAC_BITWIDTH
R/W
0b00
Determines the bit width of the data going to the DAC
00: 14 bits
01: 14 bits
10: 12 bits
11: 11 bits
13
ZERO_INVLD_DATA
R/W
1
When asserted; the data from the JESD block is zeroed in the
mapper to prevent goofy output from the DAC. For test purposes
this bit should be desasserted
12
SHORTTEST_ENA
R/W
0
Turns on the JESD SHORT pattern test (5.1.6.2)
11
Reserved
R/W
0
Reserved
10
Reserved
R/W
1
Reserved
9
MIXERAB_ENA
R/W
0
Turns on the mixer for the A and B streams
8
MIXERCD_ENA
R/W
0
Turns on the mixer for the C and D streams
7
MIXERAB_GAIN
R/W
0
Adds 6dB of gain when asserted
6
MIXERCD_GAIN
R/W
0
Adds 6dB of gain when asserted
5
NCOAB_ENA
R/W
0
When high the full NCO block is turned on.
4
NCOCD_ENA
R/W
0
When high the full NCO block is turned on.
Reserved
R/W
00
Reserved
1
TWOS
R/W
1
When asserted the chip is expecting 2's complement data is
arriving through the JESD; otherwise offset binary is expected
0
Reserved
R/W
0
Reserved
15:14
3:2
80
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.15 JESD FIFO Control Register (address = 0x0D)[reset = 0x8000]
Figure 67. JESD FIFO Control Register (JESD_FIFO)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 62. JESD_FIFO Field Descriptions
Bit
Field
Type
Reset
Description
15
FIFO_ZEROS_DATA
R/W
1
When asserted FIFO errors zero the data out of the JESD block.
For test purposes this could be turned off to allow test patterns
in the FIFO.
NOT USED
R/W
000
Not Used
12
SRDS_FIFO_ALM_CLR
R/W
0
Set to 1 to clear FIFO errors. Must be set to 0 for proper FIFO
operation
11
14:13
Not used
R/W
0
Not used
10:8
FIFO_OFFSET
R/W
0000
Used to set the difference between read and write pointers in
the JESD FIFO.
7:1
Reserved
R/W
0
Reserved
SPI_TXENABLE
R/W
0
When asserted the internal value of txenable = '1'
0
8.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]
Figure 68. Alarm Mask 1 Register (ALM_MASK1)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 63. ALM_MASK1 Field Descriptions
Bit
15:0
Field
Type
Reset
Description
ALM_MASK1
R/W
0x00FF
Each bit is used to mask an alarm. Assertion masks the alarm:
bit 15 = mask lane7 lane errors
bit 14 = mask lane6 lane errors
bit 13 = mask lane5 lane errors
bit 12 = mask lane4 lane errors
bit 11 = mask lane3 lane errors
bit 10 = mask lane2 lane errors
bit 9 = mask lane1 lane errors
bit 8 = mask lane0 lane errors
bit 7 = mask lane7 FIFO flags
bit 6 = mask lane6 FIFO flags
bit 5 = mask lane5 FIFO flags
bit 4 = mask lane4 FIFO flags
bit 3 = mask lane3 FIFO flags
bit 2 = mask lane2 FIFO flags
bit 1 = mask lane1 FIFO flags
bit 0 = mask lane0 FIFO flags
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
81
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.17 Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]
Figure 69. Alarm Mask 2 Register (ALM_MASK2)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 64. ALM_MASK2 Field Descriptions
Bit
15:0
82
Field
Type
Reset
Description
ALMS_MASK2
R/W
0xFFFF
Each bit is used to mask an alarm. Assertion masks the alarm:
bit 15 = not used
bit 14 = not used
bit 13 = not used
bit 12 = mask SYSREF errors on link0
bit 11 = mask alarm from JESD shorttest
bit 10 = mask alarm from PAPD
bit 9 = mask alarm from PAPC
bit 8 = mask alarm from PAPB
bit 7 = mask alarm from PAPA
bit 6 = not used
bit 5 = not used
bit 4 = not used
bit 3 = not used
bit 2 = not used
bit 1 = mask alarm_clkdiv192_eq_zero
bit 0 = mask alarm_clkdiv192_eq_mult1
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.18 Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]
Figure 70. Alarm Mask 3 Register (ALM_MASK3)
15
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 65. ALM_MASK3 Field Descriptions
Bit
15:0
Field
Type
Reset
Description
ALMS_MASK3
R/W
0xFFFF
Each bit is used to mask an alarm. Assertion masks the alarm:
bit 15 = mask alarm_clkdiv8_eq_zero
bit 14 = mask alarm_clkdiv12_eq_zero
bit 13 = mask alarm_clkdiv16_eq_zero
bit 12 = mask alarm_clkdiv18_eq_zero
bit 11 = mask alarm_clkdiv20_eq_zero
bit 10 = mask alarm_clkdiv32_eq_zero
bit 9 = mask alarm_clkdiv36_eq_zero
bit 8 = mask alarm_clkdiv40_eq_zero
bit 7 = mask alarm_clkdiv48_eq_zero
bit 6 = mask alarm_clkdiv64_eq_zero
bit 5 = mask alarm_clkdiv72_eq_zero
bit 4 = mask alarm_clkdiv80_eq_zero
bit 3 = mask alarm_clkdiv96_eq_zero
bit 2 = maskalarm_ clkdiv128_eq_zero
bit 1 = mask alarm_clkdiv144_eq_zero
bit 0 = mask alarm_clkdiv160_eq_zero
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
83
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.19 Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]
Figure 71. Alarm Mask 4 Register (ALM_MASK4)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 66. ALM_MASK4 Field Descriptions
Bit
15:0
84
Field
Type
Reset
Description
ALMS_MASK4
R/W
0xFFFF
Each bit is used to mask an alarm. Assertion masks the alarm:
bit 15 = mask alarm_clkdiv8_eq_mult1
bit 14 = mask alarm_clkdiv12_eq_mult1
bit 13 = mask alarm_clkdiv16_eq_mult1
bit 12 = mask alarm_clkdiv18_eq_mult1
bit 11 = mask alarm_clkdiv20_eq_mult1
bit 10 = mask alarm_clkdiv32_eq_mult1
bit 9 = mask alarm_clkdiv36_eq_mult1
bit 8 = mask alarm_clkdiv40_eq_mult1
bit 7 = mask alarm_clkdiv48_eq_mult1
bit 6 = mask alarm_clkdiv64_eq_mult1
bit 5 = mask alarm_clkdiv72_eq_mult1
bit 4 = mask alarm_clkdiv80_eq_mult1
bit 3 = mask alarm_clkdiv96_eq_mult1
bit 2 = maskalarm_ clkdiv128_eq_mult1
bit 1 = mask alarm_clkdiv144_eq_mult1
bit 0 = mask alarm_clkdiv160_eq_mult1
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.20 JESD Lane Skew Register (address = 0x12) [reset = 0x0000]
Figure 72. JESD Lane Skew Register (JESD_LN_SKEW)
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
x
R
7
0
R
6
0
R
5
0
R
4
1
R
3
0
R
2
0
R
1
1
R
0
0
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 67. JESD_LN_SKEW Field Descriptions
Bit
Field
Type
Reset
Description
15:5
NOT USED
R
0x0000
Not used
4:0
MEMIN_LANE_SKEW
R
0b00000
Measure of the lane skew for each link only. Bits are
READ_ONLY
8.5.21 CMIX Configuration Register (address = 0x17) [reset = 0x0000]
Figure 73. CMIX Configuration Register (CMIX)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
0
R/W
2
1
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 68. CMIX Field Descriptions
Bit
Field
Type
Reset
Description
15:12
CMIX_AB
R/W
0x0
These bits turn on the different coarse mixing options.
Combining the different options together can result in every
possible n x Fs/8 [n=0->7]. Below is the valid programming
table:
cmix=(mem_fs8; mem_fs4; mem_fs2; mem_fsm4)
0000 : no mixing
0001 : -fs/4
0010 : fs/2
0100 : fs/4
1000 : fs/8
1100 : 3fs/8
1010 : 5fs/8
1110 : 7fs/8
11:4
Reserved
R/W
00000000
0
Reserved
0x0
These bits turn on the different coarse mixing options.
Combining the different options together can result in every
possible n x Fs/8 [n=0->7]. Below is the valid programming
table:
cmix=(mem_fs8; mem_fs4; mem_fs2; mem_fsm4)
0000 : no mixing
0001 : -fs/4
0010 : fs/2
0100 : fs/4
1000 : fs/8
1100 : 3fs/8
1010 : 5fs/8
1110 : 7fs/8
3:0
CMIX_CD
R/W
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
85
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.22 Output Summation and Delay Register (address = 0x19) [reset = 0x0000]
Figure 74. Output Summation and Delay Register (OUTSUM)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
0
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 69. OUTSUM Field Descriptions
Bit
Field
Type
Reset
Description
15:12
OUTPUT_DELAY
R/W
0x0
Delays the output to the DAC 0 to 15 clock cycles
11:4
Reserved
R/W
0x00
Reserved
0x0
Selects the output summing functions. Each bit selects another
sample to sum. Multiple bits can be selected.
bit 0 = add the path AB sample
bit 1 = add the path CD sample
bit 2 = add adjacent DAC path AB sample
bit 3 = add adjacent DAC path CD sample
3:0
OUTSUM_SEL
R/W
8.5.23 NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000]
Figure 75. NCO Phase Path AB Register (PHASE_NCOAB)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 70. PHASE_NCOAB Field Descriptions
Bit
15:0
Field
Type
Reset
Description
PHASE_NCO1
Auto
Sync
0x0000
The phase offset for the FULL NCO1 in the AB datapath.
8.5.24 NCO Phase Path CD Register (address = 0x1D) [reset = 0x0000]
Figure 76. NCO Phase Path CD Register (PHASE_NCOCD)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 71. PHASE_NCOCD Field Descriptions
Bit
15:0
86
Field
Type
Reset
Description
PHASE_NCO12
Auto
Sync
0x0000
The phase offset for the FULL NCO2 in the CD datapath.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.25 NCO Frequency Path AB Register (address = 0x1E-0x20) [reset = 0x0000 0000 0000]
Figure 77. NCO Frequency Path AB Register (FREQ_NCOAB)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 72. FREQ_NCOAB Field Descriptions
Bit
47:0
Field
Type
Reset
Description
FREQ_NCOAB
R/W
0x0000
0000
0000
NCO frequency word for AB data path.
8.5.26 NCO Frequency Path CD Register (address = 0x21-0x23) [reset = 0x0000 0000 0000]
Figure 78. NCO Frequency Path CD Register (FREQ_NCOCD)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 73. FREQ_NCOCD Field Descriptions
Bit
47:0
Field
FREQ_NCOCD
Type
Reset
Description
R/W
0x0000
0000
0000
NCO frequency word for CD data path.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
87
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]
Figure 79. SYSREF Use for Clock Divder Register (SYSREF_CLKDIV)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
0
R/W
2
1
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 74. SYSREF_CLKDIV Field Descriptions
88
Bit
Field
Type
Reset
Description
15
Reserved
R/W
0
Reserved
14:12
CDRVSER_SYSREF_DLY
R/W
000
Programmable delay the SYSREF by N dacclk cycles to the
CDRV_SER clock dividers. By offsetting the clock to the
different multi-DUC blocks, clock mixing could potentially be
reduced.
11:7
Not used
R/W
00000
Not used
6:4
SYSREF_MODE
R/W
001
Determines how SYSREF is used to sync the clock dividers in
the CDRV_SER block.
000 = Don’t use SYSREF pulse
001 = Use all SYSREF pulses
010 = Use only the next SYSREF pulse
011 = Skip one SYSREF pulse then use only the next one
100 = Skip one SYSREF pulse then use all pulses.
3:2
SYSREF_DLY
R/W
00
Delays the SYSREF into the CDRV_SER capture FF through 1
of 4 choices. This allows for extra delay in case the timing of the
clock or SYSREF path isn’t as good as we think.
1:0
Reserved
R/W
00
Reserved
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.28 Serdes Clock Control Register (address = 0x25) [reset = 0x7700]
Figure 80. Serdes Clock Control Register (SERDES_CLK)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
0
R/W
2
1
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 75. SERDES_CLK Field Descriptions
Bit
15:12
Field
Type
CLKJESD_DIV
R/W
Reset
Description
0x7
This controls the selection of the clk_jesd output
0000 = div4
0001 = div8
0010 = div12
0011 = div16
0100 = div18
0101 = div20
0110 = div24
0111 = div32
1001 = div36
1010 = div48
1011 = div64
1100 = div5.333
1101 = div10.666
1110 = div21p333
11:8
CLKJESD_OUT_DIV
R/W
0x7
This controls the selection of the clk_jesd_out output
0000 = div8
0001 = div16
0010 = div32
0011 = div48
0100 = div64
0101 = div80
0110 = div96
0111 = div128
1000 = div144
1001 = div160
1010 = div192
7:0
Reserved
R/W
0x0
Reserved
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
89
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.29 Sync Source Control 1 Register (address = 0x27) [reset = 0x1144]
Figure 81. Sync Source Control 1 Register (SYNCSEL1)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
0
R/W
2
1
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 76. SYNCSEL1 Field Descriptions
Bit
Field
15:12
11:8
7:4
3:0
90
SYNCSEL_MIXERAB
SYNCSEL_MIXERCD
SYNCSEL_NCOAB
SYNCSEL_NCOCD
Submit Documentation Feedback
Type
R/W
R/W
R/W
R/W
Reset
Description
0x1
Controls the syncing of the double buffered SPI registers for the
mixerAB block. These bits are enables so a ‘1’ in the bit place
allows the sync to pass to the block.
bit 0 = auto-sync from SPI register write
bit 1 = sysref
bit 2 = sync_out from JESD
bit 3 = mem_spi_sync
0x1
Controls the syncing of the double buffered SPI registers for the
mixerCD block. These bits are enables so a ‘1’ in the bit place
allows the sync to pass to the block.
bit 0 = auto-sync from SPI register write
bit 1 = sysref
bit 2 = sync_out from JESD
bit 3 = mem_spi_sync
0x4
Controls the syncing of NCOAB accumulators. These bits are
enables so a ‘1’ in the bit place allows the sync to pass to the
block.
bit 0 = ‘0’
bit 1 = sysref
bit 2 = sync_out from JESD
bit 3 = mem_spi_sync
0x4
Controls the syncing of NCOCD accumulators. These bits are
enables so a ‘1’ in the bit place allows the sync to pass to the
block.
bit 0 = ‘0’
bit 1 = sysref
bit 2 = sync_out from JESD
bit 3 = mem_spi_sync
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.30 Sync Source Control 2 Register (address = 0x28) [reset = 0x0000]
Figure 82. Sync Source Control 2 Register (SYNCSEL2)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 77. SYNCSEL2 Field Descriptions
Bit
Field
Type
Reset
Description
15:12
Reserved
R/W
0x0
Reserved
11:8
SYNCSEL_PAPAB
R/W
0x0
Select the sync for the PAP A and B.
bit 0 = ‘0’
bit 1 = sysref
bit 2 = sync_out from JESD
bit 3 = mem_spi_sync
7:4
SYNCSEL_PAPCD
R/W
0x0
Select the sync for the PAP C and D.
bit 0 = ‘0’
bit 1 = sysref
bit 2 = sync_out from JESD
bit 3 = mem_spi_sync
3:2
Reserved
R/W
0b00
Reserved
1
SPI_SYNC
R/W
0
This is used to generate the SPI_SYNC signal
0
Reserved
R/W
0
Reserved
8.5.31 PAP path AB Gain Attenuation Step Register (address = 0x29) [reset = 0x0000]
Figure 83. PAP path AB Gain Attenuation Step Register (PAP_GAIN_AB)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 78. PAP_GAIN_AB Field Descriptions
Bit
15:10
9:0
Field
Type
Reset
Description
NOT USED
RW
000000
Not Used
0x000
Gain attenuation step
PAPAB_GAIN_STEP
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
91
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.32 PAP path AB Wait Time Register (address = 0x2A) [reset = 0x0000]
Figure 84. PAP path AB Wait Time Register (PAP_WAIT_AB)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 79. PAP_WAIT_AB Field Descriptions
Bit
15:10
9:0
Field
Type
Reset
Description
Reserved
R/W
000000
Reserved
PAPAB_WAIT
R/W
0x000
Number of clock cycles to wait after gain = 0
8.5.33 PAP path CD Gain Attenuation Step Register (address = 0x2B) [reset = 0x0000]
Figure 85. PAP path CD Gain Attenuation Step Register (PAP_GAIN_CD)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 80. PAP_GAIN_CD Field Descriptions
Bit
15:10
9:0
Field
Type
Reset
Description
Not Used
R/W
000000
Not Used
PAPCD_GAIN_STEP
R/W
0x000
Gain attenuation step
8.5.34 PAP Path CD Wait Time Register (address = 0x2C) [reset = 0x0000]
Figure 86. PAP path CD Wait Time Register (PAP_WAIT_CD)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 81. PAP_WAIT_CD Field Descriptions
Bit
15:10
9:0
92
Field
Type
Reset
Description
Reserved
R/W
000000
Reserved
PAPCD_WAIT
R/W
0x000
Number of clock cycles to wait after gain = 0
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.35 PAP path AB Configuration Register (address = 0x2D) [reset = 0x0FFF]
Figure 87. PAP path AB Configuration Register (PAP_CFG_AB)
15
0
R/W
14
0
R/W
13
Reserved
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 82. PAP_CFG_AB Field Descriptions
Bit
15:14
13
12:0
Field
Type
Reset
Description
PAPAB_SEL_DLY
R/W
00
Controls the length of the delayline in the PAP AB logic.
00 : N =32
01 : N = 64
10 : N = 128
11 : Not Valid
Reserved
R/W
0
Reserved
PAPAB_THRESH
R/W
0xFFF
The threshold for the PAP AB trigger.
8.5.36 PAP path CD Configuration Register (address = 0x2E) [reset = 0x0FFF]
Figure 88. PAP path CD Configuration Register (PAP_CFG_CD)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 83. PAP_CFG_CD Field Descriptions
Bit
15:14
13
12:0
Field
Type
Reset
Description
PAPCD_SEL_DLY
R/W
00
Controls the length of the delay line in the PAP CD logic.
00 : N = 32
01 : N = 64
10 : N = 128
11 : Not Valid
Reserved
R/W
0
Reserved
PAPCD_THRESH
R/W
0xFFF
The threshold for the PAP CD trigger.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
93
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.37 DAC SPI Configuration Register (address = 0x2F) [reset = 0x0000]
Figure 89. DAC SPI Constant 1 Register (SPIDAC_TEST1)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 84. SPIDAC_TEST1 Field Descriptions
Bit
15:1
0
Field
Type
Reset
Description
Reserved
R/W
0x0000
Reserved
SPIDAC_ENA
R/W
0
When asserted the DAC output is set to the value in register
SPIDAC. This can be used for trim setting and other static tests.
8.5.38 DAC SPI Constant Register (address = 0x30) [reset = 0x0000]
Figure 90. DAC SPI Constant Register (SPIDAC_TEST2)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 85. SPIDAC_TEST2 Field Descriptions
Bit
15:0
94
Field
Type
Reset
Description
SPIDAC
R/W
0x0000
This value replaces the data at the output of the JESD so that
the DAC value can be controlled
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.39 Gain for path AB Register (address = 0x32) [reset = 0x0400]
Figure 91. Gain for path AB Register (GAINAB)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 86. GAINAB Field Descriptions
Bit
Field
Type
Reset
Description
15
GAINAB_ENA
R/W
0
Turns on the path AB gain block
14:12
Reserved
R/W
0x0
Reserved
11:0
GAINAB
R/W
0x400
Extra control of gain in the GAINAB block. This allows a fix gain
to be added to the signal if needed.
8.5.40 Gain for path CD Register (address = 0x33) [reset = 0x0400]
Figure 92. Gain for path CD Register (GAINCD)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 87. GAINCD Field Descriptions
Bit
Field
Type
Reset
Description
15
GAINCD_ENA
R/W
0
Turns on the Path CD gain block
14:12
Reserved
R/W
0x0
Reserved
11:0
GAINCD
R/W
0x400
Extra control of gain in the GAINCD block. This allows a fix gain
to be added to the signal if needed.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
95
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.41 JESD Error Counter Register (address = 0x41) [reset = 0x0000]
Figure 93. JESD Error Counter Register (JESD_ERR_CNT)
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
x
R
7
0
R
6
1
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
1
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 88. JESD_ERR_CNT Field Descriptions
Bit
15:0
Field
Type
Reset
Description
JESD_ERR_CNT
R
0x0000
This is the error count for the JESD link. This is a 16bit value
that is not cleared until the JESD synchronization is required or
errcnt_clr is programmed to '1'
8.5.42 JESD ID 1 Register (address = 0x46) [reset = 0x0044]
Figure 94. JESD ID 1 Register (JESD_ID1)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
1
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 89. JESD_ID1 Field Descriptions
Bit
Field
Type
Reset
Description
15:11
LID0
R/W
00000
JESD ID for lane 0
10:6
LID1
R/W
00001
JESD ID for lane 1
5:1
LID2
R/W
00010
JESD ID for lane 2
Reserved
R/W
0
Reserved
0
96
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.43 JESD ID 2 Register (address = 0x47) [reset = 0x190A]
Figure 95. JESD ID 2 Register (JESD_ID2)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
1
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 90. JESD ID 2 Register (JESD_ID2)
Bit
Field
Type
Reset
Description
15:11
LID3
R/W
00011
JESD ID for lane 3
10:6
LID4
R/W
00100
JESD ID for lane 4
5:1
LID5
R/W
00101
JESD ID for lane 5
Reserved
R/W
0
Reserved
0
8.5.44 JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]
Figure 96. JESD ID 3 Register (JESD_ID3)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 91. JESD_ID3 Field Descriptions
Bit
Field
Type
Reset
Description
15:11
LID6
R/W
00110
JESD ID for lane 6
10:6
LID7
R/W
00111
JESD ID for lane 7
5:4
Reserved
R/W
00
Reserved
3:1
SUBCLASSV
R/W
001
Selects the JESD subclass supported.
001 = subclass 1. Note: This is the only subclass mode
supported.
JESDV
R/W
1
Selects the version of JESD support(0=A; 1=B) NOTE: JESD
204B is only supported version.
0
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
97
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.45 JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]
Figure 97. JESD Lane Enable Register (JESD_LN_EN)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 92. JESD_LN_EN Field Descriptions
Bit
Field
15:8
Reset
Description
0x00
Turn on each lane as needed. Signal is active high.
bit 15 : lane7 enable
bit 14 : lane6 enable
bit 13 : lane5 enable
bit 12 : lane4 enable
bit 11 : lane3 enable
bit 10 : lane2 enable
bit 9 : lane1 enable
bit 8 : lane0 enable
7:6
JESD_TEST_SEQ
00
Set to select and verify link layer test sequences. The error for
these sequences comes out the lane alarms bit0. 1= a fail and 0
= pass.
00 : test sequence disabled
01 : verify repeating D.21.5 high frequency pattern for random
jitter
10 : verify repeating K.28.5 mixed frequency pattern for
deterministic jitter
11 : verify repeating ILA sequence
5:2
Reserved
0x0
Reserved
11
Used to tell the JESD block how many clock phases are being
used for lanes.
00 = 1 phase
01 = 2 phases
10 = 4 phases
11 = 8 phases
1:0
98
LANE_ENA
Type
JESD_PHASE_MODE
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.46 JESD RBD Buffer and Frame Octets Register (address = 0x4B) [reset = 0x1300]
Figure 98. JESD RBD Buffer and Frame Octets Register (JESD_RBD_F)
15
14
13
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
R/W
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
0
R/W
3
2
0
R/W
1
1
R/W
0
1
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 93. JESD_RBD_F Field Descriptions
Bit
Field
Type
Reset
Description
15:13
Reserved
R/W
00
Reserved
12:8
RBD
R/W
10011
This controls the amount of elastic buffers being used in the
JESD. Larger numbers will mean more latency; but smaller
numbers may not hold enough data to capture the input skew.
This value must always be ≤ mem_k
7:0
F_M1
R/W
0x00
This is the number of octets in the frame - 1
8.5.47 JESD K and L Parameters Register (address = 0x4C) [reset = 0x1303]
Figure 99. JESD K and L Parameters Register (JESD_K_L)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 94. JESD_K_L Field Descriptions
Field
Type
Reset
Description
15:13
Bit
Reserved
R/W
000
Reserved
12:8
K_M1
R/W
10011
The number of frames in a multi-frame - 1. 0 ≤ k - 1 < 32
7:5
Reserved
R/W
0
Reserved
4:0
L_M1
R/W
00011
The number of lanes used by the JESD - 1. 0 ≤ L -1 < 8
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
99
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.48 JESD M and S Parameters Register (address = 0x4D) [reset = 0x0100]
Figure 100. JESD M and S Parameters Register (JESD_M_S)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 95. JESD_M_S Field Descriptions
Bit
Field
Type
Reset
Description
15:8
M_M1
R/W
0x01
The number of streams per frame - 1. 0 ≤ M - 1 < 256
7:5
Reserved
R/W
000
Reserved
4:0
S_M1
R/W
00000
The number of samples per stream per frame - 1.
8.5.49 JESD N, HD and SCR Parameters Register (address = 0x4E) [reset = 0x0F4F]
Figure 101. JESD N, HD and SCR Parameters Register (JESD_N_HD_SCR)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 96. JESD_N_HD_SCR Field Descriptions
Field
Type
Reset
Description
15:13
Bit
Reserved
R/W
000
Reserved
12:8
100
NPRIME_M1
R/W
01111
The number of adjusted bits per sample - 1
7
Reserved
R/W
0
Reserved
6
HD
R/W
1
High density mode. Samples can cross the lane boundary
5
SCR
R/W
0
Turn on the scrambler
4:0
N_M1
R/W
01111
The number of bits per sample - 1
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.50 JESD Character Match and Other Register (address = 0x4F) [reset = 0x1CC1]
Figure 102. JESD Character Match and Other Parameters Register (JESD_MATCH)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 97. JESD_MATCH Field Descriptions
Bit
Field
Type
Reset
Description
MATCH_DATA
R/W
0x1C
The character to match for buffer release. Normally it is a
/R/=/K28.0/-0x1C but with these bits the user can program the
value.
7
MATCH_SPECIFIC
R/W
1
Match a specific character to start the JESD buffering when
asserted; otherwise the first non-K will start the buffering.
6
MATCH_CTRL
R/W
1
When asserted the match character is a CONTROL character
instead of a DATA character.
5
NO_LANE_SYNC
R/W
0
Assert if the TX side does not support lane initialization. This
way the RX won’t flag errors in the configuration portion of the
ILA.
4:2
Not Used
R/W
000
Not Used
1
Reserved
R/W
0
Reserved
0
JESD_COMMAALIGN_ENA
R/W
1
When asserted the JESD block SERDES comma align signal
will be added with the SERDES ALIGN bit(0) to control when to
shut off comma alignment. When this bit is deasserted; then the
programmed bit(spi_config62(11)) is the only control.
15:8
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
101
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.51 JESD Link Configuration Data Register (address = 0x50) [reset = 0x0000]
Figure 103. JESD Link Configuration Data Register (JESD_LINK_CFG)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 98. JESD_Link_CFG Field Descriptions
Bit
Field
Type
Reset
Description
15:12
ADJCNT
R/W
0x0
Lane configuration data for link. Reserved by DAC38RF8x
except for lane configuration checking.
11
ADJDIR
R/W
0
Lane configuration data for link. Reserved by DAC38RF8x
except for lane configuration checking.
10:7
BID
R/W
0x0
Lane configuration data for link. Reserved by DAC38RF8x
except for lane configuration checking.
6:2
CF
R/W
00000
Lane configuration data for link. Reserved by DAC38RF8x
except for lane configuration checking.
1:0
CS
R/W
00
Lane configuration data for link. Reserved by DAC38RF8x
except for lane configuration checking.
8.5.52 JESD Sync Request Register (address = 0x51) [reset = 0x00FF]
Figure 104. JESD Sync Request Register (JESD_SYNC_REQ)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 99. JESD_SYNC_REQ Field Descriptions
Bit
15:8
7:0
102
Field
Type
Reset
Description
DID
R/W
0x00
Lane configuration
0xFF
These bits select which errors cause a sync request. Sync
requests take priority over the error notification; so if sync
request isn’t desired; set these bits to a ‘0’.
bit 7 = multi-frame alignment error
bit 6 = frame alignment error
bit 5 = link configuration error
bit 4 = elastic buffer overflow (bad RBD value)
bit 3 = elastic buffer end char mismatch (match_ctrl match_data)
bit 2 = code synchronization error
bit 1 = 8b/10b not-in-table code error
bit 0 = 8b/10b disparity error
SYNC_REQUEST
Submit Documentation Feedback
R/W
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.53 JESD Error Output Register (address = 0x52) [reset = 0x00FF]
Figure 105. JESD Error Output Register (JESD_ERR_OUT)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 100. JESD_ERR_OUT Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
R/W
000000
Reserved
9
DISABLE_ERR_RPT
R/W
0
Assertion means that errors will not be reported on the sync_n
output.
8
PHADJ
R/W
0
Lane configuration
0xFF
These bits select the errors generated are counted in the err_c
for the link. The bits also control what signals are sent out the
pad_syncb pin for error notification.
bit 7 = multi-frame alignment error
bit 6 = frame alignment error
bit 5 = link configuration error
bit 4 = elastic buffer overflow (bad RBD value)
bit 3 = elastic buffer end char mismatch (match_ctrl match_data)
bit 2 = code synchronization error
bit 1 = 8b/10b not-in-table code error
bit 0 = 8b/10b disparity error
15:10
7:0
ERR_ENA
R/W
8.5.54 JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]
Figure 106. JESD ILA Check 1 Register (JESD_ILA_CFG1)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 101. JESD_ILA_CFG1 Field Descriptions
Bit
Field
Type
Reset
Description
15:8
ILA_M
R/W
0x01
JESD M-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
7:0
ILA_F
R/W
0x00
JESD F-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
103
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.55 JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]
Figure 107. JESD ILA Check 2 Register (JESD_ILA_CFG2)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
1
R/W
3
0
R/W
2
1
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 102. JESD_ILA_CFG2 Field Descriptions
Bit
Field
Type
Reset
Description
15
ILA_HD
R/W
1
JESD HD configuration value used only for ILA checking; may
be set independently of the actual JESD mode
14:10
ILA_L
R/W
00011
JESD L-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
9:5
ILA_K
R/W
10011
JESD K-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
4:0
ILA_S
R/W
00000
JESD S-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
8.5.56 JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]
Figure 108. JESD SYSREF Mode Register (JESD_SYSR_MODE)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 103. JESD_SYSR_MODE Field Descriptions
Bit
15:4
3
2:0
104
Field
Type
Reset
Description
Reserved
R/W
0x000
Reserved
ERR_CNT_CLR
R/W
0
A transition from 0->1 causes the error_cnt to be cleared
001
Determines how SYSREF is used in the JESD synchronizing
block.
000 = Don’t use SYSREF pulse
001 = Use all SYSREF pulses
010 = Use only the next SYSREF pulse
011 = Skip one SYSREF pulse then use only the next one
100 = Skip one SYSREF pulse then use all pulses.
101 = skip two SYSREFs and then use one
110 = skip two SYSREFs and then use all
SYSREF_MODE
Submit Documentation Feedback
R/W
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.57 JESD Crossbar Configuration 1 Register (address = 0x5F) [reset = 0x0123]
Figure 109. JESD Crossbar Configuration 1 Register (JESD_CROSSBAR1)
15
Reserved
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
Reserved
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 104. JESD_CROSSBAR1 Field Descriptions
Bit
Field
Type
Reset
Description
15
Reserved
R/W
0
Reserved
14:12
11
10:8
7
6:4
3
2:0
OCTETPATH0_SEL
R/W
000
These bits are used by the cross-bar switch to map any lane to
any other lane. The 3 bit term tells the mapper block what lane
this particular lane is supposed to be treated as.
000 = treat as lane0
001 = treat as lane1
010 = treat as lane2
011 = treat as lane3
100 = treat as lane4
101 = treat as lane5
110 = treat as lane6
111 = treat as lane7
Reserved
R/W
0
Reserved
OCTETPATH1_SEL
R/W
001
These bits are used by the cross-bar switch to map any lane to
any other lane. The 3 bit term tells the mapper block what lane
this particular lane is supposed to be treated as.
000 = treat as lane0
001 = treat as lane1
010 = treat as lane2
011 = treat as lane3
100 = treat as lane4
101 = treat as lane5
110 = treat as lane6
111 = treat as lane7
Reserved
R/W
0
Reserved
OCTETPATH2_SEL
R/W
010
These bits are used by the cross-bar switch to map any lane to
any other lane. The 3 bit term tells the mapper block what lane
this particular lane is supposed to be treated as.
000 = treat as lane0
001 = treat as lane1
010 = treat as lane2
011 = treat as lane3
100 = treat as lane4
101 = treat as lane5
110 = treat as lane6
111 = treat as lane7
Reserved
R/W
0
Reserved
011
These bits are used by the cross-bar switch to map any lane to
any other lane. The 3 bit term tells the mapper block what lane
this particular lane is supposed to be treated as.
000 = treat as lane0
001 = treat as lane1
010 = treat as lane2
011 = treat as lane3
100 = treat as lane4
101 = treat as lane5
110 = treat as lane6
111 = treat as lane7
OCTETPATH3_SEL
R/W
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
105
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.58 JESD Crossbar Configuration 2 Register (address = 0x60) [reset = 0x4567]
Figure 110. JESD Crossbar Configuration 2 Register (JESD_CROSSBAR2)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
1
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 105. JESD_CROSSBAR2 Field Descriptions
Bit
Field
Type
Reset
Description
15
Reserved
R/W
0
Reserved
14:12
11
10:8
7
6:4
3
2:0
106
OCTETPATH4_SEL
R/W
100
These bits are used by the cross-bar switch to map any lane to
any other lane. The 3 bit term tells the mapper block what lane
this particular lane is supposed to be treated as.
000 = treat as lane0
001 = treat as lane1
010 = treat as lane2
011 = treat as lane3
100 = treat as lane4
101 = treat as lane5
110 = treat as lane6
111 = treat as lane7
Reserved
R/W
0
Reserved
OCTETPATH5_SEL
R/W
101
These bits are used by the cross-bar switch to map any lane to
any other lane. The 3 bit term tells the mapper block what lane
this particular lane is supposed to be treated as.
000 = treat as lane0
001 = treat as lane1
010 = treat as lane2
011 = treat as lane3
100 = treat as lane4
101 = treat as lane5
110 = treat as lane6
111 = treat as lane7
Reserved
R/W
0
Reserved
OCTETPATH6_SEL
R/W
110
These bits are used by the cross-bar switch to map any lane to
any other lane. The 3 bit term tells the mapper block what lane
this particular lane is supposed to be treated as.
000 = treat as lane0
001 = treat as lane1
010 = treat as lane2
011 = treat as lane3
100 = treat as lane4
101 = treat as lane5
110 = treat as lane6
111 = treat as lane7
Reserved
R/W
0
Reserved
111
These bits are used by the cross-bar switch to map any lane to
any other lane. The 3 bit term tells the mapper block what lane
this particular lane is supposed to be treated as.
000 = treat as lane0
001 = treat as lane1
010 = treat as lane2
011 = treat as lane3
100 = treat as lane4
101 = treat as lane5
110 = treat as lane6
111 = treat as lane7
OCTETPATH7_SEL
Submit Documentation Feedback
R/W
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.59 JESD Alarms for Lane 0 Register (address = 0x64) [reset = 0x0000]
Figure 111. JESD Alarms for Lane 0 Register (JESD_ALM_L0)
15
0
W0C
14
0
W0C
13
0
W0C
12
0
W0C
11
0
W0C
10
0
W0C
9
0
W0C
8
x
W0C
7
0
W0C
6
1
W0C
5
1
W0C
4
0
W0C
3
0
W0C
2
1
W0C
1
0
W0C
0
0
W0C
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset
Table 106. JESD_ALM_L0 Field Descriptions
Bit
Field
Type
Reset
Description
15:8
ALM_LANE0_ERR
W0C
0x00
Lane0 errors:
bit 15 = multiframe alignment error
bit 14 = frame alignment error
bit 13 = link configuration error
bit 12 = elastic buffer overflow (bad RBD value)
bit 11 = elastic buffer match error. The first non-/K/ doesn’t
match “match_ctrl” and “match_data” programmed values.
bit 10 = code synchronization error
bit 9 = 8b/10b not-in-table code error
bit 8 = 8b/10b disparity error
7:4
Reserved
W0C
0x0
Reserved
0x0
Lane0 FIFO errors:
bit 3 = write_error : High if write request and FIFO is full (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 2 = write_full : FIFO is FULL
bit 1 = read_error : High if read request with empty FIFO (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 0 = read_empty : FIFO is empty
3:0
ALM_FIFO0_FLAGS
W0C
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
107
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.60 JESD Alarms for Lane 1 Register (address = 0x65) [reset = 0x0000]
Figure 112. JESD Alarms for Lane 1 Register (JESD_ALM_L1)
15
0
W0C
14
0
W0C
13
0
W0C
12
0
W0C
11
0
W0C
10
0
W0C
9
0
W0C
8
x
W0C
7
0
W0C
6
1
W0C
5
1
W0C
4
0
W0C
3
0
W0C
2
1
W0C
1
0
W0C
0
1
W0C
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset
Table 107. JESD_ALM_L1 Field Descriptions
Bit
Type
Reset
Description
15:8
ALM_LANE1_ERR
W0C
0x00
Lane1 errors:
bit 15 = multiframe alignment error
bit 14 = frame alignment error
bit 13 = link configuration error
bit 12 = elastic buffer overflow (bad RBD value)
bit 11 = elastic buffer match error. The first non-/K/ doesn’t
match “match_ctrl” and “match_data” programmed values.
bit 10 = code synchronization error
bit 9 = 8b/10b not-in-table code error
bit 8 = 8b/10b disparity error
7:4
Reserved
W0C
0x0
Reserved
0x0
Lane1 FIFO errors:
bit 3 = write_error : High if write request and FIFO is full (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 2 = write_full : FIFO is FULL
bit 1 = read_error : High if read request with empty FIFO (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 0 = read_empty : FIFO is empty
3:0
108
Field
ALM_FIFO1_FLAGS
Submit Documentation Feedback
W0C
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.61 JESD Alarms for Lane 2 Register (address = 0x66) [reset = 0x0000]
Figure 113. JESD Alarms for Lane 2 Register (JESD_ALM_L2)
15
0
W0C
14
0
W0C
13
0
W0C
12
0
W0C
11
0
W0C
10
0
W0C
9
0
W0C
8
x
W0C
7
0
W0C
6
1
W0C
5
1
W0C
4
0
W0C
3
0
W0C
2
1
W0C
1
1
W0C
0
0
W0C
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset
Table 108. JESD_ALM_L2 Field Descriptions
Bit
Field
Type
Reset
Description
15:8
ALM_LANE2_ERR
W0C
0x00
Lane2 errors:
bit 15 = multiframe alignment error
bit 14 = frame alignment error
bit 13 = link configuration error
bit 12 = elastic buffer overflow (bad RBD value)
bit 11 = elastic buffer match error. The first non-/K/ doesn’t
match “match_ctrl” and “match_data” programmed values.
bit 10 = code synchronization error
bit 9 = 8b/10b not-in-table code error
bit 8 = 8b/10b disparity error
7:4
Reserved
W0C
0x0
Reserved
0x0
Lane2 FIFO errors:
bit 3 = write_error : High if write request and FIFO is full (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 2 = write_full : FIFO is FULL
bit 1 = read_error : High if read request with empty FIFO (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 0 = read_empty : FIFO is empty
3:0
ALM_FIFO2_FLAGS
W0C
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
109
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.62 JESD Alarms for Lane 3 Register (address = 0x67) [reset = 0x0000]
Figure 114. JESD Alarms for Lane 3 Register (JESD_ALM_L3)
15
0
W0C
14
0
W0C
13
0
W0C
12
0
W0C
11
0
W0C
10
0
W0C
9
0
W0C
8
x
W0C
7
0
W0C
6
1
W0C
5
1
W0C
4
0
W0C
3
0
W0C
2
1
W0C
1
1
W0C
0
1
W0C
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset
Table 109. JESD_ALM_L3 Field Descriptions
Bit
Type
Reset
Description
15:8
ALM_LANE3_ERR
W0C
0x00
Lane3 errors:
bit 15 = multiframe alignment error
bit 14 = frame alignment error
bit 13 = link configuration error
bit 12 = elastic buffer overflow (bad RBD value)
bit 11 = elastic buffer match error. The first non-/K/ doesn’t
match “match_ctrl” and “match_data” programmed values.
bit 10 = code synchronization error
bit 9 = 8b/10b not-in-table code error
bit 8 = 8b/10b disparity error
7:4
Reserved
W0C
0x0
Reserved
0x0
Lane3 FIFO errors:
bit 3 = write_error : High if write request and FIFO is full (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 2 = write_full : FIFO is FULL
bit 1 = read_error : High if read request with empty FIFO (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 0 = read_empty : FIFO is empty
3:0
110
Field
ALM_FIFO3_FLAGS
Submit Documentation Feedback
W0C
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.63 JESD Alarms for Lane 4 Register (address = 0x68) [reset = 0x0000]
Figure 115. JESD Alarms for Lane 4 Register (JESD_ALM_L4)
15
0
W0C
14
0
W0C
13
0
W0C
12
0
W0C
11
0
W0C
10
0
W0C
9
0
W0C
8
x
W0C
7
0
W0C
6
1
W0C
5
1
W0C
4
0
W0C
3
1
W0C
2
0
W0C
1
0
W0C
0
0
W0C
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset
Table 110. JESD_ALM_L4 Field Descriptions
Bit
Field
Type
Reset
Description
15:8
ALM_LANE4_ERR
W0C
0x00
Lane4 errors:
bit 15 = multiframe alignment error
bit 14 = frame alignment error
bit 13 = link configuration error
bit 12 = elastic buffer overflow (bad RBD value)
bit 11 = elastic buffer match error. The first non-/K/ doesn’t
match “match_ctrl” and “match_data” programmed values.
bit 10 = code synchronization error
bit 9 = 8b/10b not-in-table code error
bit 8 = 8b/10b disparity error
7:4
Reserved
W0C
0x0
Reserved
0x0
Lane4 FIFO errors:
bit 3 = write_error : High if write request and FIFO is full (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 2 = write_full : FIFO is FULL
bit 1 = read_error : High if read request with empty FIFO (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 0 = read_empty : FIFO is empty
3:0
ALM_FIFO4_FLAGS
W0C
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
111
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.64 JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]
Figure 116. JESD Alarms for Lane 5 Register (JESD_ALM_L5)
15
0
W0C
14
0
W0C
13
0
W0C
12
0
W0C
11
0
W0C
10
0
W0C
9
0
W0C
8
x
W0C
7
0
W0C
6
1
W0C
5
1
W0C
4
0
W0C
3
1
W0C
2
0
W0C
1
0
W0C
0
1
W0C
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset
Table 111. JESD_ALM_L5 Field Descriptions
Bit
Type
Reset
Description
15:8
ALM_LANE5_ERR
W0C
0x00
Lane5 errors:
bit 15 = multiframe alignment error
bit 14 = frame alignment error
bit 13 = link configuration error
bit 12 = elastic buffer overflow (bad RBD value)
bit 11 = elastic buffer match error. The first non-/K/ doesn’t
match “match_ctrl” and “match_data” programmed values.
bit 10 = code synchronization error
bit 9 = 8b/10b not-in-table code error
bit 8 = 8b/10b disparity error
7:4
Reserved
W0C
0x0
Reserved
0x0
Lane5 FIFO errors:
bit 3 = write_error : High if write request and FIFO is full (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 2 = write_full : FIFO is FULL
bit 1 = read_error : High if read request with empty FIFO (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 0 = read_empty : FIFO is empty
3:0
112
Field
ALM_FIFO5_FLAGS
Submit Documentation Feedback
W0C
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.65 JESD Alarms for Lane 6 Register (address = 0x6A [reset = 0x0000]
Figure 117. JESD Alarms for Lane 6 Register (JESD_ALM_L6)
15
0
W0C
14
0
W0C
13
0
W0C
12
0
W0C
11
0
W0C
10
0
W0C
9
0
W0C
8
x
W0C
7
0
W0C
6
1
W0C
5
1
W0C
4
0
W0C
3
1
W0C
2
0
W0C
1
1
W0C
0
0
W0C
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset
Table 112. JESD_ALM_L6 Field Descriptions
Bit
Field
Type
Reset
Description
15:8
ALM_LANE6_ERR
W0C
0x00
Lane6 errors:
bit 15 = multiframe alignment error
bit 14 = frame alignment error
bit 13 = link configuration error
bit 12 = elastic buffer overflow (bad RBD value)
bit 11 = elastic buffer match error. The first non-/K/ doesn’t
match “match_ctrl” and “match_data” programmed values.
bit 10 = code synchronization error
bit 9 = 8b/10b not-in-table code error
bit 8 = 8b/10b disparity error
7:4
Reserved
W0C
0x0
Reserved
0x0
Lane6 FIFO errors:
bit 3 = write_error : High if write request and FIFO is full (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 2 = write_full : FIFO is FULL
bit 1 = read_error : High if read request with empty FIFO (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 0 = read_empty : FIFO is empty
3:0
ALM_FIFO6_FLAGS
W0C
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
113
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.66 JESD Alarms for Lane 7 Register (address = 0x6B) [reset = 0x0000]
Figure 118. JESD Alarms for Lane 7 Register (JESD_ALM_L7)
15
0
W0C
14
0
W0C
13
0
W0C
12
0
W0C
11
0
W0C
10
0
W0C
9
0
W0C
8
x
W0C
7
0
W0C
6
1
W0C
5
1
W0C
4
0
W0C
3
1
W0C
2
0
W0C
1
1
W0C
0
1
W0C
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset
Table 113. JESD Alarms for Lane 7 Register (JESD_ALM_L7)
Bit
Field
Type
Reset
Description
15:8
ALM_LANE7_ERR
W0C
0x00
Lane7 errors:
bit 15 = multiframe alignment error
bit 14 = frame alignment error
bit 13 = link configuration error
bit 12 = elastic buffer overflow (bad RBD value)
bit 11 = elastic buffer match error. The first non-/K/ doesn’t
match “match_ctrl” and “match_data” programmed values.
bit 10 = code synchronization error
bit 9 = 8b/10b not-in-table code error
bit 8 = 8b/10b disparity error
7:4
Reserved
W0C
0x0
Reserved
0x0
Lane7 FIFO errors:
bit 3 = write_error : High if write request and FIFO is full (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 2 = write_full : FIFO is FULL
bit 1 = read_error : High if read request with empty FIFO (NOTE:
only released when JESD block is initialize with mem_init_state)
bit 0 = read_empty : FIFO is empty
3:0
ALM_FIFO7_FLAGS
W0C
8.5.67 SYSREF and PAP Alarms Register (address = 0x6C) [reset = 0x0000]
Figure 119. SYSREF and PAP Alarms Register (ALM_SYSREF_PAP)
15
0
W0C
14
0
W0C
13
0
W0C
12
0
W0C
11
0
W0C
10
0
W0C
9
0
W0C
8
x
W0C
7
0
W0C
6
1
W0C
5
1
W0C
4
0
W0C
3
1
W0C
2
1
W0C
1
0
W0C
0
0
W0C
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset
Table 114. ALM_SYSREF_PAP Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
W0C
0
Reserved
12
ALM_SYSREF_ERR
W0C
Alarm caused when the sysref is placed at an incorrect location
11
ALM_FROM_SHORTTEST
W0C
This is the alarm from JESD during the SHORT TEST checking.
10:7
ALM_PAP
W0C
0x0
The alarms from the PAP blocks indicated which PAP was
triggered. bit0 = PAPA bit1 = PAPB bit2 = PAPC bit3 = PAPD
6:2
Reserved
W0C
0x0
Reserved
1
ALM_DIV192_ZERO
W0C
0
This is asserted if the clkdiv192 in the CDRV_SER shift register
is all zeros.
0
Not Used
W0C
0
Not Used
15:13
114
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.68 Clock Divider Alarms 1 Register (address = 0x6D) [reset = 0x0000]
Figure 120. Clock Divider Alarms 1 Register (ALM_CLKDIV1)
15
0
W0C
14
0
W0C
13
0
W0C
12
0
W0C
11
0
W0C
10
0
W0C
9
0
W0C
8
x
W0C
7
0
W0C
6
1
W0C
5
1
W0C
4
0
W0C
3
1
W0C
2
1
W0C
1
0
W0C
0
1
W0C
LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset; -n = value after reset
Table 115. ALM_CLKDIV1 Field Descriptions
Bit
Field
Type
Reset
Description
15
ALM_DIV8_ZERO
W0C
0
Asserted if the clkdiv8 in the CDRV_SER shift register is all
zeros.
14
ALM_DIV12_ZERO
W0C
0
Asserted if the clkdiv12 in the CDRV_SER shift register is all
zeros.
13
ALM_DIV16_ZERO
W0C
0
Asserted if the clkdiv16 in the CDRV_SER shift register is all
zeros.
12
ALM_DIV24_ZERO
W0C
0
Asserted if the clkdiv24 in the CDRV_SER shift register is all
zeros. (Connected to the div18 port)
11
ALM_DIV20_ZERO
W0C
0
Asserted if the clkdiv20 in the CDRV_SER shift register is all
zeros.
10
ALM_DIV32_ZERO
W0C
0
Asserted if the clkdiv32 in the CDRV_SER shift register is all
zeros.
9
ALM_DIV36_ZERO
W0C
0
Asserted if the clkdiv36 in the CDRV_SER shift register is all
zeros.
8
ALM_DIV40_ZERO
W0C
0
Asserted if the clkdiv40 in the CDRV_SER shift register is all
zeros.
7
ALM_DIV48_ZERO
W0C
0
Asserted if the clkdiv48 in the CDRV_SER shift register is all
zeros.
6
ALM_DIV64_ZERO
W0C
0
Asserted if the clkdiv64 in the CDRV_SER shift register is all
zeros.
5
ALM_DIV72_ZERO
W0C
0
Asserted if the clkdiv72 in the CDRV_SER shift register is all
zeros.
4
ALM_DIV80_ZERO
W0C
0
Asserted if the clkdiv80 in the CDRV_SER shift register is all
zeros.
3
ALM_DIV96_ZERO
W0C
0
Asserted if the clkdiv96 in the CDRV_SER shift register is all
zeros.
2
ALM_DIV128_ZERO
W0C
0
Asserted if the clkdiv128 in the CDRV_SER shift register is all
zeros.
1
ALM_DIV144_ZERO
W0C
0
Asserted if the clkdiv144 in the CDRV_SER shift register is all
zeros.
0
ALM_DIV160_ZERO
W0C
0
Asserted if the clkdiv160 in the CDRV_SER shift register is all
zeros.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
115
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.69 Clock Configuration Register (address = 0x0A) [reset = 0xFC03]
Figure 121. Clock Configuration Register (CLK_CONFIG)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 116. CLK_CONFIG Field Descriptions
Bit
Field
Type
Reset
Description
15
RCLK_SYNC_ENA
RW
1
When asserted the sysref is used to sync the clock divider in the
centralclkdiv. This should be disabled after initial syncing.
14
FRCLK_DIV_ENA
RW
1
When asserted the full rate clock divider that provides the DIV4
phases to the DACs is enabled
13
DACA_FRCLK_ENA
RW
1
When asserted the full rate clock to the DACA block is enabled
12
DACB_FRCLK_ENA
RW
1
When asserted the full rate clock to the DACB block is enabled
11
DACA_DUMDATA
RW
0
Enables distortion enhancement for DACA when set high
10
DACB_DUMDATA
RW
0
Enables distortion enhancement for DACB when set high
9:2
Reserved
RW
0x000
Reserved
1
QRCLOCK_DACA_ENA
RW
1
Turns on the quarter rate clock for DACA when '1'
0
QRCLOCK_DACB_ENA
RW
1
Turns on the quarter rate clock for DACB when '1'
8.5.70 Sleep Configuration Register (address = 0x0B) [reset = 0x0022]
Figure 122. Clock Configuration Register (SLEEP_CONFIG)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 117. SLEEP_CONFIG Field Descriptions
Bit
15:9
116
Field
Type
Reset
Description
Reserved
RW
0000000
Reserved
8
VBGR_SLEEP
RW
0
Turns off the 'bandgap-over-R' bias
7
Reserved
RW
0
Reserved
6
TSENSE_SLEEP
RW
0
Turns off the temperature sensor
5
PLL_SLEEP
RW
1
Puts the PLL into sleep mode (FUSE Controlled)
4
CLKRECV_SLEEP
RW
0
When asserted the clock input receiver gets put into sleep
mode. This also affects the FIFO_OSTR receiver as well.
3
DACA_SLEEP
RW
0
Puts the DACA into sleep mode
2
DACB_SLEEP
RW
0
Puts the DACB into sleep mode
1
CLK_TX_SLEEP
RW
1
When asserted the PLL TX clock output is in low power mode.
0
Reserved
RW
0
Reserved
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.71 Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x2002]
Figure 123. Divided Output Clock Configuration Register (CLK_OUT)
15
1
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 118. CLK_OUT Field Descriptions
Bit
Field
Type
Reset
Description
15
CLK_TX_IDLE
R/W
1
When high puts the CLK_TX circuitry in idle mode during which
the CLKTX+ and CLKTX- output pins are driven to the proper
common-mode levels in order to charge the external AC
coupling caps. When low allows the divided clock to be driven
onto the CLKTX+ and CLKTX- output pins.
CLK_TX_DIVSELECT
R/W
01
Selects either div2, div3 or div 4 output.
00 = divided by 3
01 = divided by 4
10 = divided by 2
11 = not valid
14:13
Reserved
R/W
0
Reserved
11:8
12
CLK_TX_SWING
R/W
0x0
Sets desired swing on CLKTX+ and CLKTX- outputs in mVppdiff
0x0 125
0x1 232
0x2 337
0x3 440
0x4 540
0x5 639
0x6 736
0x7 831
0x8 924
0x9 1012
0xA 1097
0xB 1178
0xC 1255
0xD 1329
0xE 1398
0xF 1462
7:3
Reserved
R/W
00000
Reserved
2
CLK_TX_FLIP
R/W
0
Flips the polarity of CLKTX
1
TX_SYNC_ENA
R/W
1
Syncs the CLKTX with SYSREF when asserted
0
EXTREF_ENA
R/W
0
Allows the chip to use an external refernce(1) or the internal
reference(0)
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
117
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.72 DAC Fullscale Current Register (address = 0x0D) [reset = 0xF000]
Figure 124. DAC Fullscale Current Register (DACFS)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 119. DACFS Field Descriptions
Bit
Field
Type
Reset
Description
15:12
DACFS
R/W
0xF
Scales the output current is 16 equal steps from 10-40mA
(10mA + 2mA*DACFS)
11:0
Reserved
R/W
0x000
Reserved
8.5.73 Internal SYSREF Generator Register (address = 0x10) [reset = 0x0000]
Figure 125. Internal SYSREF Register (LCMGEN)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 120. LCMGEN Field Descriptions (1)
Bit
Field
Type
Reset
Description
Reserved
R/W
0x00
Reserved
3
LCMGEN_ENA
R/W
0
Enables the LCM custom logic
2
LCMGEN_RESET
R/W
0
Reset the LCM custom logic
1
LCMGEN_SPI_SYSREF_ENA
R/W
0
Enables SPI SYSREF for Internal SYSREF Generator
0
LCM_SYSREF_OUTSEL
R/W
0
Chooses between internal and external SYSREF
15:4
(1)
DACCLK must be ≤ 1Gsps for this function to work.
8.5.74 Counter for Internal SYSREF Generator Register (address = 0x11) [reset = 0x0000]
Figure 126. Counter for Internal SYSREF Generator Register (LCMGEN_DIV)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 121. LCMGEN_DIV Field Descriptions (1)
Bit
15:0
(1)
118
Field
Type
Reset
Description
LCMGEN_DIV
R/W
0x00
Counter setting for the LCMGEN block
DACCLK must be ≤ 1Gsps for this function to work.
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.75 SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]
Figure 127. SPI SYSREF for Internal SYSREF Generator Register (LCMGEN_SPISYSREF)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 122. LCMGEN_SPISYSREF Field Descriptions (1)
Bit
15:1
0
(1)
Field
Type
Reset
Description
Reserved
R/W
0x00
Reserved
LCMGEN_SPI_SYSREF
R/W
0
SPI SYSREF for the LCMGEN block
DACCLK must be ≤ 1Gsps for this function to work.
8.5.76 Digital Test Signals Register (address = 0x1B) [reset = 0x0000]
Figure 128. Digital Test Signals Register (DTEST)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
1
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 123. DTEST Field Descriptions
Bit
Field
Type
Reset
Description
15
Reserved
R/W
0
Reserved
DTEST_LANE
R/W
000
Selects the lane to check for the signals selected by field
DTEST
14:12
11:8
DTEST
R/W
0x0
Allows digital test signals to come out the ALARM pin.
0000 : Test disabled; normal ALARM pin function
0001 : SERDES lanes 0 – 3 PLL clock/80
0010 : SERDES lanes 4 – 7 PLL clock/80
0011 : TESTFAIL (lane selected by field DTEST_LANE)
0100 : SYNC (lane selected by field DTEST_LANE)
0101 : OCIP (lane selected by field DTEST_LANE)
0110 : EQUNDER (lane selected by field DTEST_LANE)
0111 : EQOVER (lane selected by field DTEST_LANE)
1000 – 1111 : not used
7:0
Reserved
R/W
0x00
Reserved
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
119
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.77 Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]
These fields control the routing of the SLEEP signal to different blocks. Assertion means that the SLEEP signal
will be sent to the block. These bits do not override the SPI bits; just the SLEEP signal from the PAD.
Figure 129. Sleep Pin Control Register (SLEEP_CNTL)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 124. SLEEP_CNTL Field Descriptions
Bit
15:10
Type
Reset
Description
Reserved
R/W
11111
Reserved
9
CLKOUT_SLEEP
R/W
1
Allows the output clock to sleep
8
BG_SLEEP
R/W
1
Allows the band gap to sleep
7
TEMP_SLEEP
R/W
1
Allows the temp sensor to sleep
6
PLL_CP_SLEEP
R/W
1
Allows the PLL charge pump to sleep
5
PLL_SLEEP
R/W
1
Allows the PLL to sleep
4
CLK_RECV_SLEEP
R/W
1
Allows the clock receiver to sleep
3:2
120
Field
Reserved
R/W
11
Reserved
1
DACB_SLEEP
R/W
1
Allows DACB to sleep
0
DACA_SLEEP
R/W
1
Allows DACA to sleep
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.78 SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]
Figure 130. SYSREF Capture Circuit Control Register (SYSR_CAPTURE)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
1
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
1
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 125. SYSR_CAPTURE Field Descriptions
Bit
15:14
13:12
11
10:2
1
0
Field
Type
SYSR_PHASE_WDW
R/W
SYSR_ALIGN_DLY
R/W
Reset
Description
00
sysref phase alignment tolerance window Centers sysref capture
window as follows:
00 = Centered on phase φ12 (**DEFAULT**)
01 = Centered on phase φ23
10 = Centered on phase φ34
11 = Centered on phase φ41
01
sysref alignment offset delay Optional alignment offset that
allows system designer to work around hardware (e.g. PCB)
alignment errors by letting him specify that the sysref pulse
should be treated as occurring one device clock earlier or later
than its observed position. Legal settings are as follows:
00 = Offset by -1 device clock cycles. Treat sysref as if it were
captured 1 cycle earlier.
01 = No offset (**DEFAULT**)
10 = Offset by +1 device clock cycles. Treat sysref as if it were
captured 1 cycle later.
11 = Reserved
SYSR_STATUS_ENA
R/W
0
Enable alignment status monitoring Enable logic that generates
sysref alignment status information and accumulates statistics
that can be read by the user.
0 = Disable sysref alignment status outputs (**DEFAULT**).
Used during normal operation.
1 = Enable sysref alignment status outputs. Used when
characterizing sysref capture timing.
Reserved
R/W
0x000
Reserved
SYSR_ALIGN_SYNC
R/W
0
Write a ‘1’ to this bit to clear accumulated sysref align statistics
0
Bypass sysref alignment logic. Bypass the 4x oversampled
sysref alignment logic and instead capture the sysref signal
using the legacy implementation of a flip-flop clocked directly by
the rising edge of the device clock.
0 = Capture sysref using full-featured alignment circuit
(**DEFAULT**)
1 = Bypass sysref alignment logic
NOTE: When mem_sysref_bypass_align is enabled, the other
sysref alignment controls have no effect.
SYSR_BYPS_ALIGN
R/W
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
121
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.79 Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]
Figure 131. Clock Input and PLL Configuration Register (CLK_PLL_CFG)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 126. Clock Input and PLL Configuration Register (CLK_PLL_CFG)
Bit
Field
Type
Reset
Description
Reserved
R/W
00
Reserved
13
SEL_EXTCLK_DIFFSE
R/W
0
Selects the external differential or single ended clock for
DACCLK.
0 = differential
1 = single ended
12
PLL_RESET
R/W
0
When set the M divider; N divider and PFD are held reset
11
PLL_NDIVSYNC_ENA
R/W
0
When asserted; the SYSREF input is used to sync the N
dividers of the PLL.
10
PLL_ENA
R/W
0
Enables the PLL output as the DAC clock when set; the clock
provided at the DACCLKP/N is used as the PLL reference clock.
When cleared; the PLL is bypassed and the clock provided at
the DACCLKP/N pins is used as the DAC clock
9
PLL_CP_SLEEP
R/W
1
Must be set to '0' for proper PLL operation.
1 = Charge pump is put to sleep and can be driven by external
source through the ATEST pins.
8
15:14
122
Reserved
R/W
0
Reserved
7:3
PLL_N_M1
R/W
00000
Reference clock divider; divide by is N+1
2:0
LOCKDET_ADJ
R/W
000
Adjusts the lock detector sensitivity. Upper bit isn't used:
x00 - highest sensitivity x11 - lowest sensitivity
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.80 PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]
Figure 132. PLL Configuration 1 Register (PLL_CONFIG1)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 127. CONFIG1 Field Descriptions
Bit
Field
Type
Reset
Description
15:8
PLL_M_M1
R/W
0x03
VCO feedback divider; divide by is 4(M+1)
7:4
Reserved
R/W
0x0
Reserved
3:0
PLL_VCO_RDAC
R/W
0x8
Controls the VCO amplitude
8.5.81 PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]
Figure 133. PLL Configuration 2 Register (PLL_CONFIG2)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
1
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 128. PLL_CONFIG2 Field Descriptions
Bit
Field
Type
Reset
Description
15
PLL_VCOSEL
R/W
0
Selects between two VCOs
0 = 5.9 GHz VCO(2 turn inductor in upper VCO)
1 = 8.9 GHz VCO (1 turn in the lower VCO)
14:8
PLL_VCO
R/W
1000000
VCO frequency range
7:6
Reserved
R/W
000
Reserved
5:2
PLL_CP_ADJ
R/W
0110
Adjusts the charge pump current; 0 to 1.55 mA in 50 µA steps.
Setting to 0000 will hold the LPF pin at 0 V
1
Reserved
R/W
0
Reserved
0
Reserved
R/W
0
Reserved. Always write 0
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
123
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.82 LVDS Output Configuration Register (address = 0x34) [reset = 0x0000]
Figure 134. LVDS Output Configuration Register (LVDS_CONFIG)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
1
R/W
3
0
R/W
2
1
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 129. LVDS_CONFIG Field Descriptions
Bit
Field
Type
Reset
Description
15
LVDS_LOPWRB
R/W
0
LVDS Output current control LSB; allows output current to be
scaled from ~2 mA to ~4 mA
14
LVDS_LOPWRA
R/W
0
LVDS Output current control MSB; allows output current to be
scaled from ~2 mA to ~4 mA
13
LVDS_LPSEL
R/W
0
SYNC LVDS output on chip termination control; 100 Ω when
cleared; 200 Ω
Output current settings for the combination of bits 15:13
110 = 4.00 mA
010 = 3.50 mA
100 = 3.00 mA
000 = 2.50 mA – Default current
111 = 4.00 mA
011 = 3.33 mA
101 = 2.66 mA
001 = 2.00 mA
12
LVDS_EFUSE_SEL
R/W
0
Enable LVDS bias bandgap reference voltage to the ATEST
multiplexer.
LVDS_TRIM
R/W
00
Adjusts the LVDS 1.2 V reference. LVDS_TRIM_ENA must be
set and LVDS_EFUSE_SEL must be cleared for these bits to
have any effect.
10 +70 mV
00 -70 mV
01 default
11 -20 mV.
9
LVDS_TRIM_ENA
R/W
0
When set and LVDS_EFUSE_SEL is cleared; the LVDS_TRIM
adjustment is enabled. When cleared; the LVDS_TRIM has no
effect.
8
LVDS_SYNC0\_PD
R/W
0
The SYNC0 LVDS output is in power down.
7
Reserved
R/W
0
Reserved
6
LVDS_SYNC0\_CM
R/W
0
SYNC0 LVDS output common mode is 1.2 V when cleared; 0.9
V when set.
Reserved
R/W
0x00
Reserved
11:10
5:0
124
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.83 Fuse Farm clock divider Register (address = 0x35) [reset = 0x0018]
Figure 135. Fuse Farm clock divider Register (PLL_FDIV)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/1W
4
1
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 130. PLL_FDIV Field Descriptions
Field
Type
Reset
Description
15:8
Bit
Reserved
R/W
0
Reserved
7:0
PLL_FDIV
R/W
0x18
Clock divider for the Fuse farm
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
125
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.84 Serdes Clock Configuration Register (address = 0x3B) [reset = 0x1802]
Figure 136. Serdes Clock Configuration Register (SRDS_CLK_CFG)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/1W
4
1
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after rese1t
Table 131. SRDS_CLK_CFG Field Descriptions
Bit
Field
Type
Reset
Description
15
SERDES_CLK_SEL
R/W
0
Select either the PLL output of the DACCLK from the pad.
0 = DACCLK pad
1 = PLL output
14:11
SERDES_REFCLK_DIV
R/W
0111
The divide amount for the serdes REFCLK minus 1
10:2
Reserved
R/W
0x000
Reserved
10
These bits select the pre-divide on the DACCLK input clock
before the DACCLK is used in the dividers used in the SERDES
PLL REFCLK and the Fusefarm SYSCLK.
00 = if DACCLK input ≤ 2 GHz; prediv is set to div1
01 = if DACCLK input is ≤ 4 GHz and > 2 GHz, prediv is set to
div2
10 = if DACCLK input is ≤ 9 GHz and > 4 GHz, prediv is set to
div4
11 = Not valid
1:0
SERDES_REFCLK_PREDIV
R/W
8.5.85 Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]
Figure 137. Serdes PLL Configuration Register (SRDS_PLL_CFG)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 132. SRDS_PLL_CFG Field Descriptions
Bit
Field
Type
Reset
Description
15
ENDIVCLK
R/W
1
Enable divided by 5 output clock
14:3
CLKBYP
R/W
00
Serdes clock bypass
12:11
LB
R/W
00
Serdes PLL loop bandwidth
10
SLEEPPLL
R/W
0
Serdes PLL Sleep
9
VRANGE
R/W
1
Serdes PLL loop filter range
MPY
R/W
00010100
Serdes reference clock multiplication factor Table 4
CORRECT
R/W
0
AND'ed with LANE_ENA so it must be set to 1 for correct
behavior
8:1
0
126
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.86 Serdes Configuration 1 Register (address = 0x3D) [reset = 0x0x0088]
Figure 138. Serdes Configuration 1 Register (SRDS_CFG1)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
0
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 133. RDS_CFG1 Field Descriptions
Bit
Field
Type
Reset
Description
15
Reserved
R/W
0
Reserved
TESTPATT
R/W
000
Test pattern
11
BSINRXN
R/W
0
Enable boundary scan - pins
10
BSINRXP
R/W
0
Enable boundary scan + pins
9:8
14:12
Reserved
R/W
00
Reserved
7
ENOC
R/W
1
Enable Serdes offset compensation
6
EQHLD
R/W
0
Equalizer hold
5:3
EQ
R/W
001
Serdes equalizer
2:0
CDR
R/W
000
Clock data recovery algorithm settings
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
127
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
8.5.87 Serdes Configuration 2 Register (address = 0x3E) [reset = 0x0x0909]
Figure 139. Serdes Configuration 2 Register (SRDS_CFG2)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
0
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 134. SRDS_CFG2 Field Descriptions
Bit
Field
Type
Reset
Description
15:13
LOS
R/W
000
Enables loss of signal detection.
000 - Disable detection
100 - Enable detection
other - reserved
12:11
ALIGN
R/W
01
Enables external or internal symbol alignment
00 : Disabled
01 : Comma alignment
10: Align jog
TERM
R/W
001
Valid programming:
001 – AC coupling with common mode = 0.7 V
100 – 0 V common mode.
101 – 0.25 V common mode
111 – DC coupling with common mode of 0.6 V.
(NOTE: This is not compatible with JESD)
Reserved
R/W
0
Reserved
6:5
RATE
R/W
00
Selects full (00), half (01), quarter (10) or eighth (11) rate
operation.
4:2
Reserved
R/W
010
Reserved
1
SLEEPRX
R/W
0
Powers the receiver down into the sleep (fast power up) state
when high.
0
Reserved
R/W
1
Reserved
10:8
7
128
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
8.5.88 Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]
Figure 140. Serdes Polarity Control Register (SRDS_POL)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 135. SRDS_POL Field Descriptions
Bit
15:8
7:0
Field
Type
Reset
Description
Reserved
R/W
0x00
Reserved
0x00
Allows the PN pairs of the different lanes to be inverted.
bit 7 = lane7
bit 6 = lane6
bit 5 = lane5
bit 4 = lane4
bit 3 = lane3
bit 2 = lane2
bit 1 = lane1
bit 0 = lane0
INVPAIR
R/W
8.5.89 JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]
Figure 141. JESD204B SYNCB OUTPUT Register (SYNCBOUT)
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
x
R/W
7
0
R/W
6
0
R/W
5
1
R/1W
4
1
R/W
3
1
R/W
2
0
R/W
1
1
R/W
0
1
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 136. SYNCBOUT Field Descriptions
Bit
Field
Type
Reset
Description
Reserved
R/W
0x00
Reserved
1
SYNCBOUT1
R/W
0
If the CMOS SYNC outputs are turned on, this bit will show the
status of the JESD SYNCB1 signal
0
SYNCBOUT0
R/W
0
If the CMOS SYNC outputs are turned on, this bit will show the
status of the JESD SYNCB0 signal
15:2
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
129
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Start-up Sequence
PULL TXENABLE LOW
x
x
x
x
Provide all 1V supply rails, 1.8V rails and -1.8V rail.
Pull TRSTB pin of the JTAG port low
Provide a clock to the differential or single ended clock input
Toggle RESETB pin low then high (recommended pulse duration
>10us)
Read SPI Page 0, Register 0x7F
Bits[15:10] B 10000b
Bits[15:10]=10000b
Configure the SPI resgisters for the desired mode
On chip PLL mode
YES
Increment/decrement
VCO tune value
SPI Page 4, address
0x33, bits[14:8]
Read page 0, address 0x06
Tj = bits[15:8]
LFVOLT = bits[7:5]
NO
Start SYSREF Generation
Reset encoder block:
Page 1/2:address 0x24:bits [6:4] = 000b
Page 1/2:address 0x5C:bits [2:0] = 000b
Page 4:address 0x0A:bit [15] = 1b
Ensure at least 2 SYSREF rising edges occur to reset the encoder
Page 4:address 0x0A:bit [15] = 0b
Put JESD204B core in reset
Page 0:address 0x00:bits [1:0] = 11b
Sync CDRV and JESD204B blocks
Page 1/2:address 0x24:bits [6:4] = 010b
Ensure at least 2 SYSREF rising edges occur to reset the CDRV
Page 1/2:address 0x5C:bits [2:0] = 011b
Ensure at least 2 SYSREF rising edges occur to reset the JESD
Take JESD Core out of reset
Page 0:address 0x00:bits [1:0] = 00b
Ensure at least 2 SYSREF rising edges occur
x
x
x
x
x
108 G di < 125C, LFVOLT =5or6
92 G di < 108C, LFVOLT=4or5
26 G di < 92C, LFVOLT =3or4
-40 G di < 26C, LFVOLT =2or3
Clear all DAC alarms: Write 0x0000 to alarm registers on
Page0: 0x04, 0x05 and Page1/2: 0x64 to 0x6D
Stop SYSREF generation to DAC (optional)
Pull TXENABLE HIGH
Copyright © 2017, Texas Instruments Incorporated
Figure 142. DAC38RF82/89 Recommended Startup Sequence
130
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
9.2 Typical Application
The block diagram of a typical DOCSIS downstream network is shown in Figure 143. The physical layer (PHY) of
the cable modem termination system (or CMTS) must support normal downstream operating range from 54 MHz
to 1002 MHz as well as extended operating range up to 1794 MHz. The high input bandwidth (up to 3.33 GHz) of
DAC38RF82 and DAC38RF89 makes these devices suitable for DOCSIS CMTS. Also the integrated high
performance PLL simplifies system clocking by eliminating the need to generate and distribute high frequency
sampling clock to the DAC. In the following sections, the performance of DAC38RF82 (and DAC38RF89) used to
generate DOCSIS 3.0, Annex A, 6 MHz 256-QAM carriers will be described.
CM
Hybrid fibre/coax
Network
Management
CMTS
HFC Network
Cable Modem Termination
System
CM
Cable modem
(Home Network)
Figure 143. DOCSIS Downstream Network
9.2.1 Design Requirements
Table 137. DOCSIS CMTS Design Features
Feature
Specification
Frequency range
54 MHz to 1002 MHz
No of carriers
1
Channel width
6 MHz
Modulation type
256 QAM
Modulation rate
5.3605 Msym/s
Data rate
2.4576 GSPS
MER (unequalized)
>48 dB
ACPR
>70 dBc
9.2.2 Detailed Design Procedure
A sample rate of 4.9152 GHz is selected for the DAC. This will make it possible to meet the out of band (up to
3GHz) spurious requirement of 65 dBc by pushing the DAC images to the 2nd Nyquist zone (2.4576 MHz to
4.9152 GHz). Because the input data rate is 2.4576 GSPS, the DAC interpolation is set to 2. To generate the
4.9152 GHz sampling clock for the DAC, a low frequency 409.6 MHz clock is provided to the DAC reference
clock input. A detailed block diagram is shown in Figure 144
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
131
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
409.6 MHz
Low Jitter
PLL
www.ti.com
4915.2 MHz
SYSREF
JESD204B
16 bit, real data
2.4576 GSPS
1.333 : 1
x
sin(x)
14-b
DAC
100Q
75Q
2x interp
Figure 144. DOCSIS Downstream Network
9.2.3 Calculating the JESD204B SerDes rate
SerDes rate = 1.25 x (M/L) x Baseband data rate x Number of bits per sample (16)
M is a JESD204B interface parameter that refers to the number of data streams from FPGA to DAC
L is a JESD204B interface parameter that refers to the number of SerDes lanes used to transmit data
1.25 is a factor due to the 8B10B encoding of the baseband data
Example,
if the baseband data rate = 2457.6 MSPS and L-M-F-S-Hd = 4-1-1-2-1
SerDes rate = 1.25 x (1/4) x 2457.6 x 16 = 12.288 Gbps
(19)
9.2.4 Calculating valid JESD204B SYSREF Frequency
Valid SYSREF frequencies depend on the following parameters:
1. Sample clock frequency
2. JESD204B internal clock divider value (CLKJESD_DIV). This depends on the DAC JESD204B L-M-F-S
mode and interpolation
3. Number of octets in a frame (F)
4. Number of frames in a multi-frame (K)
Maximum SYSREF frequency = (Sample clock frequency/N),
where N =LCM(CLKJESD_DIV,4 x K x F). N is the Least common multiple of 4 x K x F and CLKJESD_DIV.
All valid SYSREF frequencies are integer divisors of the maximum SYSREF frequency.
Example:
Given sampling clock frequency = 4.9152 GSPS, interpolation =2, DAC Mode=L-M-F-S=4-1-1-2 and K=20:
CLKJESD_DIV = 8 (CLKJESD_DIV)
Maximum SYSREF Frequency = 4915.2 MHz/80 = 61.44 MHz
Valid SYSREF Frequencies = 61.44 MHz/n, where n is any positive integer.
132
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
9.2.5 Application Curves
Figure 145. ACPR Performance of 6 MHz Single Carrier at 591 MHz
Figure 146. ACPR performance of 6 MHz Single Carrier at 998 MHz
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
133
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
Figure 147. Unequalized MER of 6 MHz Single Carrier at 591 MHz
Figure 148. Unequalized MER of 6 MHz Single Carrier at 998 MHz
134
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
10 Power Supply Recommendations
Internally, DAC38RF82 (DAC38RF89) comprises a digital subsystem, an analog subsystem, and a clock
subsystem. Ideally, the power supply scheme should be partitioned according to these three relatively
independent blocks to minimize interactions between them. Most importantly, sensitive analog and clock circuit
power supply must be separated from digital switching noise to reduce direct coupling and mixing of switching
spurs. Table 138 shows the power supply rails for DAC38RF82 (DAC38RF89) grouped under their respective
domains.
Table 138. Power Supply Domains
Supply rail
Nominal voltage (V)
VDDIG1
+1.0
VDDIO18
+1.8
VDDR18
+1.8
VDDS18
+1.8
VDDT1
+1.0
VDDE1
+1.0
VDDL1_1
+1.0
VEE18N
-1.8
VDDA1
+1.0
VDDA18
+1.8
VDDOUT18
+1.8
VDDPLL1
+1.0
VDDAPLL18
+1.8
VDDAVCO18
+1.8
VDDCLK1
+1.0
VDDL2_1
+1.0
VDDTX1
+1.0
VDDTX18
+1.8
Domain
Digital
Analog
Clock
An example power supply scheme suitable for most applications of DAC38RF82 (DAC38RF89) is shown in
Figure 149. It is recommended to use ferrite beads (FB) to isolate the individual rails from each other.
5Vin
TPS62085
(3 A)
1V
1V
TPS74401
(2 A)
TPS62085
(3 A)
1.8 V
LM27761
(250 mA)
1V
1.8 V
VDDDIG1 (2.5 A)
VDDT1 (375 mA)
VDDL1_1 (45 mA)
VDDL2_1 (45 mA)
VDDCLK1 (425 mA)
VDDA1 (25 mA)
VDDPLL1 (30 mA)
VDDTX1 (14 mA)
VDDE1 (650 mA)
VDDA18 (45 mA)
VDDOUT18 (100 mA)
VDDAVCO18 (40 mA)
VDDAPLL18 (20 mA)
VDDR18 + VDDS18 + VDDIO18 (135 mA)
VDDTX18 (14 mA)
±1.8 V VEE18 (152 mA)
Copyright © 2017, Texas Instruments Incorporated
Figure 149. Power Supply Scheme for DAC38RF82 (DAC38RF89)
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
135
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
10.1 Power Supply Sequencing
There are no power supply sequencing requirements for all the 1-V and 1.8-V power supplies. For the -1.8 V
VEE18 rail, it is recommended that this supply is the last to be enabled. Enabling VEE18 (while other supply
voltages are disabled) can cause a small negative voltage to be present at the other rails (that is, VDDA1 and
VDDDIG1). This small negative voltage can interfere with the startup of some DC-DC converters or LDO
connected to the 1 V and 1.8 V input power rails.
11 Layout
11.1 Layout Guidelines
•
•
DAC RF output traces
– Differential 100 Ω co-planar wave guide for output traces is recommended.
– Use short RF traces. Place DAC close to edge of PCB to shorten the length of output and clock traces.
This helps to minimize PCB loss and coupling
– Stitch the ground plane with ground vias uniformly along the output trace.
– Avoid width/spacing differences when entering a landing pad (eg. a balun) by tapering or by redefining
width/space rules for the traces
Power supply planes
– Ensure sufficient lateral spacing between two power planes (about 3x the thickness of the plane is
recommended)
– Insert ground plane between adjacent power planes where possible
Figure 150. Example Power Plane Routing
•
136
Bypass Capacitors
– Use bypass capacitors with in-pad vias and place between the pin and the power plane. Avoid sharing
ground vias or pads of bypass caps used for different power rails
– Minimize stubs on bypass capacitors to avoid parasitic inductance
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
Layout Guidelines (continued)
Figure 151. Bypass Capacitors Placed on the Power Supply Pin With In-pad Vias
•
High speed SerDes traces
– Route all SerDes traces straight and minimized sharp curves or serpentines. Route for best signal integrity
– Some skew between SerDes traces can be tolerated. It is recommended to limit skew between traces to
320ps or less
– Place ground planes between the SerDes traces for improved isolation
Figure 152. Layout Example of High Speed SerDes Traces
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
137
DAC38RF82, DAC38RF89
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
www.ti.com
11.2 Layout Example
xx
xx
xx
xx
xx
xx
xxxxx
x
xx
xx
xx
xxxx
xx
xx
A
B
C
D
12
11
10
9
x
x
x
x
x
x
x
x
8
7
x
x
x
x
6
5
4
3
x
x
x
x
x
2
1
xx
xx
xx
xx
xx
xx
xx
xx
xx
xxxx
xx
xxxx
xxxx
xxxxx
xx
xxxxx
xxxx
xx
xx
xx
xxxx
xxxx
E
F
G
H
J
K
L
M
Rbias
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Bottom Trace
Top Trace
Capacitor
Resistor
x
Via
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Figure 153. Layout Example
138
Submit Documentation Feedback
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
DAC38RF82, DAC38RF89
www.ti.com
SLASEA6D – FEBRUARY 2017 – REVISED JUNE 2020
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 139. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DAC38RF82
Click here
Click here
Click here
Click here
Click here
DAC38RF89
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2017–2020, Texas Instruments Incorporated
Product Folder Links: DAC38RF82 DAC38RF89
Submit Documentation Feedback
139
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
DAC38RF82IAAV
ACTIVE
FCBGA
AAV
144
168
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
DAC38RF82I
DAC38RF82IAAVR
ACTIVE
FCBGA
AAV
144
1000
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
DAC38RF82I
DAC38RF89IAAV
ACTIVE
FCBGA
AAV
144
168
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
DAC38RF89I
DAC38RF89IAAVR
ACTIVE
FCBGA
AAV
144
1000
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
DAC38RF89I
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
