DAC43401DSGR

Order Now Product Folder Support & Community Tools & Software Technical Documents DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 DACx3401 10-Bit and 8-Bit, Voltage-Output Digital-to-Analog Converters With Nonvolatile Memory and PMBus™ Compatible I2C Interface in Tiny 2 × 2 WSON 1 Features 3 Description • • The 10-bit DAC53401 and 8-bit DAC43401 (DACx3401) are a pin-compatible family of buffered voltage-output digital-to-analog converters (DACs). These devices consume very low power, and are available in a tiny 8-pin WSON package. The feature set combined with the tiny package and low power make the DACx3401 an excellent choice for applications such as LED and general-purpose bias point generation, power supply control, digitizers, PWM signal generation, and medical alarm tone generation. 1 • • • • • • • • 1 LSB INL and DNL (10-bit and 8-bit) Wide operating range – Power supply: 1.8 V to 5.5 V – Temperature range: –40˚C to +125˚C PMBus™ compatible I2C interface – Standard, Fast, and Fast+ modes – Digital slew rate control – 1.62-V VIH with VDD = 5.5 V User-programmable nonvolatile memory (NVM/EEPROM) – Save and recall all register settings Programmable waveform generation: Square, ramp, and sawtooth Preprogrammed medical-alarm tone-generation mode: low, medium, and high priority alarms Internal reference Very low power: 0.2 mA at 1.8 V Flexible startup: High impedance or 10K-GND Tiny package: 8-pin WSON (2 mm × 2 mm) These devices have nonvolatile memory (NVM), an internal reference, and a PMBus-compatible I2C interface. The DACx3401 operates with either an internal reference or the power supply as a reference, and provides full-scale output of 1.8 V to 5.5 V. The devices communicate through the I2C interface. These devices support I2C standard mode, fast mode, and fast+ mode. The DACx3401 are feature rich, and include PMBus voltage margin commands, user-programmable power up to high impedance, standalone waveform generator, medical alarm tone generator, dedicated feedback pin, and more. 2 Applications • • • • • • The DACx3401 operate within the temperature range of –40°C to +125°C. Rack server Exit and emergency lighting Automotive USB charge Barcode scanner Active antenna system mMIMO (AAS) CPU (PLC controller) Device Information(1) PART NUMBER DAC53401 BODY SIZE (NOM) WSON (8) DAC43401 2.00 mm × 2.00 mm (1) For all available packages, refer to the package option addendum at the end of the data sheet. Functional Block Diagram CAP PACKAGE Power-Supply Control With the DACx3401 L VDD VIN IN PH VOUT LDO BOOT CL SMPS SDA A0 I2C Interface PMBus Compatible CB SCL Internal Reference Non Volatile Memory SENSE GND VDD R1 R3 DACx3401 VFB R2 DAC Buffer DAC Register DAC + BUF - OUT R1 FB R2 Power On Reset Power Down Logic AGND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 4 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Absolute Maximum Ratings ...................................... 4 ESD Ratings.............................................................. 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics........................................... 5 Timing Requirements: I2CTM Standard mode ........... 7 Timing Requirements: I2CTM Fast mode................... 7 Timing Requirements: I2CTM Fast+ mode................. 8 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference) .................... 9 7.10 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference) ................... 11 7.11 Typical Characteristics .......................................... 13 8 Detailed Description ............................................ 18 8.1 Overview ................................................................. 18 8.2 8.3 8.4 8.5 8.6 9 Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Register Map........................................................... 18 19 25 28 32 Application and Implementation ........................ 40 9.1 Application Information............................................ 40 9.2 Typical Applications ................................................ 40 10 Power Supply Recommendations ..................... 46 11 Layout................................................................... 46 11.1 Layout Guidelines ................................................. 46 11.2 Layout Example .................................................... 46 12 Device and Documentation Support ................. 47 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Documentation Support ........................................ Related Links ........................................................ Receiving Notification of Documentation Updates Support Resources ............................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 47 47 47 47 47 47 47 13 Mechanical, Packaging, and Orderable Information ........................................................... 47 4 Revision History Changes from Original (July 2019) to Revision A • 2 Page Changed DAC53401 and DAC43401 devices from advanced information (preview) to production data (active) ................ 1 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 5 Device Comparison Table DEVICE RESOLUTION DAC53401 10-bit DAC43401 8-bit 6 Pin Configuration and Functions DSG Package 8-Pin WSON Top View A0 1 8 OUT SCL 2 7 FB SDA 3 6 VDD CAP 4 5 AGND Not to scale Pin Functions PIN NAME NO. TYPE DESCRIPTION A0 1 Input Four-state address input AGND 5 Ground CAP 4 Input External capacitor for the internal LDO. Connect a capacitor (0.5 µF to 15 µF) between CAP and AGND. FB 7 Input Voltage feedback pin OUT 8 Output SCL 2 Input SDA 3 Input/output VDD 6 Power Ground reference point for all circuitry on the device Analog output voltage from DAC Serial interface clock. This pin must be connected to the supply voltage with an external pullup resistor. Data are clocked into or out of the input register. This pin is a bidirectional, and must be connected to the supply voltage with an external pullup resistor. Analog supply voltage: 1.8 V to 5.5 V Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 3 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX Supply voltage, VDD to AGND –0.3 6 V Digital input(s) to AGND –0.3 VDD + 0.3 V CAP to AGND –0.3 1.65 VFB to AGND –0.3 VDD + 0.3 VOUT to AGND –0.3 VDD + 0.3 Current into any pin –10 10 TJ Junction temperature –40 150 Tstg Storage temperature –65 150 VDD (1) UNIT V mA °C Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins Electrostatic discharge V(ESD) (1) (2) (1) UNIT ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, pins 1, 4, 5, 8 (2) ±750 Charged device model (CDM), per JEDEC specification JESD22-C101, pins 2, 3, 6, 7 (2) ±500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VDD Positive supply voltage to ground (AGND) 1.71 VIH Digital input high voltage, 1.7 V < VDD ≤ 5.5 V 1.62 VIL Digital input low voltage TA Ambient temperature NOM MAX UNIT 5.5 V V –40 0.4 V 125 °C 7.4 Thermal Information DACx3401 THERMAL METRIC (1) DSG (WSON) UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 49 °C/W RθJC(top) Junction-to-case (top) thermal resistance 50 °C/W RθJB Junction-to-board thermal resistance 24.1 °C/W ΨJT Junction-to-top characterization parameter 1.1 °C/W ΨJB Junction-to-board characterization parameter 24.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 8.7 °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 7.5 Electrical Characteristics all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE Resolution DAC53401 10 DAC43401 8 Bits INL Relative accuracy (1) –1 1 LSB DNL Differential nonlinearity (1) –1 1 LSB Zero code error Code 0d into DAC 6 12 Internal VREF, gain = 4x, VDD = 5.5 V 6 15 Zero code error temperature coefficient ±10 Offset error (1) –0.5 Offset error temperature coefficient (1) µV/°C 0.5 ±0.0003 Gain error (1) –0.5 Gain error temperature coefficient (1) Full scale error 0.25 0.25 mV %FSR %FSR/°C 0.5 ±0.0008 %FSR %FSR/°C 1.8 V ≤ VDD ≺ 2.7 V, code 1023d into DAC, no headroom –1 0.5 1 2.7 V ≤ VDD ≤ 5.5 V, code 1023d into DAC, no headroom –0.5 0.25 0.5 %FSR Full scale error temperature coefficient ±0.0008 %FSR/°C OUTPUT CHARACTERISTICS Output voltage CL Capacitive load (2) Load regulation Short circuit current Output voltage headroom (1) Reference tied to VDD (1) (2) 5.5 1 RL = 5 kΩ, phase margin = 30° 2 DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA, VDD = 5.5 V 0.4 VDD = 1.8 V, full-scale output shorted to AGND or zero-scale output shorted to VDD 10 VDD = 2.7 V, full-scale output shorted to AGND or zero-scale output shorted to VDD 25 VDD = 5.5 V, full-scale output shorted to AGND or zero-scale output shorted to VDD 50 To VDD (DAC output unloaded, internal reference = 1.21 V), VDD ≥ 1.21 ☓ gain + 0.2 V 0.2 To VDD (DAC output unloaded, reference tied to VDD) 0.8 To VDD (ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD = 1.8 V), DAC code = full scale VOUT dc output impedance 0 RL = Infinite, phase margin = 30° V nF mV/mA mA V %FSR 10 DAC output enabled and DAC code = midscale 0.25 DAC output enabled and DAC code = 4d 0.25 DAC output enabled and DAC code = 1016d 0.26 Ω Measured with DAC output unloaded. For external reference between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution. For internal reference VDD ≥ 1.21 x gain + 0.2 V, between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution. Specified by design and characterization, not production tested. Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 5 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com Electrical Characteristics (continued) all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted) PARAMETER ZO VFB dc output impedance (3) MIN TYP MAX DAC output enabled, DAC reference tied to VDD (gain = 1x) or internal reference (gain = 1.5x or 2x) TEST CONDITIONS 160 200 240 DAC output enabled, internal VREF, gain = 3x or 4x 192 240 288 VOUT + VFB dc output leakage (2) At startup, measured when DAC output is disabled and held at VDD / 2 for VDD = 5.5 V Power supply rejection ratio (dc) Internal VREF, gain = 2x, DAC at midscale; VDD = 5 V ±10% 5 0.25 UNIT kΩ nA mV/V DYNAMIC PERFORMANCE tsett Output voltage settling time 8 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V, internal VREF, gain = 4x 12 Slew rate VDD = 5.5 V Power on glitch magnitude At startup (DAC output disabled), RL = 5 kΩ, CL = 200 pF Output enable glitch magnitude Vn 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V µs 1 V/µs 75 At startup (DAC output disabled), RL = 100 kΩ 200 DAC output disabled to enabled (DAC registers at zero scale, RL = 100 kΩ 250 mV mV 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 34 Internal VREF, gain = 4x, 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 70 Measured at 1 kHz, DAC at midscale, VDD = 5.5 V 0.2 Internal VREF, gain = 4x,, measured at 1 kHz, DAC at midscale, VDD = 5.5 V 0.7 Power supply rejection ratio (ac) (3) Internal VREF, gain = 4x, 200-mV 50 or 60 Hz sine wave superimposed on power supply voltage, DAC at midscale –71 dB Code change glitch impulse ±1 LSB change around mid code (including feedthrough) 10 nV-s Code change glitch impulse magnitude ±1 LSB change around mid code (including feedthrough) 15 mV Output noise voltage (peak to peak) Output noise density µVPP µV/√Hz EEPROM Endurance Data retention (2) –40°C ≤ TA ≤ 85°C 20000 Cycles 1000 TA = 25°C 50 EEPROM programming write cycle time (2) 5 10 Years 15 ms DIGITAL INPUTS Digital feedthrough DAC output static at midscale, fast+ mode, SCL toggling 20 nV-s Pin capacitance Per pin 10 pF POWER Load capacitor - CAP pin (2) IDD (3) 6 Current flowing into VDD 0.5 Normal mode, DACs at full scale, digital pins static 0.5 DAC power-down, internal reference power down 80 15 µF 0.8 mA µA Specified with 200-mV headroom with respect to reference value when internal reference is used. Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 7.6 Timing Requirements: I2CTM Standard mode all input signals are timed from VIL to 70% of VDD, 1.8 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, 1.8 V ≤ Vpull-up ≤ VDD V MIN fSCLK SCL frequency tBUF Bus free time between stop and start conditions tHDSTA Hold time after repeated start tSUSTA NOM MAX UNIT 0.1 MHz 4.7 µs 4 µs Repeated start setup time 4.7 µs tSUSTO Stop condition setup time 4 µs tHDDAT Data hold time 0 ns tSUDAT Data setup time 250 ns tLOW SCL clock low period 4700 ns tHIGH SCL clock high period 4000 tF Clock and data fall time 300 ns tR Clock and data rise time 1000 ns ns 7.7 Timing Requirements: I2CTM Fast mode all input signals are timed from VIL to 70% of VDD, 1.8 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, 1.8 V ≤ Vpull-up ≤ VDD V MIN NOM MAX UNIT 0.4 MHz fSCLK SCL frequency tBUF Bus free time between stop and start conditions 1.3 µs tHDSTA Hold time after repeated start 0.6 µs tSUSTA Repeated start setup time 0.6 µs tSUSTO Stop condition setup time 0.6 µs tHDDAT Data hold time 0 ns tSUDAT Data setup time 100 ns tLOW SCL clock low period 1300 ns tHIGH SCL clock high period 600 tF Clock and data fall time 300 ns tR Clock and data rise time 300 ns ns Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 7 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com 7.8 Timing Requirements: I2CTM Fast+ mode all input signals are timed from VIL to 70% of VDD, 1.8 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, 1.8 V ≤ Vpull-up ≤ VDD V MIN fSCLK SCL frequency tBUF Bus free time between stop and start conditions tHDSTA NOM MAX UNIT 1 MHz 0.5 µs Hold time after repeated start 0.26 µs tSUSTA Repeated start setup time 0.26 µs tSUSTO Stop condition setup time 0.26 µs tHDDAT Data hold time 0 ns tSUDAT Data setup time 50 ns tLOW SCL clock low period 0.5 µs tHIGH SCL clock high period 0.26 tF Clock and data fall time 120 ns tR Clock and data rise time 120 ns µs Low byte ACK cycle tLOW tR tF SCL tHDSTA tHIGH tHDDAT tSUSTA tSUSTO tSUDAT tHDSTA SDA tBUF P S S P Figure 1. Timing Diagram 8 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 7.9 Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference) 1 1 0.8 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 Reference = VDD, gain = 1x Internal reference, gain = 1.5x -0.8 Differential Linearity Error (LSB) Integral Linearity Error (LSB) at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted) 0.4 0.2 0 -0.2 -0.4 -0.6 Reference = VDD, gain = 1x Internal reference, gain = 1.5x -0.8 -1 -1 0 128 256 384 512 Code 640 768 896 1023 0 Figure 2. Integral Linearity Error vs Digital Input Code 1 0.2 0.8 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 Reference = VDD, gain = 1x Internal reference, gain = 1.5x -0.2 128 256 384 512 Code 640 768 896 512 Code 640 768 896 1023 0.4 0.2 0 -0.2 -0.4 -0.6 -1 -40 -25 -10 1023 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 5. Integral Linearity Error vs Temperature 1 1 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0.8 Total Unadjusted Error (%FSR) DNL max, reference = VDD, gain = 1x DNL min, reference = VDD, gain = 1x DNL max, internal reference, gain = 1.5x DNL min, internal reference, gain = 1.5x 0.8 Differential Linearity Error (LSB) 384 INL max, reference = VDD, gain = 1x INL min, reference = VDD, gain = 1x INL max, internal reference, gain = 1.5x INL min, internal reference, gain = 1.5x 0.6 Figure 4. Total Unadjusted Error vs Digital Input Code -1 -40 -25 -10 256 -0.8 -0.25 0 128 Figure 3. Differential Linearity Error vs Digital Input Code 0.25 Integral Linearity Error (LSB) Total Unadjusted Error (%FSR) 0.6 0.6 0.4 0.2 0 -0.2 -0.4 TUE max, reference = VDD, gain = 1x TUE min, reference = VDD, gain = 1x TUE max, internal reference, gain = 1.5x TUE min, internal reference, gain = 1.5x -0.6 -0.8 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 6. Differential Linearity Error vs Temperature -1 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 7. Total Unadjusted Error vs Temperature Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 9 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com Typical Characteristics: VDD = 1.8 V (Reference = VDD) or VDD = 2 V (Internal Reference) (continued) at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted) 0.5 8 7 Offset Error (%FSR) Zero Code Error (mV) 0.3 6 5 4 3 2 0.1 -0.1 -0.3 1 0 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 -0.5 -40 -25 -10 110 125 Reference = VDD Figure 8. Zero Code Error vs Temperature 80 95 110 125 Figure 9. Offset Error vs Temperature 0.5 Reference = VDD, gain = 1x Internal reference, gain = 1.5x 0.4 Full Scale Error (%FSR) 0.3 0.1 -0.1 -0.3 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 Reference = VDD, gain = 1x Internal reference, gain = 1.5x -0.4 -0.5 -40 -25 -10 5 20 35 50 65 Temperature (qC) 80 95 Figure 10. Gain Error vs Temperature 10 20 35 50 65 Temperature (qC) Reference = VDD 0.5 Gain Error (%FSR) 5 110 125 -0.5 -40 -25 -10 5 20 35 50 65 Temperature (qC) 80 95 110 125 Figure 11. Full-Scale Error vs Temperature Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 7.10 Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference) 1 1 0.8 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 Reference = VDD, gain = 1x Internal reference, gain = 4x -0.8 Differential Linearity Error (LSB) Integral Linearity Error (LSB) at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted) 0.4 0.2 0 -0.2 -0.4 -0.6 Reference = VDD, gain = 1x Internal reference, gain = 4x -0.8 -1 -1 0 128 256 384 512 Code 640 768 896 1023 0 Figure 12. Integral Linearity Error vs Digital Input Code 256 384 512 Code 640 768 896 1023 1 Reference = VDD, gain = 1x Internal reference, gain = 4x 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 INL min, reference = VDD, gain = 1x INL max, reference = VDD, gain = 1x INL min, internal reference, gain = 4x INL max, internal reference, gain = 4x 0.8 Integral Linearity Error (LSB) 0.4 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -0.4 -1 -40 -25 -10 -0.5 0 128 256 384 512 Code 640 768 896 1023 Figure 14. Total Unadjusted Error vs Digital Input Code 20 35 50 65 Temperature (°C) 80 95 110 125 0.5 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 TUE max, reference = VDD, gain = 1x TUE min, reference = VDD, gain = 1x TUE max, internal reference, gain = 4x TUE min, internal reference, gain = 4x 0.4 Total Unadjusted Error (%FSR) DNL max, reference = VDD, gain = 1x DNL min, reference = VDD, gain = 1x DNL max, internal reference, gain = 4x DNL min, internal reference, gain = 4x 0.8 -1 -40 -25 -10 5 Figure 15. Integral Linearity Error vs Temperature 1 Differential Linearity Error (LSB) 128 Figure 13. Differential Linearity Error vs Digital Input Code 0.5 Total Unadjusted Error (%FSR) 0.6 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 16. Differential Linearity Error vs Temperature -0.5 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 17. Total Unadjusted Error vs Temperature Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 11 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com Typical Characteristics: VDD = 5.5 V (Reference = VDD) or VDD = 5 V (Internal Reference) (continued) at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted) 0.5 2 1.5 Offset Error (%FSR) Zero Code Error (mV) 0.3 1 0.5 0 -0.5 -1 0.1 -0.1 -0.3 -1.5 -2 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 -0.5 -40 -25 -10 110 125 Reference = VDD 5 Figure 18. Zero Code Error vs Temperature 95 110 125 Figure 19. Offset Error vs Temperature 0.5 Reference = VDD, gain = 1x Internal reference, gain = 4x Reference = VDD, gain 1x Internal reference, gain 4x Full Scale Error (%FSR) 0.3 Gain Error (%FSR) 80 Reference = VDD 0.5 0.1 -0.1 -0.3 -0.5 -40 -25 -10 5 20 35 50 65 Temperature (qC) 80 95 Figure 20. Gain Error vs Temperature 12 20 35 50 65 Temperature (qC) 110 125 0.3 0.1 -0.1 -0.3 -0.5 -40 -25 -10 5 20 35 50 65 Temperature (qC) 80 95 110 125 Figure 21. Full-Scale Error vs Temperature Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 7.11 Typical Characteristics 1 1 0.8 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 INL min INL max -0.8 -1 1.8 2.725 3.65 4.575 Supply Voltage, VDD (V) Differential Linearity Error (LSB) Integral Linearity Error (LSB) at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted) 0 -0.2 -0.4 -0.6 Zero Code Error (mV) 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 TUE max TUE min -0.2 2.725 3.65 4.575 Supply Voltage, VDD (V) 5.5 Reference = VDD 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 1.8 3.65 4.575 Supply Voltage, VDD (V) 5.5 2.3 2.8 3.3 3.8 4.3 Supply Voltage, VDD (V) 4.8 5.3 Reference = VDD Figure 24. Total Unadjusted Error vs Supply Voltage Figure 25. Zero-Code Error vs Supply Voltage 0.5 0.5 0.3 0.3 Gain Error (%FSR) Offset Error (%SFR) 2.725 Figure 23. Differential Linearity Error vs Supply Voltage 0.2 0.1 -0.1 -0.3 -0.5 1.8 DNL min DNL max Reference = VDD Figure 22. Integral Linearity Error vs Supply Voltage Total Unadjusted Error (%FSR) 0.2 -1 1.8 0.25 -0.25 1.8 0.4 -0.8 5.5 Reference = VDD 0.6 0.1 -0.1 -0.3 2.3 2.8 3.3 3.8 4.3 Supply Voltage, VDD (V) 4.8 Reference = VDD 5.3 -0.5 1.8 2.3 2.8 3.3 3.8 4.3 Supply Voltage, VDD (V) 4.8 5.3 Reference = VDD Figure 26. Offset Error vs Supply Voltage Figure 27. Gain Error vs Supply Voltage Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 13 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com Typical Characteristics (continued) at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted) 0.2 0.4 Reference = VDD, gain = 1x Internal reference, gain = 1.5x 0.35 0.12 Supply Current (mA) Full Scale Error (%FSR) 0.16 0.08 0.04 0 -0.04 -0.08 0.3 0.25 0.2 0.15 0.1 -0.12 0.05 -0.16 -0.2 1.8 0 2.725 3.65 4.575 Supply Voltage, VDD (V) 5.5 0 256 384 512 Code 640 768 896 1023 VDD = 1.8 V Reference = VDD Figure 29. Supply Current vs Digital Input Code Figure 28. Full-Scale Error vs Supply Voltage 0.4 0.4 Reference = VDD, gain = 1x Internal reference, gain = 4x 0.35 0.3 0.25 0.2 0.15 0.1 IDD, VDD = 1.8 V IDD, VDD = 3.3 V IDD, VDD = 5.5 V 0.35 Supply Current (mA) Supply Current (mA) 128 0.3 0.25 0.2 0.15 0.1 0.05 0.05 0 -40 -25 -10 0 0 128 256 384 512 Code 640 768 896 1023 VDD = 5.5 V 5 20 35 50 65 Temperature (°C) 80 95 110 125 Reference = VDD, DAC at midscale Figure 30. Supply Current vs Digital Input Code Figure 31. Supply Current vs Temperature 0.5 0.4 Reference = VDD, gain = 1x Internal reference, gain = 1.5x IDD, VDD = 3.3 V IDD, VDD = 5.5 V 0.35 Supply Current (mA) Supply Current (mA) 0.4 0.3 0.25 0.2 0.15 0.1 0.3 0.2 0.1 0.05 0 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Internal reference (gain = 4x), DAC at midscale Figure 32. Supply Current vs Temperature 14 0 1.8 2.3 2.8 3.3 3.8 4.3 Supply Voltage, VDD (V) 4.8 5.3 DAC at midscale Figure 33. Supply Current vs Supply Voltage Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 Typical Characteristics (continued) 0.1 6 0.0875 5 0.075 4 Output Voltage (V) Supply Current (mA) at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted) 0.0625 0.05 0.0375 3 2 1 0.025 0 IDD, VDD = 1.8 V IDD, VDD = 3.3 V IDD, VDD = 5.5 V 0.0125 0 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 -1 Reference = VDD = 1.8 V Reference = VDD = 5.5 V -2 -20 -15 -10 -5 0 5 Load Current (mA) 10 15 20 Reference = VDD, DAC powered down Figure 34. Power-Down Current vs Temperature Figure 35. Source and Sink Capability VOUT (1 LSB / div) Trigger (3 V / div) 0 0.5 1 1.5 2 2.5 3 Time (Ps) 3.5 4 4.5 VOUT (1 LSB / div) Trigger (3 V / div) 5 0 0.5 1 1.5 2 2.5 3 Time (Ps) 3.5 4 4.5 5 Reference = VDD = 5.5 V, DAC code transition from midscale to midscale + 1 LSB, DAC load = 5kΩ || 200pF Reference = VDD = 5.5 V, DAC code transition from midscale to midscale – 1 LSB, DAC load = 5kΩ || 200pF Figure 36. Glitch Impulse, Rising Edge, 1-LSB Step Figure 37. Glitch Impulse, Falling Edge, 1-LSB Step Trigger (2 V / div) VOUT (2 V / div) VOUT (Zoomed) (1 LSB / div) Trigger (2 V / div) VOUT (2 V / div) VOUT (Zoomed) (1 LSB / div) 0 2 4 6 8 10 12 Time (Ps) 14 16 18 20 Reference = VDD = 5.5 V, DAC load = 5kΩ || 200pF Figure 38. Full-Scale Settling Time, Rising Edge 0 2 4 6 8 10 12 Time (Ps) 14 16 18 20 Reference = VDD = 5.5 V, DAC load = 5kΩ || 200pF Figure 39. Full-Scale Settling Time, Falling Edge Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 15 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com Typical Characteristics (continued) at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted) VDD (1 V / div) VOUT unloaded (500 mV / div) VOUT 10K-GND (15 mV / div) 0 5 10 15 20 25 30 Time (ms) 35 40 45 VDD (1 V / div) VOUT unloaded (500 mV / div) VOUT 10K-GND (15 mV / div) 50 Reference = VDD = 5.5 V 0 5 10 15 20 25 30 Time (ms) 35 40 45 50 Reference = VDD = 5.5 V Figure 40. Power-on Glitch Figure 41. Power-off Glitch -40 VOUT (6 mV / div) SCL (4 V / div) -50 PSRR (dB) -60 -70 -80 -90 0 1 2 3 4 -100 10 5 Time (Ps) Reference = VDD = 5.5 V, Fast+ mode, DAC at midscale, DAC load = 5kΩ || 200pF 20 30 50 70100 200 500 1000 2000 Frequency (Hz) 5000 10000 Internal reference (gain = 4x), VDD = 5.25 V + 0.25 VPP, DAC at midscale, DAC load = 5kΩ || 200pF Figure 42. Clock Feedthrough Figure 43. DAC Output AC PSRR vs Frequency 4000 3000 DAC code = 0x008 DAC code = 0x200 DAC code = 0x3F8 3500 DAC code = 0x008 DAC code = 0x200 DAC code = 0x3F8 2500 Noise (nV / —Hz) Noise (nV / —Hz) 3000 2500 2000 1500 2000 1500 1000 1000 500 500 0 100 200 500 1000 2000 5000 10000 Frequency (Hz) 100000 Reference = VDD = 5.5 V 200 500 1000 2000 5000 10000 Frequency (Hz) 100000 Internal reference (gain = 4x), VDD = 5.5 V Figure 44. DAC Output Noise Spectral Density 16 0 100 Figure 45. DAC Output Noise Spectral Density Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 Typical Characteristics (continued) at TA = 25°C, 10-bit DAC, and DAC outputs unloaded (unless otherwise noted) 30 20 25 15 20 15 10 5 Noise (PV) Noise (PV) 10 0 -5 5 0 -5 -10 -10 -15 -20 -15 -25 -20 -30 0 1 2 3 4 5 6 Time (s) 7 8 9 Reference = VDD = 5.5 V, DAC at midscale 10 0 1 2 3 4 5 6 Time (s) 7 8 9 10 Internal reference (gain = 4x), VDD = 5.5 V, DAC at midscale Figure 46. DAC Output Noise: 0.1 Hz to 10 Hz Figure 47. DAC Output Noise: 0.1 Hz to 10 Hz Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 17 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com 8 Detailed Description 8.1 Overview The 10-bit DAC53401 and 8-bit DAC43401 (DACx3401) are a pin-compatible family of buffered voltage-output, digital-to-analog converters (DACs). These DACs contain nonvolatile memory (NVM), an internal reference, and a PMBus-compatible I2C interface. The DACx3401 operate with either an internal reference or with a power supply as the reference, and provide a full-scale output of 1.8 V to 5.5 V. The devices communicate through an I2C interface. These devices support I2C standard mode (100 kbps), fast mode (400 kbps), and fast+ mode (1 Mbps). These devices also support specific PMBus commands such as turn on/off, margin high/low, and more. The DACx3401 also include digital slew rate control, and support basic signal generation such as square, ramp, and sawtooth waveforms. The DACx3401 devices have a power-on-reset (POR) circuit that makes sure all the registers start with default or user-programmed settings using NVM. The DAC output powers on in high-impedance mode (default); this setting can be programmed to 10kΩ-GND using NVM. 8.2 Functional Block Diagram CAP VDD SCL SDA A0 I2C Interface PMBus Compatible LDO Internal Reference Non Volatile Memory DAC Buffer DAC Register DAC + BUF - OUT R1 FB R2 Power On Reset Power Down Logic AGND 18 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 8.3 Feature Description 8.3.1 Digital-to-Analog Converter (DAC) Architecture The DACx3401 family of devices consists of string architecture with an output buffer amplifier. The Functional Block Diagram section shows the DAC architecture within the block diagram. This DAC architecture operates from a 1.8-V to 5.5-V power supply. These devices consume only 0.2 mA of current when using a 1.8-V power supply. The DAC output pin starts up in high impedance mode making it an excellent choice for power-supply control applications. To change the power-up mode to 10kΩ-GND, program the DAC_PDN bit (address: D1h), and load these bits in the device NVM. 8.3.1.1 Reference Selection and DAC Transfer Function The device writes the input data to the DAC data registers in straight-binary format. After a power-on or a reset event, the device sets all DAC registers to the values set in the NVM. 8.3.1.1.1 Power Supply as Reference By default, the DACx3401 operate with the power-supply pin (VDD) as a reference. Equation 1 shows DAC transfer function when the power-supply pin is used as reference. VOUT DAC _ DATA 2N u VDD where: • • • • N is the resolution in bits, either 8 (DAC43401) or 10 (DAC53401). DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC register. DAC_DATA ranges from 0 to 2N – 1. VDD is used as the DAC reference voltage. (1) 8.3.1.1.2 Internal Reference The DACx3401 also contain an internal reference that is disabled by default. Enable the internal reference by writing 1 to REF_EN (address D1h). The internal reference generates a fixed 1.21-V voltage (typical). Using DAC_SPAN (address D1h) bits, gain of 1.5X, 2X, 3X, 4X can be achieved for the DAC output voltage (VOUT) Equation 2 shows DAC transfer function when the internal reference is used. VOUT DAC _ DATA 2N u VREF u GAIN where: • • • • • N is the resolution in bits, either 8 (DAC43401) or 10 (DAC53401). DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC register DAC_DATA ranges from 0 to 2N – 1. VREF is the internal reference voltage = 1.21 V. GAIN = 1.5x, 2x, 3x, 4x based on DAC_SPAN (address D1h) bits. Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 (2) 19 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com Feature Description (continued) 8.3.2 DAC Update The DAC output pin (OUT) is updated at the end of I2C DAC write frame. 8.3.2.1 DAC Update Busy The DAC_UPDATE_BUSY bit (address D0h) is set to 1 by the device when certain DAC update operations, such as function generation, transition to margin high or low, or any of the medical alarms are in progress. When the DAC_UPDATE_BUSY bit is set to 1, do not write to any of the DAC registers. After the DAC update operation is completed (DAC_UPDATE_BUSY = 0), any of the DAC registers can be written. 8.3.3 Nonvolatile Memory (EEPROM or NVM) The DACx3401 contain nonvolatile memory (NVM) bits. These memory bits are user programmable and erasable, and retain the set values in the absence of a power supply. All the register bits, as shown in Table 1, can be stored in the device NVM by setting NVM_PROG = 1 (address D3h). The NVM_BUSY bit (address D0h) is set to 1 by device when a NVM write or reload operation is ongoing. During this time, the device blocks all write operations to the device. The NVM_BUSY bit is set to 0 after the write or reload operation is complete; at this point, all write operations to the device are allowed. The default value for all the registers in the DACx3401 is loaded from NVM as soon as a POR event is issued. Do not perform a read operation from the DAC register while NVM_BUSY = 1. The DACx3401 also implement NVM_RELOAD bit (address D3h). Set this bit to 1 for the device to start an NVM reload operation. After the operation is complete, the device autoresets this bit to 0. During the NVM_RELOAD operation, the NVM_BUSY bit is set to 1. Table 1. NVM Programmable Registers REGISTER ADDRESS D1h D2h 20 REGISTER NAME GENERAL_CONFIG MED_ALARM_CONFIG BIT ADDRESS BIT NAME 15:14 FUNC_CONFIG 13 DEVICE_LOCK 11:9 CODE_STEP 8:5 SLEW_RATE 4:3 DAC_PDN 2 REF_EN 1:0 DAC_SPAN 10 MED_ALARM_HP 9 MED_ALARM_MP 8 MED_ALARM_LP 5:4 INTERBURST_TIME 3:2 PULSE_OFF_TIME 1:0 PULSE_ON_TIME D3h TRIGGER 8 START_FUNC_GEN 10h DAC_DATA 11:2 DAC_DATA 25h DAC_MARGIN_HIGH 11:4 MARGIN_HIGH (8 most significant bits) 26h DAC_MARGIN_LOW 11:4 MARGIN_LOW (8 most significant bits) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 8.3.3.1 NVM Cyclic Redundancy Check The DACx3401 implement a cyclic redundancy check (CRC) feature for the device NVM to make sure that the data stored in the device NVM is uncorrupted. There are two types of CRC alarm bits implemented in DACx3401: NVM_CRC_ALARM_USER and NVM_CRC_ALARM_INTERNAL. The NVM_CRC_ALARM_USER bit indicates the status of user-programmable NVM bits, and the NVM_CRC_ALARM_INTERNAL bit indicates the status of internal NVM bits The CRC feature is implemented by storing a 10-Bit CRC (CRC-10-ATM) along with the NVM data each time NVM program operation (write or reload) is performed and during the device start up. The device reads the NVM data and validates the data with the stored CRC. The CRC alarm bits (NVM_CRC_ALARM_USER and NVM_CRC_ALARM_INTERNAL address D0h) report any errors after the data are read from the device NVM. 8.3.3.2 NVM_CRC_ALARM_USER Bit A logic 1 on NVM_CRC_ALARM_USER bit indicates that the user-programmable NVM data is corrupt. During this condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be written to or read from. To reset the alarm bits to 0, issue a software reset (see the Software Reset section) command, or cycle power to the DAC. Alternatively, cycle the power to reload the user-programmable NVM bits. 8.3.3.3 NVM_CRC_ALARM_INTERNAL Bit A logic 1 on NVM_CRC_ALARM_INTERNAL bit indicates that the internal NVM data is corrupt. During this condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be written to or read from. To reset the alarm bits to 0, issue a software reset (see the Software Reset section) command or cycle power to the DAC. 8.3.4 Programmable Slew Rate When the DAC data registers are written, the voltage on DAC output (VOUT) immediately transitions to the new code following the slew rate and settling time specified in the Electrical Characteristics table. The slew rate control feature allows the user to control the rate at which the output voltage (VOUT) changes. When this feature is enabled (using SLEW_RATE[3:0] bits), the DAC output changes from the current code to the code in MARGIN_HIGH (address 25h) or MARGIN_LOW (address 26h) registers (when margin high or low commands are issued to the DAC) using the step and rate set in CODE_STEP and SLEW_RATE bits. With the default slew rate control setting (CODE_STEP and SLEW_RATE bits, address D1h), the output changes smoothly at a rate limited by the output drive circuitry and the attached load. Using this feature, the output steps digitally at a rate defined by bits CODE_STEP and SLEW_RATE on address D1h. SLEW_RATE defines the rate at which the digital slew updates; CODE_STEP defines the amount by which the output value changes at each update. Table 2 and Table 3 show different settings for CODE_STEP and SLEW_RATE. When the slew rate control feature is used, the output changes happen at the programmed slew rate. This configuration results in a staircase formation at the output. Do not write to CODE_STEP, SLEW_RATE, or DAC_DATA during the output slew. Table 2. Code Step REGISTER ADDRESS AND NAME D1h, GENERAL_CONFIG CODE_STEP[2] CODE_STEP[1] CODE_STEP[0] COMMENT 0 0 0 Code step size = 1 LSB (default) 0 0 1 Code step size = 2 LSB 0 1 0 Code step size = 3 LSB 0 1 1 Code step size = 4 LSB 1 0 0 Code step size = 6 LSB 1 0 1 Code step size = 8 LSB 1 1 0 Code step size = 16 LSB 1 1 1 Code step size = 32 LSB Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 21 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com Table 3. Slew Rate REGISTER ADDRESS AND NAME D1h, GENERAL_CONFIG 22 SLEW_RATE[3] SLEW_RATE[2] SLEW_RATE[1] SLEW_RATE[0] COMMENT 0 0 0 0 25.6 µs (per step) 0 0 0 1 25.6 µs × 1.25 (per step) 0 0 1 0 25.6 µs × 1.50 (per step) 0 0 1 1 25.6 µs × 1.75 (per step) 0 1 0 0 204.8 µs (per step) 0 1 0 1 204.8 µs × 1.25 (per step) 0 1 1 0 204.8 µs × 1.50 (per step) 0 1 1 1 204.8 µs × 1.75 (per step) 1 0 0 0 1.6384 ms (per step) 1 0 0 1 1.6384 ms × 1.25 (per step) 1 0 1 0 1.6384 ms × 1.50 (per step) 1 0 1 1 1.6384 ms × 1.75 (per step) 1 1 0 0 12 µs (per step) 1 1 0 1 8 µs (per step) 1 1 1 0 4 µs (per step) 1 1 1 1 No slew (default) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 8.3.5 Power-on-Reset (POR) The DACx3401 family of devices includes a power-on reset (POR) function that controls the output voltage at power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers to initialize to default values, and communication with the device is valid only after a 30-ms, POR delay. The default value for all the registers in the DACx3401 is loaded from NVM as soon as the POR event is issued. When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific VDD levels, as indicated in Figure 48, in order to make sure that the internal capacitors discharge and reset the device on power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD drops to less than 1.65 V, but remains greater than 0.7 V (shown as the undefined region), the device may or may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR. When VDD remains greater than 1.65 V, a POR does not occur. VDD (V) 5.5 V No power-on reset Spe cified supply voltage range 1.71 V 1.65 V Undefined 0.7 V Power-on reset 0V Figure 48. Threshold Levels for VDD POR Circuit 8.3.6 Software Reset To initiate a device software reset event, write the reserved code 1010 to the SW_RESET (address D3h). A software reset initiates a POR event. 8.3.7 Device Lock Feature The DACx3401 implement a device lock feature that prevents an accidental or unintended write to the DAC registers. The device locks all the registers when the DEVICE_LOCK bit (address D1h) is set to 1. To bypass the DEVICE_LOCK setting, write 0101 to the DEVICE_UNLOCK_CODE bits (address D3h). Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 23 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com 8.3.8 PMBus Compatibility PMBus is an I2C-based communication standard for power-supply management. PMBus contains standard command codes tailored to power supply applications. The DACx3401 implement some PMBus commands such as Turn Off, Turn On, Margin Low, Margin High, Communication Failure Alert Bit (CML), as well as PMBUS revision. Figure 49 shows typical PMBus connections. The EN_PMBus bit (Bit 12, address D1h) must be set to 1 to enable the PMBus protocol. Similar to I2C, PMBus is a variable length packet of 8-bit data bytes, each with a receiver acknowledge, wrapped between a start and stop bit. The first byte is always a 7-bit slave address followed by a write bit, sometimes called the even address that identifies the intended receiver of the packet. The second byte is an 8-bit command byte, identifying the PMBus command being transmitted using the respective command code. After the command byte, the transmitter either sends data associated with the command to write to the receiver command register (from most significant byte to least significant byte), or sends a new start bit indicating the desire to read the data associated with the command register from the receiver. After, the receiver transmits the data following the same most significant byte first format (see Table 10). ALERT PMBus-compatible device #1 DATA ALERT PMBus-compatible device #2 Control signal DATA Clock CLOCK ADDRESS CONTROL Data WP System Host ² Bus Master Alert signal WP CLOCK ADDRESS CONTROL Optional Required ALERT PMBus-compatible device #3 CLOCK WP DATA ADDRESS CONTROL Figure 49. PMBus Connections 24 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 8.4 Device Functional Modes 8.4.1 Power Down Mode The DACx3401 output amplifier and internal reference can be independently powered down through the DAC_PDN bits (address D1h). At power up, the DAC output and the internal reference are disabled by default. In power-down mode, the DAC output (OUT pin) is in a high-impedance state. To change this state to 10kΩ-AGND (at power up), use the DAC_PDN bits (address D1h). The DAC power-up state can be programmed to any state (power-down or normal mode) using the NVM. Table 4 shows the DAC power-down bits. Table 4. DAC Power-Down Bits REGISTER ADDRESS AND NAME DAC_PDN[1] DAC_PDN[0] 0 0 Power up 0 1 Power down to 10 kΩ 1 0 Power down to high impedance (HiZ) (default) 1 1 Power down to 10 kΩ D1h, GENERAL_CONFIG DESCRIPTION 8.4.2 Continuous Waveform Generation (CWG) Mode The DACx3401 implement a continuous waveform generation feature. To set the device to this mode, set the START_FUNC_GEN (address D3h) to 1. In this mode, the DAC output pin (OUT) generates a continuous waveform based on the FUNC_CONFIG bits (address D1h). Table 5 shows the continuous waveforms that can be generated in this mode. The frequency of the waveform depends on the resistive and capacitive load on the OUT pin, high and low codes, and slew rate settings as shown in the following equations. fSQUARE WAVE 1 2 u SLEW _ RATE where: • SLEW_RATE is the programmable DAC slew rate specified in Table 3. fTRIANGLE WAVE (3) 1 § MARGIN _ HIGH MARGIN _ LOW 1 · 2 u SLEW _ RATE u ¨ ¸ CODE _ STEP © ¹ where: • • • SLEW_RATE is the programmable DAC slew rate specified in Table 3. MARGIN_HIGH and MARGIN_LOW are the programmable DAC codes. CODE_STEP is the programmable DAC step code in Table 2. fSAWTOOTH WAVE (4) 1 § MARGIN _HIGH MARGIN _LOW 1 · SLEW _RATE u ¨ ¸ CODE _ STEP © ¹ where: • • • SLEW_RATE is the programmable DAC slew rate specified in Table 3. MARGIN_HIGH and MARGIN_LOW are the programmable DAC codes. CODE_STEP is the programmable DAC step code in Table 2. (5) Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 25 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com Table 5. FUNC_CONFIG bits REGISTER ADDRESS AND NAME FUNC_CONFIG[1] 0 0 FUNC_CONFIG[0] DESCRIPTION 0 Generates a triangle wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code with slope defined by SLEW_RATE (address D1h) bits 1 Generates Saw-Tooth wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code, with rising slope defined by SLEW_RATE (address D1h) bits and immediate falling edge 0 Generates Saw-Tooth wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code, with falling slope defined by SLEW_RATE (address D1h) bits and immediate rising edge 1 Generates a square wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code with pulse high and low period defined by SLEW_RATE (address D1h) bits D1h, GENERAL_CONFIG 1 1 8.4.3 PMBus Compatibility Mode The DACx3401 I2C interface implements some of the PMBus commands. Table 6 shows the supported PMBus commands that are implemented in DACx3401.The DAC uses MARGIN_LOW (address 26h), MARGIN_HIGH (address 25h) bits, SLEW_RATE, and CODE_STEP bits (address D1h) for PMBUS_OPERATION_CMD. The EN_PMBus bit (Bit 12, address D1h) must be set to 1 to enable the PMBus protocol. Table 6. PMBus Operation Commands REGISTER ADDRESS AND NAME 01h, PMBUS_OPERATION PMBUS_OPERATION_CMD[15:8] DESCRIPTION 00h Turn off 80h Turn on 94h Margin low A4h Margin high The DACx3401 also implement PMBus features such as group command protocol and communication time-out failure. The CML bit (address 78h) indicates a communication fault in the PMBus. This bit is reset by writing 1. In case of timeout, if the SDA line is held low, the SDA line stays low during the time-out event until next SCL pulse is received. To get the PMBus version, read the PMBUS_VERSION bits (address 98h). 8.4.4 Medical Alarm Generation Mode The DACx3401 are also used to generate continuous alarm tones for medical devices. Use a suitable analog mixer, audio amplifier, and a speaker to generate low, medium, or high priority alarm tones. See the Application and Implementation section for more details. The DACx3401 allow tunability and configurability to support different alarm generation. Using this approach, configurable medical alarm tones can be generated with a simple circuit, and with no need for runtime software. 8.4.4.1 Low-Priority Alarm The MED_ALARM_LP bit (address D2h) is used to trigger a medical low-priority alarm generation. The DAC generates a continuous-alarm signal until this bit is set back to 0. After the bit is set to 0, the device does not abruptly end the alarm generation; the device stops only after completing the ongoing burst. 26 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 8.4.4.2 Medium-Priority Alarm The MED_ALARM_MP bit (address D2h) is used to trigger a medical medium-priority alarm generation. The DAC generates a continuous-alarm signal until this bit is set back to 0. After the bit is set to 0, the device does not abruptly end the alarm generation; the device stops only after completing the ongoing burst. 8.4.4.3 High-Priority Alarm The MED_ALARM_HP bit (address D2h) is used to trigger a medical high-priority alarm generation. The DAC generates a continuous-alarm signal until this bit is set back to 0. After the bit is set to 0, the device does not abruptly end the alarm generation; the device stops only after completing the ongoing burst. 8.4.4.4 Interburst Time The INTERBURST_TIME bit (address D2h) is used set the time between two adjacent bursts. Table 7 lists the INTERBURST_TIME settings. Table 7. Interburst Time REGISTER ADDRESS AND NAME INTERBURST_TIME[1:0] HIGH PRIORITY ALARM INTERBURST TIME MEDIUM PRIORITY ALARM INTERBURST TIME 00 2.55 s 2.60 s 01 2.96 s 3.06 s 10 3.38 s 3.52 s 11 3.80 s 4.00 s D2h, MED_ALARM_CONFIG LOW PRIORITY ALARM INTERBURST TIME 16 s 8.4.4.5 Pulse Off Time The PULSE_OFF_TIME bit (address D2h) is used to control the low period of trapezoid in a medical alarm waveform. Table 8 lists the PULSE_OFF_TIME settings. Table 8. Pulse Off Time REGISTER ADDRESS AND NAME PULSE_OFF_TIME[1:0] HIGH PRIORITY ALARM PULSE OFF TIME MEDIUM PRIORITY ALARM PULSE OFF TIME LOW PRIORITY ALARM PULSE OFF TIME 00 15 ms 40 ms 40 ms 01 36 ms 60 ms 60 ms 10 58 ms 80 ms 80 ms 11 80 ms 100 ms 100 ms D2h, MED_ALARM_CONFIG 8.4.4.6 Pulse On Time The PULSE_ON_TIME bit (address D2h) controls the high period of trapezoid in a medical alarm waveform. Table 9 lists the PULSE_ON_TIME settings. Table 9. Pulse On Time REGISTER ADDRESS AND NAME D2h, MED_ALARM_CONFIG HIGH PRIORITY ALARM PULSE ON TIME MEDIUM PRIORITY ALARM PULSE ON TIME LOW PRIORITY ALARM PULSE ON TIME 00 80 ms 130 ms 130 ms 01 103 ms 153 ms 153 ms 10 126 ms 176 ms 176 ms 11 150 ms 200 ms 200 ms PULSE_ON_TIME[1:0] Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 27 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com 8.5 Programming The DACx3401 devices have a 2-wire serial interface (SCL and SDA), and one address pin (A0), as shown in the Pin Configuration and Functions section. The I2C bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through the open drain I/O pins, SDA and SCL. The I2C specification states that the device that controls communication is called a master, and the devices that are controlled by the master are called slaves. The master device generates the SCL signal. The master device also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device on an I2C bus is typically a microcontroller or digital signal processor (DSP). The DACx3401 family operates as a slave device on the I2C bus. A slave device acknowledges master commands, and upon master control, receives or transmits data. Typically, the DACx3401 family operates as a slave receiver. A master device writes to the DACx3401, a slave receiver. However, if a master device requires the DACx3401 internal register data, the DACx3401 operate as a slave transmitter. In this case, the master device reads from the DACx3401. According to I2C terminology, read and write refer to the master device. The DACx3401 family is a slave and supports the following data transfer modes: • Standard mode (100 kbps) • Fast mode (400 kbps) • Fast+ mode (1.0 Mbps) The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred to as F/S-mode in this document. The fast+ mode protocol is supported in terms of data transfer speed, but not output current. The low-level output current would be 3 mA; similar to the case of standard and fast modes. The DACx3401 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device supports the general call reset function. Sending the following sequence initiates a software reset within the device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of the ACK bit, following the second byte. Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock cycle generates and detects an acknowledge signal. Acknowledge is when the SDA line is pulled low during the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high period of the ninth clock cycle as shown in Figure 50. Data output by transmitter Not acknowledge Data output by receiver Acknowledge 1 SCL from master 2 9 8 S Clock pulse for acknowledgement Start condition Figure 50. Acknowledge and Not Acknowledge on the I2C Bus 28 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 Programming (continued) 8.5.1 F/S Mode Protocol The following steps explain a complete transaction in F/S mode. 1. The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 51. All I2C-compatible devices recognize a start condition. 2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit (R/W) on the SDA line. During all transmissions, the master makes sure that data are valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown in Figure 52. All devices recognize the address sent by the master and compare the address to the respective internal fixed address. Only the slave device with a matching address generates an acknowledge by pulling the SDA line low during the entire high period of the 9th SCL cycle, as shown in Figure 50. When the master detects this acknowledge, the communication link with a slave has been established. 3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In either case, the receiver must acknowledge the data sent by the transmitter. The acknowledge signal can be generated by the master or by the slave, depending on which is the receiver. The 9-bit valid data sequences consists of 8-data bits and 1 acknowledge-bit, and can continue as long as necessary. 4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low-to-high while the SCL line is high (see Figure 51). This action releases the bus and stops the communication link with the addressed slave. All I2C-compatible devices recognize the stop condition. Upon receipt of a stop condition, the bus is released, and all slave devices then wait for a start condition followed by a matching address. SDA SDA SCL SCL S Start condition P Stop condition Figure 51. Start and Stop Conditions Data line stable Data valid Change of data allowed Figure 52. Bit Transfer on the I2C Bus Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 29 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com 8.5.2 DACx3401 I2C Update Sequence For a single update, the DACx3401 require a start condition, a valid I2C address byte, a command byte, and two data bytes, as listed in Table 10. Table 10. Update Sequence MSB .... LSB ACK MSB ... LSB ACK MSB ... LSB ACK MSB ... LSB Address (A) byte Address Byte Command byte Command Byte Data byte - MSDB Application Curves Data byte - LSDB Application Curves DB [31:24] DB [23:16] DB [15:8] DB [7:0] ACK After each byte is received, the DACx3401 family acknowledges the byte by pulling the SDA line low during the high period of a single clock pulse, as shown in Figure 53. These four bytes and acknowledge cycles make up the 36 clock cycles required for a single update to occur. A valid I2C address byte selects the DACx3401 devices. Recognize START or REPEATED START condition Recognize STOP or REPEATED START condition Generate ACKNOWLEDGE signal P SDA MSB Address SCL Sr Acknowledgement signal from Slave 1 R/W 7 8 9 1 2-8 9 Sr or P S or Sr ACK START or REPEATED START condition Clock line held low while interrupts are serviced ACK REPEATED START or STOP condition Figure 53. I2C Bus Protocol The command byte sets the operating mode of the selected DACx3401 device. For a data update to occur when the operating mode is selected by this byte, the DACx3401 device must receive two data bytes: the most significant data byte (MSDB) and least significant data byte (LSDB). The DACx3401 device performs an update on the falling edge of the acknowledge signal that follows the LSDB. When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 10 kSPS. Using the fast+ mode (clock = 1 MHz), the maximum DAC update rate is limited to 25 kSPS. When a stop condition is received, the DACx3401 device releases the I2C bus and awaits a new start condition. 8.5.3 Address Byte The address byte, as shown in Table 11, is the first byte received following the start condition from the master device. The first four bits (MSBs) of the address are factory preset to 1001. The next three bits of the address are controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is sampled during the first byte of each data frame to determine the address. The device latches the value of the address pin, and consequently responds to that particular address according to Table 12. The DACx3401 family supports broadcast addressing, which can be used for synchronously updating or powering down multiple DACx3401 devices. The DACx3401 family is designed to work with other members of the family to support multichip synchronous updates. Using the broadcast address, the DACx3401 devices respond regardless of the states of the address pins. Broadcast is supported only in write mode. 30 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 Table 11. Address Byte COMMENT MSB — AD6 AD5 AD4 AD3 General address 1 0 0 1 Broadcast address 1 0 0 0 LSB AD2 AD1 AD0 R/W See Table 12 (slave address column) 1 1 0 or 1 1 0 Table 12. Address Format SLAVE ADDRESS A0 PIN 000 AGND 001 VDD 010 SDA 011 SCL 8.5.4 Command Byte Table 16 lists the command byte. Table 13. Command Byte (Register Names) 8.5.5 ADDRESS REGISTER NAME D0h STATUS D1h GENERAL_CONFIG D2h MED_ALARM_CONFIG D3h TRIGGER 21h DAC_DATA 25h DAC_MARGIN_HIGH 26h DAC_MARGIN_LOW 01h PMBUS_OP 78h PMBUS_STATUS_BYTE 98h PMBUS_VERSION I2C Read Sequence To read any register the following command sequence must be used: 1. Send a start or repeated start command with a slave address and the R/W bit set to 0 for writing. The device acknowledges this event. 2. Send a command byte for the register to be read. The device acknowledges this event again. 3. Send a repeated start with the slave address and the R/W bit set to 1 for reading. The device acknowledges this event. 4. The device writes the MSDB byte of the addressed register. The master must acknowledge this byte. 5. Finally, the device writes out the LSDB of the register. An alternative reading method allows for reading back the value of the last register written. The sequence is a start or repeated start with the slave address and the R/W bit set to 1, and the two bytes of the last register are read out. Note that it is not possible to use the broadcast address for reading. Table 14. Read Sequence S MSB … R/W (0) ACK ADDRESS BYTE Address Byte From Master MSB … LSB ACK COMMAND BYTE Command Byte Slave From Master Sr MSB … Sr Slave R/W (1) ACK ADDRESS BYTE Address Byte From Master MSB … LSB ACK MSDB Slave MSB … LSB LSDB From Slave Master From Slave Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 ACK Master 31 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com 8.6 Register Map Table 15. Register Map MOST SIGNIFICANT DATA BYTE (MSDB) LEAST SIGNIFICANT DATA BYTE (LSDB) ADDRESS D0h D1h BIT15 BIT14 NVM_CRC_ ALARM_ USER NVM_CRC_ ALARM_ INTERNAL FUNC_CONFIG D2h BIT13 BIT12 NVM_BUSY DAC_ UPDATE_ BUSY DEVICE_ LOCK EN_PMBUS BIT9 BIT8 BIT7 BIT6 BIT5 X (1) X BIT3 BIT2 BIT1 DEVICE_ID CODE_STEP MED_ ALARM_HP BIT4 SLEW_RATE MED_ ALARM_MP MED_ ALARM_LP DEVICE_ CONFIG_ RESET START_ FUNC_ GEN RESERVED PMBUS_ MARGIN_ HIGH PMBUS_ MARGIN_ LOW DAC_PDN INTERBURST_TIME NVM_ RELOAD VERSION_ID REF_EN PULSE_OFF_TIME NVM_ PROG BIT0 DAC_SPAN PULSE_ON_TIME D3h DEVICE_UNLOCK_CODE 21h X DAC_DATA[9:0] (10-Bit) or DAC_DATA[7:0] (8-Bit) X 25h X MARGIN_HIGH[9:0] (10-Bit) or MARGIN_HIGH[7:0] (8-Bit) X 26h X MARGIN_LOW[9:0] (10-Bit) or MARGIN_LOW[7:0] (8-Bit) X 98h SW_RESET X PMBUS_OPERATION_CMD 78h 32 BIT10 X 01h (1) BIT11 N/A CML PMBUS_VERSION N/A N/A X = Don't care. Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 Table 16. Register Names ADDRESS REGISTER NAME SECTION D0h STATUS STATUS Register (address = D0h) (reset = 000Ch or 0014h) D1h GENERAL_CONFIG GENERAL_CONFIG Register (address = D1h) (reset = 01F0h) D2h MED_ALARM_CONFIG MED_ALARM_CONFIG Register (address = D2h) (reset = 0000h) D3h TRIGGER TRIGGER Register (address = D3h) (reset = 0008h) 21h DAC_DATA DAC_DATA Register (address = 21h) (reset = 0000h) 25h DAC_MARGIN_HIGH DAC_MARGIN_HIGH Register (address = 25h) (reset = 0000h) 26h DAC_MARGIN_LOW DAC_MARGIN_LOW Register (address = 26h) (reset = 0000h) 01h PMBUS_OPERATION PMBUS_OPERATION Register (address = 01h) (reset = 0000h) 78h PMBUS_STATUS_BYTE PMBUS_STATUS_BYTE Register (address = 78h) (reset = 0000h) 98h PMBUS_VERSION PMBUS_VERSION Register (address = 98h) (reset = 2200h) Table 17. Access Type Codes Access Type Code Description X X Don't care R Read W Write Read Type R Write Type W Reset or Default Value -n Value after reset or the default value Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 33 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com 8.6.1 STATUS Register (address = D0h) (reset = 000Ch or 0014h) Figure 54. STATUS Register 15 NVM_CRC_ ALARM_ USER R-0h 14 NVM_CRC_ ALARM_ INTERNAL R-0h 13 NVM_ BUSY 12 DAC_ UPDATE_ BUSY R-0h R-0h 11 10 9 8 7 6 5 4 3 DEVICE_ID X X-00h 2 1 0 VERSION_ID 10-bit: R-0Ch 8-bit: R-14h Table 18. STATUS Register Field Descriptions Bit Field Type Reset Description 15 NVM_CRC_ALARM_USER R 0 0 : No CRC error in user NVM bits 1: CRC error in user NVM bits 14 NVM_CRC_ALARM_INTERNAL R 0 0 : No CRC error in internal NVM 1: CRC error in internal NVM bits 13 NVM_BUSY R 0 0 : NVM write or load completed, Write to DAC registers allowed 1 : NVM write or load in progress, Write to DAC registers not allowed 12 DAC_UPDATE_BUSY R 0 0 : DAC outputs updated, Write to DAC registers allowed 1 : DAC outputs update in progress, Write to DAC registers not allowed 11 - 6 X X 00h Don't care 5-2 DEVICE_ID R 1-0 VERSION_ID DAC53401: 0Ch DAC43401: 14h DAC53401: 0Ch DAC43401: 14h 8.6.2 GENERAL_CONFIG Register (address = D1h) (reset = 01F0h) Figure 55. GENERAL_CONFIG Register 15 14 FUNC_ CONFIG R/W-0h 13 DEVICE_ LOCK W-0h 12 EN_ PMBUS R/W-0h 11 10 9 CODE_STEP 8 R/W-0h 7 6 SLEW_RATE 5 R/W-Fh 4 3 DAC_PDN 2 REF_EN 1 0 DAC_SPAN R/W-2h R/W-0h R/W-0h Table 19. GENERAL_CONFIG Register Field Descriptions Bit 34 Field Type Reset Description 15 - 14 FUNC_CONFIG R/W 00 00 : Generates a triangle wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code with slope defined by SLEW_RATE (address D1h) bits. 01: Generates Saw-Tooth wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code, with rising slope defined by SLEW_RATE (address D1h) bits and immediate falling edge. 10: Generates Saw-Tooth wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code, with falling slope defined by SLEW_RATE (address D1h) bits and immediate rising edge. 11: Generates a square wave between MARGIN_HIGH (address 25h) code to MARGIN_LOW (address 26h) code with pulse high and low period defined by SLEW_RATE (address D1h) bits. 13 DEVICE_LOCK W 0 0 : Device not locked 1: Device locked, the device locks all the registers. This bit can be reset (unlock device) by writing 0101 to the DEVICE_UNLOCK_CODE bits (address D3h) 12 EN_PMBUS R/W 0 0: PMBus mode disabled 1: PMBus mode enabled Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 Table 19. GENERAL_CONFIG Register Field Descriptions (continued) Field Type Reset Description 11 - 9 Bit CODE_STEP R/W 000 Code step for programmable slew rate control. 000: Code step size = 1 LSB (default) 001: Code step size = 2 LSB 010: Code step size = 3 LSB 011: Code step size = 4 LSB 100: Code step size = 6 LSB 101: Code step size = 8 LSB 110: Code step size = 16 LSB 111: Code step size = 32 LSB 8-5 SLEW_RATE R/W 1111 Slew rate for programmable slew rate control. 0000: 25.6 µs (per step) 0001: 25.6 µs × 1.25 (per step) 0010: 25.6 µs × 1.50 (per step) 0011: 25.6 µs × 1.75 (per step) 0100: 204.8 µs (per step) 0101: 204.8 µs × 1.25 (per step) 0110: 204.8 µs × 1.50 (per step) 0111: 204.8 µs × 1.75 (per step) 1000: 1.6384 ms (per step) 1001: 1.6384 ms × 1.25 (per step) 1010: 1.6384 ms × 1.50 (per step) 1011: 1.6384 ms × 1.75 (per step) 1100: 12 µs (per step) 1101: 8 µs (per step) 1110: 4 µs (per step) 1111: No slew (default) 4-3 DAC_PDN R/W 10 00: Power up 01: Power down to 10K 10: Power down to high impedance (default) 11: Power down to 10K REF_EN R/W 0 0: Internal reference disabled, VDD is DAC reference voltage, DAC output range from 0 to VDD. 1: Internal reference enabled, DAC reference = 1.21 V DAC_SPAN R/W 00 Only applicable when internal reference is enabled. 00: Reference to VOUT gain 1.5X 01: Reference to VOUT gain 2X 10: Reference to VOUT gain 3X 11: Reference to VOUT gain 4X 2 1-0 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 35 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com 8.6.3 MED_ALARM_CONFIG Register (address = D2h) (reset = 0000h) Figure 56. MED_ALARM_CONFIG Register 15 14 13 12 11 X X-0h 10 MED_ ALARM_ HP W-0h 9 MED_ ALARM_ MP W-0h 8 MED_ ALARM_ LP W-0h 7 6 RESERVED 5 4 MED_ALARM_ DEAD_TIME RESERVED W-0h 3 2 PULSE_ OFF_TIME 1 0 PULSE_ ON_TIME W-0h W-0h Table 20. MED_ALARM_CONFIG Register Field Descriptions Bit Field Type Reset Description X X 00h Don't care 10 MED_ALARM_HP W 0 0: No medical alarm waveform generated 1: High priority medical alarm waveform generated 9 MED_ALARM_MP W 0 0: No medical alarm waveform generated 1: Medium priority medical alarm waveform generated 8 MED_ALARM_LP W 0 0: No medical alarm waveform generated 1: Low priority medical alarm waveform generated 7-6 RESERVED Reserved 0 RESERVED 5-4 INTERBURST_TIME W 00 High priority alarm 00: 2.55 sec 01: 2.96 sec 10: 3.38 sec 11: 3.80 sec Medium priority alarm 00: 2.60 sec 01: 3.06 sec 10: 3.52 sec 11: 4.00 sec Low priority alarm 00: 16 sec 01: 16 sec 10: 16 sec 11: 16 sec 3-2 PULSE_OFF_TIME W 00 High priority alarm 00: 15 msec 01: 36 msec 10: 58 msec 11: 80 msec Medium priority alarm 00: 40 msec 01: 60 msec 10: 80 msec 11: 100 msec Low priority alarm 00: 40 msec 01: 60 msec 10: 80 msec 11: 100 msec 1-0 PULSE_ON_TIME W 00 High priority alarm 00: 80 msec 01: 103 msec 10: 126 msec 11: 150 msec Medium priority alarm 00: 130 msec 01: 153 msec 10: 176 msec 11: 200 msec Low priority alarm 00: 130 msec 01: 153 msec 10: 176 msec 11: 200 msec 15 - 11 36 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 8.6.4 TRIGGER Register (address = D3h) (reset = 0008h) Figure 57. TRIGGER Register 15 14 13 12 DEVICE_UNLOCK_CODE 11 W-0h 10 X X 9 DEVICE_ CONFIG_ RESET W-0h 8 START_ FUNC_ GEN W-0h 7 PMBUS_ MARGIN_ HIGH R/W-0h 6 PMBUS_ MARGIN_ LOW R/W-0h 5 NVM_ RELOAD 4 NVM_ PROG W-0h W-0h 3 2 1 0 SW_RESET W-8h Table 21. TRIGGER Register Field Descriptions Field Type Reset Description 15 - 12 Bit DEVICE_UNLOCK_CODE W 0000 Write 0101 to unlock the device to bypass DEVICE_LOCK bit. 11 - 10 X X 0h Don't care 9 DEVICE_CONFIG_RESET W 0 0: Device configuration reset not initiated 1: Device configuration reset initiated. All registers loaded with factory reset values. 8 START_FUNC_GEN W 0 0: Continuous waveform generation mode disabled 1: Continuous waveform generation mode enabled, device generates continuous waveform based on FUNC_CONFIG (D1h), MARGIN_LOW (address 18h), and SLEW_RATE (address D1h) bits. 7 PMBUS_MARGIN_HIGH R/W 0 0: PMBus margin high command not initiated 1: PMBus margin high command initiated, DAC output margins high to MARGIN_HIGH code (address 25h). This bit automatically resets to 0 after the DAC code reaches MARGIN_HIGH value. 6 PMBUS_MARGIN_LOW R/W 0 0: PMBus margin low command not initiated 1: PMBus margin low command initiated, DAC output margins low to MARGIN_LOW code (address 26h). This bit automatically resets to 0 after the DAC code reaches MARGIN_LOW value. 5 NVM_RELOAD W 0 0: NVM reload not initiated 1: NVM reload initiated, applicable DAC registers loaded with corresponding NVM. NVM_BUSY bit set to 1 which this operation is in progress.. This is a self-resetting bit. 4 NVM_PROG W 0 0: NVM write not initiated 1: NVM write initiated, NVM corresponding to applicable DAC registers loaded with existing register settings. NVM_BUSY bit set to 1 which this operation is in progress. This is a self-resetting bit. 3-0 SW_RESET W 1000 1000: Software reset not initiated 1010: Software reset initiated, DAC registers loaded with corresponding NVMs, all other registers loaded with default settings. Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 37 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com 8.6.5 DAC_DATA Register (address = 21h) (reset = 0000h) Figure 58. DAC_DATA Register 15 14 13 12 11 10 X X-0h 9 8 7 6 5 4 DAC_DATA[9:0] / DAC_DATA[7:0] – MSB Left aligned W-000h 3 2 1 0 X X-0h Table 22. DAC_DATA Register Field Descriptions Bit Field Type Reset Description 15-12 X X 0h Don't care 11-2 DAC_DATA[9:0] / DAC_DATA[7:0] W 000h Writing to the DAC_DATA register forces the respective DAC channel to update the active register data to the DAC_DATA. Data are in straight binary format and use the following format: DAC53401: { DATA[9:0] } DAC43401: { DATA[7:0], X, X } X = Don’t care bits 1-0 X X 0h Don't care 8.6.6 DAC_MARGIN_HIGH Register (address = 25h) (reset = 0000h) Figure 59. DAC_MARGIN_HIGH Register 15 14 13 12 11 10 9 8 7 6 5 4 3 MARGIN_HIGH[9:0] / MARGIN_HIGH[7:0] – MSB Left aligned W-000h X X-0h 2 1 0 X X-0h Table 23. DAC_MARGIN_HIGH Register Field Descriptions Bit Field Type Reset Description 15-12 X X 0h Don't care 11-2 MARGIN_HIGH[9:0] / MARGIN_HIGH[7:0] – MSB Left aligned W 000h Margin high code for DAC output. Data are in straight binary format and use the following format: DAC53401: { MARGIN_HIGH[[9:0] } DAC43401: { MARGIN_HIGH[[7:0], X, X } X = Don’t care bits 1-0 X X 0h Don't care 8.6.7 DAC_MARGIN_LOW Register (address = 26h) (reset = 0000h) Figure 60. DAC_MARGIN_LOW Register 15 14 13 12 11 X X-0h 10 9 8 7 6 5 4 3 MARGIN_LOW[9:0] / MARGIN_LOW[7:0] – MSB Left aligned W-000h 2 1 0 X X-0h Table 24. DAC_MARGIN_LOW Register Field Descriptions Field Type Reset Description 15-12 Bit X X 0h Don't care 11-2 MARGIN_LOW[9:0] / MARGIN_LOW[7:0] – MSB Left aligned W 000h Margin low code for DAC output. Data is in straight binary format and follows the format below: DAC53401: { MARGIN_LOW[[9:0] } DAC43401: { MARGIN_LOW[[7:0], X, X } X = Don’t care bits 1-0 38 X X 0h Don't care Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 8.6.8 PMBUS_OPERATION Register (address = 01h) (reset = 0000h) Figure 61. PMBUS_OPERATION Register 15 14 13 12 11 10 PMBUS_OPERATION_CMD R/W-00h 9 8 7 6 5 4 3 2 1 0 X X-00h Table 25. PMBUS_OPERATION Register Field Descriptions Bit Field Type Reset Description 15 - 8 PMBUS_OPERATION_CMD R/W 00h PMBus operation commands 00h: Turn off 80h: Turn on A4h: Margin high, DAC output margins high to MARGIN_HIGH code (address 25h) 94h: Margin low, DAC output margins low to MARGIN_LOW code (address 26h) 7-0 X X 00h Not applicable 8.6.9 PMBUS_STATUS_BYTE Register (address = 78h) (reset = 0000h) Figure 62. PMBUS_STATUS_BYTE Register 15 14 13 12 11 10 9 CML R/W0h X X-00h 8 7 6 5 4 X X-000h 3 2 1 0 Table 26. PMBUS_STATUS_BYTE Register Field Descriptions Bit 15 - 10 9 8-0 Field Type Reset Description X X 00h Don't care CML R/W 0 0: No communication Fault 1: PMBus communication fault for timeout, write with incorrect number of clocks, read before write command, and so more; reset this bit by writing 1. X X 000h Not applicable 8.6.10 PMBUS_VERSION Register (address = 98h) (reset = 2200h) Figure 63. PMBUS_VERSION Register 15 14 13 12 11 PMBUS_VERSION R-22h 10 9 8 7 6 5 4 3 2 1 0 X X-00h Table 27. PMBUS_VERSION Register Field Descriptions Field Type Reset Description 15 - 8 Bit PMBUS_VERSION R 22h PMBus version 7-0 X X 00h Not applicable Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 39 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The DACx3401 are buffered, force-sense output, single-channel, DACs that include an NVM and internal reference and are available in a tiny 3 × 3 package . These DACs are designed for general-purpose applications in a wide range of end equipment. Some of the most common applications for these devices are power-supply margining and control, adaptive voltage scaling (AVS), set-and-forget LED biasing in mobile projectors, generalpurpose function generation, medical alarm generation, and programmable comparator applications (such as smoke detectors, standalone PWM control loops, and offset and gain trimming in precision circuits). 9.2 Typical Applications This section explains the design details of three primary applications of DACx3401: programmable LED biasing, power-supply margining. and medical alarm generation. 9.2.1 Programmable LED Biasing LED and laser biasing or driving circuits often require accuracy and stability of the luminosity with respect to variation in temperature, electrical conditions, and physical characteristics. This accuracy and stability are most effectively achieved using a precision DAC, such as the DACx3401. The DACx3401 have additional features, such as the VFB pin that compensates for the gate-to-source voltage of the transistor (VGS) drop and the drift of the MOSFET. The NVM allows the microprocessor to set-and-forget the LED biasing value, even during a power cycle. Figure 64 shows the circuit diagram for LED biasing. VCC LED VDD ILED = ISET DACx340 1 VFB VOUT + VGS Q1 VDAC RSET ISET Figure 64. LED Biasing 9.2.1.1 Design Requirements • • 40 DAC output range: 0 V to 2.4 V LED current range: 0 mA to 20 mA Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 Typical Applications (continued) 9.2.1.2 Detailed Design Procedure The DAC sets the source current of a MOSFET using the integrated buffer, as shown in Figure 64. Connect the LED between the power supply and the drain of the MOSFET. This configuration allows the DAC to control or set the amount of current through the LED. The integrated buffer controls the gate-source voltage of the MOSFET inside the feedback loop, thus compensating this drop and corresponding drift due to temperature, current, and ageing of the MOSFET. Calculate the value of the LED current set by the DAC using Equation 6. In order to generate 0 mA to 20 mA from a 0-V to 2.4-V DAC output range, the value of RSET resistor is 120-Ω. Select the internal reference with a span of 2x. Given a VGS of 1.2 V, the VDD of the DAC must be at least 3.6 V. Select a VDD of 5 V to allow variation of VGS across temperature. When the VDD headroom is a constraint, use a bipolar junction transistor (BJT) in place of the MOSFET. BJTs have much less VBE drop as compared to a VGS of a MOSFET. A MOSFET provides a much better match between the current through the set register and the LED current, as compared to a BJT. ISET VDAC RSET (6) The pseudocode for getting started with an LED biasing application is as follows: //SYNTAX: WRITE , , //Power-up the device, enable internal reference with 2x output span WRITE GENERAL_CONFIG(0xD1), 0x11, 0xE5 //Write DAC code (12-bit aligned) WRITE DAC_DATA(0x21), 0x07, 0xFC //Write settings to the NVM WRITE TRIGGER(0xD3), 0x00, 0x10 9.2.1.3 Application Curves LED breathing effect in triangular pattern LED breathing effect in sawtooth pattern Figure 65. Triangular Waveform Figure 66. Sawtooth Waveform Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 41 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com Typical Applications (continued) 9.2.2 Power-Supply Margining A power-supply margining circuit is used to test and trim the output of a power converter. This circuit is used to test a system by margining the power supplies, for adaptive voltage scaling, or to program a desired value at the output. Adjustable power supplies, such as LDOs and DC/DC converters provide a feedback or adjust input that is used to set the desired output. A precision voltage-output DAC is the best choice for controlling the powersupply output linearly. Figure 67 shows a control circuit for a switch-mode power supply (SMPS) using DACx3401. Typical applications of power-supply margining are communications equipment, enterprise servers, test and measurement, and general-purpose power-supply modules. L VIN IN PH VOUT BOOT CL SMPS VDD R1 CB R3 DACx3401 SENSE VFB GND R2 Figure 67. Power-Supply Margining 9.2.2.1 Design Requirements • • • • • Power supply nominal output: 3.3 V Reference voltage of the converter (VFB): 0.6 V Margin: ±10% (that is, 2.97 V to 3.63 V) DAC output range: 1.8 V Nominal current through R1 and R2: 100 µA 9.2.2.2 Detailed Design Procedure The DACx3401 features a Hi-Z power-down mode that is set by default at power-up, unless the device is programmed otherwise using the NVM. When the DAC output is at Hi-Z, the current through R3 is zero and the SMPS is set at the nominal output voltage of 3.3 V. To have the same nominal condition when the DAC powers up, bring up the device at the same output as VFB (that is 0.6 V). This configuration makes sure there is no current through R3 even at power-up. Calculate R1 as (VOUT – VFB) / 100 µA = 27 kΩ. To achieve ±10% margin-high and margin-low conditions, the DAC must sink or source additional current through R1. Calculate the current from the DAC (IMARGIN) using Equation 7 as 12 µA. IMARGIN § VOUT u 1 MARGIN ¨¨ R1 © VFB · ¸¸ INOMINAL ¹ where • • • IMARGIN is the margin current sourced or sinked from the DAC. MARGIN is the percentage margin value divided by 100. INOMINAL is the nominal current through R1 and R2. (7) In order to calculate the value of R3, first decide the DAC output range, and make sure to avoid the codes near zero-scale and full-scale for safe operation in the linear region. A DAC output of 20 mV is a safe consideration as the minimum output, and (1.8 V – 0.6 V – 20 mV = 1.18 V) as the maximum output. When the DAC output is at 20 mV, the power supply goes to margin high, and when the DAC output is at 1.18 V, the power supply goes to margin low. Calculate the value of R3 usingEquation 8 as 48.3 kΩ. Choose a standard resistor value and adjust the DAC outputs. Choosing R3 = 47 kΩ makes the DAC margin high code as 1.164 V and the DAC margin low code as 36 mV. 42 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 Typical Applications (continued) R3 VDAC VFB IMARGIN (8) The DACx3401 have a slew rate feature that is used to toggle between margin high, margin low, and nominal outputs with a defined slew rate. See the GENERAL_CONFIG register description for the slew rate setting details. NOTE The MARGIN HIGH register value in DACx3401 results in the MARGIN LOW value at the power supply output. Similarly, the MARGIN LOW register value in DACx3401 results in the MARGIN HIGH value at the power-supply output. The pseudocode for getting started with a power-supply control application is as follows: //SYNTAX: WRITE , , //Write DAC code (12-bit aligned) for nominal output //For a 1.8-V output range, the 10-bit hex code for 0.6 V is 0x0155. With 12bit alignment, it becomes 0x0554 WRITE DAC_DATA(0x21), 0x05, 0x54 //Write DAC code (12-bit aligned) for margin-low output at the power supply //For a 1.8-V output range, the 10-bit hex code for 1.164 V is 0x0296. With 12bit alignment, it becomes 0x0A58 WRITE DAC_MARGIN_HIGH(0x25), 0x0A, 0x58 //Write DAC code (12-bit aligned) for margin-high output at the power supply //For a 1.8-V output range, the 10-bit hex code for 36 mV is 0x14. With 12bit alignment, it becomes 0x50 WRITE DAC_MARGIN_LOW(0x26), 0x00, 0x50 //Powerup the device with enable internal reference with 1.5x output span. This will output the nominal voltage (0.6 V) //CODE_STEP: 2 LSB, SLEW_RATE: 25.6 µs WRITE GENERAL_CONFIG(0xD1), 0x12, 0x14 //Trigger margin-low output at the power supply WRITE TRIGGER(0xD3), 0x00, 0x80 //Trigger margin-high output at the power supply WRITE TRIGGER(0xD3), 0x00, 0x40 //Write back DAC code (12-bit aligned) for nominal output WRITE DAC_DATA(0x21), 0x05, 0x54 9.2.2.3 Application Curves Figure 68. Power-Supply Margin High Figure 69. Power Supply Margin Low Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 43 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com Typical Applications (continued) 9.2.3 Medical Alarm Generation All medical devices implementing an alarm system shall comply to IEC60601-1-8 standard for medical alarms (as per IEC60601-1 Ed 3.1). The regulatory tests are done at a system level; therefore, system level acoustics play a major role in the compliance. A medical alarm is a common functional block in many medical devices. A portable implementation is needed that can also be customized to fit mechanical and audio or acoustic requirements. The DACx3401-based design is aimed at providing a programmable, standalone, and robust implementation at a very low cost. There are three types of alarms with different timing requirements: low priority, medium priority, and high priority. Usually, for easy identification, different timings are employed for different equipment. Medical device manufacturers prefer using their signature melodies within the limits of the standard. 2k 2k 5V 5V 0.1 µF ± ± + DACx3401 + SHDN TLV342S 1k 20 k LM158 ±5 V DACx3401 Figure 70. Medical Alarm 9.2.3.1 Design Requirements • • Alarm envelope rise and fall time: 26 ms Alarm pulse frequency: 610 Hz 9.2.3.2 Detailed Design Procedure Two DACx3401 devices are required: one device to generate the pulse envelope and the burst, and the second device to generate the pulse frequency. As shown in Figure 70, mix both these signals together using the TLV342S amplifier with shutdown. Feed the combined signal to a power amplifier, such as the LM158, to drive the speaker. This design provides a gain of 2 at the speaker amplifier. The actual gain required in a system depends on the acoustic output requirements from the speaker. The RC high-pass filter, designed for a cut-off frequency of approximately 80 Hz at the input of LM158, removes the dc component from the signal so that this signal can be applied to the speaker directly. As per the medical alarm standard, the pulse frequency must be above 150 Hz. As a result of the square-wave pulse frequency and the mixing done by TLV342S, the speaker output has multiple harmonics of the fundamental pulse frequency, thus fulfilling the requirement of the medical alarm standard. The DACx3401 provide various options to program the pulse frequency and envelope timings. See the Medical Alarm Generation Mode section for the alarm configuration options. Calculate the frequency of a square wave or pulse frequency using Equation 3. The square wave function has a limited number of frequencies because this function is programmed by the SLEW_RATE bit alone. To get a higher number of frequencies, generate a triangular waveform with comparator mode output. Generate the triangular waveform using Equation 4. Set the DAC output in the comparator mode by fixing the VFB pin to the midscale of the DAC using a resistive voltage divider from VDD. Select VDD as the reference in this case using the GENERAL_CONFIG register. 44 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 Typical Applications (continued) The pseudocode for getting started with a medical alarm application using two DACs is as follows: //SYNTAX: WRITE , , //Power-up the first DAC, enable VDD reference //SLEW_RATE: 1.6384 ms (Square wave frequency: 610 Hz) WRITE GENERAL_CONFIG(0xD1), 0xD1, 0x58 //Set MARGIN_HIGH on the first DAC WRITE DAC_MARGIN_HIGH(0x25), 0x0F, 0xFC //Set MARGIN_LOW on the first DAC WRITE DAC_MARGIN_LOW(0x26), 0x00, 0x00 //Trigger square wave generation on the first DAC WRITE TRIGGER(0xD3), 0x01, 0x00 //Power-up the second DAC, enable VDD reference //CODE_STEP: 8 LSB, SLEW_RATE: 204.8 µs x 1.75 = 358.4 µs (Envelope rise/fall times for fullscale: ~26 ms) WRITE GENERAL_CONFIG(0xD1), 0x1A, 0xE8 //OPTION-1: Configure the second DAC for low-priority alarm with minimum time settings and trigger WRITE MED_ALARM_CONFIG(0xD2), 0x01, 0x00 //OPTION-2: Configure the second DAC for medium-priority alarm with minimum time settings and trigger WRITE MED_ALARM_CONFIG(0xD2), 0x02, 0x00 //OPTION-3: Configure the second DAC for high-priority alarm with minimum time settings and trigger WRITE MED_ALARM_CONFIG(0xD2), 0x04, 0x00 //Set MARGIN_HIGH on the second DAC WRITE DAC_MARGIN_HIGH(0x25), 0x0F, 0xFC //Set MARGIN_LOW on the second DAC WRITE DAC_MARGIN_LOW(0x26), 0x00, 0x00 9.2.3.3 Application Curves Figure 71. Low Priority Alarm Figure 72. Medium Priority Alarm Figure 73. High-Priority Alarm Figure 74. Pulse Frequency Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 45 DAC53401, DAC43401 SLASES7A – JULY 2019 – REVISED DECEMBER 2019 www.ti.com 10 Power Supply Recommendations The DACx3401 family of devices does not require specific supply sequencing. These devices require a single power supply, VDD. Use a 0.1-µF decoupling capacitor for the VDD pin. Use a bypass capacitor with a value greater than 1.5-µF for the CAP pin. 11 Layout 11.1 Layout Guidelines The DACx3401 pin configuration separates the analog, digital, and power pins for an optimized layout. For signal integrity, separate the digital and analog traces, and place decoupling capacitors close to the device pins. 11.2 Layout Example Figure 75 shows an example layout drawing with decoupling capacitors and pullup resistors. Pull-down for A0 Pull-up for S CL DACx340 1 1 8 SCL 2 7 SDA 3 6 4 5 Pull-up for S DA VOUT VFB VDD Decouplin g Capacitor GND GND LDO bypass capacitor (Note: Gro und and Power plan es omitted for cla rity) Figure 75. Layout Example 46 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 DAC53401, DAC43401 www.ti.com SLASES7A – JULY 2019 – REVISED DECEMBER 2019 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: Texas, Instruments DAC53401EVM user's guide 12.2 Related Links Table 28 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 28. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY DAC53401 Click here Click here Click here Click here Click here DAC43401 Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.5 Trademarks E2E is a trademark of Texas Instruments. PMBus is a trademark of SMIF, Inc. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Product Folder Links: DAC53401 DAC43401 47 PACKAGE OPTION ADDENDUM www.ti.com 8-Sep-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DAC43401DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 4341 DAC43401DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 4341 DAC53401DSGR ACTIVE WSON DSG 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5341 DAC53401DSGT ACTIVE WSON DSG 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 5341 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of