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DAC53608, DAC43608
SLASEQ4A – OCTOBER 2018 – REVISED DECEMBER 2018
DACx3608 Octal, 10-Bit or 8-Bit, I2CTM Interface, Buffered Voltage Output DACs
in Tiny 3 × 3 WQFN Package
1 Features
3 Description
•
•
The DAC53608 and DAC43608 (DACx3608) are lowpower, eight-channel, voltage-output, 10-bit or 8-bit
digital-to-analog converters (DACs) respectively. The
DACx3608 are specified monotonic by design across
a wide power supply range from 1.8 V to 5.5 V. Using
an external reference, the DACx3608 provides a full
scale output voltage range of 1.8 V to 5.5 V while
consuming 0.1-mA quiescent current per channel.
The DACx3608 also includes per channel, user
programmable, power down registers. These
registers facilitate the DAC output buffers to start in a
power down to 10K state and remain in this state until
a power up command is issued to these output
buffers.
±1-LSB INL and DNL
Wide Operating Range
– Power Supply: 1.8 V to 5.5 V
– Temperature Range: –40˚C to 125˚C
I2CTM Serial Interface
– Standard, Fast, and Fast+ Mode
– 2.4-V, VIH with VDD = 5.5 V
LDAC Pin For Simultaneous Output Update
Very Low Power: 0.1 mA/Channel at 1.8 V
Low Power Startup Mode: Outputs powered down
to 10K State
Tiny Package
– 16-Pin WQFN (3 mm × 3 mm)
1
•
•
•
•
•
2 Applications
•
•
•
•
•
•
The devices communicate through the I2CTM
interface. These devices support I2CTM standard
mode (100 kbps), fast mode (400 kbps), and fast+
mode (1 Mbps). These devices also have a load DAC
(LDAC) pin that allows simultaneous DAC updates.
Programmable Power Supplies
Programmable Window Comparator
VCOM Biasing in Display Panel
Laser Driver In Multifunction Printers
Auto Focus Digital Still Cameras Lens
ATM Machines, Currency Counters, Barcode
Readers
IP Network Cameras, Projectors
•
Low quiescent current, wide power supply range, and
per channel power down option makes DACx3608
ideal for low power, battery operated systems.
The DACx3608 are available in small 3-mm × 3-mm,
16-pin WQFN package. The devices are fully
specified over the extended industrial temperature
range of –40°C to +125°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DAC53608
WQFN (16)
3.00 mm × 3.00 mm
DAC43608
WQFN (16)
3.00 mm × 3.00 mm
(1) For all available packages, refer to the orderable addendum
at the end of the data sheet.
Simplified Block Diagram
Programmable Window Comparator
VIO
VREFIN
VDD
DACx3608
RPULL-UP
VDAC
SDA
A0
LDAC
I2CTM Interface
SCL
CLR
DAC
Buffer
Registers
THLD-HI
DACx3608
DAC
Active
Registers
DAC
BUF
+
VOUT
VOUTA
R1
RA
Channel A
VIN
VOUTH
Channel H
R2
Power On Reset
Resistive Network
RB
+
Power Down Logic
THLD-LO
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC53608, DAC43608
SLASEQ4A – OCTOBER 2018 – REVISED DECEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configurations and Functions .......................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
8
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Timing Requirements: I2CTM Standard Mode ........... 7
Timing Requirements: I2CTM Fast Mode................... 7
Timing Requirements: I2CTM Fast+ Mode................. 8
Timing Requirements: Logic ..................................... 8
Typical Characteristics: 1.8 V ............................... 10
Typical Characteristics: 5.5 V ............................... 12
Typical Characteristics .......................................... 17
Typical Characteristics .......................................... 18
Detailed Description ............................................ 19
8.1 Overview ................................................................. 19
8.2
8.3
8.4
8.5
8.6
9
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Map...........................................................
19
20
21
22
28
Application and Implementation ........................ 31
9.1 Application Information............................................ 31
9.2 Typical Applications ................................................ 31
10 Power Supply Recommendations ..................... 34
11 Layout................................................................... 35
11.1 Layout Guidelines ................................................. 35
11.2 Layout Example .................................................... 35
12 Device and Documentation Support ................. 36
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
36
36
36
36
36
36
36
13 Mechanical, Packaging, and Orderable
Information ........................................................... 37
4 Revision History
Changes from Original (October 2018) to Revision A
•
2
Page
Changed from Advance Information to Production Data ....................................................................................................... 1
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SLASEQ4A – OCTOBER 2018 – REVISED DECEMBER 2018
5 Device Comparison Table
DEVICE
RESOLUTION
DAC53608
10-Bit
DAC43608
8-Bit
6 Pin Configurations and Functions
CLR
VREFIN
AGND
VDD
16
15
14
13
RTE Package
16-Pin WQFN
Top View
VOUTC
3
10
VOUTF
VOUTD
4
9
VOUTE
8
VOUTG
LDAC
11
7
2
A0
VOUTB
6
VOUTH
SCL
12
5
1
SDA
VOUTA
Not to scale
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A0
7
I
Four-state address input
AGND
14
GND
CLR
16
I
Asynchronous clear pin (active low)
LDAC
8
I
Load DAC pin for simultaneous output update (active low)
SCL
6
I
Serial interface clock
SDA
5
I/O
Ground reference point for all circuitry on the device.
Data is clocked into or out of the input register. This pin is a bidirectional, open
drain data line that must be connected to the supply voltage with an external
pull-up resistor.
VDD
13
PWR
VOUTA
1
O
Analog supply voltage (1.8 V to 5.5 V).
Analog output voltage from DAC A
VOUTB
2
O
Analog output voltage from DAC B
VOUTC
3
O
Analog output voltage from DAC C
VOUTD
4
O
Analog output voltage from DAC D
VOUTE
9
O
Analog output voltage from DAC E
VOUTF
10
O
Analog output voltage from DAC F
VOUTG
11
O
Analog output voltage from DAC G
VOUTH
12
O
Analog output voltage from DAC H
VREFIN
15
I/O
Reference input to the device
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VDD to AGND
–0.3
6
VREFIN to AGND
–0.3
VDD + 0.3
Digital input(s) to AGND
–0.3
VDD + 0.3
Output voltage
VOUT to AGND
–0.3
VDD + 0.3
Input Current
Current into any pin
–10
10
Junction temperature,TJ
–40
150
Storage temperature, Tstg
–65
150
Input voltage
Temperature
(1)
UNIT
V
V
mA
°C
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, allpins (1)
±1000
Charged device model (CDM), per JEDEC
specificationJESD22-C101, all pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. [Following sentence
optional; see the wiki.] Manufacturing with less than 500-V HBM is possible with the necessary precautions. [Following sentence
optional; see the wiki.] Pins listed as ±WWW V and/or ±XXX V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. [Following sentence
optional; see the wiki.] Manufacturing with less than 250-V CDM is possible with the necessary precautions. [Following sentence
optional; see the wiki.] Pins listed as ±YYY V and/or ±ZZZ V may actually have higher performance.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VDD to AGND
Positive supply voltage to ground
VREFIN to AGND
VIH
NOM
MAX
UNIT
1.8
5.5
V
Reference input supply voltage to ground
1.8
VDD
V
Digital input high voltage, 1.8 ≤ VDD ≤ 2.7
VDD – 0.3
V
VIH
Digital input high voltage, 2.7 < VDD ≤ 5.5
2.4
V
VIL
Digital input low voltage
TA
Ambient temperature
–40
0.5
V
125
°C
7.4 Thermal Information
DACx3608
THERMAL METRIC (1)
RTE (WQFN)
UNIT
16 PIN
RθJA
Junction-to-ambient thermal resistance
49
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
50
°C/W
RθJB
Junction-to-board thermal resistance
24.1
°C/W
ΨJT
Junction-to-top characterization parameter
1.1
°C/W
YJB
Junction-to-board characterization parameter
24.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
8.7
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SLASEQ4A – OCTOBER 2018 – REVISED DECEMBER 2018
7.5 Electrical Characteristics
all minimum/maximum specifications at TA = –40°C to +125°C and all typical specification at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V,
VREFIN = 2.5 V for VDD ≥ 2.7 V, VREFIN = 1.8 V for VDD ≤ 2.7 V, RL= 5 kΩ to AGND, CL = 200 pF to AGND, and digital inputs at
VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
Resolution
Relative accuracy (1)
INL
DNL
Differential nonlinearity (1)
Zero code error
DAC53608
10
DAC43608
8
DAC43608, 2.7 V ≤ VDD ≤ 5.5 V
–1
1
DAC43608, 1.8 V ≤ VDD ≤ 2.7 V
–1
1
DAC53608, 2.7 V ≤ VDD ≤ 5.5 V
–1
1
DAC53608, 1.8 V ≤ VDD ≤ 2.7 V
–1
1
DAC43608, 2.7 V ≤ VDD ≤ 5.5 V
–1
1
DAC43608, 1.8 V ≤ VDD ≤ 2.7 V
–1
1
DAC53608, 2.7 V ≤ VDD ≤ 5.5 V
–1
1
DAC53608, 1.8 V ≤ VDD ≤ 2.7 V
–1
6
12
1.8 V ≤ VDD ≤ 2.7 V, code 0d into DAC
6
12
±5
Gain error (1)
–0.5
0.25
0.5
1.8 V ≤ VDD ≤ 2.7 V
–0.5
0.25
0.5
2.7 V ≤ VDD ≤ 5.5 V
–0.5
0.25
0.5
1.8 V ≤ VDD ≤ 2.7 V
–0.5
0.25
0.5
%FSR
%FSR
%FSR/°
C
±0.0004
Full scale error
mV
%FSR/°
C
±0.0003
Gain error temperature coefficient (1)
LSB
µV/°C
2.7 V ≤ VDD ≤ 5.5 V
Offset error temperature coefficient (1)
LSB
1
2.7 V ≤ VDD ≤ 5.5 V, code 0d into DAC
Zero code error temperature coefficient
Offset error (1)
Bits
2.7 V ≤ VDD ≤ 5.5 V, code 1023d into
DAC, no headroom
–0.5
0.25
0.5
1.8 V ≤ VDD ≤ 2.7 V, code 1023d into
DAC, no headroom
–1
0.5
1
%FSR
Full scale error temperature coefficient
%FSR/°
C
±0.0004
OUTPUT CHARACTERISTICS
VOUTX
Output voltage
CL
Capacitive load (2)
Load regulation
Short circuit current
(1)
(2)
0
5.5
RL = Infinite
1
RL = 5 kΩ
2
DAC at midscale, -10 mA ≤ IOUT ≤ 10
mA, VDD = 5.5 V
0.1
VDD = 1.8 V, (per channel) full-scale
output shorted to AGND or zero-scale
output shorted to VDD
10
VDD = 2.7 V, (per channel) full-scale
output shorted to AGND or zero-scale
output shorted to VDD
25
VDD = 5.5 V, (per channel) full-scale
output shorted to AGND or zero-scale
output shorted to VDD
50
Output voltage headroom
to VDD (DAC output unloaded)
Output voltage headroom (2)
to VDD (load current = 10 mA@VDD = 5.5
V, load current = 3 mA@VDD = 2.7 V,
load current = 1 mA@VDD = 1.8 V), DAC
code = full Scale
V
nF
mV/mA
mA
0.05
10
V
%FSR
End point fit between codes Code 4 to Code 1016 for 10 bit, Code 1 to Code 251 for 8 bit
Not production tested
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Electrical Characteristics (continued)
all minimum/maximum specifications at TA = –40°C to +125°C and all typical specification at TA = 25°C, 1.8 V ≤ VDD ≤ 5.5 V,
VREFIN = 2.5 V for VDD ≥ 2.7 V, VREFIN = 1.8 V for VDD ≤ 2.7 V, RL= 5 kΩ to AGND, CL = 200 pF to AGND, and digital inputs at
VDD or AGND (unless otherwise noted)
PARAMETER
ZO
DCPSRR
TEST CONDITIONS
DC output impedance
Power supply rejection ratio (DC)
MIN
TYP
DAC at midscale
0.25
DAC at code 4d
0.25
DAC at code 1016
0.26
DAC at midscale; VDD = 5 V ± 10%
0.25
MAX
UNIT
Ω
mV/V
DYNAMIC PERFORMANCE
tsett
Output voltage settling time
1/4 to 3/4 scale and 3/4 to 1/4 scale
settling to 10%FSR, RL = 5 kΩ, CL = 200
pF, VDD = 5.5 V
SR
Slew rate
Power on glitch magnitude
Vn
Output noise
0.1 Hz to 10 Hz, DAC at midscale, VDD =
5.5 V
Vn
Output noise
0.1 Hz to 100 kHz bandwidth, DAC at
midscale, VDD = 5.5 V
0.05
measured at 1 kHz, DAC at midscale,
VDD = 5.5 V
0.2
measured at 10 kHz, DAC at midscale,
VDD = 5.5 V
0.2
Power supply rejection ratio (AC)
200 mV 50/60 Hz sine wave
superimposed on power supply voltage,
DAC at midscale
–71
dB
Channel-to-channel AC crosstalk
Full-scale swing on adjacent channel
1.5
nV-s
Channel-to-channel DC crosstalk
Full-scale swing on all channel,
measured channel at zero or full scale
0.05
LSB
Code change glitch impulse
±1 LSB change around mid code
(including feedthrough)
10
nV-s
Code change glitch impulse magnitude
±1 LSB change around mid code
(including feedthrough)
25
mV
12.5
kΩ
50
pF
Vn
ACPSRR
Output noise density
10
µs
RL = 5 kΩ, CL = 200 pF, VDD = 5.5 V
0.6
V/µs
RL = 5 kΩ, CL = 200 pF
110
mV
40
µVpp
mVrms
µV/√Hz
VOLTAGE REFERENCE INPUT
Reference input impedance
All channel powered on
Reference input capacitance
DIGITAL INPUTS
Digital feedthrough
At SCLK = 1 MHz, DAC output static at
mid scale
20
nV-s
Pin capacitance
Per pin
10
pF
POWER REQUIREMENTS
IVDD
Current flowing into VDD
Normal mode, all DACs at full scale. SPI
static.
IVDD
Current flowing into VDD
All DACs power-down
6
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3
50
5
mA
µA
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SLASEQ4A – OCTOBER 2018 – REVISED DECEMBER 2018
7.6 Timing Requirements: I2CTM Standard Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤ VDD ≤ 5.5 V, 1.8 V ≤ VREFIN ≤ VDD, –40°C ≤ TA ≤ +125°C, Vpull up
= VDD for 1.8 V ≤ VDD ≤ 2.7 V, Vpull up = 2.7 V or VDD for 2.7 V ≤ VDD ≤ 5.5 V
MIN
fSCLK
SCLK frequency
tBUF
Bus free time between stop and start conditions
tHDSTA
Hold time after repeated start
tSUSTA
NOM
MAX
UNIT
0.1
MHz
4.7
µs
4
µs
Repeated start setup time
4.7
µs
tSUSTO
Stop condition setup time
4
µs
tHDDAT
Data hold time
tSUDAT
Data setup time
tLOW
0
ns
250
ns
SCL clock low period
4700
ns
tHIGH
SCL clock high period
4700
tF
Clock and data fall time
300
ns
tR
Clock and data rise time
1000
ns
ns
7.7 Timing Requirements: I2CTM Fast Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤ VDD ≤ 5.5 V, 1.8 V ≤ VREFIN ≤ VDD, –40°C ≤ TA ≤ +125°C, Vpull up
= VDD for 1.8 V ≤ VDD ≤ 2.7 V, Vpull up = 2.7 V or VDD for 2.7 V ≤ VDD ≤ 5.5 V
MIN
NOM
MAX
UNIT
0.4
MHz
fSCLK
SCLK frequency
tBUF
Bus free time between stop and start conditions
1.3
µs
tHDSTA
Hold time after repeated start
0.6
µs
tSUSTA
Repeated start setup time
0.6
µs
tSUSTO
Stop condition setup time
0.6
µs
tHDDAT
Data hold time
0
ns
tSUDAT
Data setup time
100
ns
tLOW
SCL clock low period
1300
ns
tHIGH
SCL clock high period
600
ns
tF
Clock and data fall time
300
ns
tR
Clock and data rise time
300
ns
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7.8 Timing Requirements: I2CTM Fast+ Mode
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤ VDD ≤ 5.5 V, 1.8 V ≤ VREFIN ≤ VDD, –40°C ≤ TA ≤ +125°C, Vpull up
= VDD for 1.8 V ≤ VDD ≤ 2.7 V, Vpull up = 2.7 V or VDD for 2.7 V ≤ VDD ≤ 5.5 V
MIN
NOM
MAX
UNIT
1
MHz
fSCLK
SCL frequency
tBUF
Bus free time between stop and start conditions
0.5
µs
tHDSTA
Hold time after repeated start
0.26
µs
tSUSTA
Repeated start setup time
0.26
µs
tSUSTO
Stop condition setup time
0.26
µs
tHDDAT
Data hold time
0
ns
tSUDAT
Data setup time
50
ns
tLOW
SCL clock low period
0.5
µs
tHIGH
SCL clock high period
0.26
tF
Clock and data fall time
120
ns
tR
Clock and data rise time
120
ns
µs
7.9 Timing Requirements: Logic
all input signals are timed from VIL to 70% of VDD, 1.8 V ≤ VDD ≤ 5.5 V, 1.8 V ≤ VREFIN ≤ VDD, –40°C ≤ TA ≤ +125°C, Vpull up
= VDD for 1.8 V ≤ VDD ≤ 2.7 V, Vpull up = 2.7 V or VDD for 2.7 V ≤ VDD ≤ 5.5 V
MIN
NOM
MAX
UNIT
tLDACAH
SCL fall edge to LDAC rise edge, 1.7 V ≤ VDD ≤ 2.7 V
20
tLDACAH
SCL fall edge to LDAC rise edge, 2.7 V < VDD ≤ 5.5 V
20
ns
tLDACAL
LDAC fall edge to SCL fall edge, 1.7 V ≤ VDD ≤ 5.5 V
10
clock cycle
tLDACSH
SCL fall edge to LDAC rise edge, 1.7 V ≤ VDD ≤ 2.7 V
80
ns
tLDACSH
SCL fall edge to LDAC rise edge, 2.7 V < VDD ≤ 5.5 V
50
ns
tLDACSL
SCL fall edge to LDAC fall edge, 1.7 V ≤ VDD ≤ 2.7 V
20
ns
tLDACSL
SCL fall edge to LDAC fall edge, 2.7 V < VDD ≤ 5.5 V
20
ns
tLDACW
LDAC low time, 1.7 V ≤ VDD < 2.7 V
30
ns
tLDACW
LDAC low time, 2.7 V ≤ VDD ≤ 5.5 V
60
ns
tCLRW
CLR low time, 1.7 V ≤ VDD < 2.7 V
30
ns
tCLRW
CLR low time, 2.7 V ≤ VDD ≤ 5.5 V
60
ns
8
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SLASEQ4A – OCTOBER 2018 – REVISED DECEMBER 2018
Low byte ACK cycle
tLOW
tR
tF
SCL
tHDSTA
tHIGH
tHDDAT
tSUSTA
tSUSTO
tSUDAT
tHDSTA
SDA
tBUF
P
S
S
P
tLDACAL
tLDACAH
LDAC1
tLDACSH
LDAC2
tLDACSL
tLDACW
tCLRW
CLR
Figure 1. Serial Interface Timing Diagram
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7.10 Typical Characteristics: 1.8 V
at TA = 25°C, VDD = 1.8 V, reference = 1.8 V, and DAC outputs unloaded (unless otherwise noted)
1
1
DAC A
DAC B
DAC C
DAC D
0.8
0.6
DAC E
DAC F
DAC G
DAC H
0.6
DNL (LSB)
INL (LSB)
0.2
0
-0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
0
128
256
384
512
Code
640
768
896
0
1024
128
256
384
D001
Figure 2. Integral Linearity Error vs Digital Input Code
512
Code
640
768
896
1024
D002
Figure 3. Differential Linearity Error vs Digital Input Code
1
1
0.6
DAC E
DAC F
DAC G
DAC H
INL Max
INL Min
0.8
INL Error Max-Min (LSB)
DAC A
DAC B
DAC C
DAC D
0.8
Total Unadjusted Error (%FSR)
0.2
-0.4
-1
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
128
256
384
512
Code
640
768
896
-1
-40
1024
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
D004
Figure 5. Integral Linearity Error vs Temperature
1
1
DNL Max
DNL Min
TUE Max
TUE Min
0.8
Total Unadjusted Error (%FSR)
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-40
-25
D003
Figure 4. Total Unadjusted Error vs Digital Input Code
DNL Error Max-Min (LSB)
DAC E
DAC F
DAC G
DAC H
0.4
0.4
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
-1
-40
-25
-10
D005
Figure 6. Differential Linearity Error vs Temperature
10
DAC A
DAC B
DAC C
DAC D
0.8
5
20 35 50 65
Temperature (oC)
80
95
110 125
D006
Figure 7. Total Unadjusted Error vs Temperature
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Typical Characteristics: 1.8 V (continued)
at TA = 25°C, VDD = 1.8 V, reference = 1.8 V, and DAC outputs unloaded (unless otherwise noted)
1
6
Zero Code Error (mV)
4
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
0.8
0.6
Offset Error (%FSR)
DAC A
DAC B
DAC C
DAC D
2
0
-2
DAC E
DAC F
DAC G
DAC H
0.4
0.2
0
-0.2
-0.4
-0.6
-4
-0.8
-6
-40
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
-1
-40
110 125
-25
Figure 8. Zero Code Error vs Temperature
20 35 50 65
Temperature (oC)
80
95
110 125
D008
1
0.6
DAC E
DAC F
DAC G
DAC H
0.4
0.2
0
-0.2
-0.4
0.6
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
-1
-40
-25
-10
D009
Figure 10. Gain Error vs Temperature
DAC E
DAC F
DAC G
DAC H
0.4
-0.6
-25
DAC A
DAC B
DAC C
DAC D
0.8
Full Scale Error (%FSR)
DAC A
DAC B
DAC C
DAC D
0.8
Gain Error (%FSR)
5
Figure 9. Offset Error vs Temperature
1
-1
-40
-10
D007
5
20 35 50 65
Temperature (oC)
80
95
110 125
D010
Figure 11. Full Scale Error vs Temperature
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7.11 Typical Characteristics: 5.5 V
at TA = 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
1
1
DAC A
DAC B
DAC C
DAC D
0.8
0.6
DAC E
DAC F
DAC G
DAC H
0.6
DNL (LSB)
INL (LSB)
0.2
0
-0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1
0
128
256
384
512
Code
640
768
896
0
1024
128
256
384
D011
Figure 12. Integral Linearity Error vs Digital Input Code
512
Code
640
768
896
1024
D012
Figure 13. Differential Linearity Error vs Digital Input Code
1
1
0.6
DAC E
DAC F
DAC G
DAC H
INL Max
INL Min
0.8
INL Error Max-Min (LSB)
DAC A
DAC B
DAC C
DAC D
0.8
Total Unadjusted Error (%FSR)
0.2
-0.4
-1
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
128
256
384
512
Code
640
768
896
-1
-40
1024
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
D014
Figure 15. Integral Linearity Error vs Temperature
1
Total Unadjusted Error Max-Min (%FSR)
1
DNL Max
DNL Min
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-40
-25
D013
Figure 14. Total Unadjusted Error vs Digital Input Code
DNL Error Max-Min (LSB)
DAC E
DAC F
DAC G
DAC H
0.4
0.4
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
TUE Max
TUE Min
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-40
-25
-10
D015
Figure 16. Differential Linearity Error vs Temperature
12
DAC A
DAC B
DAC C
DAC D
0.8
5
20 35 50 65
Temperature (oC)
80
95
110 125
D016
Figure 17. Total Unadjusted Error vs Temperature
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Typical Characteristics: 5.5 V (continued)
at TA = 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
0.5
12
Zero Code Error (mV)
10
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
0.4
0.3
Offset Error (%FSR)
DAC A
DAC B
DAC C
DAC D
8
6
4
DAC E
DAC F
DAC G
DAC H
0.2
0.1
0
-0.1
-0.2
-0.3
2
-0.4
0
-40
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
-0.5
-40
110 125
Figure 18. Zero Code Error vs Temperature
DAC E
DAC F
DAC G
DAC H
20 35 50 65
Temperature (oC)
80
95
110 125
D018
DAC A
DAC B
DAC C
DAC D
0.4
Full Scale Error (%FSR)
DAC A
DAC B
DAC C
DAC D
0.3
Gain Error (%FSR)
5
0.5
0.4
0.2
0.1
0
-0.1
-0.2
-0.3
0.3
DAC E
DAC F
DAC G
DAC H
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.4
-0.5
-40
-0.5
-40
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
-25
-10
5
D019
Figure 20. Gain Error vs Temperature
20 35 50 65
Temperature (oC)
80
95
110 125
D020
Figure 21. Full Scale Error vs Temperature
1
1
0.5
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
0.75
Full Scale Error (%FSR)
DAC A
DAC B
DAC C
DAC D
0.75
Gain Error (%FSR)
-10
Figure 19. Offset Error vs Temperature
0.5
0.25
0
-0.25
-0.5
-0.75
-1
1.8
-25
D017
0.5
DAC E
DAC F
DAC G
DAC H
0.25
0
-0.25
-0.5
-0.75
2.725
3.65
VREFIN (V)
4.575
5.5
-1
1.8
D033
Figure 22. Gain Error vs Reference Voltage
2.725
3.65
VREFIN (V)
4.575
5.5
D034
Figure 23. Full Scale Error vs Reference Voltage
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Typical Characteristics: 5.5 V (continued)
3
3
2.5
2.5
2
2
IDD (mA)
IDD (mA)
at TA = 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
1.5
1.5
1
1
0.5
0.5
0
0
0
128
256
384
512
Code
640
768
896
1024
0
at VDD = 1.8 V and reference = 1.8 V
256
384
512
Code
640
768
896
1024
D036
at VDD = 5.5 V and reference = 5.5 V
Figure 24. Supply Current vs Digital Input Code
Figure 25. Supply Current vs Digital Input Code
3
5
VDD = 5.5 V
VDD = 3.65 V
VDD = 1.8 V
4.5
4
2.5
3.5
2
3
IDD (mA)
IDD (mA)
128
D035
2.5
2
1.5
1
1.5
1
0.5
0.5
0
-40
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
0
1.8
110 125
2.725
D037
DAC code at mid-scale
3.65
VDD (V)
4.575
D038
DAC code at mid-scale and reference tied to VDD
Figure 26. Supply Current vs Temperature
Figure 27. Supply Current vs Supply Voltage
4
50
Code 0x3FF
Code 0
45
3
40
DAC Output (V)
IDD (PA)
35
30
25
20
15
10
VDD = 5.5 V
VDD = 3.65 V
VDD = 1.8 V
5
0
-40
5.5
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
2
1
0
-1
110 125
-2
-20
-16
-12
D039
-8
-4
0
4
Load Current (mA)
8
12
16
20
D041
at VDD = 1.8 V and reference = 1.8 V
Figure 28. Power Down Current vs Temperature
14
Figure 29. Source and Sink Capability
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Typical Characteristics: 5.5 V (continued)
at TA = 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
6
5
DAC Output (V)
VOUT (1 LSB/div)
LDAC (2.5 V/div)
Code 0x3FF
Code 0
4
3
2
1
0
-20
-16
-12
-8
-4
0
4
Load Current (mA)
8
12
16
Time (1 Ps/div)
20
D043
D042
DAC code transition from mid-scale – 1 to mid-scale, DAC output
loaded with 5 kΩ//200 pF
at VDD = 5.5 V and reference = 5.5 V
Figure 30. Source and Sink Capability
Figure 31. Glitch Impulse, Rising Edge, 1 LSB Step
VOUT (1 LSB/div)
LDAC (2.5 V/div)
Small Signal VOUT (1 LSB/div)
Large Signal VOUT (2.5 V/div)
LDAC (2.5 V/div)
Time (1 Ps/div)
Time (5 Ps/div)
D044
DAC code transition from mid-scale to mid-scale – 1 LSB, DAC
output loaded with 5 kΩ//200 pF
D045
DAC code transition from 102d to 922d, typical channel shown,
DAC output loaded with 5 kΩ//200 pF
Figure 32. Glitch Impulse, Falling Edge, 1 LSB Step
Figure 33. Full-Scale Settling Time, Rising Edge
18
Small Signal VOUT (1 LSB/div)
Large Signal VOUT (2.5 V/div)
LDAC (2.5 V/div)
DAC A
DAC B
DAC C
DAC D
16
DAC Output (mV)
14
12
DAC E
DAC F
DAC G
DAC H
10
8
6
4
2
0
-2
-4
Time (5 Ps/div)
Time (50 Ps/div)
D046
DAC code transition from 922d to 102d, typical channel shown,
DAC output loaded with 5 kΩ//200 pF
D047
DAC output loaded with 5 kΩ//200 pF
Figure 34. Full-Scale Settling Time, Falling Edge
Figure 35. Power-on Glitch
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Typical Characteristics: 5.5 V (continued)
at TA = 25°C, VDD = 5.5 V, reference = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
20
DAC A
DAC B
DAC C
DAC D
15
DAC Output (mV)
10
VOUT (2 mV/div)
SCL (2.5 V/div)
DAC E
DAC F
DAC G
DAC H
5
0
-5
-10
-15
-20
Time (1 Ps/div)
Time (1 ms/div)
D049
D048
DAC code at mid-scale and reference tied to VDD and output
loaded with 5 kΩ//200 pF
DAC output loaded with 5 kΩ//200 pF
Figure 36. Power-off Glitch
Figure 37. Clock Feedthrough with SCL = 1 MHz
10
0
-10
VNOISE (5 PV/div)
AC PSRR (dB)
-20
-30
-40
-50
-60
-70
-80
-90
-100
10
100
1000
10000
Frequency (Hz)
100000
1000000
D052
D050
DAC code at full-scale and output loaded with 5 kΩ//200 pF, VDD =
5.25 V + 0.2 VPP and VREFIN = 4.5 V
DAC code at mid-scale
Figure 39. DAC Output Noise 0.1 Hz to 10 Hz
Figure 38. DAC Output AC PSRR vs Frequency
1000
Code 0x20
Code 0x800
Code 0xFDC
Noise (nV/—Hz)
800
600
400
200
0
10 2030 50 100 200
5001000
Frequency (Hz)
10000
100000
D051
Figure 40. DAC Output Noise Spectral Density
16
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7.12 Typical Characteristics
at TA = 25°C, and DAC outputs unloaded (unless otherwise noted)
1
1
INL Max
INL Min
0.5
0.25
0
-0.25
-0.5
2.725
3.65
VDD (V)
4.575
0
-0.25
-0.5
4.575
5.5
D022
Figure 42. Differential Linearity Error vs Supply Voltage
TUE Max
TUE Min
DAC A
DAC B
DAC C
DAC D
10
Zero Code Error (mV)
0.5
0.25
0
-0.25
-0.5
DAC E
DAC F
DAC G
DAC H
8
6
4
2
-0.75
2.725
3.65
VDD (V)
4.575
0
1.8
5.5
2.725
D023
Figure 43. Total Unadjusted Error vs Supply Voltage
3.65
VDD (V)
4.575
5.5
D024
Figure 44. Zero Code Error vs Supply Voltage
1
1
DAC A
DAC B
DAC C
DAC D
0.75
0.5
DAC E
DAC F
DAC G
DAC H
0.5
0.25
0
-0.25
0
-0.25
-0.5
-0.75
-0.75
3.65
VDD (V)
4.575
5.5
-1
1.8
2.725
D025
Figure 45. Offset Error vs Supply Voltage
DAC E
DAC F
DAC G
DAC H
0.25
-0.5
2.725
DAC A
DAC B
DAC C
DAC D
0.75
Gain Error (%FSR)
Offset Error (%FSR)
3.65
VDD (V)
12
0.75
-1
1.8
2.725
D021
Figure 41. Integral Linearity Error vs Supply Voltage
Total Unadjusted Error Max-Min (%FSR)
0.25
-1
1.8
5.5
1
-1
1.8
0.5
-0.75
-0.75
-1
1.8
DNL Max
DNL Min
0.75
DNL Error Max-Min (LSB)
INL Error Max-Min (LSB)
0.75
3.65
VDD (V)
4.575
5.5
D026
Figure 46. Gain Error vs Supply Voltage
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7.13 Typical Characteristics
at TA = 25°C, VDD = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
1
1
Full Scale Error (%FSR)
0.75
0.5
DAC E
DAC F
DAC G
DAC H
0.25
0
-0.25
-0.5
-1
1.8
2.725
3.65
VDD (V)
4.575
0
-0.25
-0.5
2.725
D027
Figure 47. Full Scale Error vs Supply Voltage
3.65
VREFIN (V)
4.575
5.5
D028
Figure 48. Integral Linearity Error vs Reference Voltage
Total Unadjusted Error Max-Min (%FSR)
1
DNL Max
DNL Min
0.75
DNL Error Max-Min (LSB)
0.25
-1
1.8
5.5
1
0.5
0.25
0
-0.25
-0.5
-0.75
-1
1.8
2.725
3.65
VREFIN (V)
4.575
TUE Max
TUE Min
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
1.8
5.5
2.725
D029
Figure 49. Differential Linearity Error vs Reference Voltage
3.65
VREFIN (V)
4.575
5.5
D030
Figure 50. Total Unadjusted Error vs Reference Voltage
12
1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
DAC A
DAC B
DAC C
DAC D
0.75
Offset Error (%FSR)
10
Zero Code Error (mV)
0.5
-0.75
-0.75
8
6
4
2
0.5
DAC E
DAC F
DAC G
DAC H
0.25
0
-0.25
-0.5
-0.75
0
1.8
2.725
3.65
VREFIN (V)
4.575
5.5
-1
1.8
2.725
D031
Figure 51. Zero Code Error vs Reference Voltage
18
INL Max
INL Min
0.75
INL Error Max-Min (LSB)
DAC A
DAC B
DAC C
DAC D
3.65
VREFIN (V)
4.575
5.5
D032
Figure 52. Offset Error vs Reference Voltage
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8 Detailed Description
8.1 Overview
The DAC53608 and DAC43608 are a pin-compatible family of eight-channel, buffered voltage-output digital-toanalog converters (DACs) in 10- and 8-bit resolution. With an external reference ranging from 1.8 V to 5.5 V, full
scale output voltage of 1.8 V to 5.5 V can be achieved. These devices are guaranteed monotonic across the
power supply range.
Communication to the devices is done through I2CTM compatible interface. The I2CTM standard (100 kbps), fast
(400 kbps), and fast+ mode (1Mbps) are supported for these devices. These devices include a load DAC (LDAC)
pin for simultaneous DAC update.
The DACx3608 devices are characterized for operation over the temperature range of -40°C to +125°C and are
available in tiny QFN packages.
8.2 Functional Block Diagram
VDD
VREFIN
DAC
Active
Registers
DAC
DACx3608
SCL
A0
LDAC
DAC
Buffer
Registers
I2CTM Interface
SDA
BUF
VOUTA
Channel A
CLR
VOUTH
Channel H
Power On Reset
Resistive Network
Power Down Logic
AGND
Figure 53. DACx3608 DAC Block Diagram
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8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC) Architecture
Each output channel in the DACx3608 family of devices consists of string architecture with an output buffer
amplifier. Figure 54 shows a block diagram of the DAC architecture.
Serial interface
DAC data register
READ
DAC
buffer
register
WRITE
DAC
active
register
VREFIN
VDD
String
VOUT
DAC output
(asynchronous mode)
LDAC Trigger
(synchronous mode)
AGND
Figure 54. DACx3608 DAC Architecture
8.3.1.1 DAC Transfer Function
The device writes the input data to the individual DAC Data registers in straight binary format. After a power-on
or a reset event, the device sets all DAC registers to zero-code. Equation 1 shows DAC transfer function.
VOUT X
DACn _ DATA
2N
u VREFIN
where:
•
•
•
•
N = resolution in bits
– Either 10 (DAC53608) or 8 (DAC43608)
DACn_DATA is the decimal equivalent of the binary code that is loaded to the DAC register
DACn_DATA ranges from 0 to 2N – 1
VREFIN is the DAC reference voltage
(1)
8.3.1.2 DAC Register Update and LDAC Functionality
The device stores the data written to the DAC Data registers in the DAC buffer registers. Transfer of data from
the DAC buffer registers to the DAC active registers can be set to happen immediately (asynchronous mode) or
initiated by an LDAC trigger (synchronous mode). Once the DAC active registers are updated, the DAC outputs
change to their new values.
The update mode for each DAC channel is determined by the status of LDAC pin.
In asynchronous mode (LDAC = 0 before the DAC write command), a write to the DAC data register results in an
immediate update of the DAC active register and DAC output at the end of I2CTM frame.
In synchronous mode (LDAC = 1 before the DAC write command), writing to the DAC data register does not
automatically update the DAC output. Instead the update occurs only after an LDAC is pulled to 0. The
synchronous update mode enables simultaneous update of all DAC outputs.
8.3.1.3 CLR Functionality
The CLR pin is an asynchronous input pin to the DAC. When this pin is pulled low (logic 0), the DAC buffers and
the DAC active registers to zero code.
20
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Feature Description (continued)
8.3.1.4 Output Amplifier
The output buffer amplifier generates rail-to-rail voltages on the output, giving a maximum output range of 0 V to
VDD. Equation 1 shows that the full-scale output range of the DAC output is determined by the voltage on the
VREFIN pin
8.3.2 Reference
The DACx3608 requires an external reference to operate. However, the reference pin VREFIN and the supply pin
VDD can be tied together. The reference input pin voltage ranges from 1.8 V to VDD. The typical input impedance
of this pin when all the channels are powered on is 12.5 kΩ.
8.3.3 Power-on-Reset (POR)
The DACx3608 family of devices includes a power-on reset (POR) function that controls the output voltage at
power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers to
initialize to the default values, and communication with the device is valid only after a 5-ms after VDD reaches
DAC operating range. The default value for the DAC data registers is zero-code . The DAC output remains at the
power-up voltage until a valid command is written to a channel.
When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific
VDD levels, as indicated in Figure 55, in order to make sure that the internal capacitors discharge and reset the
device on power up. In order to make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms.
When VDD drops to less than 1.7 V but remains greater than 0.7 V (shown as the undefined region), the device
may or may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR.
When VDD remains greater than 1.7 V, a POR does not occur.
VDD (V)
5.50
No power-on reset
Specified supply
voltage range
1.80
1.70
Undefined
0.70
Power-on reset
0.00
Figure 55. Threshold Levels for VDD POR Circuit
8.3.4 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to the SW-RST bit in the
TRIGGER register (address 2h).
8.4 Device Functional Modes
The DACx3608 has two modes of operation: normal and power-down.
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Device Functional Modes (continued)
8.4.1 Power-Down Mode
The DACx3608 DAC output amplifiers can be independently or globally powered down (10K to AGND) through the
DEVICE_CONFIG register. In this state, the device consumes 50 µA (VDD = 1.8 V). At power-up all output
channels buffer amplifiers start in power down to 10K mode until a power up command is issue by writing 0 to
the per channel power down registers.
8.5 Programming
The DACx3608 devices have a 2-wire serial interface: SCL, SDA, and one address pin, A0, as shown in Pin
Configurations and Functions. The I2CTM bus consists of a data line (SDA) and a clock line (SCL) with pull-up
structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2CTM compatible devices
connects to the I2CTM bus through open drain I/O pins, SDA and SCL.
The I2CTM specification states that the device that controls communication is called a master, and the devices
that are controlled by the master are called slaves. The master device generates the SCL signal. The master
device also generates special timing conditions (start condition, repeated start condition, and stop condition) on
the bus to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master
device on an I2CTM bus is typically a microcontroller or a digital signal processor (DSP). The DACx3608 family
operates as a slave device on the I2CTM bus. A slave device acknowledges master's commands and upon
master's control, receives or transmits data.
Typically, the DACx3608 family operates as a slave receiver. A master device writes to the DACx3608, a slave
receiver. However, if a master device requires the DACx3608 internal register data, the DACx3608 family
operates as a slave transmitter. In this case, the master device reads from the DACx3608 According to I2CTM
terminology, read and write refer to the master device.
The DACx3608 family is a slave and supports the following data transfer modes:
• Standard mode (100 kbps)
• Fast mode (400 kbps)
• Fast+ mode (1.0 Mbps)
The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/Smode in this document. The fast+ mode protocol is supported in terms of data transfer speed, but not output
current. The low-level output current would be 3 mA similar to the case of standard and fast modes. The
DACx3608 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The device supports
the general call reset function. Sending the following sequence initiates a software reset within the device;
Start/Repeated Start, 0x00, 0x06, Stop. The reset is asserted within the device on the rise edge of the ACK bit,
following the second byte.
Other than specific timing signals, the I2CTM interface works with serial bytes. At the end of each byte, a ninth
clock cycle generates and detects an acknowledge signal. Acknowledge is when the SDA line is pulled low
during the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the
high period of the ninth clock cycle as shown in Figure 56.
22
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Programming (continued)
Data output
by Transmitter
Not acknowledge
Data output
by Receiver
Acknowledge
1
SCL from
Master
2
8
9
S
Clock pulse for
acknowledgement
Start
condition
Figure 56. Acknowledge and Not Acknowledge on the I2CTM Bus
8.5.1 F/S Mode Protocol
1. The master initiates data transfer by generating a start condition. The start condition is when a high to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 57. All I2CTM compatible devices
recognize a start condition.
SDA
SCL
S
Start
condition
P
Stop
condition
Figure 57. Start and Stop Conditions
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Programming (continued)
SDA
SCL
Data line stable
Data valid
Change of data
allowed
Figure 58. Bit Transfer on the I2CTM Bus
2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
(R/W) on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse, as shown in Figure 58. All
devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the
slave device with a matching address generates an acknowledge by pulling the SDA line low during the
entire high period of the 9th SCL cycle, as shown in Figure 56 by pulling the SDA line low during the entire
high period of the 9th SCL cycle. Upon detecting this acknowledge, the master knows the communication link
with a slave has been established.
3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In
either case, the receiver must acknowledge the data sent by the transmitter. So the acknowledge signal can
be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data
sequences consists of 8-data bits and 1 acknowledge-bit, and can continue as long as necessary.
4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 57). This action releases the bus and stops the communication
link with the addressed slave. All I2CTM-compatible devices recognize the stop condition. Upon receipt of a
stop condition, the bus is released, and all slave devices then wait for a start condition followed by a
matching address.
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Programming (continued)
8.5.2 DACx3608 I2CTM Update Sequence
For a single update, the DACx3608 requires a start condition, a valid I2CTM address byte, a command byte, and
two data bytes ( the most significant data byte (MSDB) and least significant data byte (LSDB)), as listed in
Table 1.
Table 1. Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
Address (A) byte
Command byte
MSDB
LSDB
DB [32:24]
DB [23:16]
DB [15:8]
DB [7:0]
ACK
After each byte is received, the DACx3608 family acknowledges the byte by pulling the SDA line low during the
high period of a single clock pulse, as shown in Figure 59. These four bytes and acknowledge cycles make up
the 36 clock cycles required for a single update to occur. A valid I2CTM address byte selects the DACx3608
devices.
Recognize
START or
REPEATED
START
condition
Recognize
STOP or
REPEATED
START
condition
Generate ACKNOWLEDGE
signal
P
SDA
MSB
Address
SCL
Sr
Acknowledgement
signal from Slave
1
R/W
7
8
9
1
2-8
9
Sr
or
P
S
or
Sr
ACK
START or
REPEATED
START
condition
Clock line held low while
interrupts are serviced
ACK
REPEATED
START or
STOP
condition
Figure 59. I2CTM Bus Protocol
The command byte sets the operational mode of the selected DACx3608 device. When the operational mode is
selected by this byte, the DACx3608 series must receive two data bytes, the most significant data byte (MSDB)
and least significant data byte (LSDB), for a data update to occur. The DACx3608 devices perform an update on
the falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 22.22 kSPS. Using the
fast+ mode (clock = 1 MHz), the maximum DAC update rate is limited to 55.55 kSPS. When a stop condition is
received, the DACx3608 family releases the I2CTM bus and awaits a new start condition.
8.5.3 DACx3608 Address Byte
The address byte, as shown in Table 2, is the first byte received following the START condition from the master
device. The first four bits (MSBs) of the address are factory preset to 1001. The next 3 bits of the address are
controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is sampled
during the first byte of each data frame to determine the address. The device latches the value of the address pin
and consequently will respond to that particular address according to Table 3.
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The DACx3608 family supports broadcast addressing. Broadcast addressing can be used for synchronously
updating or powering down multiple DACx3608 devices. The DACx3608 family is designed to work with other
members of the family to support multichip synchronous update. Using the broadcast address, the DACx3608
devices respond regardless of the states of the address pins. Broadcast is supported only in write mode.
Table 2. DACx3608 Address Byte
COMMENT
MSB
AD6
AD5
AD4
AD3
General address
1
0
0
1
Broadcast address
1
0
0
0
LSB
AD2
AD1
AD0
See Table 3 (slave address column)
1
1
1
R/W
0 or 1
0
Table 3. Address Format
26
SLAVE ADDRESS
A0 PIN
1001 000
AGND
1001 001
VDD
1001 010
SDA
1001 011
SCL
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8.5.4 DACx3608 Command Byte
The DACx3608 command byte (shown in Table 4) controls which command is executed and which register is
being accessed when writing to or reading from the DACx3608 series.
Table 4. DACx3608 Command Byte
B23
B22
B21
B20
B19
B18
B17
B16
COMMENT
0
0
0
0
0
0
0
1
DEVICE_CONFIG
0
0
0
0
0
0
1
0
STATUS/TRIGGER
0
0
0
0
0
0
1
1
BRDCAST
0
0
0
0
1
0
0
0
DACA_DATA
0
0
0
0
1
0
0
1
DACB_DATA
0
0
0
0
1
0
1
0
DACC_DATA
0
0
0
0
1
0
1
1
DACD_DATA
0
0
0
0
1
1
0
0
DACE_DATA
0
0
0
0
1
1
0
1
DACF_DATA
0
0
0
0
1
1
1
0
DACG_DATA
0
0
0
0
1
1
1
1
DACH_DATA
8.5.5 DACx3608 Data Byte (MSDB and LSDB)
The MSDB and LSDB contain the data that are passed to the register(s) specified by the command byte as
shown in Table 5. The DACx3608 family updates at the falling edge of the acknowledge signal that follows the
LSDB[0] bit.
Table 5. DACx3608 Data Byte
COMMAND BITS
DATA BITS
MSDB
B19 - B16
B15 - B12
B11
0
LSDB
B10
0
B9
B8
0
PD
NAll
B7
B6
B5
B3
B2
B1
x
STATUS/TRIGGER
x
BRDCAST
x
BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0] – MSB left aligned
x
x
DACA_DATA
x
DACA_DATA[9:0] / DACA_DATA[7:0] – MSB left aligned
x
x
x
PDNE PDND PDNC PDNB
B0
DEVICE_CONFIG
DEVICE_ID
PDNH PDNG PDNF
B4
x
PDNA
SW_RST
DACB_DATA
x
DACB_DATA[9:0] / DACB_DATA[7:0] – MSB left aligned
x
x
DACC_DATA
x
DACC_DATA[9:0] / DACC_DATA[7:0] – MSB left aligned
x
x
DACD_DATA
x
DACD_DATA[9:0] / DACD_DATA[7:0] – MSB left aligned
x
x
DACE_DATA
x
DACE_DATA[9:0] / DACE_DATA[7:0] – MSB left aligned
x
x
DACF_DATA
x
DACF_DATA[9:0] / DACF_DATA[7:0] – MSB left aligned
x
x
DACG_DATA
x
DACG_DATA[9:0] / DACG_DATA[7:0] – MSB left aligned
x
x
DACH_DATA
x
DACH_DATA[9:0] / DACAH_DATA[7:0] – MSB left aligned
x
x
8.5.6 DACx3608 I2CTM Read Sequence
To read any register the following command sequence must be used:
1. Send a start or repeated start command with a slave address and the R/W bit set to 0 for writing. The device
acknowledges this event.
2. Send a command byte for the register to be read. The device acknowledges this event again.
3. Send a repeated start with the slave address and the R/W bit set to '1' for reading. The device acknowledges
this event.
4. The device writes the MSDB byte of the addressed register. The master must acknowledge this byte.
5. Finally, the device writes out the LSDB of the register.
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An alternative reading method allows for reading back the value of the last register written. The sequence is a
start or repeated start with the slave address and the R/W bit set to 1, and the two bytes of the last register are
read out. All the registers in DACx3608 family can be read out with the exception of SW-RST register. Table 5
shows the read command set.
Note that it is not possible to use the broadcast address for reading.
Table 6. Read Sequence
S MSB …
R/W
(0)
ACK
MSB … LSB
ADDRESS
BYTE
From Master
ACK
COMMAND
BYTE
Slave
Slave
ACK
MSB … LSB
ADDRESS
BYTE
Sr
From Master
R/W
(1)
Sr MSB …
ACK
MSB … LSB
MSDB
From Master
Slave
ACK
LSDB
From Slave
Master
From Slave
Master
8.6 Register Map
Table 7. Register Address
B23
B22
B21
B20
B19
B18
B17
B16
COMMENT
0
0
0
0
0
0
0
1
DEVICE_CONFIG
0
0
0
0
0
0
1
0
STATUS/TRIGGER
0
0
0
0
0
0
1
1
BRDCAST
0
0
0
0
1
0
0
0
DACA_DATA
0
0
0
0
1
0
0
1
DACB_DATA
0
0
0
0
1
0
1
0
DACC_DATA
0
0
0
0
1
0
1
1
DACD_DATA
0
0
0
0
1
1
0
0
DACE_DATA
0
0
0
0
1
1
0
1
DACF_DATA
0
0
0
0
1
1
1
0
DACG_DATA
0
0
0
0
1
1
1
1
DACH_DATA
Table 8. Register Map
COMMAND BITS
DATA BITS
MSDB
LSDB
B19 - B16
B15 - B12
B11
B10
B9
DEVICE_CONFIG
x
0
0
0
STATUS/TRIGGER
x
B8
B7
B6
B5
PD
N- PDNH PDNG PDNF
All
DEVICE_ID
x
B4
PDNE
B3
B2
B1
PDND PDNC PDNB
x
B0
PDNA
SW_RST
BRDCAST
x
BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0] – MSB left aligned
x
x
DACA_DATA
x
DACA_DATA[9:0] / DACA_DATA[7:0] – MSB left aligned
x
x
DACB_DATA
x
DACB_DATA[9:0] / DACB_DATA[7:0] – MSB left aligned
x
x
DACC_DATA
x
DACC_DATA[9:0] / DACC_DATA[7:0] – MSB left aligned
x
x
DACD_DATA
x
DACD_DATA[9:0] / DACD_DATA[7:0] – MSB left aligned
x
x
DACE_DATA
x
DACE_DATA[9:0] / DACE_DATA[7:0] – MSB left aligned
x
x
DACF_DATA
x
DACF_DATA[9:0] / DACF_DATA[7:0] – MSB left aligned
x
x
DACG_DATA
x
DACG_DATA[9:0] / DACG_DATA[7:0] – MSB left aligned
x
x
DACH_DATA
x
DACH_DATA[9:0] / DACAH_DATA[7:0] – MSB left aligned
x
x
Table 9. DACx3608 Register Names
28
OFFSET
ACRONYM
REGISTER NAME
SECTION
01h
DEVICE_CONFIG
Device Configuration Register
DEVICE_CONFIG Register (offset =
01h) [reset = 00FFh]
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Table 9. DACx3608 Register Names (continued)
OFFSET
ACRONYM
REGISTER NAME
SECTION
02h
STATUS/TRIGGER
Status and Trigger Register
STATUS/TRIGGER Register (offset =
02h) [reset = 0300h for DAC53608,
reset = 0500h for DAC43608]
03h
BRDCAST
Broadcast Data Register
BRDCAST Register (offset = 03h)
[reset = 0000h]
08h - 0Fh
DACn_DATA
DACn Data Register
DACn_DATA Register (offset = 08h to
0Fh) [reset = 0000h]
8.6.1 DEVICE_CONFIG Register (offset = 01h) [reset = 00FFh]
Figure 60. DEVICE_CONFIG Register
15
14
13
Don't Care
12
11
0
10
0
9
0
8
PDNAlll
7
PDNH
6
PDNG
5
PDNF
W
4
PDNE
3
PDND
2
PDNC
1
PDNB
0
PDNA
R/W
Table 10. DEVICE_CONFIG Register Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-12
Don't Care
W
0h
Don't Care
11-9
RESERVED
W
00
Reserved
PDN-All
R/W
0
Global power down bit, When set to '1', all channels and all bias
blocks are powered down
PDNn
R/W
FFh
DACn in power down mode (Output buffers power down 10K to
AGND) when this bit is set to '1' (default). At power-up all output
channels buffer amplifiers start in power down to 10K mode until
a power up command is issue by writing 0 to these registers.
8
7-0
8.6.2 STATUS/TRIGGER Register (offset = 02h) [reset = 0300h for DAC53608, reset = 0500h for
DAC43608]
Figure 61. STATUS/TRIGGER Register
15
14
13
Don't Care
12
11
10
9
8
DEVICE_ID
W
7
6
R
5
Don't
Care
W
4
Don't
Care
W
3
2
1
SW_RST
0
W
Table 11. STATUS/TRIGGER Register Field Descriptions
FIELD
TYPE
RESET
DESCRIPTION
15-12
BIT
Don't Care
W
0h
Don't Care
11-6
DEVICE_ID
R
DAC536
08:
001100
DAC436
08:
010100
Device Identification number
DAC53608: 001100
DAC43608: 010100
5-4
Don't Care
W
0h
Don't Care
3-0
SW_RST
W
0h
Device resets to default value when this register is set to 1010
8.6.3 BRDCAST Register (offset = 03h) [reset = 0000h]
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Figure 62. BRDCAST Register
15
14
13
Don't Care
12
11
10
9
8
7
6
5
4
3
BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0] – MSB Left aligned
W
2
W
1
Don't
Care
W
0
Don't
Care
W
Table 12. BRDCAST Register Field Descriptions
FIELD
TYPE
RESET
DESCRIPTION
15-12
BIT
Don't Care
W
0h
Don't Care
11-2
BRDCAST_DATA[9:0] /
BRDCAST_DATA[7:0]
W
000h
Writing to the BRDCAST register forces the DAC channel to
update its active register data to the BRDCAST_DATA one.
Data is MSB aligned in straight binary format and follows the
format below:
DAC53608: { DATA[9:0] }
DAC43608: { DATA[7:0], x, x }
x – Don’t care bits
1-0
Don't Care
W
00
Don't Care
8.6.4 DACn_DATA Register (offset = 08h to 0Fh) [reset = 0000h]
Figure 63. DACn_DATA Register
15
14
13
Don't Care
12
11
10
9
8
7
6
5
4
3
BRDCAST_DATA[9:0] / BRDCAST_DATA[7:0] – MSB Left aligned
W
W
2
1
Don't
Care
W
0
Don't
Care
W
Table 13. DACn_DATA Register Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
15-12
Don't Care
W
0h
Don't Care
11-2
DACn_DATA[9:0] /
DACn_DATA[7:0]
W
000h
Writing to the DACn_DATA register forces the respective DAC
channel to update its active register data to the DACn_DATA.
Data is MSB aligned in straight binary format and follows the
format below:
DAC53608: { DATA[9:0] }
DAC43608: { DATA[7:0], x, x }
x – Don’t care bits
1-0
30
Don't Care
W
00
Don't Care
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The DACx3608 is a buffered output, 8-channel, low power DAC available in a tiny 3X3 package. The multichannel, low power, and small package makes this DAC suitable for general purpose applications in wide range
of end equipments. Some of the most common applications for this devices are LED biasing in multi-function
printers, power supply supervision with programmable comparators, offset and gain trimming in precision circuits,
and power supply margining.
9.2 Typical Applications
9.2.1 Programmable LED Biasing
End equipments such as multi-function printers, projectors and electronic point-of-sale (EPOS) require a steady
luminous intensity from the LED. Figure 64 shows a simplified circuit diagram for biasing an LED using
DACx3608.
VCC
LED
ILED = ISET
DAC536 08
VDAC
+
Q1
VDAC
RSET
ISET
Figure 64. LED Biasing
9.2.1.1 Design Requirements
•
•
•
Programmable Constant Current through an LED tied to power supply on one end
DAC Output Range: 0 – 5 V
LED Current Range: 0 – 20 mA
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
The DAC is used to set the source current of a MOSFET using a unity-gain buffer as shown in Figure 64. The
LED is connected between the power supply and the drain of the MOSFET. This configuration allows the DAC to
control or set the amount of current through the LED. The buffer following the DAC controls the gate-source
voltage of the MOSFET inside the feedback loop thus compensating this drop and corresponding drift due to
temperature, current, and ageing of the MOSFET. The current set by the DAC that flows through the LED can be
calculated with Equation 2. in order to generate 0 – 20mA from a 0 – 5 V DAC output range, a 250-Ω RSETis
required.
ISET
VDAC
R SET
(2)
The pseudocode for getting started with the LED biasing application is given below.
//SYNTAX: WRITE ,
//Power-up the device and channels
WRITE DEVICE_CONFIG(0x01), 0x0000
//Program mid code (or the desired voltage) on all channels
WRITE DACA_DATA(0x08), 0x07FC //10-bit MSB aligned
WRITE DACB_DATA(0x09), 0x07FC //10-bit MSB aligned
WRITE DACC_DATA(0x0A), 0x07FC //10-bit MSB aligned
WRITE DACD_DATA(0x0B), 0x07FC //10-bit MSB aligned
WRITE DACE_DATA(0x0C), 0x07FC //10-bit MSB aligned
WRITE DACF_DATA(0x0D), 0x07FC //10-bit MSB aligned
WRITE DACG_DATA(0x0E), 0x07FC //10-bit MSB aligned
WRITE DACH_DATA(0x0F), 0x07FC //10-bit MSB aligned
9.2.1.3 Application Curve
Figure 65. DC Transfer Characteristics of LED Biasing Circuit
32
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Typical Applications (continued)
9.2.2 Programmable Window Comparator
End equipments that use a centralized power supply such as network servers, optical modules, and others
require the monitoring of power buses in order to protect the components. This monitoring or supervision is
accomplished using a window comparator. A window comparator monitors a signal input for upper and lower
threshold violations. A trigger signal is generated when the threshold violations occur. Multi-channel monitoring is
required in order to supervise all power supplies available in a module. DACx3608 provides a easy to use, lowfootprint method to address this requirement.
VIO
RPULL-UP
VDAC
THLD-HI
DACx3608
+
VOUT
R1
RA
VIN
RB
R2
+
THLD-LO
Figure 66. Programmable Window Comparator
9.2.2.1 Design Requirements
•
•
•
•
Voltage to be Monitored: 5 V
High Threshold: 5 V + 10%
Low Threshold: 5 V – 10%
Trigger Output: 3.3-V Open-Drain Single Output
9.2.2.2 Detailed Design Procedure
Figure 66 provides an example in which single DAC channel is used to compare both high and low thresholds. A
dual comparator is used per DAC channel as shown. A voltage divider formed by resistors RA and RB are used in
order to bring the signal level within the DAC range. Another pair of resistors R1 and R2 are used for setting the
low threshold as a factor of the high threshold. This configuration allows the use of a single DAC channel for
monitoring both high and low threshold levels. The comparators should be open-drain in order to provide the
following advantages.
• Generate a logic output level suitable for the monitoring processor
• Allow shorting of the two outputs in order to generate a single trigger
In the circuit depicted in Figure 66 the output of the circuit remains HIGH as long as the signal input remains
within the high and low threshold levels. Upon violation of any one threshold, the output goes LOW. Equation 3
provides the derivation of the low threshold voltage from the high threshold set by the DAC.
§ R ·
¸
© R +R ¹
VTHLD-LO =VDAC × ¨
2
1
(3)
2
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Typical Applications (continued)
In order to monitor a power supply of 5 V within ±10%, it is recommended to place the nominal value at the DAC
mid code. The output range of DACx3608 to be 0 – 5 V, thus the mid code voltage output is 2.5 V. Hence, RA
and RB can be chosen in such a way that the voltage to be compared is 2.5 V. For this example, RA is equal to
RB and we can use 10-kΩ resistors for both of them. One channel of the DACx3608 must be programmed to
VTHLD-HI, for example 2.5 V + 5% = 2.625 V. This corresponds to a 10-bit DAC code of (210÷5 V) × 2.625 V =
537.6 (0x21 Ah). In order to generate VTHLD-LO(for example, 2.5 V – 5% = 2.405 V) from 2.625 V, the values of R1
and R2 can be calculated as 7.5 kΩ and 82 kΩ, respectively using Equation 3. The pseudocode for getting
started with the programmable window comparator application with the desired DAC value is given below.
//SYNTAX: WRITE ,
//Power-up the device and channels
WRITE DEVICE_CONFIG(0x01), 0x0000
//Program 2.625V on channel A
WRITE DACA_DATA(0x08), 0x0868 //10-bit MSB aligned
9.2.2.3 Application Curve
Figure 67. Programmable Comparator Output Waveform
10 Power Supply Recommendations
The DACx3608 family of devices does not require specific supply sequencing. It requires a single power supply,
VDD. A 0.1-µF decoupling capacitor is recommended for the VDD pin.
34
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11 Layout
11.1 Layout Guidelines
The DACx3608 pinout separates the analog, digital, and power pins for an optimized layout. For signal integrity,
it is recommended that digital and analog traces be separated and decoupling capacitors places close with the
device pins.
11.2 Layout Example
Figure 68 shows an example layout drawing with decoupling capacitors and pull-up resistors.
VREF
VDD
Analog
Outputs
Analog
Outputs
Digital IO
Figure 68. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following: DAC53608EVM User's Guide (SLAU790)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 14. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DAC53608
Click here
Click here
Click here
Click here
Click here
DAC43608
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
36
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC43608RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D43608
DAC43608RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D43608
DAC53608RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D53608
DAC53608RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D53608
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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