DAC5571IDBVR

DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 +2.7 V to +5.5 V, I2C INTERFACE, VOLTAGE OUTPUT, 8-BIT DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION • • • • • • • The DAC5571 is a low-power, single-channel, 8-bit buffered voltage output DAC. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The DAC5571 utilizes an I2C-compatible, two-wire serial interface that operates at clock rates up to 3.4 Mbps with address support of up to two DAC5571s on the same data bus. • • • • Micropower Operation: 125 µA @ 3 V Fast Update Rate: 188 KSPS Power-On Reset to Zero +2.7-V to +5.5-V Power Supply Specified Monotonic by Design I2C™ Interface up to 3.4 Mbps On-Chip Output Buffer Amplifier, Rail-to-Rail Operation Double-Buffered Input Register Address Support for up to Two DAC5571s Small 6 Lead SOT 23 Package Operation From –40°C to 105°C The output voltage range of the DAC is 0 V to VDD. The DAC5571 incorporates a power-on-reset circuit that ensures that the DAC output powers up at zero volts and remains there until a valid write to the device takes place. The DAC5571 contains a power-down feature, accessed via the internal control register, that reduces the current consumption of the device to 50 nA at 5 V. APPLICATIONS • • • • • The low-power consumption of this part in normal operation makes it ideally suited for portable battery operated equipment. The power consumption is less than 0.7 mW at VDD = 5 V reducing to 1 µW in power-down mode. Process Control Data Acquistion Systems Closed-Loop Servo Control PC Peripherals Portable Instrumentation DAC7571/6571/5571 are 12/10/8-bit, single-channel I2C DACs from the same family. DAC7574/6574/5574 and DAC7573/6573/5573 are 12/10/8-bit quad-channel I2C DACs. Also see DAC8571/8574 for single/quad-channel, 16-bit I2C DACs. VDD GND Power-On Reset Ref (+) Ref(−) 8-Bit DAC DAC Register I2C Control Logic A0 SCL Output Buffer Power-Down Control Logic VOUT Resistor Network SDA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of Philips Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2005, Texas Instruments Incorporated DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING DAC5571 SOT23-6 DBV –40°C to +105°C D571 ORDERING NUMBER TRANSPORT MEDIA DAC5571IDBVT 250-Piece Small Tape and Reel DAC5571IDBVR 3000-Piece Tape and Reel PIN CONFIGURATIONS (TOP VIEW) 1 2 3 D571 VOUT GND VDD 6 5 4 PIN DESCRIPTION (SOT23-6) A0 SCL SDA (BOTTOM VIEW) 5 4 YMLL 6 1 2 PIN NAME 1 VOUT Analog output voltage from DAC 2 GND Ground reference point for all circuitry 3 VDD Analog Voltage Supply Input 4 SDA Serial Data Input 5 SCL Serial Clock Input 6 A0 LOT TRACE CODE: 3 DESCRIPTION Device Address Select Year (3 = 2003); M onth (1–9 = JAN–SEP; A=OCT, B=NOV, C=DEC); LL– Random code generated when assembly is requested Lot Trace Code ABSOLUTE MAXIMUM RATINGS (1) UNITS VDD to GND – 0.3 V to +6 V Digital input voltage to GND –0.3 V to +VDD+0.3 V VOUT to GND – 0.3 V to +VDD+0.3 V Operating temperature range –40°C to +105°C Storage temperature range –65°C to +150°C Junction temperature range (TJ max) +150°C Power dissipation (TJmax - TA)RΘJA Thermal impedance, RΘJA Lead temperature, soldering (1) 2 240°C/W Vapor phase (60s) 215°C Infrared (15s) 220°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 ELECTRICAL CHARACTERISTICS VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to +105°C unless otherwise noted. PARAMETER CONDITIONS DAC5571 MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 8 Bits Relative accuracy Differential nonlinearity Assured monotonic by design Zero code error Full-scale error All ones loaded to DAC register ±0.5 LSB ±0.25 LSB 5 20 mV -0.15 -1.25 % of FSR ±1.25 % of FSR Gain error Zero code error drift ±7 µV/°C Gain temperature coefficient ±3 ppm of FSR/°C OUTPUT CHARACTERISTICS (2) Output voltage range Output voltage settling time 0 1/4 Scale to 3/4 scale change (400H to C00H) ; RL= ∞ 6 Slew rate Capacitive load stability Code change glitch impulse 8 µs 1 V/µs pF RL = ∞ 470 1000 pF 1 LSB Change around major carry 20 nV-s 0.5 nV-s 1 Ω VDD = +5 V 50 mA VDD = +3 V 20 mA Coming out of power-down mode, VDD = +5 V 2.5 µs Coming out of power-down mode, VDD = +3 V 5 µs DC output impedance Power-up time V RL = 2 kΩ Digital feedthrough Short-circuit current VDD LOGIC INPUTS (3) Input current VINL, Input low voltage VDD = +3 V VINH, Input high voltage VDD = +5 V ±1 µA 0.3×VDD V 3 pF 5.5 V 0.7×VDD V Pin capacitance POWER REQUIREMENTS VDD 2.7 IDD (normal operation) DAC active and excluding load current VDD = +3.6 V to +5.5 V VIH = VDD and VIL = GND 155 200 µA VDD = +2.7 V to +3.6 V VIH = VDD and VIL = GND 125 160 µA IDD (all power-down modes) VDD = +3.6 V to +5.5 V VIH = VDD and VIL = GND 0.2 1 µA VDD = +2.7 V to +3.6 V VIH = VDD and VIL = GND 0.05 1 µA ILOAD = 2 mA, VDD = +5 V 93 POWER EFFICIENCY IOUT/IDD (1) (2) (3) % Linearity calculated using a reduced code range of 3 to 253; output unloaded. Specified by design and characterization, not production tested. Specified by design and characterization, not production tested. 3 DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TIMING CHARACTERISTICS SYMBOL PARAMETER TEST CONDITIONS fSCL SCL Clock Frequency MIN MAX UNITS Standard mode 100 kHz Fast mode 400 kHz High-speed mode, CB - 100 pF max 3.4 MHz 1.7 MHz High-Speed mode, CB - 400 pF max tBUF tHD; tSTA tLOW tHIGH tSU; tSTA tSU; tDAT tHD; tDAT tRCL Bus Free Time Between a STOP and START Condition Standard mode 4.7 µs Fast mode 1.3 µs Hold Time (Repeated) START Condition Standard mode 4.0 µs Fast mode 600 ns High-speed mode 160 ns Standard mode 4.7 µs LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Setup Time Data Hold Time Rise Time of SCL Signal Fast mode 1.3 µs High-speed mode, CB - 100 pF max 160 ns High-speed mode, CB - 400 pF max 320 ns Standard mode 4.0 µs Fast mode 600 ns High-speed mode, CB - 100 pF max 60 ns High-speed mode, CB - 400 pF max 120 ns Standard mode 4.7 µs Fast mode 600 ns High-speed mode 160 ns Standard mode 250 ns Fast mode 100 ns High-speed mode 10 ns Standard mode 0 3.45 µs Fast mode 0 0.9 µs High-speed mode, CB - 100 pF max 0 70 ns High-speed mode, CB - 400 pF max 0 150 ns 1000 ns 20 + 0.1CB 300 ns High-speed mode, CB - 100 pF max 10 40 ns High-speed mode, CB - 400 pF max 20 Standard mode Fast mode tRCL1 tFCL Rise Time of SCL Signal After a Repeated START Condition and After an Acknowledge BIT Fall Time of SCL Signal Standard mode Fast mode Rise Time of SDA Signal Fall Time of SDA Signal ns 300 ns 10 80 ns 20 160 ns 300 ns Standard mode 20 + 0.1CB 300 ns High-speed mode, CB - 100 pF max 10 40 ns High-speed mode, CB - 400 pF max 20 80 ns 1000 ns Standard mode 20 + 0.1CB 300 ns High-speed mode, CB - 100 pF max 10 80 ns High-speed mode, CB - 400 pF max 20 160 ns Standard mode 300 ns 20 + 0.1CB 300 ns High-speed mode, CB - 100 pF max 10 80 ns High-speed mode, CB - 400 pF max 20 160 ns Fast mode 4 ns High-speed mode, CB - 400 pF max Fast mode tFDA 20 + 0.1CB 80 1000 High-speed mode, CB - 100 pF max Fast mode tRDA TYP DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TIMING CHARACTERISTICS (continued) SYMBOL PARAMETER TEST CONDITIONS tSU; tSTO Setup Time for STOP Condition Standard mode 4.0 µs Fast mode 600 ns High-speed mode 160 ns CB Capacitive Load for SDA and SCL tSP Pulse Width of Spike Suppressed VNH Noise Margin at the HIGH Level for Each Connected Device (Including Hysteresis) MIN TYP MAX UNITS 400 pF Fast mode 50 ns High-speed mode 10 ns Standard mode 0.2VDD V 0.1VDD V Fast mode High-speed mode VNL Noise Margin at the LOW Level for Each Connected Device (Including Hysteresis) Standard mode Fast mode High-speed mode TYPICAL CHARACTERISTICS: VDD = +5 V At TA = +25°C, +VDD = +5 V, unless otherwise noted. 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 0.25 0.2 0.15 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 −0.25 VDD = 5 V at −40°C DLE − LSB 0.25 0.2 0.15 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 −0.25 LE − LSB 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C ) DLE − LSB LE − LSB LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (-40°C) 0 32 64 96 128 160 192 224 256 VDD = 5 V at 25°C 0 32 64 96 DLE − LSB 0.25 0.2 0.15 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 −0.25 160 Figure 1. Figure 2. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105°C) ABSOLUTE ERROR 192 224 256 192 224 256 16 VDD = 5 V, TA = 25°C VDD = 5 V at 105°C 8 Output Error − mV LE − LSB 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 128 Digital Input Code Digital Input Code 0 −8 −16 0 32 64 96 128 160 Digital Input Code Figure 3. 192 224 256 0 32 64 96 128 160 Digital Input Code Figure 4. 5 DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. ZERO-SCALE ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 30 30 VDD = 5 V VDD = 5 V 20 Full-Scale Error − mV Zero-Scale Error 20 10 0 −10 −20 10 0 −10 −20 −30 −50 −40 −30 −20 −10 0 −30 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 T − Temperature −
C 10 20 30 40 50 60 70 80 90 100 110 T − Temperature −
C Figure 5. Figure 6. IDD HISTOGRAM SOURCE AND SINK CURRENT CAPABILITY 2500 5 2000 4 1500 3 V O U T (V) f − Frequency − Hz VDD = 5 V 1000 500 DAC Loaded with FFH 2 1 190 200 180 170 160 150 140 130 110 120 90 100 80 DAC Loaded with 00H 0 0 0 IDD − Supply Current −
A 5 10 15 ISOURCE/SINK (mA) Figure 7. Figure 8. SUPPLY CURRENT vs CODE SUPPLY CURRENT vs TEMPERATURE 500 300 VDD = 5 V 250 400 I DD − Supply Current − µ A I DD − Supply Current − µ A VDD = 5 V 300 200 100 0 0 2 32 64 96 128 160 Code Figure 9. 6 192 224 252 255 200 150 100 50 0 −50 −40 −30 −20 −10 0 10 20 30 40 50 60 70 80 90 100 110 T − Temperature −
C Figure 10. DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. SUPPLY CURRENT vs SUPPLY VOLTAGE POWER-DOWN CURRENT vs SUPPLY VOLTAGE 300 100 90 80 200 70 150 IDD (nA) I DD − Supply Current − µ A 250 100 60 +105°C 50 –40°C 40 30 50 20 0 2.7 3.2 3.7 4.2 4.7 5.2 5.7 +25°C 10 0 VDD − Supply Voltage − V 2.7 3.2 3.7 4.2 4.7 5.2 5.7 VDD (V) Figure 11. Figure 12. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE FULL-SCALE SETTLING TIME CLK (5V/div) 2500 IDD (µA) 2000 VOUT (1V/div) 1500 1000 Full−Scale Code Change 00 H to FF H Output Loaded with 2kΩ and 200pF to GND 500 0 Time (1µs/div) 0 1 2 3 4 5 VLOGIC (V) Figure 13. Figure 14. 7 DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS: VDD = +5 V (continued) At TA = +25°C, +VDD = +5 V, unless otherwise noted. FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME CLK (5V/div) CLK (5V/div) VOUT (1V/div) Full−Scale Code Change FF H to 00 H Output Loaded with 2k Ω and 200pF to GND Half−Scale Code Change 40 H to C0 H Output Loaded with 2k Ω and 200 pF to GND VOUT (1V/div) Time (1µ s/div) Time (1 µs/div) Figure 15. Figure 16. HALF-SCALE SETTLING TIME POWER-ON RESET TO 0V C LK (5 V/div) H alf−S ca le C o de C ha nge C 0 H to 40 H Loaded with 2kΩ to VDD. O utpu t Lo ad ed w ith 2k Ω an d 20 0pF to G N D VDD (1V/div) V O U T (1V /div) VOUT (1V/div) T ime (1 µ s/d iv ) 1m Time (20µs/div) Figure 17. Figure 18. EXITING POWER DOWN (80HLoaded) CODE CHANGE GLITCH Loa ded w ith 2 kΩ and 2 00p F to G N D . C od e C ha nge : CLK (5V/div) VOUT (20mV/div) 80 H t o 7 FH VOUT (1V/div) Tim e (0 .5 µs/div ) Time (5µs/div) Figure 19. 8 Figure 20. DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. LE − LSB 0.25 0.2 0.15 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 −0.25 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 DLE − LSB LE − LSB 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 DLE − LSB LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (-40°C) 0.25 0.2 0.15 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 −0.25 VDD = 2.7 V at −40°C 0 32 64 96 128 160 192 224 256 VDD = 2.7 V at 25°C 0 32 64 96 DLE − LSB 0.25 0.2 0.15 0.1 0.05 0 −0.05 −0.1 −0.15 −0.2 −0.25 192 Figure 22. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105°C) ABSOLUTE ERRORS 224 256 224 256 90 110 16 VDD = 2.7 V at 105°C VDD = 2.7 V TA = 25°C 8 0 −8 0 32 64 96 128 160 192 224 −16 256 0 32 64 96 Digital Input Code 160 192 Figure 23. Figure 24. ZERO-SCALE ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 30 V =5V VDD DD = 2.7 V VDD = 2.7 V 20 Full-Scale Error − mV 20 10 0 −10 −20 −30 −50 128 Digital Input Code 30 Zero-ScalenError − mV 160 Figure 21. Output Error − mV LE − LSB 0.5 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 128 Digital Input Code Digital Input Code 10 0 −10 −20 −30 −10 10 30 50 T − Temperature −
C Figure 25. 70 90 110 −30 −50 −30 −10 10 30 50 70 T − Temperature −
C Figure 26. 9 DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. IDD HISTOGRAM SOURCE AND SINK CURRENT CAPABILITY 3 2500 VDD = 2.7 V V D D = + 3V D AC Lo ad ed w ith F F H 2 1500 VOUT (V) f − Frequency − Hz 2000 1000 1 500 200 190 180 170 160 150 140 130 120 110 100 90 80 0 D AC Lo ade d w ith 00 H 0 0 IDD − Supply Current −
A 5 10 15 I S O U R C E /S IN K (m A) Figure 27. Figure 28. SUPPLY CURRENT vs CODE SUPPLY CURRENT vs TEMPERATURE 300 500 VDD = 2.7 V 250 400 I DD − Supply Current − µ A I DD − Supply Current − µ A VDD = 2.7 V 300 200 100 0 0 2 32 64 96 128 160 192 224 252 255 200 150 100 50 0 −50 −30 −10 Code 10 30 50 70 90 T − Temperature −
C Figure 29. Figure 30. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE FULL SCALE SETTLING TIME 2500 C LK (2.7V /div) IDD (µA) 2000 1500 1000 F ull−S c ale C o de C h an ge 00 H to F F H O utpu t L oad ed w ith 500 V O U T (1V /div ) 0 2 k Ω an d 200 pF to G N D Time (1 µ s/d iv ) 0 1 2 3 4 5 VLOGIC (V) Figure 31. 10 Figure 32. 110 DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued) At TA = +25°C, +VDD = +2.7 V, unless otherwise noted. FULL-SCALE SETTLING TIME HALF-SCALE SETTLING TIME CLK (2.7V/div) CLK (2.7V/div) Full−Scale Code Change FFH to 00H Output Loaded with 2k Ω and 200pF to GND VOUT (1V/div) VOUT (1V/div) Time (1µs/div) Half−Scale Code Change 40 H to C0H Output Loaded with 2 k Ω and 200 pF to GND Time (1
s/div) Figure 33. Figure 34. HALF-SCALE SETTLING TIME POWER-ON RESET 0 V POWER-ON RESET to 0V C LK (2.7V /div) H alf−Sca le C ode C ha nge C 0 H to 40 H O u tp ut Lo aded w ith 2kΩ and 2 00p F to G N D V O U T (1V/d iv) T im e (1 µ s/d iv) Time (20µs/div) Figure 35. Figure 36. EXITING-POWER DOWN (80HLoaded) CODE CHANGE GLITCH H Loa de d w ith 2k
and 2 00pF to G N D . CLK (2.7V/div) VOUT (1V/div) Time (5µs/div) Figure 37. VOUT (20mV/div) C ode C hange : 8 0 H to 7F H . Tim e (0 .5 s/div ) Figure 38. 11 DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 THEORY OF OPERATION D/A SECTION The architecture of the DAC5571 consists of a string DAC followed by an output buffer amplifier. Figure 39 shows a block diagram of the DAC architecture. VDD REF (+) Resistor String DAC Register VOUT Output Amplifier REF (-) GND Figure 39. R-String DAC Architecture The input coding to the DAC5571 is unsigned binary, which gives the ideal output voltage as: V OUT  




 where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 255. RESISTOR STRING The resistor string section is shown in Figure 40. It is basically a divide-by-2 resistor, followed by a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. Because the architecture consists of a string of resistors, it is specified monotonic. To Output Amplifier VDD GND R R R R Figure 40. Resistor String OUTPUT AMPLIFIER The output buffer amplifier is a gain-of-2 amplifier, capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical characteristics curves. The slew rate is 1 V/µs with a half-scale settling time of 7 µs with the output unloaded. I2C Interface I2C is a two-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. The DAC5571 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus 12 DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 THEORY OF OPERATION (continued) Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HS-mode. The DAC5571 supports 7-bit addressing; 10-bit addressing and general call address are not supported. F/S-Mode Protocol • • • • The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 41. All I2C-compatible devices should recognize a start condition. The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 42). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 43) by pulling the SDA line low during the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a communication link with a slave has been established. The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 41). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. On the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. HS-Mode Protocol • • • When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices. The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation. The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS-mode. SDA SDA SCL SCL S P Start Condition Stop Condition Figure 41. START and STOP Conditions 13 DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 THEORY OF OPERATION (continued) SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 42. Bit Transfer on the I2C Bus Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgement START Condition Figure 43. Acknowledge on the I2C Bus Recognize START or REPEATED START Condition Recognize STOP or REPEATED START Condition Generate ACKNOWLEDGE Signal P SDA MSB Acknowledgement Signal From Slave Sr Address R/W SCL S or Sr START or Repeated START Condition 1 2 7 8 9 ACK 1 3-8 9 ACK Sr or P Clock Line Held Low While Interrupts are Serviced STOP or Repeated START Condition Figure 44. Bus Protocol 14 2 DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 THEORY OF OPERATION (continued) DAC5571 I2C Update Sequence The DAC5571 requires a start condition, a valid I2C address, a control-MSB byte, and an LSB byte for a single update. After the receipt of each byte, DAC5571 acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the DAC5571. The CTRL/MSB byte sets the operational mode of the DAC5571, and the four most significant bits. The DAC5571 then receives the LSB byte containing four least significant data bits followed by four don't care bits. DAC5571 performs an update on the falling edge of the acknowledge signal that follows the LSB byte. For the first update, DAC5571 requires a start condition, a valid I2C address, a CTRL/MSB byte, an LSB byte. For all consecutive updates, DAC5571 needs a CTRL/MSB byte, and an LSB byte. Using the I2C high-speed mode (fscl= 3.4 MHz), the clock running at 3.4 MHz, each 8-bit DAC update other than the first update can be done within 18 clock cycles (CTRL/MSB byte, acknowledge signal, LSB byte, acknowledge signal), at 188.88 KSPS. Using the fast mode (fscl= 400 kHz), clock running at 400 kHz, maximum DAC update rate is limited to 22.22 KSPS. Once a stop condition is received, DAC5571 releases the I2C bus and awaits a new start condition. Address Byte MSB 1 LSB 0 0 1 1 0 A0 0 The address byte is the first byte received following the START condition from the master device. The first six bits (MSBs) of the address are factory preset to 100110. The next bit of the address is the device select bit A0. The A0 address input can be connected to VDD or digital GND, or can be actively driven by TTL/CMOS logic levels. The device address is set by the state of this pin during the power-up sequence of the DAC5571. Up to two devices (DAC5571) can be connected to the same I2C-Bus without requiring additional glue logic. Broadcast Address Byte MSB 1 LSB 0 0 1 0 0 0 0 Broadcast addressing is also supported by DAC5571. Broadcast addressing can be used for synchronously updating or powering down multiple DAC5571 devices. Using the broadcast address, DAC5571 responds regardless of the state of the address pin A0. Control - Most Significant Byte Most Significant Byte CTRL/MSB[7:0] consists of two zeros, two power-down bits, and four most significant bits of 8-bit unsigned binary D/A conversion data. Least Significant Byte Least Significant Byte LSB[7:0] consists of the four least significant bits of the 8-bit unsigned binary D/A conversion data, followed by four don't care bits. DAC5571 updates at the falling edge of the acknowledge signal that follows the LSB[0] bit. 15 DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 Standard- and Fast-Mode: S SLAVE ADDRESS R/W A Ctrl/MS-Byte A LS-Byte A/A P Data Transferred (n* Words + Acknowledge) Word = 16 Bit ”0” (write) From Master to DAC5571 DAC5571 I2C-SLAVE ADDRESS: From DAC5571 to Master MSB A = A = S = Sr = P = LSB 1 Acknowledge (SDA LOW) Not Acknowledge (SDA HIGH) START Condition Repeated START Condition STOP Condition 0 0 1 1 0 A0 R/W ’0’ = Write to DAC5571 Factory Preset A0 = I2C Address Pin High-Speed Mode (HS Mode): F/S-Mode S HS Mode HS-Master Code A Sr Slave Address R/W A Ctrl/MS-Byte HS-Mode Master Code: A/A P HS Mode Continues Sr Slave Address MSB LSB 0 0 0 1 X X R/W Ctrl/MS-Byte: LS-Byte: MSB 0 A LS-Byte Data Transferred (n* Words + Acknowledge) Word = 16 Bit ”0” (write) 0 F/S Mode 0 PD1 PD0 D7 D6 D5 LSB MSB D4 D3 LSB D2 D1 D0 X X X X D7 − D0 = Data Bits Figure 45. Master Transmitter Addressing DAC5571 as a Slave Receiver With a 7-Bit Address 16 DAC5571 www.ti.com SLAS405A – DECEMBER 2003 – REVISED AUGUST 2005 POWER-ON RESET The DAC5571 contains a power-on reset circuit that controls the output voltage during power up. On power up, the DAC register is filled with zeros and the output voltage is 0 V. It remains at a zero-code output until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the DAC output while it is in the process of powering up. POWER-DOWN MODES The DAC5571 contains four separate modes of operation. These modes are programmable via two bits (PD1 and PD0). Table 1 shows how the state of these bits correspond to the mode of operation. Table 1. Modes of Operation for the DAC5571 PD1 PD0 0 0 OPERATING MODE Normal Operation 0 1 1k Ω to AGND, PWD 1 0 100 kΩ to AGND, PWD 1 1 High Impedance, PWD When both bits are set to zero, the device works normally with normal power consumption of 150 µA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while in power-down mode. There are three different options: The output is connected internally to AGND through a 1-kΩ resistor, a 100-kΩ resistor, or it is left open-circuited (high impedance). The output stage is illustrated in Figure 46. Amplifier Resistor String DAC VOUT Power-Down Circuitry Resistor Network Figure 46. Output Stage During Power Down All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power down. The time required to exit power down is typically 2.5 µs for AVDD = 5 V and 5 µs for AVDD = 3 V. See the Typical Characteristics section for more information. CURRENT CONSUMPTION The DAC5571 typically consumes 150 µA at VDD = 5 V and 120 µA at VDD = 3 V. Additional current consumption can occur due to the digital inputs if VIH