DAC5574IDGSR

DAC5574 www.ti.com SLAS407 – DECEMBER 2003 QUAD, 8-BIT, LOW-POWER, VOLTAGE OUTPUT, I C INTERFACE DIGITAL-TO-ANALOG CONVERTER 2 FEATURES • • • • • • • • • • • • • • DESCRIPTION Micropower Operation: 500 µA at 3 V VDD Fast Update Rate: 188 kSPS Per-channel Power-down Capability Power-On Reset to Zero 2.7-V to 5.5-V Analog Power Supply 8-bit Monotonic I2C™ Interface Up to 3.4 Mbps Data Transmit Capability On-Chip Output Buffer Amplifier, Rail-to-Rail Operation Double-Buffered Input Register Address Support for up to Four DAC5574s Synchronous Update Support for up to 16 Channels Operation From –40°C to 105°C Small 10 Lead MSOP Package APPLICATIONS • • • • • Process Control Data Acquisition Systems Closed-Loop Servo Control PC Peripherals Portable Instrumentation The DAC5574 is a low-power, quad channel, 8-bit buffered voltage output DAC. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The DAC5574 utilizes an I2C compatible two wire serial interface supporting high-speed interface mode with address support of up to four DAC5574s for a total of 16 channels on the bus. The DAC5574 uses VDD and GND to set the output range of the DAC. The DAC5574 incorporates a power-on-reset circuit that ensures that the DAC output powers up at zero volts and remains there until a valid write takes place to the device. The DAC5574 contains a per-channel power-down feature, accessed via the internal control register, reducing the current consumption of the device to 200 nA at 5 V. The low power consumption of this part in normal operation makes it ideally suited to portable battery operated equipment. The power consumption is less than 3mW at VDD = 5 V reducing to 1 µW in power-down mode. TI offers a variety of data converters with I2C interface. See DACx57x family of 16/12/10/8 bit, single and quad channel DACs. Also see ADS7823 and ADS1100, 12-bit octal channel and 16-bit single channel ADCs. VDD Data Buffer A DAC Register A VOUTA DAC A VOUTB VOUTC Data Buffer D DAC Register D Buffer Control Register Control DAC D VOUTD 14 SCL I2C Block SDA 8 A0 A1 Power-Down Control Logic Resistor Network GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of Philips Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003, Texas Instruments Incorporated DAC5574 www.ti.com SLAS407 – DECEMBER 2003 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE PACKAGE DRAWING NUMBER SPECIFICATION TEMPERATURE RANGE PACKAGE MARKING DAC5574 10-MSOP DGS –40°C TO +105°C D574 (1) ORDERING NUMBER TRANSPORT MEDIA DAC5574IDGS 80 Piece Tube DAC5574IDGSR 2500 Piece Tape and Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DGS PACKAGE (TOPVIEW) PIN DESCRIPTIONS PIN NAME VOUTA 1 10 A1 1 VOUTA Analog output voltage from DAC A VOUTB 2 9 A0 2 VOUTB Analog output voltage from DAC B GND 3 8 VDD 3 GND VOUTC 4 7 SDA 4 VOUTC Analog output voltage from DAC C VOUTD 5 6 SCL 5 VOUTD Analog output voltage from DAC D 6 SCL Serial clock input 7 SDA Serial data input and output 8 VDD Analog voltage supply input 9 A0 Device address select - I2C 10 A1 Device address select - I2C DAC5574 DESCRIPTION Ground reference point for all circuitry on the part . ABSOLUTE MAXIMUM RATINGS (1) VDD to GND –0.3 V to +6 V Digital input voltage to GND –0.3 V to VDD + 0.3 V VOUT to GND –0.3 V to VDD + 0.3 V Operating temperature range –40°C to +105°C Storage temperature range –65°C to +150°C Junction temperature range (TJ max) Power dissipation: Lead temperature, soldering: (1) 2 +150°C Thermal impedance (ΘJA) 270°C/W Thermal impedance (ΘJC) 77°C/W Vapor phase (60s) 215°C Infrared (15s) 220°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. DAC5574 www.ti.com SLAS407 – DECEMBER 2003 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to +105°C, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 8 Bits ±0.15 ±0.5 LSB ±0.02 ±0.25 LSB Zero-scale error 5 20 mV Full-scale error -0.15 ±1.0 % of FSR ±1.0 % of FSR Relative accuracy Differential nonlinearity Specified monotonic by design Gain error Zero code error drift ±7 µV/°C Gain temperature coefficient ±3 ppm of FSR/°C OUTPUT CHARACTERISTICS (2) Output voltage range Output voltage settling time (full scale) 0 Digital-to-analog glitch impulse µs 1 V/µs 0.0025 LSB 1 kHz Sine Wave -100 dB RL= ∞ 470 pF RL= 2 kΩ 1000 pF 1 LSB change around major carry 12 nV-s 0.3 nV-s 1 Ω VDD= 5 V 50 mA VDD= 3 V 20 mA Coming out of power-down mode, VDD= +5 V 2.5 µs Coming out of power-down mode, VDD= +3 V 5 µs dc output impedance Power-up time LOGIC INPUTS µs 12 Digital feedthrough Short-circuit current 8 6 RL = ∞ ; CL = 500 pF dc crosstalk (channel-to-channel) Capacitive load stability V RL = ∞; 0 pF < CL < 200 pF Slew rate ac crosstalk (channel-to-channel) VDD (2) Input current VIN_L, Input low voltage VIN_H, Input high voltage VDD= 3 V ±1 µA 0.3xVDD V 0.7xVDD V Pin Capacitance 3 pF 5.5 V POWER REQUIREMENTS VDD 2.7 IDD(normal operation), including reference current Excluding load current IDD@ VDD=+3.6V to +5.5V VIH= VDD and VIL=GND 600 900 µA IDD@ VDD =+2.7V to +3.6V VIH= VDD and VIL=GND 500 750 µA IDD (all power-down modes) IDD@ VDD=+3.6V to +5.5V VIH= VDD and VIL=GND 0.2 1 µA IDD@ VDD =+2.7V to +3.6V VIH= VDD and VIL=GND 0.05 1 µA ILOAD= 2 mA, VDD= +5 V 93% +105 °C POWER EFFICIENCY IOUT/IDD TEMPERATURE RANGE Specified performance (1) (2) -40 Linearity tested using a reduced code range of 48 to 4047; output unloaded. Specified by design and characterization, not production tested. 3 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 TIMING CHARACTERISTICS VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to +105°C, unless otherwise specified. SYMBOL fSCL tBUF tHD; tSTA tLOW tHIGH tSU; tSTA tSU; tDAT tHD; tDAT PARAMETER SCL clock frequency Bus free time between a STOP and START condition Hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data setup time Data hold time TEST CONDITIONS MAX UNITS Standard mode MIN 100 kHz Fast mode 400 kHz High-Speed Mode, CB = 100 pF max 3.4 MHz High-speed mode, CB = 400 pF max 1.7 MHz Standard mode 4.7 µs Fast mode 1.3 µs Standard mode 4.0 µs Fast mode 600 ns High-speed mode 160 ns Standard mode 4.7 µs Fast mode 1.3 µs High-speed mode, CB = 100 pF max 160 ns High-speed mode, CB = 400 pF max 320 ns Standard mode 4.0 µs Fast mode 600 ns High-Speed Mode, CB = 100 pF max 60 ns High-speed mode, CB = 400 pF max 120 ns Standard mode 4.7 µs Fast mode 600 ns High-speed mode 160 ns Standard mode 250 ns Fast mode 100 ns High-speed mode 10 Standard mode 0 3.45 µs Fast mode 0 0.9 µs High-speed mode, CB = 100 pF max 0 70 ns High-speed mode, CB = 400 pF max 0 150 ns 1000 ns Standard mode tRCL tRCL1 Rise time of SCL signal Rise time of SCL signal after a repeated START condition and after an acknowledge BIT Fast mode Fall time of SCL signal 20 + 0.1CB 300 ns 10 40 ns High-speed mode, CB = 400 pF max 20 80 ns 1000 ns Standard mode 20 + 0.1CB 300 ns High-speed mode, CB = 100 pF max Fast mode 10 80 ns High-speed mode, CB = 400 pF max 20 160 ns 300 ns 20 + 0.1CB 300 ns High-speed mode, CB = 100 pF max 10 40 ns High-speed mode, CB = 400 pF max 20 Fast mode 80 ns 1000 ns 20 + 0.1CB 300 ns High-speed mode, CB = 100 pF max 10 80 ns High-speed mode, CB = 400 pF max 20 160 ns Standard mode tRDA 4 Rise time of SDA signal ns High-speed mode, CB = 100 pF max Standard mode tFCL TYP Fast mode DAC5574 www.ti.com SLAS407 – DECEMBER 2003 TIMING CHARACTERISTICS (continued) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to +105°C, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 300 ns 300 ns Standard mode tFDA Fast mode Fall time of SDA signal High-speed mode, CB = 100 pF max 10 80 ns High-speed mode, CB = 400 pF max 20 160 ns Standard mode 4.0 µs Fast mode 600 ns High-speed mode 160 ns Setup time for STOP condition tSU; tSTO CB Capacitive load for SDA and SCL tSP Pulse width of spike suppressed pF Fast mode 50 ns High-speed mode 10 ns Fast mode 0.2 VDD V 0.1 VDD V High-speed mode Standard mode Noise margin at the LOW level for each connected device (including hysteresis) VNL 400 Standard mode Noise margin at the HIGH level for each connected device (including hysteresis) VNH 20 + 0.1CB Fast mode High-speed mode TYPICAL CHARACTERISTICS At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 1 VDD = 5 V Channel B LE − LSB 0 −0.5 0 −0.5 −1 −1 0.5 0.25 0.25 0 −0.25 VDD = 5 V 0.5 0.5 DLE − LSB DLE − LSB LE − LSB Channel A 0.5 0 −0.25 −0.5 −0.5 0 32 64 96 128 160 Digital Input Code Figure 1. 192 224 255 0 32 64 96 128 160 192 224 255 Digital Input Code Figure 2. 5 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 1 Channel D VDD = 5 V 0.5 LE − LSB LE − LSB Channel C 0 −0.5 0.5 0.25 0.25 DLE − LSB DLE − LSB 0.5 0 −0.25 0 32 64 96 128 160 Digital Input Code 192 224 0 255 64 96 128 160 Digital Input Code 192 224 255 Figure 4. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 Channel A Channel B LE − LSB VDD = 2.7 V 0 −0.5 0 −0.5 −1 −1 0.5 0.25 0.25 0 −0.25 −0.5 VDD = 2.7 V 0.5 0.5 DLE − LSB LE − LSB DLE − LSB 32 Figure 3. 1 0.5 0 −0.25 −0.5 0 32 64 96 128 160 Digital Input Code 192 224 0 255 32 64 96 128 160 192 224 255 Digital Input Code Figure 5. Figure 6. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 1 Channel C VDD = 2.7 V LE − LSB 0.5 0 −0.5 0 −1 0.5 0.25 0.25 0 −0.5 VDD = 2.7 V −0.5 −1 −0.25 Channel D 0.5 0.5 DLE − LSB LE − LSB 0 −0.25 −0.5 −0.5 DLE − LSB 0 −0.5 −1 −1 0 −0.25 −0.5 0 6 VDD = 5 V 0.5 32 64 Digital Input Code 96 128 160 Digital Input Code Figure 7. Figure 8. 96 128 160 192 224 255 0 32 64 192 224 255 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. ZERO-SCALE ERROR vs TEMPERATURE ZERO-SCALE ERROR vs TEMPERATURE 20 15 VDD = 2.7 V 15 Zero-Scale Error − mV Zero-Scale Error − mV VDD = 5 V CH A CH C CH D 10 CH B 5 10 CH A CH C CH D 5 CH B 0 −40 −10 20 50 80 −40 −10 TA − Free−Air Temperature − °C Figure 10. FULL-SCALE ERROR vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 80 20 VDD = 5 V VDD = 2.7 V 25 Full-Scale Error − mV CH C CH A 20 CH D 15 10 CH B CH C 15 CH A 10 CH D 5 5 CH B 0 0 −40 −10 20 50 80 −40 −10 TA − Free−Air Temperature − °C 20 50 80 TA − Free−Air Temperature − °C Figure 11. Figure 12. SINK CURRENT CAPABILITY AT NEGATIVE RAIL SOURCE CURRENT CAPABILITY AT POSITIVE RAIL 0.150 5.50 Typical For All Channels Typical For All Channels 0.125 0.100 VOUT − Output Voltage − V VOUT − Output Voltage − V 50 Figure 9. 30 Full-Scale Error − mV 20 TA − Free−Air Temperature − °C VDD = 2.7 V VDD = 5.5 V 0.075 0.050 0.025 5.45 5.40 5.35 DAC Loaded With FFH VDD = 5.5 V DAC Loaded With 00H 0.000 5.30 0 1 2 3 ISINK − Sink Current − mA Figure 13. 4 5 0 1 2 3 4 5 ISOURCE − Source Current − mA Figure 14. 7 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. SOURCE CURRENT CAPABILITY AT POSITIVE RAIL SUPPLY CURRENT vs DIGITAL INPUT CODE 2.7 800 700 IDD − Supply Current − µA VOUT − Output Voltage − V Typical For All Channels 2.6 2.5 2.4 DAC Loaded With FFH VDD = 2.7 V VDD = 5.5 V 600 500 400 VDD = 2.7 V 300 200 100 2.3 All Channels Powered, No Load 0 0 1 2 3 4 5 0 32 64 96 ISOURCE − Source Current − mA 192 Figure 16. SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 224 255 5.1 5.5 700 650 600 IDD − Supply Current − µA IDD − Supply Current − µA 160 Figure 15. 700 VDD = 5.5 V 500 400 VDD = 2.7 V 300 200 100 600 550 500 450 400 350 300 250 All Channels Powered, No Load 0 All DACs Powered, No Load 200 −40 −10 20 50 80 110 2.7 3.1 3.5 TA − Free−Air Temperature − °C 1200 3.9 4.3 4.7 VDD − Supply Voltage − V Figure 17. Figure 18. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION 2000 TA = 25°C A0 Input (All Other Inputs = GND) VDD = 5 V 1000 1500 Frequency IDD − Supply Current − µA 128 Digital Input Code 800 VDD = 5.5 V 600 1000 500 400 VDD = 2.7 V 200 0 0 1 2 3 VLogic − Logic Input Voltage − V Figure 19. 8 4 5 500 520 540 560 580 600 620 640 660 680 700 720 740 IDD − Current Consumption − µA Figure 20. DAC5574 www.ti.com SLAS407 – DECEMBER 2003 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, unless otherwise noted. HISTOGRAM OF CURRENT CONSUMPTION EXITING POWER-DOWN MODE 2000 6 VDD = 2.7 V VOUT − Output Voltage − V 1500 Frequency 5 1000 500 0 VDD = 5 V Powerup to Code 250 4 3 2 1 0 −1 400 420 440 460 480 500 520 540 560 580 600 620 Time (2 µs/div) IDD − Current Consumption − µA Figure 21. Figure 22. LARGE SIGNAL SETTLING TIME LARGE SIGNAL SETTLING TIME 3.0 VOUT − Output Voltage − V VOUT − Output Voltage − V 5 4 VDD = 5 V Output Loaded with 200 pF to GND 10% to 90% FSR 3 2 1 0 2.5 2.0 VDD = 2.7 V Output Loaded with 200 pF to GND 10% to 90% FSR 1.5 1.0 0.5 0.0 Time (25 µs/div) Time (25 µs/div) Figure 23. Figure 24. ABSOLUTE ERROR† ABSOLUTE ERROR† 18 24 VDD = 5 V, TA = 25°C VDD = 2.7 V, TA = 25°C 14 Channel A Output Channel D Output 16 Output Error (mV) Output Error (mV) 20 12 8 Channel C Output Channel B Output 4 Channel A Output 10 6 2 Channel B Output −2 Channel D Output Channel C Output −6 0 0 32 64 96 128 160 Digital Input Code Figure 25. 192 224 255 0 32 64 96 128 160 Digital Input Code 192 224 255 Figure 26. † Absolute error is the deviation from ideal DAC characteristics. It includes affects of offset, gain, and integral linearity. 9 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 THEORY OF OPERATION D/A SECTION The architecture of the DAC5574 consists of a string DAC followed by an output buffer amplifier. Figure 27 shows a generalized block diagram of the DAC architecture. VDD 50 k
50 k
70 k
_ Ref+ Resistor String Ref- DAC Register + VOUT GND Figure 27. R-String DAC Architecture The input coding to the DAC5574 is unsigned binary, which gives the ideal output voltage as: V OUT  VDD
D 256 Where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 255. RESISTOR STRING The resistor string section is shown in Figure 28. It is basically a divide-by-2 resistor, followed by a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. Because the architecture consists of a string of resistors, it is specified monotonic. To Output Amplifier VDD GND R R R R Figure 28. Typical Resistor String Output Amplifier The output buffer is a gain-of-2 noninverting amplifiers, capable of generating rail-to-rail voltages on its output, which gives an output range of 0V to VDD. It is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/µs with a half-scale settling time of 6µs with the output unloaded. I2C Interface I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus under control of the master device. 10 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 THEORY OF OPERATION (continued) The DAC5574 works as a slave and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps). The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as H/S-mode. The DAC5574 supports 7-bit addressing; 10-bit addressing and general call address are not supported. F/S-Mode Protocol • • • • The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 29. All I2C-compatible devices should recognize a start condition. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 30). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 31) by pulling the SDA line low during the entire high period of the 9th SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a slave has been established. The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 29). This releases the bus and stops the communication link with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. H/S-Mode Protocol • • • When the bus is idle, both SDA and SCL lines are pulled high by the pullup devices. The master generates a start condition followed by a valid serial byte containing H/S master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the H/S master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation. The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the H/S-mode and switches all the internal settings of the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in H/S-mode. SDA SDA SCL SCL S P Start Condition Stop Condition Figure 29. START and STOP Conditions 11 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 THEORY OF OPERATION (continued) SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 30. Bit Transfer on the I2C Bus Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgement START Condition Figure 31. Acknowledge on the I2C Bus Recognize START or REPEATED START Condition Recognize STOP or REPEATED START Condition Generate ACKNOWLEDGE Signal P SDA MSB Acknowledgement Signal From Slave Sr Address R/W SCL S or Sr START or Repeated START Condition 1 2 7 8 9 ACK 1 3-8 9 ACK Sr or P Clock Line Held Low While Interrupts are Serviced STOP or Repeated START Condition Figure 32. Bus Protocol 12 2 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 2 DAC5574 I C Update Sequence The DAC5574 requires a start condition, a valid I2C address, a control byte, an MSB byte, and an LSB byte for a single update. After the receipt of each byte, DAC5574 acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the DAC5574. The control byte sets the operational mode of the selected DAC5574. Once the operational mode is selected by the control byte, DAC5574 expects an MSB byte followed by an LSB byte for data update to occur. DAC5574 performs an update on the falling edge of the acknowledge signal that follows the LSB byte. Control byte needs not to be resent until a change in operational mode is required. The bits of the control byte continuously determine the type of update performed. Thus, for the first update, DAC5574 requires a start condition, a valid I2C address, a control byte, an MSB byte and an LSB byte. For all consecutive updates, DAC5574 needs an MSB byte and an LSB byte as long as the control command remains the same. Using the I2C high-speed mode (fscl= 3.4 MHz), the clock running at 3.4 MHz, each 8-bit DAC update other than the first update can be done within 18 clock cycles (MSB byte, acknowledge signal, LSB byte, acknowledge signal), at 188.88 KSPS. Using the fast mode (fscl= 400 kHz), clock running at 400 kHz, maximum DAC update rate is limited to 22.22 KSPS. Once a stop condition is received DAC5574 releases the I2C bus and awaits a new start condition. Address Byte MSB 1 LSB 0 0 1 1 A1 A0 R/W The address byte is the first byte received following the START condition from the master device. The first five bits (MSBs) of the address are factory preset to 10011. The next two bits of the address are the device select bits A1 and A0. The A1, A0 address inputs can be connected to VDD or digital GND, or can be actively driven by TTL/CMOS logic levels. The device address is set by the state of these pins during the power-up sequence of the DAC5574. Up to 4 devices (DAC5574) can still be connected to the same I2C-Bus. Broadcast Address Byte MSB 1 LSB 0 0 1 0 0 0 0 Broadcast addressing is also supported by DAC5574. Broadcast addressing can be used for synchronously updating or powering down multiple DAC5574 devices. DAC5574 is designed to work with other members of the DAC857x and DAC757x families to support multichannel synchronous update. Using the broadcast address, DAC5574 responds regardless of the states of the address pins. Broadcast is supported only in write mode (Master writes to DAC5574). 13 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 Control Byte MSB LSB 0 0 L1 L0 X Sel1 Sel0 PD0 Table 1. Control Register Bit Descriptions Bit Name Bit Number/Description L1 Load1 (Mode Select) Bit L2 Load0 (Mode Select) Bit 14 00 Store I2C data. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the temporary register of a selected channel. This mode does not change the DAC output of the selected channel. 01 Update selected DAC with I2C data. Most commonly utilized mode. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the temporary register and in the DAC register of the selected channel. This mode changes the DAC output of the selected channel with the new data. 10 4-Channel synchronous update. The contents of MS-BYTE and LS-BYTE (or power down information) are stored in the temporary register and in the DAC register of the selected channel. Simultaneously, the other three channels get updated with previously stored data from the temporary register. This mode updates all four channels together. 11 Broadcast update mode. This mode has two functions. In broadcast mode, DAC5574 responds regardless of local address matching, and channel selection becomes irrelevant as all channels update. This mode is intended to enable up to 16 channels simultaneous update, if used with the I2C broadcast address (1001 0000). Sel1 Buff Sel1 Bit Sel0 Buff Sel0 Bit PD0 Are used for selecting the update mode. If Sel1=0 All four channels are updated with the contents of their temporary register data. If Sel1=1 All four channels are updated with the MS-BYTE and LS-BYTE data or powerdown. Channel Select Bits 00 Channel A 01 Channel B 10 Channel C 11 Channel D Power Down Flag 0 Normal operation 1 Power-down flag (MSB7 and MSB6 indicate a power-down operation, as shown in Table 2). DAC5574 www.ti.com SLAS407 – DECEMBER 2003 Table 2. Control Byte C7 C6 C5 C4 C3 C2 C1 C0 MSB7 MSB6 MSB5... 0 0 Load1 Load0 Don't Care Ch Sel 1 Ch Sel 0 PD0 MSB (PD1) MSB-1 (PD2) MSB-2 ...LSB 0 0 X 0 0 0 Data Write to temporary register A (TRA) with data 0 0 X 0 1 0 Data Write to temporary register B (TRB) with data 0 0 X 1 0 0 Data Write to temporary register C (TRC) with data 0 0 X 1 1 0 Data Write to temporary register D (TRD) with data 0 0 X 0 1 X 0 1 X 1 0 X 1 0 X DESCRIPTION (Address Select) (00, 01, 10, or 11) 1 see Table 8 0 (00, 01, 10, or 11) 0 Write to TRx (selected by C2 &C1 and load DACx w/data Data (00, 01, 10, or 11) 1 see Table 8 0 (00, 01, 10, or 11) 0 see Table 8 Power-down DACx (selected by C2 and C1) Write to TRx (selected by C2 &C1 w/ data and load all DACs Data (00, 01, 10, or 11) 1 Write to TRx (selected by C2 &C1 w/Powerdown Command 0 Power-down DACx (selected by C2 and C1) & load all DACs Broadcast Modes (controls up to 4 devices on a single serial bus) X X 1 1 X 0 X X X Update all DACs, all devices with previously stored TRx data X X 1 1 X 1 X 0 Data Update all DACs, all devices with MSB[7:0] and LSB[7:0] data X X 1 1 X 1 X 1 see Table 8 0 Power-down all DACs, all devices Most Significant Byte Most significant byte MSB[7:0] consists of eight most significant bits of 8-bit unsigned binary D/A conversion data. If C0=1, MSB[7], MSB[6] indicate a powerdown operation as shown in Table 8. Least Significant Byte Least significant byte LSB[7:0] consists of 8 don't care bits. DAC5574 updates at the falling edge of the acknowledge signal that follows the LSB[0] bit. Therefore, LSB [7:0] is needed for the update to occur. Default Readback Condition If the user initiates a readback of a specified channel without first writing data to that specified channel, the default readback is all zeros, since the readback register is initialized to 0 during the power on reset phase. 15 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 DAC5574 Registers Table 3. DAC5574 Architecture Register Descriptions REGISTER DESCRIPTION CTRL[7:0] Stores 8-bit wide control byte sent by the master MSB[7:0] Stores the 8 most significant bits of unsigned binary data sent by the master. Can also store 2-bit power-down data. TRA[9:0], TRB[9:0], TRC[9:0], TRD[9:0] 10-bit temporary storage registers assigned to each channel. Two MSBs store power-down information, 8 LSBs store data. DRA[9:0], DRB[9:0], DRC[9:0], DRD[9:0] 10-bit DAC registers for each channel. Two MSBs store power-down information, 8 LSBs store DAC data. An update of this register means a DAC update with data or power down. DAC5574 as a Slave Receiver - Standard and Fast Mode Figure 33 shows the standard and fast mode master transmitter addressing a DAC5574 Slave Receiver with a 7-bit address. S SLAVE ADDRESS R/W A Ctrl-Byte A MS-Byte A LS-Byte 0 (write) A/A P Data Transferred (n* Words + Acknowledge) Word = 16 Bit From Master to DAC5574 DAC5574 I2C-SLAVE ADDRESS: From DAC5574 to Master MSB A = A = S = Sr = P = Acknowledge (SDA LOW) Not Acknowledge (SDA HIGH) START Condition Repeated START Condition STOP Condition 1 LSB 0 0 1 1 A1 A0 R/W 0 = Write to DAC5574 1 = Read from DAC5574 Factory Preset A0 = I2C Address Pin A1 = I2C Address Pin Figure 33. Standard and Fast Mode: Slave Receiver 16 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 DAC5574 as a Slave Receiver - High-Speed Mode Figure 34 shows the high-speed mode master transmitter addressing a DAC5574 Slave Receiver with a 7-bit address. F/S-Mode S HS-Mode HS-Master Code A Sr Slave Address F/S-Mode R/W A Ctrl-Byte A MS-Byte A LS-Byte Data Transferred (n* Words + Acknowledge) Word = 16 Bit 0 (write) HS-Mode Master Code: P HS-Mode Continues Sr Slave Address MSB 0 A/A LSB 0 0 0 1 X X R/W Control Byte: MSB A3 LSB A2 L1 L0 X Sel1 Sel2 PD0 MS-Byte: MSB D7 LSB D6 D5 D4 D3 D2 D1 X X X X X D0 LS-Byte: MSB X LSB X D11 − D0 = Data Bits X A3 A2 L1 L0 Sel1 Sel0 PD0 = = = = = = = Extended Address Bit Extended Address Bit Load1 (Mode Select) Bit Load0 (Mode Select) Bit Buff Sel1 (Channel) Select Bit Buff Sel0 (Channel) Select Bit Power Down Flag X = Don’t Care Figure 34. High-Speed Mode: Slave Receiver 17 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 Master Transmitter Writing to a Slave Receiver (DAC5574) in Standard/Fast Modes All write access sequences begin with the device address (with R/W = 0) followed by the control byte. This control byte specifies the operation mode of DAC5574 and determines which channel of DAC5574 is being accessed in the subsequent read/write operation. The LSB of the control byte (PD0-Bit) determines if the following data is power-down data or regular data. With (PD0-Bit = 0) the DAC5574 expects to receive data in the following sequence HIGH-BYTE –LOW-BYTE – HIGH-BYTE – LOW-BYTE..., until a STOP Condition or REPEATED START Condition on the I2C-Bus is recognized (refer to the DATA INPUT MODE section of Table 4). With (PD0-Bit = 1) the DAC5574 expects to receive 2 Bytes of power-down data (refer to the POWER DOWN MODE section of Table 4). Table 4. Write Sequence in F/S Mode DATA INPUT MODE Transmitter MSB 6 5 4 Master Master 1 0 0 1 DAC5574 Master 0 0 Load 1 1 LSB 1 Comment A1 A0 R/W Write addressing (R/W=0) Buff Sel 0 PD0 Control byte (PD0=0) D1 D0 Writing data word, high byte x x Writing data word, low byte Begin sequence Load 0 x Buff Sel 1 DAC5574 Acknowledges D7 D6 D5 x x x D4 DAC5574 Master 2 DAC5574 Acknowledges DAC5574 Master 3 Start D3 D2 DAC5574 Acknowledges x DAC5574 x x DAC5574 Acknowledges Data or Stop or Repeated Start (1) Master Data or done (2) POWER DOWN MODE Transmitter MSB 6 5 4 Master Master 1 0 0 DAC5574 Master 0 0 Load 1 PD1 PD2 0 1 1 A1 Load 0 x Comment A0 R/W Write addressing (R/W=0) Buff Sel 0 PD0 Control byte (PD0 = 1) 0 0 0 Writing data word, high byte x x x Writing data word, low byte Buff Sel 1 0 0 DAC5574 Acknowledges x x x x x DAC5574 Acknowledges Master Stop or Repeated Start (1) 18 LSB Begin sequence DAC5574 (1) (2) 1 DAC5574 Acknowledges DAC5574 Master 2 DAC5574 Acknowledges DAC5574 Master 3 Start Done Use repeated START to secure bus operation and loop back to the stage of write addressing for next Write. Once DAC5574 is properly addressed and control byte is sent, HIGH–BYTE–LOW–BYTE sequences can repeat until a STOP condition or repeated START condition is received. DAC5574 www.ti.com SLAS407 – DECEMBER 2003 Master Transmitter Writing to a Slave Receiver (DAC5574) in HS Mode When writing data to the DAC5574 in HS-mode, the master begins to transmit what is called the HS-Master Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master Code is followed by a NOT acknowledge. The master then switches to HS-mode and issues a repeated start condition, followed by the address byte (with R/W = 0) after which the DAC5574 acknowledges by pulling SDA low. This address byte is usually followed by the control byte, which is also acknowledged by the DAC5574. The LSB of the control byte (PD0-Bit) determines if the following data is power-down data or regular data. With (PD0-Bit = 0) the DAC5574 expects to receive data in the following sequence HIGH-BYTE – LOW-BYTE – HIGH-BYTE – LOW-BYTE...., until a STOP condition or repeated start condition on the I2C-Bus is recognized (refer to Table 5 HS-MODE WRITE SEQUENCE - DATA). With (PD0-Bit = 1) the DAC5574 expects to receive 2 bytes of power-down data (refer to Table 5 HS-MODE WRITE SEQUENCE - POWER DOWN). Table 5. Master Transmitter Writes to Slave Receiver (DAC5574) in HS-Mode HS MODE WRITE SEQUENCE - DATA Transmitter MSB 6 5 4 0 0 0 0 Master Master 0 0 1 X X X Comment Begin sequence 1 HS Mode Master Code No device may acknowledge HS master code 1 A1 A0 R/W Write addressing (R/W=0) Buff Sel 0 PD0 Control byte (PD0=0) D1 D0 Writing data word, MSB x x Writing data word, LSB DAC5574 Acknowledges 0 0 Load 1 DAC5574 Load 0 0 Buff Sel 1 DAC5574 Acknowledges D7 D6 D5 x x x D4 DAC5574 Master LSB Repeated Start 1 DAC5574 Master 1 Not Acknowledge Master Master 2 Start NONE Master 3 D3 D2 DAC5574 Acknowledges x DAC5574 x x DAC5574 Acknowledges Data or Stop or Repeated Start (1) Master Data or done (2) HS MODE WRITE SEQUENCE - POWER DOWN Transmitter MSB 6 5 4 Master Master 3 2 0 0 0 0 1 X Not Acknowledge Master Repeated Start 1 0 0 DAC5574 Master 0 0 Load 1 PD1 PD2 0 1 X HS Mode Master Code No device may acknowledge HS master code A1 Load 2 0 A0 R/W Write addressing (R/W = 0) Buff Sel 0 PD0 Control Byte (PD0=1) 0 0 0 Writing data word, high byte x x x Writing data word, low byte Buff Sel 1 0 0 DAC5574 Acknowledges x x x x x DAC5574 DAC5574 Acknowledges Master Stop or repeated start (1) (1) (2) X DAC5574 Acknowledges DAC5574 Master 1 Comment DAC5574 Acknowledges DAC5574 Master LSB Begin sequence NONE Master 1 Start Done Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write. Once DAC5574 is properly addressed and control byte is sent, high-byte-low-byte sequences can repeat until a stop or repeated start condition is received. 19 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 DAC5574 as a Slave Transmitter - Standard and Fast Mode Figure 35 shows the standard and fast mode master transmitter addressing a DAC5574 Slave Transmitter with a 7-bit address. (DAC5574) (DAC5574) (MASTER) (DAC5574) S SLAVE ADDRESS R/W A Ctrl PD0 A Sr Slave Address R/W A MS-Byte A LS-Byte A P 1 (read) 0 (write) 0 = (Normal Mode) Data Transferred (2 Bytes + Acknowledge) (DAC5574) PD0 A Sr Slave Address 1 = (Power Down Flag) (MASTER) R/W A PDN-Byte A (MASTER) (MASTER) MS-Byte A LS-Byte A P Data Transferred (3 Bytes + Acknowledge) 1 (read) PDN-Byte: MSB (MASTER) LSB PD1 PD2 1 1 1 1 1 1 PD1 = Power−Down Bit PD2 = Power−Down Bit Figure 35. Standard and Fast Mode: Slave Transmitter DAC5574 as a Slave Transmitter - High-Speed Mode Figure 36 shows an I2C-Master addressing DAC5574 in high-speed mode (with a 7-bit address), as a Slave Transmitter. F/S-Mode HS-Master Code S A HS-Mode (DAC5574) Sr Slave Address (DAC5574) R/W A Ctrl PD0 A Sr (DAC5574) Slave Address 0 = (Normal Mode) Data Transferred (2 Bytes + Acknowledge) (DAC5574) PD0 A Sr Slave Address 1 = (Power −Down Flag) (MASTER) R/W A PDN-Byte A 1 (read) Figure 36. High-Speed Mode: Slave Transmitter 20 (MASTER) R/W A MS-Byte A LS-Byte A P 1 (read) 0 (write) (MASTER) (MASTER) (MASTER) MS-Byte A LS-Byte A P Data Transferred (3 Bytes + Acknowledge) DAC5574 www.ti.com SLAS407 – DECEMBER 2003 Master Receiver Reading From a Slave Transmitter (DAC5574) in Standard/Fast Modes When reading data back from the DAC5574, the user begins with an address byte (with R/W = 0) after which the DAC5574 will acknowledge by pulling SDA low. This address byte is usually followed by the Control Byte, which is also acknowledged by the DAC5574. Following this there is a REPEATED START condition by the Master and the address is resent with (R/W = 1). This is acknowledged by the DAC5574, indicating that it is prepared to transmit data. Two or three bytes of data are then read back from the DAC5574, depending on the (PD0-Bit). The value of Buff-Sel1 and Buff-Sel0 determines, which channel data is read back. A STOP Condition follows. With the (PD0-Bit = 0) the DAC5574 transmits 2 bytes of data, HIGH-BYTE followed by the LOW-BYTE (refer to Table 2. Data Readback Mode - 2 bytes). With the (PD0-Bit = 1) the DAC5574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the HIGH-BYTE followed by the LOW-BYTE (refer to Table 2. Data Readback Mode - 3 bytes). Table 6. Read Sequence in F/S Mode DATA READBACK MODE - 2 BYTES Transmitter MSB 6 5 4 1 0 0 1 3 Master Master 0 0 Load 1 Comment A0 R/W Write addressing (R/W=0) Buff Sel 1 Buff Sel 0 PD0 Control byte (PD0=0) A1 A0 R/W Read addressing (R/W = 1) D2 D1 D0 Reading data word, high byte x x x Reading data word, low byte Begin sequence x DAC5574 Acknowledges Repeated Start 1 0 0 D7 D6 D5 DAC5574 1 1 DAC5574 Acknowledges Master DAC5574 A1 1 Load 0 Master DAC5574 LSB DAC5574 Acknowledges DAC5574 Master 1 Start DAC5574 Master 2 D4 D3 Master Acknowledges x x x x x Master Master Not Acknowledges Master signal end of read Master Stop or Repeated Start (1) Done DATA READBACK MODE - 3 BYTES Transmitter MSB 6 5 4 3 Master Master 1 0 0 1 0 0 Load 1 Load 0 DAC5574 Master 0 0 A1 A0 R/W Write addressing (R/W=0) Buff Sel 1 Buff Sel 0 PD0 Control byte (PD0=1) A1 A0 R/W Read addressing (R/W = 1) 1 1 1 D2 D1 D0 Reading data word, high byte x x x Reading data word, low byte Begin sequence 1 x 1 1 DAC5574 Acknowledges PD1 PD2 1 D7 D6 D5 Master 1 1 Read power down byte Master Acknowledges Master DAC5574 Comment Repeated Start 1 DAC5574 DAC5574 LSB DAC5574 Acknowledges Master DAC5574 1 DAC5574 Acknowledges DAC5574 Master 2 Start D4 D3 Master Acknowledges x x x x x Master Master Not Acknowledges Master signal end of read Master Stop or Repeated Start (1) Done (1) Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write. 21 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 Master Receiver Reading From a Slave Transmitter (DAC5574) in HS-Mode When reading data to the DAC5574 in HS-MODE, the master begins to transmit, what is called the HS-Master Code (0000 1XXX) in F/S-mode. No device is allowed to acknowledge the HS-Master Code, so the HS-Master Code is followed by a NOT acknowledge. The Master then switches to HS-mode and issues a REPEATED START condition, followed by the address byte (with R/W = 0) after which the DAC5574 acknowledges by pulling SDA low. This address byte is usually followed by the control byte, which is also acknowledged by the DAC5574. Then there is a REPEATED START condition initiated by the master and the address is resent with (R/W = 1). This is acknowledged by the DAC5574, indicating that it is prepared to transmit data. Two or Three bytes of data are then read back from the DAC5574, depending on the (PD0-Bit). The value of Buff-Sel1 and Buff-Sel0 determines, which channel data is read back. A STOP condition follows. With the (PD0-Bit = 0) the DAC5574 transmits 2 bytes of data, HIGH-BYTE followed by LOW-BYTE (refer to Table 7 HS-Mode Readback Sequence). With the (PD0-Bit = 1) the DAC5574 transmits 3 bytes of data, POWER-DOWN-BYTE followed by the HIGH-BYTE followed by the LOW-BYTE (refer to Table 7 HS-Mode Readback Sequence). Table 7. Master Receiver Reading Slave Transmitter (DAC5574) in HS-Mode HS MODE READBACK SEQUENCE Transmitter MSB 6 5 4 0 0 0 0 3 Master Master LSB Comment X X X HS Mode Master Code Begin sequence 1 No device may acknowledge HS master code Not Acknowledge Master Repeated Start 1 0 0 DAC5574 Master 1 Start NONE Master 2 1 1 A1 0 0 Load 1 Load 0 X Buff Sel 1 DAC5574 DAC5574 Acknowledges Master Repeated Start Master 1 0 0 DAC5574 DAC5574 PD1 PD2 1 Write addressing (R/W=0) Buff Sel 0 PD0 Control byte (PD0 = 1) 1 1 A1 A0 R/W Read addressing (R/W=1) 1 1 1 1 1 Power-down byte D1 D0 Reading data word, high byte x x Reading data word, low byte Master Acknowledges D7 D6 D5 Master DAC5574 R/W DAC5574 Acknowledges Master DAC5574 A0 DAC5574 Acknowledges D4 D3 D2 Master Acknowledges x x x x x x Master Master Not Acknowledges Master signal end of read Master Stop or Repeated Start Done Power-On Reset The DAC5574 contains a power-on-reset circuit that controls the output voltage during power up. On power up, the DAC register is filled with zeros and the output voltage is 0 V; it remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. No device pin should be brought high before supply is applied. Power-Down Modes The DAC5574 contains four separate power-down modes of operation. The modes are programmable via two most significant bits of the MSB byte, while (CTRL[0] = PD0 = 1). Table 8 shows how the state of these bits correspond to the mode of operation of the device. 22 DAC5574 www.ti.com SLAS407 – DECEMBER 2003 Table 8. Power-Down Modes of Operation for the DAC5574 CTRL[0] MSB[7] MSB[6] OPERATING MODE 1 0 0 High Impedance Output 1 0 1 1 kΩ to GND 1 1 0 100 kΩ to GND 1 1 1 High Impedance When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 150 µA at 5 V per channel. However, for the power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but also the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while in power-down mode. There are three different options: The output is connected internally to GND through a 1-kΩ resistor, a 100-kΩ resistor or left open-circuit (high impedance). The output stage is illustrated in Figure 37. Amplifier Resistor String DAC VOUT Powerdown Circuitry Resistor Network Figure 37. Output Stage During Power Down All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit power down is typically 2.5 µs for VDD = 5 V and 5 µs for VDD = 3 V. (See the Typical Curves section for additional information.) The DAC5574 offers a flexible power-down interface based on channel register operation. A channel consists of a single 8-bit DAC with power-down circuitry, a temporary storage register (TR) and a DAC register (DR). TR and DR are both 10 bits wide. Two MSBs represent the power-down condition and the 8 LSBs represent data for TR and DR. By using bits 9 and 8 of TR and DR, a power-down condition can be temporarily stored and used just like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[9] and TR[8] (DR[9] and DR[8]) when the power-down flag (CTRL[0] = PD0) is set. Therefore, DAC5574 treats power-down conditions like data and all the operational modes are still valid for power down. It is possible to broadcast a power-down condition to all the DAC5574s in the system, or it is possible to simultaneously power down a channel while updating data on other channels. CURRENT CONSUMPTION The DAC5574 typically consumes 150µA at VDD = 5 V and 125µA at VDD = 3 V for each active channel, including reference current consumption. Additional current consumption can occur at the digital inputs if VIH