DAC5662
SLAS425D – JULY 2004 – REVISED OCTOBER 2021
DAC5662 Dual, 12-BIT 275 MSPS Digital-to-Analog Converter
1 Features
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12-Bit dual transmit DAC
275 MSPS Update rate
Single supply: 3 V to 3.6 V
High SFDR: 85 dBc at 5 MHz
High IMD3: 78 dBc at 15.1 and 16.1 MHz
WCDMA ACLR: 70 dB at 30.72 MHz
Independent or single resistor gain control
Dual or interleaved data
On-chip 1.2-V reference
Low power: 330 mW
Power-down mode: 15 mW
Package: 48-Pin TQFP
2 Applications
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Cellular base transceiver station transmit channel
– CDMA: W-CDMA, CDMA2000, IS-95
– TDMA: GSM, IS-136, EDGE/UWC-136
Medical, test instrumentation
Arbitrary waveform generators (AWG)
Direct digital synthesis (DDS)
Cable modem termination system (CMTS)
3 Description
The DAC5662 is a monolithic, dual-channel 12-bit
high-speed digital-to-analog converter (DAC) with onchip voltage reference.
Operating with update rates of up to 275 MSPS,
the DAC5662 offers exceptional dynamic performance
and tight-gain and offset matching, characteristics that
make it suitable in either I/Q baseband or direct IF
communication applications.
Each DAC has a high-impedance differential current
output, suitable for single-ended or differential analogoutput configurations. External resistors allow scaling
the full-scale output current for each DAC separately
or together, typically between 2 mA and 20 mA. An
accurate on-chip voltage reference is temperature
compensated and delivers a stable 1.2-V reference
voltage. Optionally, an external reference may be
used.
The DAC5662 has two 12-bit parallel input ports with
separate clocks and data latches. For flexibility, the
DAC5662 also supports multiplexed data for each
DAC on one port when operating in the interleaved
mode.
The DAC5662 has been specifically designed for a
differential transformer coupled output with a 50-Ω
doubly terminated load. For a 20-mA full-scale output
current a 4:1 impedance ratio (resulting in an output
power of
4 dBm) and 1:1 impedance ratio transformer (-2 dBm
output power) are supported.
The DAC5662 is available in a 48-pin thin quad
FlatPack (TQFP). Pin compatibility between family
members provides 12-bit (DAC5662) and 14-bit
(DAC5672) resolution. Furthermore, the DAC5662 is
pin compatible to the DAC2902 and AD9765 dual
DACs. The device is characterized for operation over
the industrial temperature range of -40°C to 85°C.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
DAC5662
TQFP
7.00 mm x 7.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
WRTB
WRTA
CLKB
CLKA
DE
MUX
IOUTA1
Latch A
12−b DAC
DA[11:0]
IOUTA2
BIASJ_A
IOUTB1
Latch B
DB[11:0]
12−b DAC
MODE
IOUTB2
BIASJ_B
GSET
1.2 V Reference
EXTIO
SLEEP
DVDD
DGND
AVDD
AGND
Functional Block diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC5662
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SLAS425D – JULY 2004 – REVISED OCTOBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 3
5 Pin Configurations and Functions.................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Resistance Characteristics........................... 6
6.5 Electrical Characteristics.............................................7
6.6 Electrical Characteristics.............................................8
6.7 Electrical Characteristics, AC......................................9
6.8 Electrical Characteristics, DC................................... 10
6.9 Switching Characteristics..........................................10
6.10 Typical Characteristics............................................ 11
7 Parameter Measurement Information.......................... 14
7.1 Digital Inputs and Timing...........................................14
8 Detailed Description......................................................17
2
8.1 Overview................................................................... 17
8.2 Functional Block Diagram......................................... 17
8.3 Feature Description...................................................18
8.4 Device Functional Modes..........................................22
9 Application and Implementation.................................. 23
9.1 Application Informmation.......................................... 23
9.2 Typical Application.................................................... 23
10 Power Supply Recommendations..............................25
11 Layout........................................................................... 26
11.1 Layout Guidelines................................................... 26
11.2 Layout Example...................................................... 26
12 Device and Documentation Support..........................30
12.1 Documentation Support.......................................... 30
12.2 Receiving Notification of Documentation Updates..30
12.3 Support Resources................................................. 30
12.4 Trademarks............................................................. 30
12.5 Electrostatic Discharge Caution..............................30
12.6 Glossary..................................................................30
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SLAS425D – JULY 2004 – REVISED OCTOBER 2021
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (October 2020) to Revision D (October 2021)
Page
• Chnaged the device number from: DAC566452 to: DAC5662 in the Device Information table..........................1
Changes from Revision B (July 2004) to Revision C (October 2020)
Page
• Added Device Information table, ESD Ratings table, Thermal Resistance Characteristics table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section...................................................................................................1
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SLAS425D – JULY 2004 – REVISED OCTOBER 2021
MODE
AVDD
IOUTA1
IOUTA2
BIASJ_A
EXTIO
GSET
BIASJ_B
IOUTB2
IOUTB1
AGND
SLEEP
5 Pin Configurations and Functions
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
33
4
5
Top View
48−Pin TQFP
PFB Package
6
7
32
31
30
8
29
9
28
10
27
11
26
25
12
13 14 15 16 17 18 19 20 21 22 23 24
NC
NC
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
NC
NC
DGND
DVDD
WRTA/WRTIQ
CLKA/CLKIQ
CLKB/RESETIQ
WRTB/SELECTIQ
DGND
DVDD
DB11 (MSB)
DB10
DA11 (MSB)
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0 (LSB)
Table 5-1. Pin Functions
PIN
I/O
DESCRIPTION
38
I
Analog ground
47
I
Analog supply voltage
BIASJ_A
44
O
Full-scale output current bias for DACA
BIASJ_B
41
O
Full-scale output current bias for DACB
CLKA/CLKIQ
18
I
Clock input for DACA, CLKIQ in interleaved mode.
CLKB/
RESETIQ
19
I
Clock input for DACB, RESETIQ in interleaved mode.
DA[11:0]
1-12
I
Data port A. DA11 is MSB and DA0 is LSB. Internal pulldown.
DB[11:0]
23-34
I
Data port B. DB11 is MSB and DB0 is LSB. Internal pulldown.
DGND
15, 21
I
Digital ground
DVDD
16, 22
I
Digital supply voltage
EXTIO
43
I/O
GSET
42
I
Gain-setting mode: H - 1 resistor, L - 2 resistors. Internal pullup.
IOUTA1
46
O
DACA current output. Full-scale with all bits of DA high.
IOUTA2
45
O
DACA complementary current output. Full-scale with all bits of DA low.
IOUTB1
39
O
DACB current output. Full-scale with all bits of DB high.
IOUTB2
40
O
DACB complementary current output. Full-scale with all bits of DB low.
MODE
48
I
Mode Select: H – Dual Bus, L – Interleaved. Internal pullup.
13, 14, 35,
36
-
No connection
SLEEP
37
I
Sleep function control input: H – DAC in power-down mode, L – DAC in operating mode. Internal
pulldown.
WRTA/WRTIQ
17
I
Input write signal for PORT A (WRTIQ in interleaving mode).
WRTB/
SELECTIQ
20
I
Input write signal for PORT B (SELECTIQ in interleaving mode).
NAME
NO.
AGND
AVDD
NC
4
Internal reference output (bypass with 0.1 μF to AGND) or external reference input.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
Supply voltage range
Min
Max
AVDD(2)
-0.5
4
V
DVDD(3)
-0.5
4
V
-0.5
0.5
V
Voltage between AGND and DGND
Voltage between AVDD and DVDD
Supply voltage range
UNIT
-0.5
0.5
V
DA[11:0] and DB[11:0](3)
-0.5
DVDD + 0.5
V
MODE, SLEEP, CLKA, CLKB, WRTA,
WRTB(3)
-0.5
DVDD + 0.5
V
IOUTA1, IOUTA2, IOUTB1, IOUTB2(2)
-1
AVDD + 0.5
V
-0.5
AVDD + 0.5
EXTIO, BIASJ_A, BIASJ_B,
GSET(2)
Peak input current (any input)
Peak total input current (all inputs)
V
+20
mA
-30
mA
Operating free-air temperature range
-40
85
°C
Storage temperature range
-65
150
°C
(1)
(2)
(3)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
Measured with respect to AGND.
Measured with respect to DGND.
6.2 ESD Ratings
VALUE
V (ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
over operating free-air temperature range (unless otherwise noted)
6.3 Recommended Operating Conditions
MIN
NOM
MAX
UNIT
AVDD
3
3.3
3.6
V
DVDD
3
3.3
3.6
V
I(AVDD) Analog supply current
75
90
mA
I(DVDD) Digital supply current
25
38
mA
2
20
mA
-1
1.25
V
275
MHz
Supplies
Analog Output
IO(FS) Full-Scale output current
Output voltage compliance range
Clock Interface (CLK, CLKC)
CLKINPUT Frequency
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6.4 Thermal Resistance Characteristics
DAC5652
THERMAL
METRIC(1)
TQFP (PFB)
UNIT
48-Pins
R θJA
Junction-to-ambient thermal resistance
65.3
°C/W
R θJC(top)
Junction-to-case (top) thermal resistance
16.4
°C/W
R θJB
Junction-to-board thermal resistance
28.6
°C/W
ψ JT
Junction-to-top characterization parameter
0.4
°C/W
ψ JB
Junction-to-board characterization parameter
28.4
°C/W
R θJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, independent gain set mode (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC Specifications
Resolution
12
Bits
DC Accuracy(1)
INL
Integral nonlinearity
DNL
Differential nonlinearity
1 LSB = IOUTFS/212, TA = 25°C
-2
±0.3
2
LSB
-2
±0.2
2
LSB
Analog Output
Offset error
Gain error
0.03
%FSR
With external reference
±0.25
%FSR
With internal reference
±0.5
%FSR
current(2)
2
mA
Maximum full-scale output current(2)
20
mA
Minimum full-scale output
Gain mismatch
With internal reference
Output voltage compliance range(3)
RO
Output resistance
CO
Output capacitance
-2
0.07
-1
+2
1.25
%FSR
V
300
kΩ
5
pF
Reference Output
Reference voltage
Reference output
1.14
current(4)
1.2
1.26
100
V
nA
Reference Input
VEXTIO
Input voltage
RI
Input resistance
CI
0.1
1.25
V
1
MΩ
Small signal bandwidth
300
kHz
Input capacitance
100
pF
Temperature Coefficients
0
ppm of
FSR/°C
With external reference
±50
ppm of
FSR/°C
With internal reference
±50
ppm of
FSR/°C
±20
ppm/°C
Offset drift
Gain drift
Reference voltage drift
(1)
(2)
(3)
(4)
Measured differentially through 50 Ω to AGND.
Nominal full-scale current, IOUTFS, equals 32x the IBIAS current.
The lower limit of the output compliance is determined by the CMOS process. Exceeding this limit may result in transistor breakdown,
resulting in reduced reliability of the DAC5662 device. The upper limit of the output compliance is determined by the load resistors and
full-scale output current. Exceeding the upper limit adversely affects distortion performance and intergral nonlinearity.
Use an external buffer amplifier with high impedance input to drive any external load.
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6.6 Electrical Characteristics
over operating free-air temperature range, AVDD = DVDD = 3.3 V, IOUTFS = 20 mA, fDATA = 200 MSPS, fOUT = 1 MHz,
independent gain set mode (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply
AVDD
Analog supply voltage
3
3.3
3.6
V
DVDD
Digital supply voltage
3
3.3
3.6
V
Including output current through load
resistor
75
90
mA
Sleep mode with clock
2.5
6
mA
Sleep mode without clock
2.5
IAVDD
Supply current, analog
IDVDD
Supply current, digital
25
38
mA
Sleep mode with clock
12.5
18
mA
Sleep mode without clock