DAC5687 EVM
User's Guide
Literature Number: SLWU017C
APRIL 2005 – Revised August 2013
Contents
............................................................................................................................ 4
................................................................................................................... 4
1.2
EVM Basic Functions ................................................................................................... 4
1.3
Power Requirements .................................................................................................... 4
1.4
Software Installation ..................................................................................................... 5
1.5
Hardware Configuration ................................................................................................ 5
2
DAC5687 EVM Operational Procedure ................................................................................... 6
2.1
Starting the Serial Interface Program ................................................................................. 9
2.2
DAC5687 Initial Setup Tests ......................................................................................... 10
2.3
Basic Test Procedure with TSW1400 ............................................................................... 12
2.4
DAC5687 GUI Register Descriptions ............................................................................... 18
3
Physical Description .......................................................................................................... 20
3.1
PCB Layout ............................................................................................................. 20
3.2
Parts List ................................................................................................................ 24
4
Circuit Description ............................................................................................................. 26
4.1
Input Clocks ............................................................................................................ 26
4.2
Input Data ............................................................................................................... 26
4.3
Output Data ............................................................................................................. 27
4.4
Control Inputs .......................................................................................................... 28
4.5
Internal Reference Operation ........................................................................................ 28
4.6
External Reference Operation ........................................................................................ 28
5
Schematics ....................................................................................................................... 29
Revision A History ...................................................................................................................... 30
Revision B History ...................................................................................................................... 30
Revision C History ...................................................................................................................... 30
1
Overview
1.1
2
Purpose
Table of Contents
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List of Figures
1
Serial Interface GUI .........................................................................................................
9
2
DAC5687 Setup for X4L Mode and NCO Tone at FDAC/25 ...........................................................
10
3
Spectrum with CLK2 = 500 MHz, X4L Interpolation and NCO Frequency = 343597383 ........................
11
4
DAC5687 Setup for X4 Mode and NCO Tone at FDAC/15 ............................................................
12
5
Connecting TSW1400 and DAC5687 Together .......................................................................
13
6
Clocks Synchronisation Between DAC5687 and TSW1400 .........................................................
14
7
DAC5687 GUI Setup ......................................................................................................
15
8
Select CMOS in HSDC PRO.............................................................................................
15
9
Load DAC Firmware Prompt .............................................................................................
16
10
HSDC Pro Setup for One Tone Generation
...........................................................................
1 Tone Test, no NCO .....................................................................................................
NCO Configuration ........................................................................................................
1 Tone Test, NCO Activated, IF = 20Mhz ..............................................................................
Top Layer 1 ................................................................................................................
Layer 2, Ground Plane ....................................................................................................
Layer 3, Power Plane .....................................................................................................
Bottom Layer ...............................................................................................................
16
11
12
13
14
15
16
17
17
17
18
21
22
23
24
List of Tables
1
2
3
4
................................................................................................
Input Connector J13 (Data A Bus) .....................................................................................
Input Connector J14 (Data B Bus) .....................................................................................
Transformer Output Configuration.......................................................................................
DAC5687 EVM Parts List
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List of Figures
25
26
27
27
3
User's Guide
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DAC5687 EVM
1
Overview
This user's guide document gives a general overview of the DAC5687 evaluation module (EVM) and
provides a general description of the features and functions to be considered while using this module.
1.1
Purpose
The DAC5687 EVM provides a platform for evaluating the DAC5687 digital-to-analog converter (DAC)
under various signal, reference, and supply conditions. This document should be used in combination with
the EVM schematic diagram supplied.
1.2
EVM Basic Functions
Digital inputs to the DAC can be provided with CMOS level signals up to 250 MSPS (external clock mode)
through two 34-pin headers. This enables the user to provide high-speed digital data to the DAC5687
device.
The analog outputs from the DAC are available via SMA connectors. Because of its flexible design the
analog outputs of the DAC5687 device can be configured to drive a 50-Ω terminated cable using a 4:1 or
1:1 impedance ratio transformer, or single-ended referred to AVDD. The EVM also allows for an option to
double the output power by summing the DAC A and DAC B outputs through a 1:1 transformer.
The EVM allows the user to input single-ended, TTL/CMOS level signals, to generate differential clock
sources for both CLK1 and CLK2. See Section 4.1, Input Clocks, for proper configuration and operation.
Power connections to the EVM are via banana jack sockets.
In addition to the internal bandgap reference provided by the DAC5687 device, options on the EVM allow
an external reference to be provided to the DAC.
The DAC5687 EVM allows the user to program the DAC5687 internal registers with the supplied computer
parallel port cable and serial interface software. The interface allows read and write access to all registers
that define the operation mode of the DAC5687 device.
1.3
Power Requirements
The demonstration board requires only two power supplies. 3.3 Vdc is required at banana jack J7, with the
return connected to J9. 1.8 Vdc is required at banana jack J8, with the return to J10.
1.3.1
Voltage Limits
CAUTION
Exceeding the maximum input voltages can damage EVM components.
Undervoltage may cause improper operation of some or all of the EVM
components.
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Overview
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1.4
Software Installation
All necessary software to operate the serial interface is provided on the enclosed CD-ROM.
1. Insert the CD-ROM into the computer to be used to operate the serial interface.
2. Click on the zipped directory called DAC5687SPI_Installv2p2.zip. Extract all of the files into a new
directory, called C:\temp, on the PC.
3. Go the following directory: C:\temp\Installer. Double click on the file called setup.exe.
4. The software will create a top level directory at the following location: C:\Program
Files\TI.fdr\DAC5687_SPI. This directory will contain the required files as well as a labwindows-cvi
runtime engine to run the software.
5. Once the installation is complete, the software is launched by running DAC5687_SPI.exe. See
Chapter 2, DAC5687 EVM Operational Procedure, for instructions on operating the serial interface
software.
1.5
Hardware Configuration
The DAC5687 EVM can be set up in a variety of configurations to accommodate a specific mode of
operation. Before starting evaluation, the user should decide on the configuration and make the
appropriate connections or changes. The demonstration board comes with the following factory-set
configuration:
• Differential clock mode using transformers T3 and T4. Input single-ended clocks are required at J3 and
J4.
• Transformer-coupled outputs using 4:1 transformers T1 and T2.
• The converter is set to operate with internal reference. Jumper W1 is installed between pins 2 and 3.
• Full-scale output current set to 20 mA through RBIAS resistor R1.
• The DAC5687 output is enabled (sleep mode disabled).
• TxENABLE is set high to enable the DAC5687 device to process data. A jumper is installed between
pins 11 and 12 on J15.
• Internal PLL disabled. Jumper W3 is installed between pins 2 and 3.
• Input data level is set to +3.3VDC. Jumper W2 is installed between pins 1 and 2.
To
1.
2.
3.
prepare the DAC5687 EVM for evaluation, connect the following:
3.3 V to J7 and the return to J9.
1.8 V to J8 and the return to J10.
Provide a single-ended, 1-VPP, 0-V offset sine-wave signal to SMA connector J3 (CLK1) if the internal
PLL is to be used. Connect this signal to SMA connector J4 (CLK2) if the PLL is disabled. A second
sine-wave source is required only for dual clock mode. In this mode, the signal on CLK1 is used to
clock data into the DAC5687 and the signal on CLK2 is used to clock the internal DAC. CLK1 and
CLK2 must be phase-aligned for this option to work properly. In order to preserve the specified
performance of the DAC5687 converter, the clock sources must feature very low jitter. Using a clock
with a 50% duty cycle gives optimum dynamic performance.
4. Use a digital test pattern generator with 50-Ω outputs to provide 3.3-V CMOS logic level inputs to
connectors J13 and J14. Adjust the digital inputs to provide the proper voltage levels and setup and
hold times at the DAC5687 inputs. See the DAC5687 data sheet (SLWS164) for timing information.
Another solution is to use the TSW1400 pattern generator card as explained in Section 2.3
5. Connect one end of the supplied serial interface cable to the parallel port of a PC. Connect the other
end of the cable to J1 on the EVM. The user can also use the provided USB to SPI adapter, setup is
explained in Section 2.
6. The DAC5687 outputs can be monitored using SMA connector J5 for IOUTA and SMA connector J19
for IOUTB.
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DAC5687 EVM Operational Procedure
To prepare the DAC5687 EVM for operation, follow these steps:
1. Parallel Port Interface: Connect one end of the supplied serial interface cable to the parallel port of a
PC and the other end of the cable to J1 on the EVM and skip steps 2 to 7.
2. USB Interface: Connect the provided USB to SPI adapter board to the parallel port connector on the
EVM and to a spare USB port on the host PC using the supplied USB cable. The Windows Found New
Hardware Wizard should open; if this is not the case make sure the cable is connected properly. Select
“No, not this time” from the options available and then click “Next” to proceed with the installation.
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3. Select "Install the software automatically (recommended)" as shown below and then click "Next".
4. If Windows is not able to find the appropriate USB drivers press “Back” and select “Install from a list or
specific location (advanced)”. Click “Next”.
5. Select "Search for the best driver in these locations" and browse for the folder where the DAC5687
program was installed (the default location is C:\Program Files\Texas Instruments\DAC5687). Once the
file path has been selected, click “Next” to proceed.
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6. If Windows XP is configured to warn when unsigned (non-WHQL certified) drivers are about to be
installed, the following screen is displayed unless installing a Microsoft WHQL certified driver. Click on
"Continue Anyway" to continue with the installation. If Windows XP is configured to ignore file
signature warnings, no message will appear.
7. Windows should then display a message indicating that the installation was successful. Click "Finish"
to complete the installation.
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2.1
Starting the Serial Interface Program
Power up the EVM. After power up, depress switch S1 to reset the DAC5687. Start the software by
running the following executable:
C:\Program Files\TI.fdr\DAC5687_SPI\ DAC5687_SPI.exe.
If the EVM is powered on with the parallel port connected properly, then the GUI shown in Figure 1 is
displayed with the default settings read from the device. If using the USB interface card, change mode to
USB in the upper right corner window. The hardware and software are now ready for testing. For serial
interface operation, simply click on the switches, up/down arrows, etc., to select the desired settings of the
DAC5687. If there is a problem with the communication, such as the EVM is not powered on or the
parallel port cable is not connected, an error message will be displayed instructing the user to correct the
problem. Once corrected, hit the "Read All" button, located in the lower right corner of the GUI, to read the
default settings of the device.
Figure 1. Serial Interface GUI
For normal operation, the user needs only to select values and switches as desired. The values are
automatically sent to the device and read back to verify their configuration.
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2.2
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DAC5687 Initial Setup Tests
There are several initial tests with the DAC5687 that can be done without any input data. The following
setup steps are suggested to familiarize the user with the DAC5687 and EVM software and verify that the
DAC5687 is functioning properly.
1. Provide a CLK2 input if the PLL is disabled or a CLK1 input if the PLL is enabled (W3). Do not provide
parallel input data.
2. Power up EVM with 1.8V DVDD and 3.3V AVDD
3. Start DAC5687_SPI software.
4. Click on the "Load Regs" button on the GUI. A new directory window will open. Click on the file called
"User Guide Test.reg5687". Click on "OK". This will load a test setting for the DAC, corresponding to
FNCO/12.5 = 20 MHz for CLK2 = 500 MSPS (FNCO = FDAC/2 for X4L mode). The GUI should now look as
shown in Figure 2.
Figure 2. DAC5687 Setup for X4L Mode and NCO Tone at FDAC/25
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This tone is being generated by the DAC5687 NCO. With no input data provided to connectors J13
and J14, the Channel A and B data bus inputs will all be zeros, or a full scale negative value in the
default offset binary format. In the X4L mode, after the first 2x interpolation, the full scale DC input
signal at a clock rate of 250 MSPS is mixed with the NCO running at the setting of FNCO/12.5
(343597383) to generate a tone at 20 MHz. After a second 2x interpolation, a 20 MHz tone is output
from the DAC sampling at 500 MSPS. The output spectrum should be similar to Figure 3.
Figure 3. Spectrum with CLK2 = 500 MHz, X4L Interpolation and NCO Frequency = 343597383
5. Change the Mode to 1000 FDAC/4 (+,+), corresponding to FDAC/4 (see data sheet). This will increase the
output by FDAC/4 to 20 MHz + 125 MHz = 145 MHz.
6. Changing the NCO DDS to 3951369913 (232 x (1-20/250)) will now result in an output tone at 125 MHz
- 20 MHz = 105 MHz.
7. Change the interpolation to X4, and the mode to No Mixing, the NCO DDC to 286331153 (FNCO/15) and
reduce the CLK2 frequency to < 320 MSPS. The GUI should look as shown in Figure 4. The NCO is
now running at the DAC update rate (= CLK2). For CLK2 = 300 MSPS, the result is an output tone at
20 MHz.
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Figure 4. DAC5687 Setup for X4 Mode and NCO Tone at FDAC/15
2.3
Basic Test Procedure with TSW1400
This section outlines the basic test procedure for testing the EVM with the TSW1400.
2.3.1
TSW1400 Overview
The TSW1400 is a high speed data capture and pattern generator board. For more detailed explanation of
the TSW1400 setup and operation, see the TSW1400 user’s guide (SLWU079). This document assumes
that the High Speed Data Converter Pro software (available to download here:
http://www.ti.com/tool/tsw1400evm) is installed and functioning properly.
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2.3.2
Test Block Diagrams for TSW1400
As described in Figure 5, the first steps consist in connecting boards together through CMOS interface,
connecting USB interfaces to a PC and connecting a source clock to CLK2 and one output to a signal
analyzer.
Figure 5. Connecting TSW1400 and DAC5687 Together
Next, as shown in Figure 6, it is important to connect the PLL output of the DAC5687 “PLLLOCK out” to
the “CMOS CLK” input of the TSW1400 in order to synchronize the data rates. Finally, supply the
DAC5687 with 1.8V and 3.3V, and supplying the TSW with a 5V jack.
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Figure 6. Clocks Synchronisation Between DAC5687 and TSW1400
2.3.3
DAC5687 Example Setup Procedure
Launch the DAC5687 GUI and check for valid connection for either parallel or USB connection. Press
reset button on the DAC5687 EVM and press "Read All" button on the GUI to update the DAC5687 reset
value to the GUI.
For this first test, disable NCO and leave the rest as default.
NOTE: One important detail is to make sure to enable Rev B bus since channel B is B(15:0) when A
is A(0:15) on Rev. B of the EVM.
The Bus B is reversed to avoid data lines crossing on the layout, see Section 4.2 for details.
The setup should look like Figure 7.
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Figure 7. DAC5687 GUI Setup
2.3.4
TSW1400 Example Setup Procedure
A single tone with HSDC pro is generated in this section.
1. Start the High Speed Converter Pro GUI program. When the program starts, select the DAC tab and
then select CMOS firmware in the “Select DAC” menu.
Figure 8. Select CMOS in HSDC PRO
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2. When prompted ‘load DAC firmware?’, select YES.
Figure 9. Load DAC Firmware Prompt
In this test, a 122.88MHz DAC clock is used with 2x interpolation, so Data rate is 61.44MHz.
3. Select 61.44Mhz Data rate, Offset bin
4. Generate a one tone test, here a 5MHz complex
Result should look like Figure 10.
Figure 10. HSDC Pro Setup for One Tone Generation
Send the generated signal clicking on send. Remove and put the TXenable jumper to synchronize the
FIFO.
Result on the signal analyzer should be similar to Figure 11.
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Figure 11. 1 Tone Test, no NCO
Next step can be to activate the NCO. To do so:
1. Switch on the NCO feature on the DAC5687 GUI.
2. Set FDAC to 122.88Mhz and NCO IF to 20MHz for instance
3. Click on update, it will automatically calculate the NCO DDs value and send it
Result of the setup is shown in Figure 12.
Figure 12. NCO Configuration
Result on the signal analyzer is shown in Figure 13.
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Figure 13. 1 Tone Test, NCO Activated, IF = 20Mhz
2.4
DAC5687 GUI Register Descriptions
2.4.1
Register Controls
⋅
⋅
⋅
⋅
2.4.2
Loads register values from a saved file to the DAC5687 and updates the GUI.
Saves current GUI registers settings to a text file for future use.
Reads the current registers of the DAC5687. This is used to verify settings on the front panel.
Sends the current front panel registers to the device. This is generally only used when the EVM
power has recycled or the device has been reset and the user wants to load the displayed settings
to the device.
Configuration Controls
⋅
⋅
⋅
⋅
⋅
⋅
18
Load Regs:
Save Regs:
Read All:
Send All:
Full Bypass:
FIR Bypass:
FIFO Bypass:
FIR A:
FIR B:
Dual Clk:
DAC5687 EVM
When set, all filtering, QMC, and NCO functions are bypassed.
When set, the interpolation filters are bypassed.
When set to bypass, the internal 4 sample FIFO is disabled. When cleared, the FIFO is enabled.
A side first FIR filter in highpass mode when set, lowpass mode when cleared.
B side first FIR filter in highpass mode when set, lowpass mode when cleared.
Only used when the PLL is disabled. When set, two differential clocks are used to input the data to
the chip; CLK1/CLK1C is used to latch the input data into the chip, and CLK2/CLK2C is used as the
DAC sample clock
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⋅
Interleave:
⋅
⋅
Inverse Sinc:
Half Rate Input:
⋅
Sif:
⋅
Inv. PLL Lock:
⋅
⋅
⋅
PLL Freq:
PLL Kv:
Qflag:
⋅
2's Comp:
⋅
Rev A Bus:
⋅
Rev B Bus:
⋅
⋅
⋅
⋅
⋅
⋅
USB:
Inv. Clk I(Q):
Sync_Phstr:
Sync_cm:
Sync_NCO:
Phstr Clk Div
Select:
⋅
DAC Serial Data:
o
o
⋅
NCO:
o
⋅
QMC:
o
o
o
⋅
⋅
⋅
Mode:
PLL Divider:
Interpolation:
⋅
⋅
Phstr Init. Phase:
Sync FIFO:
⋅
Alt. PLLLOCK
Output:
When set, interleaved input data mode is enabled; both A and B data streams are input at the
DA(15:0) input pins.
Enables inverse sinc filter.
Enables half rate input mode. Input data for the DAC A data path is input to the chip at half speed
using both the DA(15:0) and DB(15:0) input pins.
Sets sif_4pin bit. 4 pin serial interface mode is enabled when on, 3 pin mode when off. The
DAC5687 EVM is configured for a 3 pin serial interface. The 4 bit serial interface will not work with
the DAC5687 EVM.
Only used when PLL is disabled and dual clock mode is disabled. When cleared, input data is
latched into the chip on the rising edge of the PLLLOCK output pin. When set, input data is latched
into the chip on the falling edge of the PLLLOCK output pin.
Sets PLL VCO center frequency to low or high center frequency.
Sets PLL VCO gain to either high or low gain.
Sets qflag bit. When set, the QFLAG input pin operates as a B sample indicator when interleaved
data is enabled. When cleared, the TXENABLE rising determines the A/B timing relationship.
When set, input data is interpreted as 2's complement. When cleared, input data is interpreted as
offset binary.
When cleared, Channel A input data MSB to LSB order is DA(15) = MSB and DA(0) = LSB. When
set, Channel A input data MSB to LSB order is reversed, DA(15) = LSB and DA(0) = MSB.
When cleared, Channel B input data MSB to LSB order is DB(15) = MSB and DB(0) = LSB. When
set, Channel B input data MSB to LSB order is reversed, DB(15) = LSB and DB(0) = MSB.
When set, the data to DACB is inverted to generate upper side band output.
Inverts the DAC core sample clock when set, normal when cleared.
When set, the internal clock divider logic is initialized with a PHSTR pin low to high transition.
When set, the coarse mixer is synchronized with a PHSTR low to high transition.
When set, the NCO phase accumulator is cleared with a phstr low to high transition.
Selects the clock used to latch the PHSTR input when restarting the internal clock dividers. When
set, the full rate CLK2 signal latches PHSTR. When cleared, the divided down input clock signal
latches PHSTR.
When set, both DAC A and DAC B input data is replaced with fixed data loaded into the 16 bit
serial interface DAC Static Data.
Counter Mode: Controls the internal counter that can be used as the DAC data source. See the
data sheet for more information.
DAC Static Data: When DAC Serial Data is set, both DAC A and DAC B input data is replaced
with fixed data loaded with this value. Range = 0 to 65535.
When set, enables NCO.
NCO Gain: Sets NCO gain resulting in a 2x increase in NCO output amplitude. Except for FS/2 and
FS/4 mixing NCO frequencies, this selection can result in saturation for full scale inputs. Consider
using QMC gain for lower gains.
When set, enables the QMC.
QMCA Gain: Sets QMC gain A to a range = 0 to 2047. See the data sheet for more information.
QMC B Gain: Sets QMC gain B to a range = 0 to 2047. See the data sheet for more information.
QMC Phase: Sets QMC phase to a range = -512 to 511. See the data sheet for more information.
Used to select the coarse mixer mode. See the DAC5687 data sheet for more information.
Sets VCO divider to div by 1, 2, 4, or 8.
Sets FIR Interpolation factor: {X2, X4, X4L, X8}. X4 uses lower power than 4xL, but FDAC = 320
MSPS max when NCO or QMC are used.
Adjusts the initial phase of the FS/2 and FS/4 cmix block at PHSTR.
Sync source selection mode for the FIFO. When a low to high transition is detected on the selected
sync source, the FIFO input and output pointers are initialized. See the DAC5687 data sheet for
source description.
Sets PLLLOCK output pin to FDAC frequency when operating in the PLL mode. Settings must be
used in conjunction with the interpolation setting to achieved desired rate (i.e. set to FDAC/2 for 2x
interpolation, set to FDAC/4 for 4x interpolation). Note, there is no option for the 8x mode. The
jumper at W1 (EXTLO) must be removed to utilize this functionality.
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Physical Description
2.4.3
DAC A(B) Gain
⋅
2.4.4
⋅
DAC Coarse
Gain:
DAC Fine Gain:
⋅
⋅
DAC DC Offset:
Sleep:
Sets coarse gain of DAC A(B) full scale current. Range is 0 to 15. See the DAC5687 data sheet for
full scale gain equation.
Sets fine gain of DAC A(B) full scale current. Range is -128 to 127. See the DAC5687 data sheet for
full scale gain equation.
Sets DAC A(B) DC offset register. Range is -4096 to 4095.
DAC A(B) sleeps when set, operational when cleared.
NCO DDS:
NCO Phase:
FDac:
NCO IF:
Sets NCO DDS registers. See the DAC5687 data sheet for formula.
Sets initial NCO phase registers. See the DAC5687 data sheet for more information.
Set the DAC frequency in Mhz for NCO DDS calculation
Set IF in Mhz for NCO DDS calculation
NCO
⋅
⋅
2.4.5
3
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Additional Control/Monitor Registers
⋅
Pll Port Config:
⋅
⋅
Quit:
Version:
⋅
About:
Selection of this button will bring up a separate window that shows the parallel port configuration of
the software. The EVM Menu should be loaded with DAC EVM. This button also allows the user to
change the LPT address used by the PC. This is set by entering a valid address inside the box
labeled "LPT Address". The default setting is 378.
Quits the operation of the DAC5687 software.
Displays the version of the silicon. If a version of 0 is read then the communication is not functioning
and an error message will be displayed.
Opens an additional window with help related topics for the software.
Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM and lists the components
used on the module.
3.1
PCB Layout
The EVM is constructed on a 4-layer, 4.9-inch x 6.5-inch, 0.055-inch thick PCB using FR-4 material.
Figure 14 through Figure 17 show the PCB layout for the EVM.
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Physical Description
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Figure 14. Top Layer 1
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21
Physical Description
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Figure 15. Layer 2, Ground Plane
22
DAC5687 EVM
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Physical Description
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Figure 16. Layer 3, Power Plane
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DAC5687 EVM
23
Physical Description
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Figure 17. Bottom Layer
3.2
Parts List
Table 1 lists the parts used in constructing the EVM.
24
DAC5687 EVM
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Physical Description
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Table 1. DAC5687 EVM Parts List
Bill of Material For DAC5687
Value
Qty.
Part Number
Vendor
Ref Des
Not Installed
CAPACITORS
47 uF, tantalum, 10%, 10 V
6
10TPA47M
Sanyo
C53-C58
10 uF, 10 V, 10% capacitor
12
GRM42X5R106K10
Murata
C24, C26-C28, C30-C32,
C35, C37-C39, C41
1 uF, 16 V, 10% capacitor
6
ECJ-3YB1C105K
Panasonic
C36, C42-C46
0.1 uF, 16 V, 10% capacitor
3
ECJ-2VB1C104K
Panasonic
C21, C22, C23
0.01 uF, 50 V, 5% capacitor
6
ECJ-2VB1H103K
Panasonic
C47-C52
0.01 uF, 16 V, 10% capacitor
2
ECJ-1VB1C103K
Panasonic
C19, C20
0.1 uF, 16 V, 10% capacitor
4
ECJ-1VB1C104K
Panasonic
C25, C40, C60, C61
0.1 uF, 16 V, +80/-20% capacitor
21
ECJ-0EF1C104Z
Panasonic
C1 C2 C4-C13, C15-C18,
C29, C59, C84-C86
0.01 uF, 25 V, 10% capacitor
1
ECJ-0EF1E103Z
Panasonic
C14
0.033 uF, 25 V, +80/-20%
capacitor
1
ECU-E1C333ZFQ
Panasonic
C34
10 pF, 50 V, 5% capacitor
1
ECU-E1H100DCQ
Panasonic
C3
330 pF, 50 V, 5% capacitor
1
ECU-V1H331JCV
Panasonic
C33
RESISTORS
10-kΩ resistor 1/16 W, 1%
4
ERJ-6ENF1002V
Panasonic
R34-R37
10-Ω resistor 1/16 W, 1%
1
ERJ-6ENF10R0V
Panasonic
R3
10-Ω resistor 1/16 W, 1%
1
ERJ-2RFK10R0X
Panasonic
R43
0-Ω resistor, 1/16 W, 1%
4
ERJ-3GEY0R00V
Panasonic
R23, R26, R38, R42
R6-R9, R24, R27-R33
49.9-Ω resistor, 1/16 W, 1%
3
ERJ-3EKF49R9V
Panasonic
R12, R13, R39
R40
110-Ω resistor, 1/10 W, 1%
0
ERA-3EKF110V
Panasonic
200-Ω resistor, 1/16 W, 1%
2
ERJ-3EKF200V
Panasonic
R11, R14
93.1-Ω resistor, 1/16 W, 1%
1
ERJ-3EKF93R1V
Panasonic
R25
1-kΩ resistor, 1/16 W, 1%
2
ERJ-3EKF1001V
Panasonic
R1, R4
221-Ω resistor, 1/10 W, 1%
0
ERA-3EKF221V
Panasonic
22.1-Ω resistor, 1/10 W, 1%
2
ERJ-3EKF22R1V
Panasonic
R2, R16
100-Ω resistor, 1/10 W, 1%
4
ERA-3EKF100V
Panasonic
R5, R10, R19, R20
Surface mount socket strips
4
310-93-164-41-105000
Mill-Max
RP5, RP6, RP9, RP10
51-Ω resistor pack
0
770-101-R51
CTS
22-Ω resistor pack
4
4816P-001-220
BOURNS
Ferrite bead
6
EXC-ML32A680U
Diode
2
MBRB2515LT4
On-Semiconducter
D1, D2
SMA connectors
8
713-4339 (901-144-8RFX)
Allied
J2-J6, J11, J18, J19
Red test point
1
5010K
Keystone
TP6
Black test point
4
5011K
Keystone
TP2-TP5
3POS_header
3
TSW-150-07-L-S
Samtec
W1-W3
30-pin header
1
TSW-120-07-L-T
Samtec
J15
34-pin header
2
TSW-117-01-S-DV-LC
Samtec
J13, J14
Red banana jacks
2
ST-351A
Allied
J7, J8
Black banana jacks
2
ST-351B
Allied
J9, J10
DAC5687
1
DAC5687IPZP
TI
U1
CDCV304
1
CDCV304PW
TI
U5
SN74HC241
1
SN74HC241DW
TI
U4
SN74HCT14
2
SN74HCT14PWR
TI
U2, U3
Transformer
2
T4-1-KK8
Mini-circuits
T1, T2
Transformer
2
TCM4-1W
Mini-circuits
T3, T4
Transformer
1
T1-6T-KK81
Mini-circuits
T5
DB25F-RA
1
745536-2
AMP
J1
Switch
1
EVQ-PJX04M
Panasonic
S1
R15
R18
R17
R21, R22, R41
RP5, RP6, RP9, RP10
RP1-RP4
FERRITE BEADS, CONNECTORS, JUMPERS, JACKS, ICs, etc.
FB1-FB6
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25
Circuit Description
4
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Circuit Description
This chapter describes the circuit functions of the DAC5687 EVM.
4.1
Input Clocks
The initial configuration of this EVM provides transformer-coupled differential clocks from single-ended
input sources. With the EVM configured for PLL clock mode, a 1-VPP, 0-V offset, 50% duty cycle external
square wave is applied to SMA connector J3 to be used as the data input rate clock. The signal is
converted to a differential clock by transformer T3 and provides the CLK1 and CLK1C inputs to the
DAC5687 device. This input represents a 50-Ω load to the source. In order to preserve the specified
performance of the DAC5687 converter, the clock source should feature very low jitter. Using a clock with
a 50% duty cycle gives optimum dynamic performance.
With the EVM configured for external clock mode, a 1-VPP, 0-V offset, 50% duty cycle external square
wave is applied to SMA connector J4 to be used as the DAC sample clock. The signal is converted to a
differential clock by transformer T4 and provides the CLK2 and CLK2C inputs to the DAC5687 device.
This input represents a 50-Ω load to the source. In order to preserve the specified performance of the
DAC5687 converter, the clock source should feature low jitter. Using a clock with a 50% duty cycle gives
optimum dynamic performance.
4.2
Input Data
The DAC5687 EVM can accept 1.8-V or 3.3-V CMOS logic level data inputs through the 34-pin headers
J13 and J14 per Table 2 and Table 3. The board provides options for 50-Ω termination to ground and
series dampening resistors to minimize digital ringing and switching noise. Jumper W2 determines which
voltage level is to be used for the logic inputs.
Table 2. Input Connector J13 (Data A Bus)
Pin
26
Description
Pin
Description
1
CMOS data bit 15 (MSB)
18
GND
2
GND
19
CMOS data bit 6
3
CMOS data bit 14
20
GND
4
GND
21
CMOS data bit 5
5
CMOS data bit 13
22
GND
6
GND
23
CMOS data bit 4
7
CMOS data bit 12
24
GND
8
GND
25
CMOS data bit 3
9
CMOS data bit 11
26
GND
10
GND
27
CMOS data bit 2
11
CMOS data bit 10
28
GND
12
GND
29
CMOS data bit 1
13
CMOS data bit 9
30
GND
14
GND
31
CMOS data bit 0 (LSB)
15
CMOS data bit 8
32
GND
16
GND
33
17
CMOS data bit 7
34
DAC5687 EVM
GND
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Table 3. Input Connector J14 (Data B Bus)
Pin
4.3
Description
Pin
Description
1
CMOS data bit 0 (LSB)
18
GND
2
GND
19
CMOS data bit 9
3
CMOS data bit 1
20
GND
4
GND
21
CMOS data bit 10
5
CMOS data bit 2
22
GND
6
GND
23
CMOS data bit 11
7
CMOS data bit 3
24
GND
8
GND
25
CMOS data bit 12
9
CMOS data bit 4
26
GND
10
GND
27
CMOS data bit 13
11
CMOS data bit 5
28
GND
12
GND
29
CMOS data bit 14
13
CMOS data bit 6
30
GND
14
GND
31
CMOS data bit 15 (MSB)
15
CMOS data bit 7
32
GND
16
GND
33
17
CMOS data bit 8
34
GND
Output Data
The DAC5687 EVM can be configured to drive a doubly terminated 50-Ω cable or provide unbuffered
differential outputs.
4.3.1
Transformer-Coupled Signal Output
The factory-set configuration of the demonstration board provides the user with single-ended output
signals at SMA connectors J5 and J19. The DAC5687 outputs are configured to drive a doubly terminated
50-Ω cable using a 4:1 impedance ratio transformer with the center tap of the transformers connected to
+3.3 VA as shown in Table 4. When using a 1:1 impedance ratio transformer, configure the EVM as
shown in Table 4. The common mode input voltage of T1 and T2 can be adjusted by using the resistor
divider networks. With the board configured to use transformer T5 per Table 4, the DAC outputs will be
summed together and provide 40-mA full-scale output power at SMA connector J11.
Table 4. Transformer Output Configuration
Components Installed
1:1 Impedance ratio
transformer
R5 (49.9), R10 (49.9), R19 (49.9), R20 (49.9), R21, R22,
R23, R26, C60, C61, T1(1:1), T2 (1:1)
R6-R9, R24, R27-R33
4:1 Impedance ratio
transformer
R5, R10, R19, R20, R23, R26, C60, C61, T1(4:1), T2 (4:1)
R6-R9, R21, R22, R24, R27-R33
Combined Output through
1:1 Impedance ratio
Transformer
R6-R9, R42, C40, T5
R5, R10, R19-R22, R27-R33, R41,
T1, T2
(1)
4.3.2
(1)
Configuration
Components Not Installed
All component values are per the schematic except where shown in parenthesis.
Unbuffered Differential Output
To provide unbuffered differential outputs, the EVM must be configured as follows: remove R6-R9, R21,
R22, T1, and T2; install R5 (24.9), R10 (24.9), R19 (24.9), R20 (24.9), R24, R27-R30, and R32. With a 20
mA full-scale output current, this configuration will provide a 0.5 Vpp output.
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DAC5687 EVM
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Circuit Description
4.3.3
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PLL Lock
With the internal PLL enabled (W3 installed between pins 1 and 2), when the PLL is locked to the CLK1
input, PLLOCK OUT (J2) is driven high. With the internal PLL disabled, the PLLLOCK OUT is an output
clock that can be used by external devices to clock the input data to the DAC5687. This signal is the
CLK2 signal divided down by the interpolation rate and phase-aligned to allow the user to clock data into
the DAC5687 with the required setup and hold times.
4.4
Control Inputs
The DAC5687 device has five discrete inputs to control the operation of the device.
4.4.1
Sleep Mode
The DAC5687 EVM provides a means of placing the DAC5687 device into a power-down mode. This
mode is activated by placing a jumper between pins 5 and 6 on header J15.
4.4.2
Reset
The DAC5687 EVM provides a means of resetting the DAC5687 device. Pressing switch S1 or sending
J15 pin 29 low provides an active low reset signal to the DAC5687 device.
4.4.3
Phase Synchronization
The DAC5687 EVM provides a means to phase synchronize the DAC5687 device. Placing an active high
signal on J15 pin 8 (PHSTR) resets the internal NCO accumulator register.
4.4.4
TxENABLE
TxENABLE must be high to enable the DAC5687 to process data. When low, the DAC5687 device is
forced to a constant dc output at IOUTA and IOUTB. When in the interleaved mode and MEM_QFLAG bit
is set to 0, TxENABLE syncronizes the data of channels A and B. When TxENABLE goes high, data
present at the next clock rising edge is treated as I data. The next valid data is then treated as Q data and
so on. TxENABLE is controlled by J15 pin 11.
4.4.5
QFLAG
QFLAG is an input used to indicate Q sample data during the interleaved mode when the QFLAG
interleave bit (3) is set in register #9, MEM_QFLAG. When QFLAG is high, input data is treated as Q data,
and when low, data is treated as I data. QFLAG is controlled by J15 pin 14.
4.5
Internal Reference Operation
The full-scale output current is set by applying an external resistor (R1) between the BIASJ pin of the
DAC5687 device and ground. The full-scale output current can be adjusted from 20 mA down to 2 mA by
varying R1 or changing the externally applied reference voltage. The full-scale output current, IOUTFS, is
defined as follows:
ǒ
V
IOUT
FS
+ 16
EXTIO
R1
Ǔ
where VEXTIO is the voltage at pin EXTIO. This voltage is 1.2 V typical when using the internally provided
bandgap reference voltage source.
4.6
External Reference Operation
The internal reference can be disabled and overridden by an external reference by connecting a voltage
source to EXTI/O and connecting EXTLO to +3.3VA (jumper W1 installed between pins 1 and 2). The
specified range for external reference voltages must be observed (see the DAC5687 data sheet
(SLWS164) for details).
28
DAC5687 EVM
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Schematics
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5
Schematics
This chapter contains the DAC5687 EVM schematic diagrams.
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DAC5687 EVM
29
1
2
3
4
5
6
+3.3VA
C84
C85
C86
.1uF
.1uF
.1uF
.1uF
.1uF
+3.3VA
+
1K
R4
+3.3VA
+3.3VA
1
C29
IOVDD
R1
C24
C15
10uF
1K
+1.8VD
W1
(2-3)
R5
R10
SW-PB
C16
100
100
RESET
+1.8VD
10uF
C2
.1uF
C4
.1uF
.1uF
C5
C6
.1uF
.1uF
2
100
(Note 1)
C59
C7
.1uF
+3.3VA
3
+3.3VA
TXENABLE
(Note 1)
R40
49.9
DA15
DA14
DA13
DA12
DA11
DA10
DA9
DA8
IOVDD
C39
+
C37
+
10uF
DA7
DA6
DA5
10uF
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
DVDD
DGND
QFLAG
TESTMODE
SLEEP
/RESETB
PHSTR
DGND
DB15
DB14
DB13
DVDD
DGND
DB12
DB11
DB10
DB9
DB8
DVDD
DGND
IOVDD
IOGND
DB7
DB6
DB5
U1
DAC5687
C17
C12
.1uF
QFLAG
(Note 1)
QFLAG
SLEEP
PHSTR
DB15
DB14
DB13
R12
49.9
R39
49.9
DA4
DA3
DA2
DA1
DA0
B
(SH 2)
SLEEP
(SH 2)
PHSTR
(SH 2)
R42
IOVDD
R6
0
.1uF
R8
0
.1uF
+3.3VA
R30
0
3
100
(SH 2)
+3.3VA
U5
CDCV304
CLK1
221
(Note 1)
(SH 3)
(SH 3)
CLK1C
(SH 3)
CLK1
(SH 3)
6
2
4
R31
0
(Note 1)
TP6
CLKIN
1Y0
VDD/3.3V
1Y1
OE
1Y2
GND
1Y3
3
5
7
8
R2
C60
.1uF
R32
22.1
R38
C25
.1uF
SMA
0
+
ti
C26
Title:
10uF
Engineer:
J.SETON
Drawn By:
Y. DEWONCK
FILE:
3
A
12500 TI Boulevard. Dallas, Texas 75243
NOTE 1. DO NOT INSTALL
2
SMA
J2
1
+3.3VA
1
J6
1
0
(Note 1)
2
3
4
5
CLK1C
CLK2
6
R18
110
(Note 1)
93.1
1
CLK2
B
J19
SMA
1
T4-1-KK81
330pF
CLK2C
IOUTB
2
1
R17
CLK2C
4
(Note 1)
.01uF
.1uF
T2
R22
C33
C41
10uF
(Note 1)
R27
100
100
C13
+
0
(Note 1)
0
R20
.033uF
+3.3VCLK
6
T1-6T-KK81
(Note 1)
C18
C34
C14
J11
SMA
1
2
1
R19
10pF
4
R41
100
C40
DA(0..15)
+3.3VPLL
T5
3
R26
C3
C
0
R13
DB(0..15)
A
0
(Note 1)
+3.3VA
R25
SMA
(Note 1)
DB7
DB6
DB5
22.1
J18
+3.3VA
(Note 1)
R16
10
0
49.9
DB12
DB11
DB10
DB9
DB8
.1uF
(SH 2)
DB4
DB3
DB2
DB1
DB0
R43
R7
1
0
(Note 1)
2
3
4
5
R9
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
.1uF
C11
.1uF
R28
C61
2
3
4
5
TXENABLE
DVDD
DGND
SDENB
SCLK
SDIO
SDO
DVDD
TXENABLE
DA15
DA14
DA13
DVDD
DGND
DA12
DA11
DA10
DA9
DA8
DVDD
DGND
IOVDD
IOGND
DA7
DA6
DA5
C10
.1uF
R33
0
(Note 1)
2
3
4
5
(SH 2)
SDENB
SCLK
SDIO
SDO
AGND
AVDD
AVDD
AGND
IOUTA1
IOUTA2
AGND
AVDD
AGND
AVDD
EXTLO
AVDD
BIASJ
AGND
EXTIO
AVDD
AGND
AVDD
AGND
IOUTB2
IOUTB1
AGND
AVDD
AVDD
AGND
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C9
.1uF
DA4
DA3
DA2
DA1
DA0
DVDD
DGND
CLKGND
CLK1
CLK1C
CLKVDD
CLK2
CLK2C
CLKGND
PLLGND
LPF
PLLVDD
DVDD
DGND
PLLLOCK
DB0
DB1
DB2
DB3
DB4
(SH 4)
(SH 4)
(SH 4)
(SH 4)
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
4
T4-1-KK81
.1uF
SDENB
SCLK
SDIO
SDO
SMA
2
3
4
5
C1
J5
1
2
3
4
5
+1.8VD
+
6
D
IOUTA
(Sh 2)
R21
C38
T1
1
RESET
R24
0
(Note 1)
0
.1uF
.1uF
C
0
(Note 1)
R23
C8
3
D
R29
S1
2
4
5
DAC5687
DOCUMENTCONTROL #
DATE:
14-Jul-2005
REV:
SIZE:
6
SHEET:
1
OF:
B
5
1
2
3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
5
6
RP1
22
DATA PORT 1
J13
4
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DA15
DA14
DA13
DA12
DA11
DA10
DA9
DA8
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
D
IOVDD
RP2
34PIN_IDC
DA(0..15)
(SH 1)
10
9
8
7
6
5
4
3
2
22
J15
1
3
RP5
4
6
51
7
9
10
12
13
15
16
18
19
21
22
24
25
27
28
30
10
9
8
7
6
5
4
3
2
1
(Note 1)
C
RP6
51
2
5
(Note 1)
1
8
11
14
C
SLEEP
SLEEP
PHSTR
TXENABLE
QFLAG
PHSTR
TXENABLE
QFLAG
(SH 1)
(SH 1)
(SH 1)
(SH 1)
17
20
DATA PORT 2
J14
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
B
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
23
RP4
22
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
26
RESET
29
(SH 1, 5)
RESET
3 ROW 30 PIN CONNECTOR
B
34PIN_IDC
DB(0..15)
(SH 1)
10
9
8
7
6
5
4
3
2
RP3
22
RP9
51
10
9
8
7
6
5
4
3
2
1
(Note 1)
ti
RP10
A
51
(Note 1)
1
12500 TI Boulevard. Dallas, Texas 75243
Title:
NOTE 1. DO NOT INSTALL
Engineer:
J. SETON
Drawn By:
Y. DEWONCK
FILE:
1
2
A
3
4
5
DAC5687
DOCUMENTCONTROL #
DATE:
14-Jul-2005
REV:
SIZE:
6
SHEET:
2
OF:
B
5
1
2
3
4
5
6
D
D
J3
SMA
C19
1
CLK1
4
T3
CLK1
3
.01uF
CLK1
(SH 1)
CLK1C
(SH 1)
R11
5
4
3
2
2
200
6
CLK1C
1
TCM4-1W
C
C
J4
SMA
B
1
CLK2
B
T4
C20
6
CLK2
1
.01uF
CLK2
(SH 1)
CLK2C
(SH 1)
R14
5
4
3
2
2
200
4
CLK2C
3
TCM4-1W
ti
A
A
12500 TI Boulevard. Dallas, Texas 75243
Title:
NOTES:
1. PART NOT INSTALLED
Engineer:
J. SETON
Drawn By:
Y. DEWONCK
FILE:
1
2
3
4
5
DAC5687
DOCUMENTCONTROL #
DATE:
14-Jul-2005
REV:
SIZE:
6
SHEET:
3
OF:
B
5
1
2
3
4
5
6
D
D
+3.3V_SER
+3.3V_SER
C21
+3.3V_SER
.1uF
C22
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SDEN
SCLK
SDIO
OE_
C
.1uF
U2
SN74HCT14
J1
DB25F-RA
VCC
R34
10K
1
R35
10K
3
R36
10K
5
R37
10K
9
11
13
7
1A
2A
C23
1Y
2Y
3A
3Y
4A
4Y
5A
5Y
6A
6Y
.1uF
U3
SN74HCT14
14
U4
SN74HC241
VCC
2
1
4
3
6
5
8
9
10
11
12
13
7
GND
1A
2A
1Y
2Y
3A
3Y
4A
4Y
5A
5Y
6A
6Y
14
1
2
2
4
4
6
6
8
8
10
11
12
13
15
GND
17
10
OE1_
VCC
1A1
OE2
1A2
1Y1
1A3
1Y2
1A4
1Y3
2A1
1Y4
2A2
2Y1
2A3
2Y2
2A4
2Y3
GND
2Y4
20
19
18
SDIO
16
SCLK
14
SDENB
(Sh 1)
SCLK
(Sh 1)
SDENB
(Sh 1)
C
12
9
7
5
3
(Note 1)
R15
10
R3
SDIO
SDO
SDO
(Sh 1)
10
B
B
ti
A
A
12500 TI Boulevard. Dallas, Texas 75243
Title:
NOTE 1. DO NOT INSTALL
Engineer:
J. SETON
Drawn By:
Y. DEWONCK
FILE:
1
2
3
4
5
DAC5687
DOCUMENTCONTROL #
DATE:
14-Jul-2005
REV:
SIZE:
6
SHEET:
4
OF:
B
5
1
2
3
4
5
6
+3.3VA
VA
J7
D1
MBRB2515L
+ C27
C36
C47
10uF
1uF
0.01uF
+
FB2
D
+1.8VD
C53
3
RED
W2
2
(1-2)
4
D
FB1
VA
IOVDD
1
+3.3VA
+ C28
C42
C48
10uF
1uF
0.01uF
47 uF
+
C54
47 uF
3
1
J9
BLACK
VD
VA
FB4
FB3
4
VD
RED
D2
MBRB2515L
C
+3.3V_SER
+1.8VD
J8
+ C30
10uF
C43
C49
1uF
0.01uF
+
C55
+ C31
C44
C50
10uF
1uF
0.01uF
47 uF
+
C56
47 uF
C
3
1
J10
BLACK
+3.3VA
1
+3.3VPLL
W3
2
3
(2-3)
FB5
+ C32
C45
C51
10uF
1uF
0.01uF
VA
+
C57
47 uF
+3.3VCLK
FB6
B
TP2
BLACK
A
TP3
BLACK
TP4
BLACK
B
+ C35
C46
C52
10uF
1uF
0.01uF
+
C58
47 uF
ti
TP5
BLACK
A
12500 TI Boulevard. Dallas, Texas 75243
Title:
NOTES:
1. PART NOT INSTALLED
Engineer:
Drawn By:
FILE:
1
2
3
4
5
J. SETON
Y. DEWONCK
DAC5687
DOCUMENTCONTROL #
DATE:
14-Jul-2005
SIZE:
6
SHEET:
5
REV:
B
OF:
5
Revision A History
www.ti.com
Revision A History
Changes from Original (April 2005) to A Revision .......................................................................................................... Page
•
•
•
•
•
•
Hardware Configuration Step 3: Changed input clock level from 300 mVpp to 1 Vpp. ......................................... 5
Changed Figure 1 - Updated to reflect new version of DAC5687 SPI software (V2.3). ........................................ 9
Changed Figure 2 - Updated to reflect new version of DAC5687 SPI software (V2.3). ....................................... 10
Changed Figure 3 - Updated to reflect new initial test setup. ..................................................................... 11
Changed Figure 4 - Updated to reflect new version of DAC5687 SPI software (V2.3). ....................................... 12
Changed the Pll Port Config: description in Section 2.4.5 ....................................................................... 20
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Revision B History
Changes from A Revision (August 2005) to B Revision ................................................................................................ Page
•
Changed Section 2 - DAC5687 EVM Operational Procedure. Added steps to prepare the DAC5687 EVM for operation.
6
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Revision C History
Changes from B Revision (March 2007) to C Revision .................................................................................................. Page
•
•
•
•
•
•
•
•
•
•
Hardware Configuration Step 4: Added text "Another solution is to use the TSW1400 pattern generator .." ................ 5
Hardware Configuration Step 5: Added text "The user can also use the provided USB to SPI adapter .." .................. 5
Added text to Section 2.1 - "If you are using the USB interface card, change mode to USB in the upper right corner
window." ................................................................................................................................... 9
Changed Figure 1 ........................................................................................................................ 9
Changed Figure 2 ....................................................................................................................... 10
Changed Figure 3 ....................................................................................................................... 11
Changed Figure 4 ....................................................................................................................... 12
Added Section 2.3 - Basic Test Procedure with TSW1400 ....................................................................... 12
Added FDAC: to Section 2.4.4 ........................................................................................................... 20
Added NCO IF: to Section 2.4.4 ...................................................................................................... 20
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
30
Revision History
SLWU017C – APRIL 2005 – Revised August 2013
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