DAC60004IPWR

Order Now Product Folder Support & Community Tools & Software Technical Documents DAC80004, DAC70004, DAC60004 SLASED6D – APRIL 2016 – REVISED DECEMBER 2017 DACx0004, Quad 16-,14-,12-Bit, 1 LSB INL, Buffered, Voltage-Output Digital-to-Analog Converters 1 Features 3 Description • • • • • • • • • • The DAC80004/70004/60004 (DACx0004) are highly accurate, low-power, voltage-output, quad-channel, 16-, 14-, 12-bit digital-to-analog converters (DACs) respectively. The DACx0004 devices are ensured monotonic by design and offer excellent linearity of less than 1 LSB (Max). The reference input of the DAC is buffered internally using a dedicated reference buffer. 1 True 16-Bit Performance: 1 LSB INL/DNL (Max) Ultra Low Glitch Energy: 1 nV-s Wide Power-Supply Range: 2.7 V to 5.5 V Output Buffer with Rail-to-Rail Operation Current Consumption: 1 mA/Channel 50-MHz, 4- or 3-Wire SPI Compatible Interface SDO Pin for Readback and Daisy Chain Power-On Reset to Zero or Mid Scale Temperature Range: –40°C to +125°C Multiple Packages: – Tiny 14-Pin VSON – 14-Pin TSSOP 2 Applications • • • • The DACx0004 devices incorporate a power-on-reset circuit that ensures the DAC output powers up at zero scale or mid scale depending on status of the POR pin and remains in this state until a valid code is written to the device. These devices consume very low current of 1 mA/channel making them ideal for portable, battery-operated equipment. These devices also contain a power-down feature that reduces current consumption to typically 3 µA at 5 V. The DACx0004 devices use a versatile 4- or 3-wire serial interface that operates at clock rates up to 50 MHz. The DACx0004 devices also include a SDO pin to daisy chain multiple devices. The interface is compatible with standard SPI™, QSPI™, Microwire, and digital signal processor (DSP) interfaces. The DACx0004 devices are offered in easy-to-assemble 14-pin TSSOP packages or an ultra small 14-pin VSON package and are fully specified over the extended industrial temperature range of –40°C to 125°C. Portable Instrumentation PLC Analog Output Module (4-20 mA) Closed-Loop Servo Control Data Acquisition Systems Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) DACx0004 VSON (14) 3.00 mm x 4.00 mm DACx0004 TSSOP (14) 5.00 mm x 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. DACx0004 Block Diagram VDD Linearity Error vs Digital Input Code 1.00 REFIN 0.75 DAC Buffer DAC Register DAC 0.50 BUF VOUTA Channel A VOUTB VOUTC VOUTD Channel B Channel C Channel D INL Error (LSB) SCLK SDIN SYNC SDO CLR LDAC POR Interface Logic REF BUF 0.25 0.00 -0.25 -0.50 Channel A Channel B Channel C Channel D -0.75 Power Down Logic Power On Reset Resistive Network DACx0004 -1.00 0 GND 8192 16384 24576 32768 40960 49152 57344 65536 Digital Input Code D001 Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC80004, DAC70004, DAC60004 SLASED6D – APRIL 2016 – REVISED DECEMBER 2017 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Device Comparison Table..................................... Pin Configuration and Functions ......................... Specifications......................................................... 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 1 1 1 2 3 3 4 Absolute Maximum Ratings ...................................... 4 ESD Ratings ............................................................ 4 Recommended Operating Conditions....................... 4 Thermal Information .................................................. 4 Electrical Characteristics........................................... 5 DACx0004 Timing Requirements ............................. 8 Typical Characteristics ............................................ 10 Detailed Description ............................................ 18 8.1 Overview ................................................................. 18 8.2 Functional Block Diagram ....................................... 18 8.3 Feature Description................................................. 19 8.4 Device Functional Modes........................................ 20 9 Application and Implementation ........................ 26 9.1 Application Information............................................ 26 9.2 Typical Application - Digitally Controlled Asymmetric Bipolar Output .......................................................... 26 10 Power Supply Recommendations ..................... 28 11 Layout................................................................... 29 11.1 Layout Guidelines ................................................. 29 11.2 Layout Example .................................................... 29 12 Device and Documentation Support ................. 30 12.1 12.2 12.3 12.4 12.5 12.6 Receiving Notification of Documentation Updates Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 30 30 30 30 30 30 13 Mechanical, Packaging, and Orderable Information ........................................................... 31 4 Revision History Changes from Revision C (August 2016) to Revision D Page • Changed 2.4 µs From MAX to MIN value for t20 in the DACx0004 Timing Requirements table............................................ 8 • Changed From: t19 To: t20 in Figure 1 .................................................................................................................................... 8 Changes from Revision B (June 2016) to Revision C • Page Deleted thermal pad from PW-TSSOP pin configuration ....................................................................................................... 3 Changes from Revision A (June 2016) to Revision B • Page Added DAC80004IPW Device Marking Addendum to Mechanical, Packaging, and Orderable Information ...................... 31 Changes from Original (April 2016) to Revision A • 2 Page Changed from Product Preview to Production Data .............................................................................................................. 1 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6D – APRIL 2016 – REVISED DECEMBER 2017 5 Device Comparison Table DEVICE RESOLUTION DAC80004 16 DAC70004 14 DAC60004 12 6 Pin Configuration and Functions 14-Pin VSON DMD Package Top View 14-Pin TSSOP PW Package Top View LDAC 1 14 SCLK SYNC 2 13 SDIN VDD 3 12 GND VOUTA 4 11 VOUTB VOUTC 5 10 VOUTD POR 6 9 CLR REFIN 7 8 SDO Thermal Pad LDAC 1 14 SCLK SYNC 2 13 SDIN VDD 3 12 GND VOUTA 4 11 VOUTB VOUTC 5 10 VOUTD POR 6 9 CLR REFIN 7 8 SDO Not to scale Pin Functions PIN NAME NUMBER I/O DESCRIPTION CLR 9 Digital Input GND 12 Power Clear DAC pin, falling edge sensitive LDAC 1 Digital Input Load DAC pin, active low POR 6 Digital Input Power-on-reset configuration, Connecting the POR pin to GND powers up all four DACs to zero scale. Connecting this pin to VDD powers up all four DACs to midscale. REFIN 7 Analog Input Voltage reference input for all channels SCLK 14 Digital Input Serial interface shift clock SDIN 13 Digital Input Serial interface digital input SDO 8 Digital Output SYNC 2 Digital Input VDD 3 Power VOUTA 4 Analog Output DAC A output VOUTB 11 Analog Output DAC B output VOUTC 5 Analog Output DAC C output VOUTD 10 Analog Output DAC D output Ground Serial interface digital output for readback and daisy chaining Serial interface synchronization, active low Positive power supply (2.7 V to 5.5 V) Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 3 DAC80004, DAC70004, DAC60004 SLASED6D – APRIL 2016 – REVISED DECEMBER 2017 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Voltage, VDD to GND –0.3 7 V Voltage, digital input or output to GND –0.3 VDD + 0.3 V Voltage, analog input (REFIN) or output (VOUTx) to GND –0.3 VDD + 0.3 V Input current to any pin except supply pins –10 10 mA 150 °C 150 °C Maximum junction temperature Storage temperature range, Tstg (1) -60 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±1000 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN Voltage, VDD to GND Voltage, analog input (REFIN) or output (VOUTx) to GND NOM MAX UNIT 2.7 5.5 V 2.7 V ≤ VDD ≤ 4.5 V 2.2 VDD – 0.2 V 4.5 V ≤ VDD ≤ 5.5 V 2.2 VDD V -40 125 °C Ambient Operating Temperature, TA 7.4 Thermal Information DACx0004 THERMAL METRIC (1) DMD (VSON) PW (TSSOP) 14 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal resistance 39.6 99.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 27.3 23.4 °C/W RθJB Junction-to-board thermal resistance 9.0 42.8 °C/W ψJT Junction-to-top characterization parameter 0.3 0.9 °C/W ψJB Junction-to-board characterization parameter 8.9 42.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 6.5 N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 DAC80004, DAC70004, DAC60004 www.ti.com SLASED6D – APRIL 2016 – REVISED DECEMBER 2017 7.5 Electrical Characteristics All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN (1) ≤ VDD, Rload = 5 kΩ to GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE (2) Resolution DAC80004 16 DAC70004 14 DAC60004 12 Bits Relative accuracy (3) INL DNL Differential nonlinearity (3) TUE Total unadjusted error (3) ZCE Zero code error ZCE-TC ±1 LSB Ensured monotonic ±1 LSB TA = +20°C to +40°C 1.5 TA = –40°C to +125°C Zero code error TC TA = –40°C to +125°C, Code 0d into DAC ±0.2 TA = +25°C, Code 0d into DAC ±0.1 TA = –40°C to +125°C Offset error (3) OE-TC Offset error drift ±0.2 TA = +25°C ±0.2 Full-scale error (4) µV/°C ±1.8 ±4 TA = +20°C to +40°C, Code 65535d into DAC FSE mV ±1.2 TA = –40°C to +125°C TA = –40°C to +125°C ±2 ±5 TA = +20°C to +40°C OE mV 2 µV/°C ±0.05 TA = –40°C to +125°C, Code 65535d into DAC ±0.01 TA = +25°C ±0.01 TA = –40°C to +125°C ±2 TA = –40°C to +125°C ±0.005 TA = +25°C ±0.005 mV ±0.07 %FSR %FSR ppm FSR/°C FSE-TC Full-scale error drift (4) GE Gain error (3) GE-TC Gain drift TA = –40°C to +125°C ±2 ppm FSR/°C Output voltage drift vs.Time TA = +25°C, Vout = ¾ of full scale, 1900 hr 20 ppm FSR Load Regulation TA = +25°C, Vout =Mid Scale 0.003% DC Power supply rejection ratio (4) TA = +25°C, Vout = full scale –92 PSRR (1) (2) (3) (4) ±0.05 %FSR dB 200 mV headroom is required between REFIN and VDD when 2.7 V ≤ VDD ≤ 4.5 V. Output unloaded End point fit between codes Code 512 to Code 65,024 - DAC80004, Code 128 to Code 16,256 - DAC70004, Code 32 to Code 4064 DAC60004, Output unloaded. With 100 mV headroom between DAC output and VDD. Copyright © 2016–2017, Texas Instruments Incorporated Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback 5 DAC80004, DAC70004, DAC60004 SLASED6D – APRIL 2016 – REVISED DECEMBER 2017 www.ti.com Electrical Characteristics (continued) All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN(1) ≤ VDD, Rload = 5 kΩ to GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V PARAMETER TEST CONDITIONS MIN TYP MAX 5.8 8 UNIT DYNAMIC PERFORMANCE ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ, Cload = 200 pF to GND Output voltage settling time Slew rate Power-up time 1.5 (5) µs V/µs 100 µs Power-on glitch energy Supply slew rate