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DAC80502, DAC70502, DAC60502
SBAS793A – NOVEMBER 2019 – REVISED APRIL 2020
DACx0502, Dual, 16-Bit, 14-Bit, and 12-Bit, 1-LSB INL, Voltage-Output DACs
With Precision Internal Reference
1 Features
3 Description
•
•
•
•
•
•
The 16-bit DAC80502, 14-bit DAC70502, and 12-bit
DAC60502 (DACx0502) digital-to-analog converters
(DACs) are highly accurate, low-power devices with
voltage output.
1
•
•
•
•
•
16-bit performance: 1-LSB INL and DNL (max)
Low glitch energy: 4 nV-s
Wide power supply: 2.7 V to 5.5 V
Buffered output range: 5 V, 2.5 V, or 1.25 V
Low power: 1 mA per channel at 5.5 V
Integrated 5-ppm/˚C (max), 2.5-V precision
reference
Pin-selectable serial interface
– 3-wire, SPI compatible up to 50-MHz
– 2-wire, I2C compatible
Power-on-reset: zero scale or midscale
1.62-V VIH with VDD = 5.5 V
Temperature range: –40˚C to +125˚C
Package: Tiny 10-pin WSON
The DACx0502 offer linearity of < 1 LSB. The high
accuracy combined with tiny package make the
DACx0502 an excellent choice for applications such
as gain and offset calibration, current or voltage set
point generation, and power-supply control. These
devices include a 2.5-V, 5-ppm/°C internal reference,
giving full-scale output voltage ranges of 1.25 V,
2.5 V, or 5 V. The DACx0502 incorporate a poweron-reset circuit that makes sure the DAC output
powers up at zero scale or midscale based on the
status of RSTSEL pin, and remains at that scale until
a valid code is written to the device.
The digital interface of the DACx0502 can be
configured to SPI or I2C mode using the SPI2C pin.
In SPI mode, the DACx0502 use a versatile 3-wire
serial interface that operates at clock rates up to 50
MHz. In I2C mode, the DACx0502 operate in
standard (100 kbps), fast (400 kbps), and fast+ (1.0
Mbps) modes.
2 Applications
•
•
•
•
•
•
•
•
•
Oscilloscope (DSO)
Battery test
Semiconductor test
Data acquisition (DAQ)
LCD test
Small cell base station
Analog output module
Process analytics (pH, gas, concentration, force
and humidity)
DC power supply, ac source, electronic load
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
DAC80502
DAC70502
WSON (10)
2.50 mm × 2.50 mm
DAC60502
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Functional Block Diagram
VREFIO
VDD
Internal
Reference
SCLK or SCL
SDIN or SDA
SYNC or A0
Interface Logic
SPI2C
DAC
Buffer
DAC
Register
DAC
BUF
VOUTA
Channel A
VOUTB
Channel B
RSTSEL
Power On Reset
Power Down Logic
Resistive Network
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC80502, DAC70502, DAC60502
SBAS793A – NOVEMBER 2019 – REVISED APRIL 2020
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Timing Requirements : SPI Mode ............................. 9
Timing Requirements : I2C Standard Mode .............. 9
Timing Requirements : I2C Fast Mode...................... 9
Timing Requirements : I2C Fast-Mode Plus ........... 10
Typical Characteristics .......................................... 11
Detailed Description ............................................ 20
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
20
20
20
22
8.5 Programming........................................................... 23
8.6 Register Maps ......................................................... 29
9
Application and Implementation ........................ 34
9.1
9.2
9.3
9.4
9.5
Application Information............................................
Typical Application ..................................................
System Examples ..................................................
What To Do and What Not To Do...........................
Initialization Setup ...................................................
34
34
36
37
37
10 Power Supply Recommendations ..................... 38
11 Layout................................................................... 38
11.1 Layout Guidelines ................................................. 38
11.2 Layout Example .................................................... 38
12 Device and Documentation Support ................. 39
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Support Resources ...............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
39
39
39
39
39
39
39
13 Mechanical, Packaging, and Orderable
Information ........................................................... 39
4 Revision History
Changes from Original (November 2019) to Revision A
•
2
Page
Changed devices from advanced information (preview) to production data (active) ............................................................. 1
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Copyright © 2019–2020, Texas Instruments Incorporated
Product Folder Links: DAC80502 DAC70502 DAC60502
DAC80502, DAC70502, DAC60502
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SBAS793A – NOVEMBER 2019 – REVISED APRIL 2020
5 Device Comparison Table
DEVICE
RESOLUTION
REFERENCE
DAC80502
16-bit
Internal (default) or external
DAC70502
14-bit
Internal (default) or external
DAC60502
12-bit
Internal (default) or external
6 Pin Configuration and Functions
DRX Package
10-Pin WSON
Top View
VDD
1
10
VREFIO
VOUTA
2
9
VOUTB
RSTSEL
3
8
SDIN/SDA
AGND
4
7
SYNC/A0
SPI2C
5
6
SCLK/SCL
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
AGND
4
Ground
RSTSEL
3
Input
Reset select pin.
DACs power up to zero scale if RSTSEL = AGND.
DACs power up to midscale if RSTSEL = VDD
SCLK/SCL
6
Input
Serial interface clock. SPI or I2C mode.
SDIN/SDA
8
Input/Output
SPI2C
5
Input
Interface select pin. The SPI2C pin must be kept static after device powers up.
If SPI2C = 0, the digital interface is in SPI mode
If SPI2C = 1, the digital interface is in I2C mode
SYNC/A0
7
Input
SPI mode: Active low serial data enable. This input is the frame-synchronization signal for the
serial data. When the signal goes low, the serial interface input shift register is enabled.
I2C mode: Four-state address input.
VDD
1
Power
Analog supply voltage (2.7 V to 5.5 V)
VOUTA
2
Output
Analog output voltage from DAC A
VOUTB
9
Output
Analog output voltage from DAC B
VREFIO
10
Input/Output
Ground reference point for all circuitry on the device
SPI mode: Serial interface data input. Data are clocked into the input shift register on each falling
edge of the SCLK pin.
I2C mode: Data are clocked into or out of the input register. This pin is a bidirectional, SDA drain
data line that must be connected to the supply voltage with an external pull-up resistor.
When using the internal reference, this pin is the reference output voltage pin (default).
When operating with an external reference, this pin is the reference input to the device.
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SBAS793A – NOVEMBER 2019 – REVISED APRIL 2020
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
VDD to AGND
–0.3
6
VREFIO to AGND
–0.3
VDD + 0.3
Digital input(s) to AGND
–0.3
VDD + 0.3
Output voltage
VOUTx to AGND
–0.3
VDD + 0.3
Input current
Current into any pin
–10
10
Junction temperature (TJ)
–40
150
Storage temperature (Tstg)
–65
150
Input voltage
Temperature
(1)
UNIT
V
V
mA
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS001, all pins (1)
±2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
VDD to AGND
Positive supply voltage to ground
2.7
5.5
V
DIGITAL INPUTS
VIH
Input high voltage
VIL
Input low voltage
1.62
V
0.45
V
REFERENCE INPUT
VREFIO to AGND
2.7 V ≤ VDD < 3.3 V,
reference divider disabled (REF-DIV bit = 0)
1.2
0.5 × (VDD – 0.2)
V
VREFIO to AGND
2.7 V ≤ VDD < 3.3 V,
reference divider enabled (REF-DIV bit = 1)
2.4
(VDD – 0.2)
V
VREFIO to AGND
3.3 V ≤ VDD ≤ 5.5 V,
reference divider disabled (REF-DIV bit = 0)
1.2
0.5 × VDD
V
VREFIO to AGND
3.3 V ≤ VDD ≤ 5.5 V,
reference divider enabled (REF-DIV bit = 1)
2.4
VDD
V
Operating temperature
–40
125
°C
TEMPERATURE
TA
4
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SBAS793A – NOVEMBER 2019 – REVISED APRIL 2020
7.4 Thermal Information
DACx0502
THERMAL METRIC (1)
DRX (WSON)
UNIT
10 PINS
RθJA
Junction-to-ambient thermal resistance
99.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
49.9
°C/W
RθJB
Junction-to-board thermal resistance
35.9
°C/W
ΨJT
Junction-to-top characterization parameter
1.7
°C/W
ΨJB
Junction-to-board characterization parameter
35.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external
or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
Resolution
DAC80502
16
DAC70502
14
DAC60502
12
Bits
INL
Integral nonlinearity (1)
–1
1
DNL
Differential nonlinearity (1)
–1
1
TUE
Total unadjusted error (1)
Zero code error (1)
DAC loaded with zero scale code
0.04
0.1
%FSR
–1.5
0.5
1.5
mV
±2
–1.5
Offset error temperature
coefficient (1)
–0.1
Gain error temperature
coefficient (1)
1.5
0.04
–0.1
Full-scale error temperature
coefficient (1)
0.04
±2
mV
µV/°C
0.1
%FSR
ppm
FSR/°C
±1
Full-scale error (1)
(1)
0.5
µV/°C
±2
Gain error (1)
LSB
–0.1
Zero code error temperature
coefficient (1)
Offset error (1)
LSB
0.1
%FSR
ppm
FSR/°C
End point fit between code 256 to code 64,511 for 16-bit, code 64 to code 16,127 for 14-bit, code 16 to code 4031 for 12-bit, DAC
output unloaded, performance under resistive and capacitive load conditions are specified by design and characterization, DAC output
range ≥ 2.5 V.
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SBAS793A – NOVEMBER 2019 – REVISED APRIL 2020
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Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external
or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT CHARACTERISTICS
VO
Output voltage
BUFF-GAIN bit set to 1, REF-DIV bit set to 0
0
2×
VREFIO
BUFF-GAIN bit set to 1, REF-DIV bit set to 1
0
VREFIO
0
0.5 ×
VREFIO
BUFF-GAIN bit set to 0, REF-DIV bit set to 1
RLOAD
Resistive load (2)
CLOAD
Capacitive load (2)
ZO
VDD = 2.7 V
0.25
VDD = 5.5 V
0.5
kΩ
RLOAD = infinite
2
RLOAD = 2 kΩ
10
Load regulation
DAC at midscale, –10 mA ≤ IOUT ≤ 10 mA
80
Short circuit current
Full scale output shorted to AGND (per
channel)
30
Zero output shorted to VDD (per channel)
30
Output voltage headroom
to VDD, DAC at full code, IOUT = 10 mA
(sourcing)
0.3
Output voltage footroom
to AGND, DAC at zero code, IOUT = 10 mA
(sinking)
0.3
DC small signal output impedance DAC at code 256
10
Output voltage drift vs time
mA
V
V
0.1
Power supply rejection ratio (DC)
nF
µV/mA
0.1
DAC at midscale
DAC at code 65279
V
Ω
10
DAC at midscale; VDD = 5 V ± 10%
0.15
TA = 35°C, VOUT = midscale, 1900 hr
mV/V
20
ppm of
FSR
100
kΩ
5
pF
VOLTAGE REFERENCE INPUT
ZVREFIO
Reference input impedance
(VREFIO)
CVREFIO
Reference input capacitance
(VREFIO)
VOLTAGE REFERENCE OUTPUT
Output (initial accuracy)
Output drift
TA = 25°C
2.4975
5
DAC70502, DAC60502
10
Output impedance
Output noise
0.1 Hz to 10 Hz
Output noise density
Measured at 10 kHz, reference load = 10 nF
Load current
Load regulation
Sourcing and sinking
Line regulation
Output voltage drift vs time
Thermal hysteresis
(2)
6
2.5025
DAC80502
TA = 35°C, 1900 hr
1st cycle
Additional cycle
V
ppm/℃
0.1
Ω
14
µVPP
140
nV/√Hz
±5
mA
90
µV/mA
20
µV/V
20
µV
480
ppm
25
ppm
Not production tested.
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SBAS793A – NOVEMBER 2019 – REVISED APRIL 2020
Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external
or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
Output voltage settling time (3)
ts
Vn
5
10-mV settling to ±2 LSB, VDD = 5.5 V,
VREFIO = 2.5 V
3
Slew rate (3)
VDD = 5.5 V, VREFIO = 2.5 V
Power on glitch magnitude
CLOAD = 50 pF
Output noise (3)
Vn
¼ to ¾ scale and ¾ to ¼ scale settling to ±2
LSB, VDD = 5.5 V, VREFIO = 2.5 V
Output noise density
µs
2
V/µs
200
mV
0.1 Hz to 10 Hz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V
14
µVPP
100-kHz Bandwidth, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V
23
µVrms
Measured at 1 kHz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V,
gain = 2X (BUFF-GAIN bit = 1)
78
Measured at 10 kHz, DAC at midscale,
VDD = 5.5 V, external VREFIO = 2.5 V,
gain = 2X (BUFF-GAIN bit = 1)
74
Measured at 1 kHz, DAC at full scale,
VDD = 2.7 V, external VREFIO = 2.5 V,
gain = 1X (BUFF-GAIN bit = 0)
55
Measured at 10 kHz, DAC at full scale,
VDD = 2.7 V, external VREFIO = 2.5 V,
gain = 1X (BUFF-GAIN bit = 0)
50
nV/√Hz
SFDR
Spurious free dynamic range
1-kHz sinusiod at DAC output, DAC updated
at 500 kHz, include up to 7th harmonics, no
filter on DAC output
70
dB
THD
Total harmonic distortion
1-kHz sinusiod at DAC output, DAC updated
at 500 kHz, include up to 7th harmonics, no
filter on DAC output
70
dB
Power supply rejection ratio (ac)
200-mV, 50-Hz to 60-Hz sine wave on VDD,
DAC at midscale.
85
dB
Code change glitch impulse
Midcode ±1 LSB (including feedthrough)
4
nV-s
Code change glitch magnitude
Midcode ±1 LSB (including feedthrough)
gain = 1X (BUFF-GAIN bit = 0)
7.5
mV
Channel to channel ac crosstalk
Full scale swing on adjacent channel,
measured channel at midscale
4
nV-s
Channel to channel dc crosstalk
Full scale swing on adjacent channel,
measured channel at midscale
1
LSB
Digital feedthrough
At SCLK = 1 MHz, DAC output at midscale
4
nV-s
DIGITAL INPUTS
Hysteresis voltage
0.4
Input current
Pin capacitance
(3)
–5
Per pin
V
5
10
µA
pF
Output buffer in gain = 2X setting (BUFF-GAIN bit = 1).
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Electrical Characteristics (continued)
all minimum and maximum values at TA = –40°C to +125°C and all typcal values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, external
or internal VREFIO = 1.25 V to 5.5 V , RLOAD = 2 kΩ to AGND, CLOAD = 200 pF to AGND, and digital inputs at VDD or AGND
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Normal mode, internal reference enabled, all
DACs at full scale, SPI static
1.9
2.6
Normal mode, external reference = 2.5 V, all
DACs at full scale, SPI static
1.5
1.9
All DACs and Internal reference power-down
15
µA
0-V to 5-V range, midscale code
25
µA
POWER
IVDD
Current flowing into VDD
IVREFIO
Current flowing into VREFIO
8
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mA
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SBAS793A – NOVEMBER 2019 – REVISED APRIL 2020
7.6 Timing Requirements : SPI Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.15 V, VREFIO = 1.25 V to 5.5 V, and TA = –40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
50
MHz
fSCLK
SCLK frequency
tSCLKHIGH
SCLK high time
9
ns
tSCLKLOW
SCLK low time
9
ns
tSDIS
SDIN setup
5
ns
tSDIH
SDIN hold
10
ns
tSYNCS
SYNC falling edge to SCLK falling edge setup
13
ns
tSYNCH
SCLK falling edge to SYNC rising edge
10
ns
tSYNCHIGH
SYNC high time
160
ns
tSYNCIGNORE
SCLK falling edge to SYNC ignore
15
ns
tDACWAIT
Sequential DAC update wait time
1
µs
7.7 Timing Requirements : I2C Standard Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
0.1
MHz
fSCLK
SCL frequency
tBUF
Bus free time between stop and start conditions
tHDSTA
Hold time after repeated start
tSUSTA
Repeated start setup time
tSUSTO
Stop condition setup time
4
µs
tHDDAT
Data hold time
tSUDAT
Data setup time
tLOW
4.7
µs
4
µs
4.7
µs
0
ns
250
ns
SCL clock low period
4700
ns
tHIGH
SCL clock high period
4000
tR
Clock and data fall time
300
tF
Clock and data rise time
1000
tUPDATE
Sequential DAC update wait time
ns
ns
ns
1
µs
7.8 Timing Requirements : I2C Fast Mode
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C (unless otherwise noted)
MIN
NOM
MAX
UNIT
0.4
MHz
fSCLK
SCL frequency
tBUF
Bus free time between stop and start conditions
1.3
µs
tHDSTA
Hold time after repeated start
0.6
µs
tSUSTA
Repeated start setup time
0.6
µs
tSUSTO
Stop condition setup time
0.6
µs
tHDDAT
Data hold time
0
ns
tSUDAT
Data setup time
100
ns
tLOW
SCL clock low period
1300
ns
tHIGH
SCL clock high period
600
tR
Clock and data fall time
300
ns
tF
Clock and data rise time
300
ns
tUPDATE
Sequential DAC update wait time
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1
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µs
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7.9 Timing Requirements : I2C Fast-Mode Plus
all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V,
VIH = 1.62 V, VIL = 0.45 V, VREFIO = 1.25 V to 5.5 V, and TA = – 40°C to +125°C (unless otherwise noted)
MIN
fSCLK
SCL frequency
tBUF
Bus free time between stop and start conditions
tHDSTA
NOM
MAX
UNIT
1
MHz
0.5
µs
Hold time after repeated start
0.26
µs
tSUSTA
Repeated start setup time
0.26
µs
tSUSTO
Stop condition setup time
0.26
µs
tHDDAT
Data hold time
0
ns
tSUDAT
Data setup time
50
ns
tLOW
SCL clock low period
500
ns
tHIGH
SCL clock high period
260
tR
Clock and data fall time
tF
Clock and data rise time
tUPDATE
Sequential DAC update wait time
ns
120
120
1
ns
ns
µs
tSYNC HIGH
tSYNC H
tSYNC S
SYNC
tSYNC IGN OR E
tSCL KLOW
SCLK
tSCL KHIGH
SDIN
Bit 23
tSDIS
Bit 1
Bit 0
tSDIH
Figure 1. SPI Mode Timing
Low byte ACK cycle
tLOW
tR
tF
SCL
tHD STA
tHIGH
tHD DAT
tSUSTA
tSUSTO
tSUD AT
tHD STA
SDA
tBUF
P
S
S
P
Figure 2. I2C Mode Timing
10
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7.10 Typical Characteristics
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
1
1
DACA Unloaded
DACA 5 k: || 200 pF
DACB Unloaded
DACB 5 k: || 200 pF
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
0.4
0.2
0
-0.2
-0.4
-0.6
-1
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D001
0
Figure 3. Integral Linearity Error vs Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Code
D002
Figure 4. Differential Linearity Error vs Digital Input Code
0.08
1
DACA Unloaded
DACA 5 k: || 200 pF
DACB Unloaded
DACB 5 k: || 200 pF
0.06
0.04
INL Max, Unloaded
INL Min, Unloaded
INL Max, 5 k: || 200 pF
INL Min, 5 k: || 200 pF
0.75
Integral Linearity Error (LSB)
Total Unadjusted Error (%FSR)
0.6
-0.8
-1
0.02
0
-0.02
-0.04
0.5
0.25
0
-0.25
-0.5
-0.75
-0.06
-1
-40
-0.08
0
8192 16384 24576 32768 40960 49152 57344 65536
Code
D003
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
D004
0.08
1
0.5
Total Unadjusted Error (%FSR)
DNL Max, Unloaded
DNL Min, Unloaded
DNL Max, 5 k: || 200 pF
DNL Min, 5 k: || 200 pF
0.75
0.25
0
-0.25
-0.5
-0.75
-1
-40
-25
Figure 6. Integral Linearity Error vs Temperature
Figure 5. Total Unadjusted Error vs Digital Input Code
Differential Linearity Error (LSB)
DACA Unloaded
DACA 5 k: || 200 pF
DACB Unloaded
DACB 5 k: || 200 pF
0.8
Differential Linearity Error (LSB)
Integral Linearity Error (LSB)
0.8
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
Unloaded
5 k: || 200 pF
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
-40
-25
-10
5
D005
Figure 7. Differential Linearity Error vs Temperature
20 35 50 65
Temperature (oC)
80
95
110 125
D006
Figure 8. Total Unadjusted Error vs Temperature
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Typical Characteristics (continued)
1.5
1.5
1.25
1
Offset Error (mV)
Zero-Code Error (mV)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
1
0.75
0.5
0.25
0
-40
0.5
0
-0.5
-1
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
-1.5
-40
110 125
80
95
110 125
D008
Unloaded
5 k: || 200 pF
0.04
0.04
Gain Error (%FSR)
Full-Scale Error (%FSR)
20 35 50 65
Temperature (oC)
0.06
0.02
0
-0.02
0.02
0
-0.02
-0.04
-0.04
-0.06
-0.06
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
-0.08
-40
110 125
-25
-10
5
D009
Data
Figure 11. Full-Scale Error vs Temperature
20 35 50 65
Temperature (oC)
80
95
110 125
D010
Figure 12. Gain Error vs Temperature
1
1
Differential Linearity Error (LSB)
Max INL
Min INL
0.75
Integral Linearity Error (LSB)
5
0.08
Unloaded
5 k: || 200 pF
0.06
0.5
0.25
0
-0.25
-0.5
-0.75
3.1
3.5
3.9
4.3
4.7
Supply Voltage, VDD (V)
5.1
5.5
D011
REF-DIV = 0 and BUFF-GAIN = 0
Figure 13. Integral Linearity Error vs Supply Voltage
12
-10
Figure 10. Offset Error vs Temperature
0.08
-1
2.7
-25
D007
Figure 9. Zero-Code Error vs Temperature
-0.08
-40
Unloaded
5 k: || 200 pF
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Max DNL
Min DNL
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
2.7
3.1
3.5
3.9
4.3
4.7
Supply Voltage, VDD (V)
5.1
5.5
D012
REF-DIV = 0 and BUFF-GAIN = 0
Figure 14. Differential Linearity Error vs Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
1.5
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
0.06
0.04
0.02
0
-0.02
-0.04
0.5
0
-0.5
-1
-0.06
-0.08
2.7
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
1
Zero-Code Error (mV)
Total Unadjusted Error (%FSR)
0.08
3.1
3.5
3.9
4.3
4.7
Supply Voltage, VDD (V)
5.1
-1.5
2.7
5.5
3.1
3.5
3.9
4.3
4.7
Supply Voltage, VDD (V)
D013
Figure 15. Total Unadjusted Error vs Supply Voltage
5.1
5.5
D014
Figure 16. Zero-Code Error vs Supply Voltage
0.08
1.5
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
1
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
0.06
Gain Error (%FSR)
Offset Error (mV)
0.04
0.5
0
-0.5
0.02
0
-0.02
-0.04
-1
-1.5
2.7
-0.06
3.1
3.5
3.9
4.3
4.7
Supply Voltage, VDD (V)
5.1
-0.08
2.7
5.5
Figure 17. Offset Error vs Supply Voltage
5.1
5.5
D016
1
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
Max, REFDIV = 0
Max, REFDIV = 1
Min, REFDIV = 0
Min, REFDIV = 1
0.75
Integral Linearity Error (LSB)
0.06
Full-Scale Error (%FSR)
3.5
3.9
4.3
4.7
Supply Voltage, VDD (V)
Figure 18. Gain Error vs Supply Voltage
0.08
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
2.7
3.1
D015
0.5
0.25
0
-0.25
-0.5
-0.75
3.1
3.5
3.9
4.3
4.7
Supply Voltage, VDD (V)
5.1
Figure 19. Full-Scale Error vs Supply Voltage
5.5
D017
-1
1.25
2
2.75
3.5
4.25
Supply Volltage, VREFIN (V)
5
5.5
D018
Figure 20. Integral Linearity Error vs Reference Voltage
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
0.08
Max, REFDIV = 0
Max, REFDIV = 1
Min, REFDIV = 0
Min, REFDIV = 1
0.75
0.5
Total Unadjusted Error (%FSR)
Differential Linearity Error (LSB)
1
0.25
0
-0.25
-0.5
-0.75
-1
1.25
2
2.75
3.5
4.25
Supply Volltage, VREFIN (V)
5
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
1.25
5.5
5
5.5
D020
1.5
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
1
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
Offset Error (mV)
1
0.5
0
-0.5
-1
0.5
0
-0.5
-1
-1.5
1.25
2
2.75
3.5
4.25
Supply Volltage, VREFIN (V)
5
-1.5
1.25
5.5
Figure 23. Zero-Code Error vs Reference Voltage
2.75
3.5
4.25
Supply Volltage, VREFIN (V)
5
5.5
D022
Figure 24. Offset Error vs Reference Voltage
0.08
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
REF-DIV = 0, BUFF-GAIN = 0
REF-DIV = 1, BUFF-GAIN = 1
0.06
Full-Scale Error (%FSR)
0.06
0.04
0.02
0
-0.02
-0.04
-0.06
-0.08
1.25
2
D021
0.08
Gain Error (%FSR)
2.75
3.5
4.25
Supply Volltage, VREFIN (V)
Figure 22. Total Unadjusted Error vs Reference Voltage
1.5
0.04
0.02
0
-0.02
-0.04
-0.06
2
2.75
3.5
4.25
Supply Volltage, VREFIN (V)
5
Figure 25. Gain Error vs Reference Voltage
14
2
D019
Figure 21. Differential Linearity Error vs Reference Voltage
Zero-Code Error (mV)
REFDIV = 0
REFDIV = 1
0.06
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5.5
D023
-0.08
1.25
2
2.75
3.5
4.25
Supply Volltage, VREFIN (V)
5
5.5
D024
Figure 26. Full-Scale Error vs Reference Voltage
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Typical Characteristics (continued)
2
2
1.75
1.75
Supply Current, IVDD (mA)
Supply Current, IVDD (mA)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
1.5
1.25
1
0.75
0.5
Internal Reference, BUFF-GAIN = 0
Internal Reference, BUFF-GAIN = 1
External Reference, BUFF-GAIN = 0
External Reference, BUFF-GAIN = 1
0.25
1.25
1
0.75
0.5
Internal Reference, BUFF-GAIN = 0
Internal Reference, BUFF-GAIN = 1
External Reference, BUFF-GAIN = 0
External Reference, BUFF-GAIN = 1
0.25
0
0
1.5
0
-40
8192 16384 24576 32768 40960 49152 57344 65536
Code
D025
-25
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D026
DAC code at midscale
Figure 27. Supply Current vs Digital Input Code
Figure 28. Supply Current vs Temperature
3
12
Supply Current, IVDD (mA)
2.5
Power-Down Current, IVDD (PA)
Internal Reference, BUFF-GAIN = 0
Internal Reference, BUFF-GAIN = 1
External Reference, BUFF-GAIN = 0
External Reference, BUFF-GAIN = 1
2
1.5
1
0.5
0
2.7
3.1
3.5
3.9
4.3
4.7
Supply Voltage, VDD (V)
5.1
10
8
6
4
2
0
-40
5.5
DAC code at midscale
-10
5
20 35 50 65
Temperature (qC)
80
95
110 125
D028
REF-DIV = 0 and BUFF-GAIN = 0
Figure 29. Supply Current vs Supply Voltage
Figure 30. Power-Down Current vs Temperature
15
2.5
12
Sourcing, VDD = 2.7, REF-DIV = 1, BUFF-GAIN = 1
Sourcing, VDD = 5.5, REF-DIV = 0, BUFF-GAIN = 0
Sinking VDD = 2.7,REF-DIV = 1, BUFF-GAIN = 1
Sinking VDD = 5.5, REF-DIV = 0, BUFF-GAIN = 0
2
DAC Output (V)
Power-Down Current, IVDD (PA)
-25
D027
9
6
3
1.5
1
0.5
0
2.7
0
3.1
3.5
3.9
4.3
4.7
Supply Voltage, VDD (V)
5.1
5.5
0
5
10
15
Load Current (mA)
D029
External reference = 2.5 V, REF-DIV = 1 and BUFF-GAIN = 0
Figure 31. Power Down Current vs Supply Voltage
20
25
D030
External reference = 2.5 V
Figure 32. Headroom and Footroom vs Load Current
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
8
7
0xFFFF
0xC000
0x8000
0x4000
0x0
DAC Output (V)
5
0xFFFF
0xC000
0x8000
7
6
DAC Output (V)
6
4
3
2
1
0x4000
0x0
5
4
3
2
1
0
0
-1
-50
-40
-30
-20
-10
0
10
20
Load Current (mA)
30
40
50
-1
-50
-40
-30
-20
D031
REF-DIV = 0 and BUFF-GAIN = 0
-10
0
10
20
Load Current (mA)
30
40
50
D032
REF-DIV = 0 and BUFF-GAIN = 1
Figure 33. Source and Sink Capability
Figure 34. Source and Sink Capability
7
0xFFFF
0xC000
0x8000
0x4000
0x0
6
DAC Output (V)
5
4
3
3 nV-s
2
1
VOUT (2.5 mV/div)
CS (5 V/div)
0
-1
-50
-40
-30
-20
-10
0
10
20
Load Current (mA)
30
40
50
Time (0.5 Ps/div)
D034
D033
DAC code transition from midscale – 1 to midscale LSB,
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 1 and BUFF-GAIN = 0
Figure 36. Glitch Impulse, Rising Edge, 1-LSB Step
Figure 35. Source and Sink Capability
Small Singal VOUT (3 LSB/div)
Large Singal VOUT (2 V/div)
CS (5 V/div)
2 nV-s
VOUT (2.5mV/div)
CS (5 V/div)
Time (0.5 Ps/div)
Time (2 Ps/div)
D035
DAC code transition from midscale to midscale – 1 LSB,
REF-DIV = 0 and BUFF-GAIN = 0
Figure 37. Glitch Impulse, Falling Edge, 1-LSB Step
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D036
REF-DIV = 0 and BUFF-GAIN = 0
Figure 38. Full-Scale Settling Time, Rising Edge
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
Small Singal VOUT (3 LSB/div)
Large Singal VOUT (2 V/div)
CS (5 V/div)
VDD (2 V/div)
DAC Output (40 mV/div)
Time (2 Ps/div)
Time (1 ms/div)
D037
D038
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 0 and BUFF-GAIN = 0
Figure 39. Full-Scale Settling Time, Falling Edge
Figure 40. Power-On Glitch
0
VDD (2 V/div)
DAC Output (40 mV/div)
-10
-20
AC PSRR (dB)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
1
Time (1 ms/div)
10
100
1000
Frequency (Hz)
D039
10000
100000
D040
DAC code at midscale, VDD = 5.0 V + 0.2 VPP,
REF-DIV = 0 and BUFF-GAIN = 0
REF-DIV = 0 and BUFF-GAIN = 0
Figure 42. DAC Output AC PSRR vs Frequency
Figure 41. Power-Off Glitch
20
300
0
DAC Code = 0x0
DAC Code = 0x8000
DAC Code = 0xFFFF
250
Noise (nV/—Hz)
Noise (dB)
-20
-40
-60
-80
200
150
100
-100
50
-120
-140
0
4000
8000
12000
Frequency (Hz)
16000
20000
D041
fo = 1 kHz, fs = 400 kHz, includes 7 harmonics,
measurement bandwidth = 20 kHz, external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
Figure 43. DAC Output THD+N vs Frequency
0
10 2030 50 100 200
5001000
Frequency (Hz)
10000
100000
D042
Gain = 1X (REF-DIV = 1 and BUFF-GAIN = 1),
external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
Figure 44. DAC Output Noise Spectral Density
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Typical Characteristics (continued)
DAC Output Noise (2 PV/div)
DAC Output Noise (2 PV/div)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
D043
D044
DAC code at midscale, external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
DAC code at midscale, internal reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
Figure 45. DAC Output Noise: 0.1 Hz to 10 Hz
Figure 46. DAC Output Noise: 0.1 Hz to 10 Hz
2.505
Internal Reference Voltage (V)
SCLK (5 V/div)
VOUT (1 mV/div)
2.5025
2.5
2.4975
2.495
-40
Time (5 Ps/div)
-25
-10
5
D045
SCLK = 1 MHz, DAC code at midscale, external reference = 2.5 V,
REF-DIV = 0 and BUFF-GAIN = 0
20 35 50 65
Temperature (oC)
80
95
110 125
D046
30 units
Figure 47. Clock Feedthrough
Figure 48. Internal Reference Voltage vs Temperature
100
2.505
2.5025
Reference Drift (ppm)
Internal Reference Voltage (V)
75
2.5
2.4975
50
25
0
-25
-50
-75
2.495
2.7
-100
3.1
3.5
3.9
4.3
4.7
Supply Voltage, VDD (V)
5.1
5.5
Figure 49. Internal Reference Voltage vs Supply Voltage
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0
200
400
D047
600
800
Time (Hours)
1000
1200
D048
Figure 50. Internal Reference Voltage vs Time
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Typical Characteristics (continued)
at TA = 25°C, VDD = 5.5 V, internal reference = 2.5 V, REF-DIV = 0 and BUFF-GAIN = 1, channel A shown, and DAC outputs
unloaded (unless otherwise noted)
Internal Reference Noise (2 PV/div)
800
700
Noise (nV/—Hz)
600
500
400
300
200
100
0
10 2030 50 100 200
500 1000
Frequency (Hz)
10000
100000
D050
D049
Figure 52. Internal Reference Noise: 0.1 Hz to 10 Hz
Figure 51. Internal Reference Noise Density vs Frequency
55
100%
50
90%
45
80%
Percentage of Units
Number of Units
40
35
30
25
20
15
Presolder Heat Reflow
Postsolder Heat Reflow
70%
60%
50%
40%
30%
10
20%
5
10%
0
0
0
1
2
3
4
Temperature Drift (ppm/qC)
5
2.4975 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010
VREFOUT (V)
D051
Percentage of Units
Figure 53. Internal Reference Temperature Drift Histogram
D053
Figure 54. Internal Reference Initial Accuracy
(Pre- and Post-Solder) Histogram
28%
26%
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0
-3 -2.5 -2 -1.5 -1 -0.5 0
0.5
1
1.5
VREFOUT Drift Delta (ppm/qC)
2
2.5
3
D054
Figure 55. Internal Reference Temperature Drift (Pre-Solder and Post-Solder) Histogram
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8 Detailed Description
8.1 Overview
The DAC80502, DAC70502, DAC60502 (DACx0502) family of devices are dual-channel, buffered voltage output,
16-bit, 14-bit, or 12-bit digital-to-analog converters (DACs), respectively. These devices include a 2.5-V, 5ppm/˚C internal reference, giving full-scale output voltage ranges of 1.25 V, 2.5 V, or 5 V. The DACx0502
devices incorporate a power-on-reset circuit that makes sure that the DAC output powers up at zero scale or
midscale, depending on status of the RSTSEL pin, and remains at that scale until a valid code is written to the
device.
The digital interface of the DACx0502 can be configured to SPI or I2C mode using the SPI2C pin. In SPI mode,
the DACx0502 family uses a 3-wire serial interface that operates at clock rates up to 50 MHz. In I2C mode, the
DACx0502 devices operate in standard (100 kbps), fast (400 kbps), and fast+ (1.0 Mbps) modes.
8.2 Functional Block Diagram
VREFIO
VDD
Internal
Reference
SCLK or SCL
SDIN or SDA
SYNC or A0
Interface Logic
SPI2C
DAC
Buffer
DAC
Register
BUF
DAC
VOUTA
Channel A
VOUTB
Channel B
RSTSEL
Power Down Logic
Power On Reset
Resistive Network
AGND
8.3 Feature Description
8.3.1 Digital-to-Analog Converter (DAC) Architecture
Each output channel in the DACx0502 family of devices consists of a rail-to-rail ladder architecture with an output
buffer amplifier. The devices include an internal 2.5-V reference. Figure 56 shows a block diagram of the DAC
architecture.
2.5 V
Reference
VREFIO
REF di vide r
(x1 or x0.5)
Ser ial i nte rface
DAC da ta reg ister
DAC
buffer r egister
REF-DIV
bit
BUFF-GAIN
bit
DAC
acti ve regi ster
R-2R
Gai n
(x1 or x2)
VOUT
DAC
output
AGND
Figure 56. DACx0502 DAC Block Diagram
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Feature Description (continued)
8.3.1.1 DAC Transfer Function
The input data writes to the individual DAC data registers in straight binary format. After a power-on or a reset
event, all DAC registers are set to zero code (RSTSEL = 0) or midscale code (RSTSEL = 1). The DAC transfer
function is shown by Equation 1.
VOUT
DAC_DATA
N
2
u
VREFIO
u GAIN
DIV
where:
•
•
•
•
•
N = resolution in bits = either 12 (DAC60502), 14 (DAC70502) or 16 (DAC80502).
DAC_DATA = decimal equivalent of the binary code that is loaded to the DAC register (address 8h), DAC_DATA
ranges from 0 to 2N – 1.
VREFIO = DAC reference voltage. Either VREFIO from the internal 2.5-V reference or VREFIO from an external
reference.
DIV = 1 (default) or 2 as set by the REF-DIV bit in the GAIN register (address 4h).
GAIN = 1 or 2 (default) as set by the BUFF-GAIN bit for that DAC channel in the GAIN register (address 4h).
(1)
8.3.1.2 DAC Register Structure
Data written to the DAC data registers are initially stored in the DAC buffer registers. The update mode of the
DAC output is determined by the status of the DAC_SYNC_EN bit (address 2h).
In asynchronous mode (default, DAC_SYNC_EN = 0), a write to the DAC buffer register results in an immediate
update of the DAC active register. In SPI mode, the DAC output (VOUTx pin) updates on the rising edge of
SYNC. In I2C mode, the DAC output (VOUT pin) updates on the falling edge of SCL on the last acknowledge bit.
In synchronous mode (DAC_SYNC_EN = 1), writing to the DAC buffer register does not automatically update the
DAC active register. Instead, the update occurs only after a software LDAC trigger event. A software LDAC
trigger generates through the LDAC bit in the TRIGGER register (address 5h). When the host reads from a DAC
buffer register, the value held in the DAC buffer register is returned (not the value held in the DAC active
register).
8.3.1.3 Output Amplifier
The output buffer amplifier generates rail-to-rail voltages on the output, giving a maximum output range of 0 V to
VDD. Equation 1 shows that the full-scale output range of the DAC output is determined by the voltage on the
VREFIO pin, the reference divider setting (DIV) as set by the REF-DIV bit (address 4h), and the gain
configuration for that channel set by the corresponding BUFF-GAIN bit (address 4h).
8.3.2 Internal Reference
The DAx0502 family of devices includes a 2.5-V precision band-gap reference enabled by default. Operation
from an external reference is supported by disabling the internal reference in the REF_PWDWN bit (address 3h).
The internal reference is externally available at the VREFIO pin and sources up to 5 mA. For noise filtering, use
a minimum 150-nF capacitor between the reference output and AGND.
The reference voltage to the device, either from the internal reference or an external one, can be divided by a
factor of two by setting the REF-DIV bit (address 4h) to 1. The REF-DIV bit provides additional flexibility in setting
the full-scale output range of the DAC output. Make sure to configure REF-DIV so that there is sufficient
headroom from VDD to the DAC operating reference voltage, VREFIO (see Equation 1). See the Recommended
Operating Conditions for more information.
Improper configuration of the reference divider triggers a reference alarm condition. In this case, the reference
buffer is shut down, and all the DAC outputs go to 0 V. The DAC data registers are unaffected by the alarm
condition, and thus enable the DAC output to return to normal operation after the reference divider is configured
correctly.
8.3.2.1 Solder Heat Reflow
A known behavior of IC reference voltage circuits is the shift induced by the soldering process. Figure 54 and
Figure 55 show the effect of solder heat reflow for the DACx0502 internal reference.
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Feature Description (continued)
8.3.3 Power-On Reset (POR)
The DACx0502 family of devices includes a power-on reset function that controls the output voltage at power up.
After the VDD supply has been established, a POR event is issued. The POR causes all registers to initialize to
default values, and communication with the device is valid only after a 250-µs, power-on-reset delay. The default
value for all DACs is zero code if RSTSEL = 0, and midscale code if RSTSEL = 1. Each DAC channel remains at
the power-up voltage until a valid command is written to a channel.
When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific
VDD levels, as indicated in Figure 57, in order to make sure that the internal capacitors discharge and reset the
device on power up. In order to make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms.
When VDD drops to less than 2.2 V but remains greater than 0.7 V (shown as the undefined region), the device
may or may not reset under all specified temperature and power-supply conditions. In this case, initiate a POR.
When VDD remains greater than 2.2 V, a POR does not occur.
VDD (V)
5.50
No power-on reset
Spe cified supply
voltage range
2.70
2.20
Undefined
0.70
Power-on reset
0.00
Figure 57. Threshold Levels for the VDD POR Circuit
8.3.4 Software Reset
A device software reset event is initiated by writing the reserved code 0x1010 to the SOFT-RESET bit in the
TRIGGER register (address 5h). A software reset initiates a POR event.
8.4 Device Functional Modes
The DACx0502 have two modes of operation: normal and power-down.
8.4.1 Power-Down Mode
The DACx0502 output amplifiers and internal reference can be independently powered down through the
CONFIG register (3h). At power up, the DAC output and the internal reference are active by default. In powerdown mode, the DACs output (VOUTx pin) is internally connected to AGND through a 1-kΩ resistor.
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8.5 Programming
8.5.1 Serial Interface
The DACx0502 family of devices is controlled through either a 3-wire SPI or a 2-wire I2C interface.
The type of interface is determined at device power up based on the logic level of the SPI2C pin. A logic 0 on the
SPI2C pin puts the DACx0502 in SPI mode; whereas, logic 1 on SPI2C puts the DACx0502 in I2C mode. The
SPI2C pin must be kept static after the device powers up.
8.5.1.1 SPI Mode
The DACx0502 digital interface is programmed to work in SPI mode when the logic level of the SPI2C pin is 0 at
power up. Table 1 shows the frame format for SPI mode. In SPI mode, the DACx0502 have a 3-wire serial
interface: SYNC, SCLK, and SDIN. The serial interface is compatible with SPI, QSPI, and Microwire interface
standards, and most digital signal processors (DSPs). The serial interface operates at up to 50 MHz. The input
shift register is 24-bits wide.
Table 1. SPI Mode Frame Format
BIT
DESC
23
22
R/W
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
16-Bit MSB-Aligned DAC Data:
DAC80502 {15:0}, DAC70502 {13:0, x, x}, DAC60502 {11:0, x, x, x, x}
Register Address - Command Byte
Serial clock SCLK is a continuous or a gated clock. The first falling edge of SYNC starts the operation cycle.
When SYNC is high, the SCLK and SDIN signals are blocked. The device internal registers are updated from the
shift register on the rising edge of SYNC.
8.5.1.1.1 SYNC Interrupt
For SPI-mode operation, the SYNC line stays low for at least 24 falling edges of SCLK, and the addressed DAC
register updates on the SYNC rising edge. However, if the SYNC line is brought high before the 24th SCLK
falling edge, this event acts as an interrupt to the write sequence. The shift register resets and the write
sequence is discarded. The data buffer contents and the DAC register contents do not update, and the the
operating mode does not change, as shown in Figure 58.
SCLK
1
2
24
SYNC
SDIN
DB23
DB0
Inva lid/Inte rrupted wr ite sequen ce
SCLK
1
2
24
SYNC
SDIN
DB23
DB0
Vali d write se quence
Figure 58. SYNC Interrupt
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8.5.1.2 I2C Mode
The DACx0502 digital interface is programmed to work in I2C mode when the logic level of the SPI2C pin is 1 at
power up. In I2C mode, the DACx0502 have a 2-wire serial interface: SCL, SDA, and one address pin, A0. The
I2C bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both
the SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain
I/O pins SDA and SCL.
The I2C specification states that the device that controls communication is called a master, and the devices that
are controlled by the master are called slaves. The master device generates the SCL signal. The master device
also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus
to indicate the start or stop of a data transfer. Device addressing is completed by the master. The master device
on an I2C bus is typically a microcontroller or DSP. The DACx0502 operate as a slave device on the I2C bus. A
slave device acknowledges master commands, and upon master control, receives or transmits data.
Typically, the DACx0502 operate as a slave receiver. A master device writes to the DACx0502, a slave receiver.
However, if a master device requires the DACx0502 internal register data, the DACx0502 operate as a slave
transmitter. In this case, the master device reads from the DACx0502 According to I2C terminology, read and
write refer to the master device.
The DACx0502 are slave devices that support the following data transfer modes:
1. Standard mode (100 kbps)
2. Fast mode (400 kbps)
3. Fast-mode plus (1.0 Mbps)
The data transfer protocol for standard and fast modes is exactly the same; therefore, these modes are referred
to as F/S-mode in this document. The fast-mode plus protocol is supported in terms of data transfer speed, but
not output current. The low-level output current would be 3 mA, similar to the case of standard and fast modes.
The DACx0502 support 7-bit addressing. The 10-bit addressing mode is not supported. These devices support
the general call reset function. Sending the following sequence initiates a software reset within the device:
start/repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the falling edge of the ACK bit,
following the second byte.
Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock
cycle generates and detects an acknowledge signal. Acknowledge is when the SDA line is pulled low during the
high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high period of
the ninth clock cycle as shown in Figure 59.
Data ou tpu t
by Tran smitte r
Not acknowledge
Data ou tpu t
by Receiver
Acknowledge
1
SCL fro m
Master
2
9
8
S
Start
condition
Clock pulse fo r
acknowledgemen t
Figure 59. Acknowledge and Not Acknowledge on the I2C Bus
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8.5.1.2.1 F/S Mode Protocol
1. The master initiates data transfer by generating a start condition. The start condition is when a high to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 60. All I2C-compatible devices
recognize a start condition.
SDA
SCL
S
P
Start
condition
Stop
condition
Figure 60. Start and Stop Conditions
SDA
SCL
Data lin e stable
Data valid
Chang e of data
allo wed
Figure 61. Bit Transfer on the I2C Bus
2. The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit
(R/W) on the SDA line. During all transmissions, the master makes sure that data are valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown in
Figure 61. All devices recognize the address sent by the master and compare it to their internal fixed
addresses. Only the slave device with a matching address generates an acknowledge by pulling the SDA
line low during the entire high period of the 9th SCL cycle, as shown in Figure 59. Upon detecting this
acknowledge, the master knows the communication link with a slave has been established.
3. The master generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the slave. In
either case, the receiver must acknowledge the data sent by the transmitter so that the acknowledge signal
can be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data
sequences consists of eight data bits and one acknowledge-bit, and can continue for as long as necessary.
4. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from
low-to-high while the SCL line is high (see Figure 60). This action releases the bus and stops the
communication link with the addressed slave. All I2C-compatible devices recognize the stop condition. Upon
receipt of a stop condition, the bus is released, and all slave devices then wait for a start condition followed
by a matching address.
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8.5.1.2.2 DACx0502 I2C Update Sequence
For a single update, the DACx0502 requires a start condition, a valid I2C address byte, a command byte, and two
data bytes (the most significant data byte, MSDB, and least significant data byte, LSDB), as listed in Table 2.
Table 2. Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
Address (A) byte
Command byte
MSDB
LSDB
DB [31:24]
DB [23:16]
DB [15:8]
DB [7:0]
ACK
After each byte is received, the DACx0502 acknowledges the byte by pulling the SDA line low during the high
period of a single clock pulse, as shown in Figure 62. These four bytes and acknowledge cycles make up the 36
clock cycles required for a single update to occur. A valid I2C™ address byte selects the DACx0502 devices.
Recognize
START or
REPEA TE D
START
condition
Recognize
STOP or
REPEA TE D
START
condition
Gen erate ACK NO WLEDGE
signal
P
SDA
MSB
Add ress
SCL
Sr
Acknowledge men t
signal from Sl ave
1
R/W
7
8
9
1
2-8
9
Sr
or
P
S
or
Sr
ACK
ACK
START or
REPEA TE D
START
condition
REPEA TE D
START or
STOP
condition
Clock line hel d lo w while
interrup ts a re ser viced
Figure 62. I2C Bus Protocol
The command byte sets the operating mode of the selected DACx0502 device. When the operating mode is
selected by this byte, the DACx0502 series must receive two data bytes, the most significant data byte (MSDB)
and least significant data byte (LSDB), for a data update to occur. The DACx0502 devices perform an update on
the falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 22.22 kSPS. Using the
fast-mode plus (clock = 1 MHz), the maximum DAC update rate is limited to 55.55 kSPS. When a stop condition
is received, the DACx0502 family releases the I2C bus and awaits a new start condition.
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8.5.1.2.2.1 DACx0502 Address Byte
The address byte, as shown in Table 3, is the first byte received following the start condition from the master
device. The first four bits (MSBs) of the address are factory preset to 1001. The next three bits of the address
are controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is
sampled during the first byte of each data frame to determine the address. The device latches the value of the
address pin and consequently responds to that particular address according to Table 4.
Table 3. DACx0502 Address Byte
B31
B30
B29
B28
AD6
AD5
AD4
AD3
1
0
0
1
B27
B26
B25
AD2
AD1
AD0
B24
COMMENT
R/W
See Table 4 (slave address column)
0 or 1
General address
Table 4. Address Format
SLAVE ADDRESS
A0 PIN
1001 000
AGND
1001 001
VDD
1001 010
SDA
1001 011
SCL
8.5.1.2.2.2 DACx0502 Command Byte
The DACx0502 command byte (shown in Table 5) controls which command is executed and which register is
being accessed when writing to or reading from the DACx0502 series.
Table 5. DACx0502 Command Byte
B23
B22
B21
B20
B19
B18
B17
B16
0
0
0
0
0
0
0
0
NOOP
0
0
0
0
0
0
0
1
DEVID
0
0
0
0
0
0
1
0
SYNC
0
0
0
0
0
0
1
1
CONFIG
0
0
0
0
0
1
0
0
GAIN
0
0
0
0
0
1
0
1
TRIGGER
0
0
0
0
0
1
1
0
BRDCAST
0
0
0
0
0
1
1
1
STATUS
0
0
0
0
1
0
0
0
DAC-A DATA
0
0
0
0
1
0
0
1
DAC-B DATA
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8.5.1.2.2.3 DACx0502 Data Byte (MSDB and LSDB)
The MSDB and LSDB contain the data that are passed to the register(s) specified by the command byte, as
shown in Table 6. The DACx0502 updates at the falling edge of the acknowledge signal that follows the LSDB[0]
bit.
Table 6. DACx0502 Data Byte
REGISTER
NAME
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
MSDB
B3
B2
B1
B0
LSDB
NOOP
NOOP - No operation
DEVID
0
RESOLUTION
SYNC
0
0
1
RESERVED
0
0
DAC-BDAC-ABRDCST BRDCST
-EN
-EN
0
0
1
0
1
0
1
RESERVED
DAC-BSYNCEN
DAC-ASYNCEN
CONFIG
RESERVED
REFPWDWN
RESERVED
DAC-BPWDWN
DAC-APWDWN
GAIN
RESERVED
REF-DIV
RESERVED
BUF-BGAIN
BUF-AGAIN
TRIGGER
LDAC
BRDCAST
SOFT-RESET [3:0]
BROADCAST-DAC-DATA [15:0] / BROADCAST-DAC-DATA [13:0] / BROADCAST-DAC-DATA [11:0] -- left Aligned
STATUS
REFALARM
RESERVED
DAC-A
DAC-A-DATA [15:0] for 16-bit / DAC-A-DATA [13:0] for 14-bit / DAC-A-DATA [11:0] for 12-bit -- left Aligned
DAC-B
DAC-B-DATA [15:0] for 16-bit / DAC-B-DATA [13:0] for 14-bit / DAC-B-DATA [11:0] for 12-bit -- left Aligned
8.5.1.2.3 DACx0502 I2C Read Sequence
To read any register the following command sequence must be used:
1. Send a start or repeated start command with a slave address and the R/W bit set to 0 for writing. The device
acknowledges this event.
2. Send a command byte for the register to be read. The device acknowledges this event again.
3. Send a repeated start with the slave address and the R/W bit set to 1 for reading. The device acknowledges
this event.
4. The device writes the MSDB byte of the addressed register. The master must acknowledge this byte.
5. Finally, the device writes out the LSDB of the register
An alternative reading method allows for reading back the value of the last register written. The sequence is a
start or repeated start with the slave address and the R/W bit set to 1, and the two bytes of the last register are
read out. All the registers in DACx0502 family can be read out with the exception of SOFT-RESET register.
Table 6 shows the read command set.
Table 7. Read Sequence
S
MSB
...
R/W(0)
ACK
ADDRESS BYTE
From Master
28
MSB
...
LSB
ACK
COMMAND BYTE
Slave
From Master
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Sr
Sr
Slave
MSB
...
R/W(1)
ACK
ADDRESS BYTE
From Master
MSB
...
LSB
ACK
MSDB
Slave
From Slave
MSB
...
LSB
NACK
LSDB
Mast
er
From Slave
Master
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8.6 Register Maps
8.6.1 Registers
Table 8. DACx0502 Register Map
Offset
Register Name
Section
0h
No Operation
NOOP Register
1h
Device Identification
DEVID Register
2h
Synchronization
SYNC Register
3h
Configuration
CONFIG Register
4h
Gain
GAIN Register
5h
Trigger
TRIGGER Register
6h
Broadcast
BRDCAST Register
7h
Device Status
STATUS Register
8h
DAC-A
DAC-A Register
9h
DAC-B
DAC-B Register
8.6.1.1 NOOP Register (offset = 0h) [reset = 0000h]
Figure 63. NOOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOOP
W-0h
Table 9. NOOP Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
No operation
W
0h
No Operation command
8.6.1.2 DEVID Register (offset = 1h) [reset = 0214h for DAC80502, 1214h for DAC70502, 2214h for
DAC60502]
Figure 64. DEVID Register
15
0
R-0h
14
13
12
RESOLUTION
R/W-0000h (DAC80502)
or 0001h (DAC70502) or
0020h (DAC60502)
11
0
R-0h
10
0
R-0h
9
1
R-1h
8
0
R-0h
7
0
R-0h
6
0
R-0h
5
0
R-0h
4
1
R-1h
3
0
R-0h
2
1
R-1h
1
0
R-0h
0
1
R-1h
Table 10. DEVID Register Field Descriptions
Bit
Field
Type
Reset
Description
15
RESERVED
R
0h
RESERVED
14-12
RESOLUTION
R
0000h
(DAC80502)
0001h
(DAC70502)
0020h
(DAC60502)
DAC Resolution:
0000h (DAC80502 16-bit)
0001h (DAC70502 14-bit)
0020h (DAC60502 12-bit)
11-0
RESERVED
R
0215h
RESERVED
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8.6.1.3 SYNC Register (offset = 2h) [reset = 0300h]
Figure 65. SYNC Register
15
14
13
12
RESERVED
11
10
9
DAC-BBRDCASTEN
R/W-1h
R/W-0h
8
DAC-ABRDCASTEN
R/W-1h
7
6
5
4
RESERVED
3
2
R/W-0h
1
DAC-BSYNC-EN
0
DAC-ASYNC-EN
R/W-0h
R/W-0h
Table 11. SYNC Register Field Descriptions
Bit
15-10
9
Field
Type
Reset
Description
RESERVED
RW
0h
RESERVED
DAC-B-BRDCAST-EN
RW
1h
When set to 1 the corresponding DAC is set to update its output
after a serial interface write to the BRDCAST register.
When cleared to 0 the corresponding DAC output remains
unaffected after a serial interface write to the BRDCAST
register.
8
DAC-A-BRDCAST-EN
RW
1h
When set to 1 the corresponding DAC is set to update its output
after a serial interface write to the BRDCAST register.
When cleared to 0 the corresponding DAC output remains
unaffected after a serial interface write to the BRDCAST
register.
7-2
1
RESERVED
RW
0h
RESERVED
DAC-B-SYNC-EN
RW
0h
When set to 1, the DAC output is set to update in response to
an LDAC trigger (synchronous mode).
When cleared to 0 ,the DAC output is set to update immediately
(asynchronous mode), default.
0
DAC-A-SYNC-EN
RW
0h
When set to 1, the DAC output is set to update in response to
an LDAC trigger (synchronous mode).
When cleared to 0 ,the DAC output is set to update immediately
(asynchronous mode), default.
8.6.1.4 CONFIG Register (offset = 3h) [reset = 0000h]
Figure 66. CONFIG Register
15
14
13
12
11
RESERVED
10
9
8
REF-PWDWN
R/W-0h
R/W-0h
7
6
5
4
RESERVED
3
R/W-0h
2
1
DAC-BPWDWN
R/W-0h
0
DAC-APWDWN
R/W-0h
Table 12. CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
RW
0h
RESERVED
REF-PWDWN
RW
0h
When set to 1 disables the device internal reference
RESERVED
RW
0h
RESERVED
1
DAC-B-PWDWN
RW
0h
When set to 1, the corresponding DAC in power-down mode and
output is connected to GND through a 1-kΩ internal resistor.
0
DAC-A-PWDWN
RW
0h
When set to 1, the corresponding DAC in power-down mode and
output is connected to GND through a 1-kΩ internal resistor.
15-9
8
7-2
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8.6.1.5 GAIN Register (offset = 4h) [reset = 0003h]
Figure 67. GAIN Register
15
14
13
12
11
RESERVED
10
9
8
REF-DIV
R/W-0h
7
6
R/W-0h
5
4
RESERVED
3
2
1
BUFF-BGAIN
R/W-1h
R/W-0h
0
BUFF-AGAIN
R/W-1h
Table 13. GAIN Register Field Descriptions
Bit
15-9
8
Field
Type
Reset
Description
RESERVED
RW
0h
RESERVED
REF-DIV
RW
0h
The reference voltage to the device (either from the internal or
external reference) can be divided by a factor of two by setting
the REF-DIV bit to 1. Make sure to configure REF-DIV so that
there is sufficient headroom from VDD to the DAC operating
reference voltage. Improper configuration of the reference
divider triggers a reference alarm condition. In the case of an
alarm condition, the reference buffer is shut down, and all the
DAC outputs go to 0 V. The DAC data registers are unaffected
by the alarm condition, and thus enable the DAC output to return
to normal operation after the reference divider is configured
correctly.
When set to 1 the reference voltage is internally divided by a
factor of 2.
When cleared to 0 the reference voltage is unaffected.
7-2
1
RESERVED
RW
0h
RESERVED
BUFF-B-GAIN
RW
1h
When set to 1 the buffer amplifier for corresponding DAC has a
gain of 2.
When cleared to 0 the buffer amplifier for corresponding DAC
has a gain of 1.
0
BUFF-A-GAIN
RW
1h
When set to 1 the buffer amplifier for corresponding DAC has a
gain of 2.
When cleared to 0 the buffer amplifier for corresponding DAC
has a gain of 1.
8.6.1.6 TRIGGER Register (offset = 5h) [reset = 0000h]
Figure 68. TRIGGER Register
15
14
13
12
11
10
9
RESERVED
R/W-0h
8
7
6
5
4
LDAC
W-0h
3
2
1
SOFT-RESET [3:0]
W-0h
0
Table 14. TRIGGER Register Field Descriptions
Bit
15-5
4
3-0
Field
Type
Reset
Description
RESERVED
RW
0h
RESERVED
LDAC
W
0h
Set this bit to 1 to synchronously load those DACs who have
been set in synchronous mode in the SYNC register. This is a
self resetting bit.
SOFT-RESET [3:0]
W
0h
When set to the reserved code 1010 resets the device to its
default state. This is a self resetting bit.
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8.6.1.7 BRDCAST Register (offset = 6h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
Figure 69. BRDCAST Register
15
14
13
12
11
10
9
8
7
6
5
4
DAC-DATA [15:0]
W-0000h when RSTSEL = 0 or reset = 8000h when RSTSEL = 1
3
2
1
0
Table 15. BRDCAST Register Field Descriptions
Bit
15-0
Field
Type
Reset
Description
BRDCAST-DATA [15:0]
W
0000h when
RSTSEL = 0
or
8000h when
RSTSEL = 1
Writing to the BRDCAST register forces those DAC channels
who have been set to broadcast in the SYNC register to update
its active register data to the BRDCAST-DATA one.
Data is MSB aligned in straight binary format and follows the
format below:
DAC80502: { DATA[15:0] }
DAC70502: { DATA[13:0], x, x }
DAC60502: { DATA[11:0], x, x, x, x}
x – Don’t care bits
8.6.1.8 STATUS Register (offset = 7h) [reset = 0000h]
Figure 70. STATUS Register
15
14
13
12
11
10
9
8
7
RESERVED
R/W-0h
6
5
4
3
2
1
0
REF-ALARM
R-0h
Table 16. STATUS Register Field Descriptions
Bit
32
Field
Type
Reset
Description
15-1
RESERVED
RW
0h
RESERVED
0
REF-ALARM
R
0
REF-ALARM bit. Reads 1 when the difference between the
reference and supply pins is below a minimum analog threshold.
Reads 0 otherwise. When 1, the reference buffer is shut down,
and the DAC outputs are all 0 V. The DAC codes are
unaffected, and the DAC output returns to normal when the
difference is above the analog threshold.
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8.6.1.9 DAC-n Register (offset = 8h–9h) [reset = 0000h for RSTSEL = 0, or reset = 8000h for RSTSEL = 1]
Figure 71. DAC-n Register
15
14
13
12
11
10
9
8
7
6
5
4
DAC-n-DATA [15:0]
R/W-0000h when RSTSEL = 0 or reset = 8000h when RSTSEL = 1
3
2
1
0
Table 17. DAC-A Data Register Field Descriptions (8h)
Bit
15-0
Field
Type
Reset
Description
DAC-A-DATA [15:0]
RW
0000h when
RSTSEL = 0
or
8000h when
RSTSEL = 1
Data is MSB aligned in straight binary format and follows the
format below:
DAC80502: { DATA[15:0] }
DAC70502: { DATA[13:0], x, x }
DAC60502: { DATA[11:0], x, x, x, x}
x – Don’t care bits
Table 18. DAC-B Data Register Field Descriptions (9h)
Bit
15-0
Field
Type
Reset
Description
DAC-B-DATA [15:0]
RW
0000h when
RSTSEL = 0
or
8000h when
RSTSEL = 1
Data is MSB aligned in straight binary format and follows the
format below:
DAC80502: { DATA[15:0] }
DAC70502: { DATA[13:0], x, x }
DAC60502: { DATA[11:0], x, x, x, x}
x – Don’t care bits
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Generating accurate, stable programmable dc voltages is a key requirement in most precision end equipment.
The DACx0502 family of precision DACs are an excellent choice for such applications. The DACx0502 tiny
package, high resolution, and simple interface makes these devices a great choice for applications such as offset
and gain control, VCO tuning, programmable reference, and more. With the aforementioned features, this family
of DACs caters to a wide range of end equipment, such as battery testers, communications equipment, factory
automation and control, test and measurement, and more.
9.2 Typical Application
Battery test equipment requires a two-channel DAC for every channel of battery test output. A battery tester
operates in constant-current (CC) and constant-voltage (CV) modes. The two DAC channels are used to set the
voltage and current for battery charge and discharge control. The low INL of the DACx0502 makes system
calibration simple. The integrated reference and the small package make the design very compact.
VDD
VSE T
DACx050 2
ISET
Battery
Charge/
Discha rge
Circuit
RSENS E
Figure 72. Battery Test Equipment
9.2.1 Design Requirements
•
•
•
DAC output range: 0 V to 2.5 V
DAC output accuracy after calibration: 0.05%FSR
Operating temperature: 0°C to 100°C
9.2.2 Detailed Design Procedure
Figure 72 shows a simplified circuit diagram of a battery test system. Use the internal reference (2.5 V) and gain
of 1 for an output range of 2.5 V. The reference divider is 1. Select the 16-bit DAC80502 for the best accuracy.
The typical value of the TUE is 0.02%FSR, as specified in the Typical Characteristics table. The absolute error at
the DAC output includes the error from the reference, the error from the DAC, and the temperatures drifts of
offset error, gain error, and reference. Ignore the load regulation, line regulation, and long-term drift of the
reference as compared to the initial accuracy and temperature drift. Write the total TUE at the DAC output, as
given in Equation 2.
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Typical Application (continued)
2
TUETOTAL = TUE
(TCOE )2
(TCGE )2
(EREF u GAIN)2
(TCREF u GAIN)2
where
•
•
•
•
•
TCOE is the temperature drift of the offset error.
TCGE is the temperature drift of the gain error.
EREF is the initial accuracy of the reference.
TCREF is the temperature drift of the reference.
GAIN is the gain setting of the DAC in combination with the reference divider.
(2)
Convert the INL value in LSB to %FSR using Equation 3.
%FSR=
LSB
2N
u 100
(3)
Convert the temperature drift values in ppm/°C to %FSR using Equation 4.
%FSR
PPM / qC u 'T
104
where
•
∆T is the temperature range.
(4)
Calculate the total error after the offset and gain of DAC are calibrated using Equation 5
TUETOTAL = INL
2
(TCOE )2
(TCGE )2
(TCREF u GAIN)2
(5)
The total error at the DAC output calculated using the previous equations is 0.112%FSR before calibration, and
0.05%FSR after calibration. For better accuracy, perform a temperature calibration. Figure 73 and Figure 74
show the drift in the internal reference voltage and TUE, respectively over 0°C to 100°C.
9.2.3 Application Curves
Figure 73. Internal Reference vs Temperature
Figure 74. TUE vs Temperature
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9.3 System Examples
The DACx0502 come with a pin-selectable SPI or I2C interface. This configuration makes the system design
generic. Pull the SPI2C pin low for SPI or high for I2C. The RSTSEL pin provides a known output at the DAC
channels at power up, which helps the system achieve a predictable behavior during start up. When using a
processor with multiple power-supply domains, make sure the input/output power (IOVDD) never exceeds the
VDD voltage of the DAC. Switching on the IOVDD before VDD can violate the absolute maximum ratings. When
there is no power-supply sequencing implemented on the system between the processor and the DAC, use a
series resistor on the digital lines so that the current flow on the digital lines is limited to ±10 mA on any pin.
9.3.1 SPI Connection to a Processor
The DACx0502 provides a 3-wire serial peripheral interface (SPI). The connections can be made to a processor,
as shown in Figure 75. Connect the SPI2C pin to ground either directly or through a pulldown resistor. Pull the
RSTSEL pin low or high based on the desired output state at power-up. Use a pullup resistor on the SYNC
signal so that the signal is high by default. Use termination resistors at the digital source so that the transmission
line reflections are minimized. The source termination resistors also help in slowing down the rise and fall times
of the digital signals, and in turn, help in minimizing the digital feedthrough of the DAC.
IOVDD
RPUL LU P
IOVDD
VDD
RS
SCLK
SCLK
RS
MOSI
SDIN
RS
PROCESS OR
CS
SYNC
DACx050 2
RSTSEL
SPI2C
Figure 75. SPI Connection to a Processor
9.3.2 I2C Interface Connection to a Processor
The I2C interface on DACx0502 provides a slave address selection pin A0 in addition to the standard SCL and
SDA signals. The A0 can be configured to provide four slave addresses, as specified in Table 3. Pull up the SCL
and SDA pins, as shown in Figure 76. The pullup resistor must be selected considering the parasitic capacitance
of the I2C bus on the printed circuit board (PCB). A small resistance provides better speed, but at the cost of
increased power consumption.
IOVDD
RPUL LU P
IOVDD
VDD
SCL
SCL
SDA
SDA
PROCESS OR
A0
IOVDD
DACx050 2
RSTSEL
SPI2C
Figure 76. I2C Interface Connection to a Processor
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9.4 What To Do and What Not To Do
9.4.1 What To Do
•
•
•
When using an external reference, disable the internal reference. This step must be the first step after power
on, especially when the external reference is greater than the 2.5-V internal reference.
Maintain the required headroom between the reference voltage and VDD.
Use the reference divider when the headroom exceeds the limit.
9.4.2 What Not To Do
•
Do not use an external reference when the internal reference is on. There is no current limit on the internal
reference.
9.5 Initialization Setup
The DACx0502 requires a simple software initialization process based on the interface, power supply, and
reference selection. The initialization steps are as follows:
1. When using an external reference, disable the internal reference.
2. Divide the reference by two when the reference voltage exceeds the headroom required from VDD. For
example, when using 3.3-V VDD and the internal reference of 2.5 V, the DAC outputs are disabled unless
the reference is divided by two.
3. Set the output gain.
4. Write to the DAC register.
The following text shows the pseudocode to get started with the DACx0502:
//SPI Settings
//Mode: Mode-1 (CPOL: 0, CPHA: 1)
//CS Type: Active Low, Per Packet
//Frame length: 24
//SYNTAX: ,
//Disable internal reference (only in case of external reference)
WRITE CONFIG (0x03), 0x0100
//Select REFDIV=1 (reference divided by 2) and GAIN=1 (gain at both the DAC outputs is 2)
WRITE GAIN (0x04), 0x0103
//Write mid-code to DACA
WRITE DAC-A (0x08), 0x7FFF
//Write Full-code to DACB
WRITE DAC-B (0x09), 0xFFFF
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10 Power Supply Recommendations
The DACx0502 operate within the specified VDD supply range of 2.7 V to 5.5 V. The DACx0502 do not require
specific supply sequencing. The VDD supply must be well regulated and low noise. Switching power supplies
and DC/DC converters often have high-frequency glitches or spikes riding on the output voltage. In addition,
digital components create similar high-frequency spikes. This noise can easily couple into the DAC output
voltage through various paths between the power connections and analog output. To further minimize noise from
the power supply, include a 1-μF to 10- μF capacitor and 0.1-μF bypass capacitor. The current consumption on
the VDD pin, the short-circuit current limit, and the load current for the device is listed in the Electrical
Characteristics section. The power supply must meet the aforementioned current requirements.
11 Layout
11.1 Layout Guidelines
A precision analog component requires careful layout. The following list provides some insight into good layout
practices.
• Bypass the VDD to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass
capacitance is 0.1-µF to 0.22-µF ceramic capacitor, with a X7R or NP0 dielectric.
• Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize
performance.
• Use a high-quality, ceramic-type NP0 or X7R for optimal performance across temperature, and a very low
dissipation factor.
• The digital and analog sections must have proper placement with respect to the digital pins and analog pins
of the DACx0502 devices. The separation of analog and digital blocks minimizes coupling into neighboring
blocks, as well as interaction between analog and digital return currents.
11.2 Layout Example
GND
Decouplin g
Capacitor
GND
Reference
Bypass
Capacitor
DACx050 2
Optiona l
REFIN or
REFOUT
VDD
1
10
VOUTA
2
9
VOUTB
3
8
4
7
SDIN/SDA
Pull-up
5
6
GND
VDD
GND
SYNC/A0
SCLK/SCL
Pull-down fo r
SPI Mo de
(Note: Gro und and Power plan es omitted for cla rity)
Figure 77. Layout Example
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following: DAC80502EVM user's guide
12.2 Related Links
Table 19 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 19. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
DAC80502
Click here
Click here
Click here
Click here
Click here
DAC70502
Click here
Click here
Click here
Click here
Click here
DAC60502
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC60502DRXR
ACTIVE
WSON
DRX
10
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D652
DAC60502DRXT
ACTIVE
WSON
DRX
10
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D652
DAC70502DRXR
ACTIVE
WSON
DRX
10
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D752
DAC70502DRXT
ACTIVE
WSON
DRX
10
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D752
DAC80502DRXR
ACTIVE
WSON
DRX
10
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D852
DAC80502DRXT
ACTIVE
WSON
DRX
10
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
D852
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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