DAC63004, DAC53004
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
DACx3004 12-Bit and 10-Bit, Ultra-Low-Power, Quad Voltage and Current Output
Smart DACs With Auto-Detected I2C, PMBus™, or SPI
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
Land mobile radio
Pulse oximeter
Optical module
Standard notebook PC
3 Description
The 12-bit DAC63004 and 10-bit DAC53004
(DACx3004) are a pin-compatible family of ultralow-power, quad-channel, buffered, voltage-output
and current-output smart digital-to-analog converters
(DACs). These DACx3004 support Hi-Z power-down
mode and Hi-Z output during power-off condition.
The DAC outputs provide a force-sense option for
use as a programmable comparator and current
sink. The multifunction GPIO, function generation,
and NVM enable these smart DACs for processorless applications and design reuse. These devices
automatically detect I2C, PMBus, and SPI interfaces
and contain an internal reference.
The feature set combined with the tiny package
and ultra-low power make these smart DACs an
excellent choice for applications such as land mobile
radios, pulseoximeters, notebook PCs, and other
battery-operated applications for biasing, calibration,
and waveform generation.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
DACx3004
WQFN (16)
3.00 mm x 3.00 mm
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
CAP
VDD
VREF
TX-VCO
LDO
NVM
SDA/SCLK
SCL/SYNC
A0/SDI
Digital Interface
•
•
•
•
Programmable voltage or current outputs with
flexible configuration:
– Voltage outputs:
• 1 LSB INL and DNL (10-bit)
• Gains of 1x, 1.5x, 2x, 3x, and 4x
– Current outputs:
• 1 LSB INL and DNL (8-bit)
• Unipolar and bipolar output range options
from 25 μA to 250 μA
35-μA/channel IDD in voltage-output mode
Programmable comparator mode for all channels
High-impedance output when VDD is off
High-impedance and resistive pulldown powerdown modes
50-MHz SPI-compatible interface
Automatically detected I2C, PMBus™, or SPI
interface
– 1.62-V VIH with VDD = 5.5 V
General-purpose input/output (GPIO) configurable
as multiple functions
Predefined waveform generation: sine wave,
triangular, sawtooth
User-programmable nonvolatile memory (NVM)
Internal, external, or power-supply as reference
Wide operating range:
– Power supply: 1.8 V to 5.5 V
– Temperature range: –40˚C to +125˚C
Tiny package: 16-pin WQFN (3 mm × 3 mm)
GPIO/SDO
DACx3004
Simplified Block Diagram
Internal
Reference
DAC
BUF
DAC
REG
VOUT/
IOUT
DAC
BUF
DAC
REG
VOUT/
IOUT
DAC
BUF
DAC
REG
VOUT/
IOUT
DAC
BUF
DAC
REG
VOUT/
IOUT
Output Configuration
Logic
RX-VCO
Crystal
Oscillator
Power
Amplifier
AGND
DACx3004 for Biasing in Land Mobile Radio
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics: Voltage Output...................5
6.6 Electrical Characteristics: Current Output...................7
6.7 Electrical Characteristics: Comparator Mode..............8
6.8 Electrical Characteristics: General..............................9
6.9 Timing Requirements: I2C Standard Mode............... 10
6.10 Timing Requirements: I2C Fast Mode.....................10
6.11 Timing Requirements: I2C Fast Mode Plus............. 10
6.12 Timing Requirements: SPI Write Operation............ 11
6.13 Timing Requirements: SPI Read and Daisy
Chain Operation (FSDO = 0)....................................... 11
6.14 Timing Requirements: SPI Read and Daisy
Chain Operation (FSDO = 1)....................................... 11
6.15 Timing Requirements: GPIO................................... 12
6.16 Timing Diagrams..................................................... 12
6.17 Typical Characteristics: Voltage Output.................. 14
6.18 Typical Characteristics: Current Output.................. 19
6.19 Typical Characteristics: Comparator....................... 24
6.20 Typical Characteristics: General............................. 25
7 Detailed Description......................................................26
7.1 Overview................................................................... 26
7.2 Functional Block Diagram......................................... 26
7.3 Feature Description...................................................27
7.4 Device Functional Modes..........................................29
7.5 Programming............................................................ 45
7.6 Register Map.............................................................53
8 Application and Implementation.................................. 71
8.1 Application Information............................................. 71
8.2 Typical Application.................................................... 71
9 Power Supply Recommendations................................74
10 Layout...........................................................................74
10.1 Layout Guidelines................................................... 74
10.2 Layout Example...................................................... 74
11 Device and Documentation Support..........................75
11.1 Receiving Notification of Documentation Updates.. 75
11.2 Support Resources................................................. 75
11.3 Trademarks............................................................. 75
11.4 Electrostatic Discharge Caution.............................. 75
11.5 Glossary.................................................................. 75
12 Mechanical, Packaging, and Orderable
Information.................................................................... 75
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (April 2021) to Revision A (December 2021)
Page
• Changed DACx3004 devices from advanced information (preview) to production data (active)........................1
2
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
FB3
1
OUT3
2
VREF
VDD
AGND
CAP
16
15
14
13
5 Pin Configuration and Functions
12
FB0
11
OUT0
OUT1
Thermal Pad
7
8
SDA/SCLK
9
A0/SDI
4
6
FB2
SCL/SYNC
10
5
3
GPIO/SDO
OUT2
FB1
Not to scale
Figure 5-1. RTE Package, 16-pin WQFN, Top View
Table 5-1. Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
Voltage feedback pin for channel 3. In voltage-output mode, connect to OUT3 for closed-loop amplifier
output. In current-output mode, keep the FB3 pin unconnected to minimize leakage current.
1
FB3
Input
2
OUT3
Output
Analog output voltage from DAC channel 3.
3
OUT2
Output
Analog output voltage from DAC channel 2.
4
FB2
Input
5
GPIO/SDO
6
SCL/SYNC
Output
I2C serial interface clock or SPI chip select input. This pin must be connected to the IO voltage using
an external pullup resistor. This pin can ramp up before VDD.
7
A0/SDI
Input
Address configuration pin for I2C or serial data input for SPI.
For A0, connect this pin to VDD, AGND, SDA, or SCL for address configuration (Section 7.5.2.2.1).
For SDI, this pin need not be pulled up or pulled down. This pin can ramp up before VDD.
8
SDA/SCLK
Input/Output
Bidirectional I2C serial data bus or SPI clock input. This pin must be connected to the IO voltage using
an external pullup resistor in the I2C mode. This pin can ramp up before VDD.
9
FB1
Input
Voltage feedback pin for channel 1. In voltage-output mode, connect to OUT1 for closed-loop amplifier
output. In current-output mode, keep the FB1 pin unconnected to minimize leakage current.
10
OUT1
Output
Analog output voltage from DAC channel 1.
11
OUT0
Output
Analog output voltage from DAC channel 0.
12
FB0
Input
13
CAP
Power
External bypass capacitor for the internal LDO. Connect a capacitor (approximately 1.5 μF) between
CAP and AGND.
14
AGND
Ground
Ground reference point for all circuitry on the device.
15
VDD
Power
Supply voltage.
16
VREF
Power
External reference input. Connect a capacitor (approximately 0.1 μF) between VREF and AGND.
Use a pullup resistor to VDD when the external reference is not used. This pin must not ramp up
before VDD. In case an external reference is used, make sure the reference ramps up after VDD.
—
Thermal Pad
Ground
Connect the thermal pad to AGND.
Voltage feedback pin for channel 2. In voltage-output mode, connect to OUT2 for closed-loop amplifier
output. In current-output mode, keep the FB2 pin unconnected to minimize leakage current.
General-purpose input/output configurable as LDAC, PD, PROTECT, RESET, SDO, and STATUS.
Input/Output For STATUS and SDO, connect the pin to the IO voltage with an external pullup resistor. If unused,
connect the GPIO pin to VDD or AGND using an external resistor. This pin can ramp up before VDD.
Voltage feedback pin for channel 0. In voltage-output mode, connect to OUT0 for closed-loop amplifier
output. In current-output mode, keep the FB0 pin unconnected to minimize leakage current.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
3
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
VDD
VREF
MAX
UNIT
Supply voltage, VDD to AGND
–0.3
6
V
Digital inputs to AGND
–0.3
VDD + 0.3
V
CAP to AGND
–0.3
1.65
V
VFBX to AGND
–0.3
VDD + 0.3
V
VOUTX to AGND
–0.3
VDD + 0.3
V
External reference, VREF to AGND
–0.3
VDD + 0.3
V
Current into any pin except the OUTx pins
–10
10
mA
TJ
Junction temperature
–40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
UNIT
±2000
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD
Positive supply voltage to ground (AGND)
1.7
5.5
V
VREF
External reference to ground (AGND)
VIH
Digital input high voltage, 1.7 V < VDD ≤ 5.5 V
1.7
VDD
V
VIL
Digital input low voltage
0.4
V
CCAP
External capacitor on CAP pin
0.5
15
μF
TA
Ambient temperature
–40
125
°C
1.62
V
6.4 Thermal Information
DACx3004
THERMAL
METRIC(1)
RTE (WQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
49
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
50
°C/W
RθJB
Junction-to-board thermal resistance
24.1
°C/W
ΨJT
Junction-to-top characterization parameter
1.1
°C/W
ΨJB
Junction-to-board characterization parameter
24.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
8.7
°C/W
(1)
4
For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.5 Electrical Characteristics: Voltage Output
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V,
DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
Resolution
INL
Integral nonlinearity(1)
DNL
Differential nonlinearity(1)
Zero-code error(4)
Zero-code error temperature
coefficient(4)
Offset
error(4) (6)
DAC63004
12
DAC53004
10
DAC63004
–4
4
DAC53004
–1
1
–1
6
12
Code 0d into DAC, internal VREF, gain = 4x, VDD = 5.5 V
6
15
Code 0d into DAC
±10
–0.75
0.3
0.75
2.7 V ≤ VDD ≤ 5.5 V, FBx pin shorted to OUTx,
DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution
–0.5
0.25
0.5
Gain error(4)
Between end-point codes: 32d to 4064d for 12-bit resolution,
8d to 1016d for 10-bit resolution
Gain-error temperature
coefficient(4)
Between end-point codes: 32d to 4064d for 12-bit resolution,
8d to 1016d for 10-bit resolution
LSB
LSB
mV
µV/°C
1.7 V ≤ VDD < 2.7 V, FBx pin shorted to OUTx,
DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution
FBx pin shorted to OUTx,
DAC code: 32d for 12-bit resolution, 8d for 10-bit resolution
Full-scale-error temperature
coefficient(4)
1
Code 0d into DAC, external reference, VDD = 5.5 V
Offset-error temperature
coefficient(4)
Full-scale error(4) (6)
Bits
%FSR
±0.0003
–0.5
0.25
%FSR/°C
0.5
±0.0008
%FSR/°C
1.7 V ≤ VDD < 2.7 V, DAC at full-scale
–1
1
2.7 V ≤ VDD ≤ 5.5 V, DAC at full-scale
–0.5
0.5
DAC at full-scale
%FSR
±0.0008
%FSR
%FSR/°C
OUTPUT
Output voltage
CL
Capacitive load(2)
Short-circuit current
Output-voltage headroom(2)
ZO
VFB dc output impedance(3)
Power supply rejection ratio (dc)
Reference tied to VDD
0
VDD
RL = infinite, phase margin = 30°
200
Phase margin = 30°
1000
VDD = 1.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
15
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
50
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD
60
To VDD (DAC output unloaded, internal reference = 1.21 V),
VDD ≥ 1.21 V ☓ gain + 0.2 V
0.2
To VDD and AGND (DAC output unloaded, external reference at
VDD, gain = 1x, the VREF pin is not shorted to VDD)
0.8
To VDD and AGND (ILOAD = 10 mA at VDD = 5.5 V,
ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD =
1.8 V), external reference at VDD, gain = 1x, the VREF pin
is not shorted to VDD
10
pF
mA
V
%FSR
DAC output enabled, internal reference (gain = 1.5x or 2x) or
external reference at VDD (gain = 1x), the VREF pin is not
shorted to VDD
400
DAC output enabled, internal VREF, gain = 3x or 4x
325
Internal VREF, gain = 2x, DAC at midscale, VDD = 5 V ±10%
V
500
600
400
485
0.25
kΩ
mV/V
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
5
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.5 Electrical Characteristics: Voltage Output (continued)
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V,
DAC reference tied to VDD, gain = 1x, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive
load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC PERFORMANCE
tsett
Output voltage settling time
Slew rate
Power-on glitch magnitude
Output-enable glitch magnitude
Vn
Output noise voltage (peak to
peak)
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR,
VDD = 5.5 V
20
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR,
VDD = 5.5 V, internal VREF, gain = 4x
25
VDD = 5.5 V
0.3
At startup (DAC output disabled)
75
µs
At startup (DAC output disabled), RL = 100 kΩ
200
DAC output disabled to enabled (DAC registers at zero scale),
RL = 100 kΩ
250
f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V
50
Internal VREF, gain = 4x, f = 0.1 Hz to 10 Hz,
DAC at midscale, VDD = 5.5 V
90
f = 1 kHz, DAC at midscale, VDD = 5.5 V
V/µs
mV
mV
µVPP
0.35
Output noise density
Internal VREF, gain = 4x, f = 1 kHz, DAC at midscale,
VDD = 5.5 V
0.9
µV/√Hz
Power supply rejection ratio (ac)(3)
Internal VREF, gain = 4x, 200-mV 50-Hz or 60-Hz sine wave
superimposed on power supply voltage, DAC at midscale
-68
dB
Code change glitch impulse
±1 LSB change around midscale (including feedthrough)
10
nV-s
Code change glitch impulse
magnitude
±1 LSB change around midscale (including feedthrough)
15
mV
Normal operation, DACs at full scale, digital pins static,
external reference at VDD but the VREF pin is not shorted to
VDD
35
POWER
IDD
(1)
(2)
(3)
(4)
(5)
(6)
6
Current flowing into VDD(4) (5)
50
µA/ch
Measured with DAC output unloaded. For external reference and internal reference VDD ≥ 1.21 x gain + 0.2 V, between end-point
codes: 32d to 4064d for 12-bit resolution, 8d to 1016d for 10-bit resolution.
Specified by design and characterization, not production tested.
Specified with 200-mV headroom with respect to reference value when internal reference is used.
Measured with DAC output unloaded.
The total power consumption is calculated by IDD x (total number of channels powered on) + (sleep-mode current).
When a DAC channel is configured in IOUT mode for long term and then switched to VOUT mode, the VOUT mode can show
parametric drift.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.6 Electrical Characteristics: Current Output
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V,
±250µA output range, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC PERFORMANCE
Resolution
INL
8
Integral nonlinearity
DNL Differential nonlinearity
Offset error
Gain error
Bits
DAC codes between 10d and 255d for current output
range of 0 µA to 25 µA, DAC codes between 0d and
255d for other ranges
–1
1
LSB
DAC codes between 10d and 255d for current output
range of 0 µA to 25 µA, DAC codes between 0d and
255d for other ranges
–1
1
LSB
DAC output range: 0 µA to 25 µA, DAC at code 10d
±1.5
DAC output ranges: 0 µA to 50 µA, 0 µA to 125 µA,
and 0 µA to 250 µA; DAC at zero-scale
5
all unipolar negative ranges, DAC at zero-scale
-5
DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and
±250 µA; DAC at midscale
±1
DAC output range: 0 µA to 25 µA, DAC codes between
10d and 255d
±1.5
DAC output ranges: 0 µA to 50 µA, 0 µA to 125 µA,
and 0 µA to 250 µA; DAC codes between 0d and 255d
±1.5
%FSR
%FSR
all unipolar negative ranges, DAC codes between 0d
and 255d
±5
DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and
±250 µA; DAC codes between 0d and 255d
±1.3
OUTPUT
Output compliance
ZO
voltage(1)
IOUT dc output impedance(2)
Power supply rejection ratio
(dc)
DAC output range: 0 µA to 25 µA, to VDD and to AGND
200
DAC output ranges: 0 µA to 50 µA, 0 µA to 125 µA,
and 0 µA to 250 µA; to VDD
400
all unipolar negative ranges, to VDD
400
DAC output ranges: ±25 µA, ±50 µA, ±125 µA, and
±250 µA; to VDD and to AGND
400
DAC at midscale, DAC output kept at VDD/2
mV
60
MΩ
DAC at midscale, output range: 0 µA to 25 µA, VDD
changed from 4.5 V to 5.5 V
0.28
DAC at midscale, all unipolar positive ranges, VDD
changed from 4.5 V to 5.5V
0.33
DAC at midscale, all unipolar negative ranges, VDD
changed from 4.5 V to 5.5V
0.83
DAC at midscale, all bipolar ranges, VDD changed from
4.5V to 5.5V
0.23
60
µs
nAPP
LSB/V
DYNAMIC PERFORMANCE
tsett
Output current settling time
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 1 LSB
at 8-bit resolution, VDD = 5.5 V, common-mode voltage
at OUTx pin is VDD/2
Vn
Output noise current (peak to
peak)
0.1 Hz to 10 Hz, DAC at midscale,
VDD = 5.5 V, ±250-µA output range
150
Output noise density
f = 1 kHz, DAC at midscale,
VDD = 5.5 V, ±250-µA output range
1
nA/√Hz
Power supply rejection ratio
(ac)(3)
±250 µA output range, 200-mV 50-Hz or 60-Hz sine
wave superimposed on power-supply voltage, DAC at
midscale
0.65
LSB/V
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
7
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.6 Electrical Characteristics: Current Output (continued)
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V,
±250µA output range, and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Normal operation, DACs at midscale, all unipolar
output ranges, digital pins static
18
24
Normal operation, DACs at full scale, ±25-µA output
range, digital pins static
42
50
Normal operation, DACs at full scale, ±50-µA output
range, digital pins static
56
70
Normal operation, DACs at full scale, ±125-µA output
range, digital pins static
98
120
Normal operation, DACs at full scale, ±250-µA output
range, digital pins static
167
200
UNIT
POWER
IDD
(1)
(2)
(3)
(4)
Current flowing into VDD(3) (4)
µA/ch
Measured between DAC codes 0d and 255d.
Specified by design and characterization, not production tested.
The current flowing into VDD does not account for the load current sourced or sinked on the OUTx pins. The VREF pin is connected to
VDD.
The total power consumption is calculated by IDD x (total number of channels powered on) + (sleep-mode current).
6.7 Electrical Characteristics: Comparator Mode
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V,
DAC reference tied to VDD, gain = 1x in voltage output mode, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to
AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
–5
0
5 mV
4
mV
STATIC PERFORMANCE
1.7 V ≤ VDD ≤ 5.5 V, DAC at midscale, comparator
input at Hi-Z, and DAC operating with external
reference
Offset error(1) (2)
Offset error time
drift(1)
VDD = 5.5 V, external reference, TA = 125°C, FBx in
Hi-Z mode, DAC at full scale and VFB at 0 V or DAC
at zero scale and VFB at 1.84 V, drift specified for 10
years of continuous operation
OUTPUT
Input voltage
VOL
Logic low output voltage
VREF connected to VDD, FBx resistor network
connected to ground
0
VDD
VREF connected to VDD, FBx resistor network
disconnected from ground
0
VDD (1/3 – 1/100)
V
ILOAD = 100 μA, output in open-drain mode
0.1
V
DAC at midscale with 10-bit resolution, FBx input at
Hi-Z, and transition step at FBx node is (VDAC – 2
LSB) to (VDAC + 2 LSB), transition time measured
between 10% and 90% of output, output current of
100 µA, comparator output configured in push-pull
mode, load capacitor at DAC output is 25 pF
10
µs
DYNAMIC PERFORMANCE
tresp
(1)
(2)
8
Output response time
Specified by design and characterization, not production tested.
This specification does not include the total unadjusted error (TUE) of the DAC.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.8 Electrical Characteristics: General
all minimum/maximum specifications at TA = –40°C to +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V,
DAC reference tied to VDD, gain = 1x in voltage output mode or ±250µA output range in current output mode, DAC output
pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) in voltage-output mode and capacitive load (CL = 200 pF to
AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.1979
1.212
1.224
V
INTERNAL REFERENCE
Initial accuracy
TA = 25°C
Reference output temperature
coefficient(1) (2)
50
ppm/°C
EXTERNAL REFERENCE
VREF input impedance(1) (3)
192
kΩ/ch
EEPROM
Endurance(1)
Data retention(1)
–40°C ≤ TA ≤ +85°C
TA = 125°C
TA = 25°C
20000
50
EEPROM programming write
cycle time(1)
Device boot-up time(1)
Cycles
1000
Years
200
Time taken from power valid (VDD ≥ 1.7 V) to output
valid state (output state as programmed in EEPROM),
0.5-µF capacitor on the CAP pin
ms
5
ms
DIGITAL INPUTS
Digital feedthrough
Voltage output mode, DAC output static at midscale,
fast mode plus, SCL toggling
20
nV-s
Pin capacitance
Per pin
10
pF
POWER-DOWN MODE
DAC in sleep mode, internal reference powered down,
external reference at 5.5 V
Current flowing into VDD(1)
IDD
Current flowing into VDD
28
DAC in sleep mode, internal reference
enabled, additional current through internal reference
10
DAC channels enabled, internal reference enabled,
additional current through internal reference per DAC
channel in voltage-output mode
12.5
DAC in deep-sleep mode, internal reference powered
down, SDO mode disabled
1.5
DAC in Hi-Z output mode, 1.7 V ≤ VDD ≤ 5.5 V
10
µA
3
HIGH-IMPEDANCE OUTPUT
VDD = 0 V, VOUT ≤ 1.5 V, decoupling capacitor between
VDD and AGND = 0.1 μF
ILEAK
Current flowing into VOUTX and
VDD = 0 V, 1.5 V < VOUT ≤ 5.5 V, decoupling capacitor
VFBX
between VDD and AGND = 0.1 μF
100 kΩ between VDD and AGND, VOUT ≤ 1.25 V, series
resistance of 10 kΩ at OUTx pin
(1)
(2)
(3)
200
nA
500
±2
µA
Specified by design and characterization, not production tested.
Measured at –40°C and +125°C and calculated the slope.
Impedances for the DAC channels are connected in parallel.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
9
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.9 Timing Requirements: I2C Standard Mode
all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and 1.7 V ≤ Vpull-up ≤ VDD V
MIN
fSCLK
SCL frequency
tBUF
Bus free time between stop and start conditions
tHDSTA
Hold time after repeated start
tSUSTA
NOM
MAX
UNIT
100
kHz
4.7
µs
4
µs
Repeated start setup time
4.7
µs
tSUSTO
Stop condition setup time
4
µs
tHDDAT
Data hold time
0
ns
tSUDAT
Data setup time
250
ns
tLOW
SCL clock low period
4700
ns
tHIGH
SCL clock high period
4000
ns
tF
Clock and data fall time
300
tR
Clock and data rise time
1000
ns
tVD_DAT
Data valid time
3.45
µs
tVD_ACK
Data valid acknowledge time
3.45
µs
ns
6.10 Timing Requirements: I2C Fast Mode
all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and 1.7 V ≤ Vpull-up ≤ VDD V
MIN
NOM
MAX
UNIT
400
kHz
fSCLK
SCL frequency
tBUF
Bus free time between stop and start conditions
1.3
µs
tHDSTA
Hold time after repeated start
0.6
µs
tSUSTA
Repeated start setup time
0.6
µs
tSUSTO
Stop condition setup time
0.6
µs
tHDDAT
Data hold time
0
ns
tSUDAT
Data setup time
100
ns
tLOW
SCL clock low period
1300
ns
tHIGH
SCL clock high period
600
tF
Clock and data fall time
300
tR
Clock and data rise time
300
ns
tVD_DAT
Data valid time
0.9
µs
tVD_ACK
Data valid acknowledge time
0.9
µs
ns
ns
6.11 Timing Requirements: I2C Fast Mode Plus
all input signals are timed from VIL to 70% of Vpull-up, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and 1.7 V ≤ Vpull-up ≤ VDD V
MIN
fSCLK
SCL frequency
tBUF
Bus free time between stop and start conditions
tHDSTA
NOM
MAX
UNIT
1
MHz
0.5
µs
Hold time after repeated start
0.26
µs
tSUSTA
Repeated start setup time
0.26
µs
tSUSTO
Stop condition setup time
0.26
µs
tHDDAT
Data hold time
0
ns
tSUDAT
Data setup time
50
ns
tLOW
SCL clock low period
0.5
µs
tHIGH
SCL clock high period
0.26
tF
Clock and data fall time
120
tR
Clock and data rise time
120
ns
tVD_DAT
Data valid time
0.45
µs
tVD_ACK
Data valid acknowledge time
0.45
µs
10
Submit Document Feedback
µs
ns
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.12 Timing Requirements: SPI Write Operation
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤ VIO ≤ 5.5 V, 1.7 V ≤ VDD ≤ 5.5 V, and –40°C ≤ TA ≤ +125°C
MIN
NOM
MAX
UNIT
50
MHz
f(SCLK)
Serial clock frequency
tSCLKHIGH
SCLK high time
9
ns
tSCLKLOW
SCLK low time
9
ns
tSDIS
SDI setup time
8
ns
tSDIH
SDI hold time
8
ns
tCSS
CS to SCLK falling edge setup time
18
ns
tCSH
SCLK falling edge to CS rising edge
10
ns
tCSHIGH
CS hight time
50
ns
tDACWAIT
Sequential DAC update wait time for same channel
2
µs
tBCASTWAIT
Broadcast DAC update wait time
2
µs
6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤ VIO ≤ 5.5 V, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and FSDO = 0
MIN
NOM
MAX
UNIT
1.25
MHz
f(SCLK)
Serial clock frequency
tSCLKHIGH
SCLK high time
350
ns
tSCLKLOW
SCLK low time
350
ns
tSDIS
SDI setup time
8
ns
tSDIH
SDI hold time
8
ns
tCSS
SYNC to SCLK falling edge setup time
400
ns
tCSH
SCLK falling edge to SYNC rising edge
400
ns
tCSHIGH
SYNC hight time
1
µs
tSDODLY
SCLK rising edge to SDO falling edge, IOL ≤ 5 mA, CL = 20 pF.
300
ns
6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤ VIO ≤ 5.5 V, 1.7 V ≤ VDD ≤ 5.5 V, –40°C ≤ TA ≤ +125°C, and FSDO = 1
MIN
NOM
MAX
UNIT
2.5
MHz
f(SCLK)
Serial clock frequency
tSCLKHIGH
SCLK high time
175
ns
tSCLKLOW
SCLK low time
175
ns
tSDIS
SDI setup time
8
ns
tSDIH
SDI hold time
8
ns
tCSS
SYNC to SCLK falling edge setup time
300
ns
tCSH
SCLK falling edge to SYNC rising edge
300
ns
tCSHIGH
SYNC hight time
tSDODLY
SCLK rising edge to SDO falling edge, IOL ≤ 5 mA, CL = 20 pF.
1
µs
300
ns
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
11
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.15 Timing Requirements: GPIO
all input signals are specified with tr = tf = 1 V/ns (10% to 90% of VIO) and timed from a voltage level of (VIL + VIH) / 2,
1.7 V ≤ VIO ≤ 5.5 V, 1.7 V ≤ VDD ≤ 5.5 V, and –40°C ≤ TA ≤ +125°C
MIN
GPI high time(1)
tGPIHIGH
NOM
MAX
2
time(1)
UNIT
µs
tGPILOW
GPI low
tGPAWGD
LDAC falling edge to DAC update delay(2)
tCS2LDAC
SYNC rising edge to LDAC falling edge
1
µs
tSTP2LDAC
I2C stop bit rising edge to LDAC falling edge
1
µs
tLDACW
LDAC low time
2
µs
(1)
2
µs
2
µs
The SCL, SDA, A0, and A1 pins can be configured as GPIOs that perform different channel-specific or independent operations. The
actual response time of the GPIO is determined by the delay provided by the configured function and the settling time of the DAC.
The GPIOs can be configured as channel-specific or global LDAC function.
(2)
6.16 Timing Diagrams
Low byte ACK cycle
tR
tLOW
tF
SCL
tHDSTA
tHIGH
tHDDAT
tSUSTA
tSUSTO
tSUDAT
tHDSTA
SDA
tBUF
P
S
S
P
Figure 6-1. I2C Timing Diagram
tCSHIGH
tCSS
tCSH
SYNC
tSCLKLOW
SCLK
tSCLKHIGH
tSDIS
SDI
tSDIH
Bit 23
Bit 1
Bit 0
GPIO/
LDAC
tCS2LDAC tLDACW
Figure 6-2. SPI Write Timing Diagram
12
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
tCSHIGH
tCSS
tCSH
SYNC
tSCLKLOW tSCLKHIGH
SCLK
FIRST READ COMMAND
SDI
Bit 23
tSDIS
Bit 22
ANY COMMAND
Bit 0
Bit 23
Bit 1
Bit 0
Bit 23
Bit 1
Bit 0
tSDIH
SDO
FSDO = 0
tSDODLY
DATA FROM FIRST READ COMMAND
SDO
FSDO = 1
Bit 23
Bit 1
tSDODZ
Bit 0
tSDODLY
DATA FROM FIRST READ COMMAND
Figure 6-3. SPI Read Timing Diagram
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
13
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.17 Typical Characteristics: Voltage Output
4
4
3.2
3.2
2.4
2.4
1.6
0.8
0
-0.8
-1.6
Channel
Channel
Channel
Channel
-2.4
-3.2
-4
32
544
1056
1568
2080
Code
2592
3104
0
1
2
3
Voltage Output INL (LSB)
Voltage Output INL (LSB)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
1.6
0.8
0
-0.8
-1.6
Channel
Channel
Channel
Channel
-2.4
-3.2
-4
32
3616 4064
544
1056
1568
2080
Code
2592
3104
0
1
2
3
3616 4064
Internal reference, gain = 4x
Figure 6-5. Voltage Output INL vs Digital Input Code
4
4
3.2
3.2
2.4
2.4
1.6
0.8
0
-0.8
-1.6
CH0
CH1
CH2
CH3
-2.4
-3.2
-4
-40
-25
-10
5
MAX
MAX
MAX
MAX
20
35
50
65
Temperature (C)
80
CH0
CH1
CH2
CH3
95
MIN
MIN
MIN
MIN
Voltage Output INL (LSB)
Voltage Output INL (LSB)
Figure 6-4. Voltage Output INL vs Digital Input Code
0
-0.8
-1.6
CH0
CH1
CH2
CH3
-2.4
-4
1.8
110 125
Figure 6-6. Voltage Output INL vs Temperature
2.725
MAX
MAX
MAX
MAX
3.65
Supply Voltage (V)
CH0
CH1
CH2
CH3
MIN
MIN
MIN
MIN
4.575
5.5
Figure 6-7. Voltage Output INL vs Supply Voltage
1
0.6
0
1
2
3
0.4
0.2
0
-0.2
-0.4
-0.6
Channel
Channel
Channel
Channel
0.8
Voltage Output DNL (LSB)
Channel
Channel
Channel
Channel
0.8
Voltage Output DNL (LSB)
0.8
-3.2
1
0.6
0
1
2
3
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
-1
32
1.6
544
1056
1568
2080
Code
2592
3104
3616 4064
-1
32
544
1056
1568
2080
Code
2592
3104
3616 4064
Internal reference, gain = 4x
Figure 6-8. Voltage Output DNL vs Digital Input Code
14
Figure 6-9. Voltage Output DNL vs Digital Input Code
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.17 Typical Characteristics: Voltage Output (continued)
1
1
0.8
0.8
0.6
0.6
0.4
0.2
0
-0.2
-0.4
CH0
CH1
CH2
CH3
-0.6
-0.8
-1
-40
-25
-10
5
MAX
MAX
MAX
MAX
20
35
50
65
Temperature (C)
80
CH0
CH1
CH2
CH3
95
MIN
MIN
MIN
MIN
Voltage Output DNL (LSB)
Voltage Output DNL (LSB)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
0.4
0.2
0
-0.2
-0.4
CH0
CH1
CH2
CH3
-0.6
-0.8
-1
1.8
110 125
Figure 6-10. Voltage Output DNL vs Temperature
2.725
MAX
MAX
MAX
MAX
3.65
Supply Voltage (V)
CH0
CH1
CH2
CH3
MIN
MIN
MIN
MIN
4.575
5.5
Figure 6-11. Voltage Output DNL vs Supply Voltage
1.5
Voltage Output TUE (%FSR)
1.2
0.9
0.6
0.3
0
-0.3
-0.6
Channel
Channel
Channel
Channel
-0.9
-1.2
0
1
2
3
-1.5
0
512
1024
1536
2048
Code
2560
3072
3584
4095
Internal reference, gain = 4x
Figure 6-13. Voltage Output TUE vs Digital Input Code
1.5
1.5
1.2
1.2
0.9
0.6
0.3
0
-0.3
-0.6
Channel
Channel
Channel
Channel
-0.9
-1.2
-1.5
-40
-25
-10
5
20
35
50
65
Temperature (C)
80
95
0
1
2
3
110 125
Voltage Output TUE (%FSR)
Voltage Output TUE (%FSR)
Figure 6-12. Voltage Output TUE vs Digital Input Code
0.9
0.6
0.3
0
-0.3
-0.6
Channel
Channel
Channel
Channel
-0.9
-1.2
-1.5
1.8
2.725
DAC channels at midscale
Figure 6-14. Voltage Output TUE vs Temperature
3.65
Supply Voltage (V)
4.575
0
1
2
3
5.5
DAC channels at midscale
Figure 6-15. Voltage Output TUE vs Supply Voltage
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
15
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.17 Typical Characteristics: Voltage Output (continued)
0.5
0.5
0.4
0.4
Voltage Output Gain Error (%FSR)
Voltage Output Offset Error (%FSR)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
0.3
0.2
0.1
0
-0.1
-0.2
Channel
Channel
Channel
Channel
-0.3
-0.4
-0.5
-40
-25
-10
5
20
35
50
65
Temperature (C)
80
95
0
1
2
3
0.3
0.2
0.1
0
-0.1
-0.2
-0.4
-0.5
-40
110 125
Figure 6-16. Voltage Output Offset Error vs Temperature
Channel
Channel
Channel
Channel
-0.3
-25
-10
5
20
35
50
65
Temperature (C)
80
95
0
1
2
3
110 125
Figure 6-17. Voltage Output Gain Error vs Temperature
2.76
LDAC (1 V/div)
VOUT (1 LSB/div)
2.758
Voltage Output (V)
2.756
2.754
2.752
2.75
2.748
2.746
2.744
Channel 0
Channel 1
2.742
2.74
-5
-3.75
-2.5
-1.25
0
1.25
Load Current (mA)
Channel 2
Channel 3
2.5
3.75
5
0
10
20
30
40
50
Time (s)
DAC channels at midscale
Figure 6-19. Voltage Output Code-to-Code Glitch - Rising Edge
Figure 6-18. Voltage Output vs Load Current
LDAC (1 V/div)
VOUT (1 LSB/div)
Trigger (1 V/div)
VOUT (1 V/div)
Settling Band (+10% FSR)
Settling Band (-10% FSR)
0
10
20
30
40
50
0
10
20
30
40
Time (s)
Time (s)
Figure 6-20. Voltage Output Code-to-Code Glitch - Falling Edge
Figure 6-21. Voltage Output Setting Time - Rising Edge
50
Zero scale to full scale swing
16
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.17 Typical Characteristics: Voltage Output (continued)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
Trigger (1 V/div)
VOUT (1 V/div)
Settling Band (+10% FSR)
Settling Band (-10% FSR)
VDD (1 V/div)
VOUT (15 mV/div)
0
10
20
30
40
50
0
200
400
600
Time (s)
CH0
CH1
CH2
CH3
VDD (1 V/div)
VOUT (1 mV/div)
400
600
800
1000
Time (s)
1200
1400
1600
0
5
2
1.8
2.4
1.6
Noise Density (V/Hz)
Noise Density (V/Hz)
3
2.7
2.1
1.8
1.5
1.2
0.9
V/div)
V/div)
mV/div)
V/div)
10
15
20
25
Time (s)
30
35
40
1.4
1.2
1
0.8
0.6
0.6
0.4
0.3
0.2
500 1000
Frequency (Hz)
(1
(1
(1
(1
Figure 6-25. Voltage Output Channel-to-Channel Crosstalk
Figure 6-24. Voltage Output Power-Off Glitch
2030 50 100 200
1600
Channel 2 is victim, all other channels are aggressors
DAC at zero scale
0
10
1400
Figure 6-23. Voltage Output Power-On Glitch
Figure 6-22. Voltage Output Setting Time - Falling Edge
200
1200
DAC in Hi-Z power-down mode
Full scale to zero scale swing
0
800
1000
Time (s)
10000
100000
0
10
2030 50 100 200
500 1000
Frequency (Hz)
10000
100000
Internal reference, gain = 4x
Figure 6-26. Voltage Output Noise Density
Figure 6-27. Voltage Output Noise Density
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
17
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.17 Typical Characteristics: Voltage Output (continued)
35
30
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
-35
25
20
15
Noise Voltage (V)
Noise Voltage (V)
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, and DAC outputs unloaded (unless
otherwise noted)
10
5
0
-5
-10
-15
-20
-25
0
1
2
3
4
5
6
Time (s)
7
8
9
10
0
1
2
3
Internal reference, gain = 4x, f = 0.1 Hz to 10 Hz
4
5
6
Time (s)
7
8
9
10
f = 0.1 Hz to 10 Hz
Figure 6-28. Voltage Output Flicker Noise
Figure 6-29. Voltage Output Flicker Noise
AC Power-Supply Rejection Ratio (dB)
10
0
-10
-20
-30
-40
-50
-60
-70
10
2030 50 100 200
500 1000
Frequency (Hz)
10000
100000
Figure 6-30. Voltage Output AC PSRR vs Frequency
18
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.18 Typical Characteristics: Current Output
1
1
0.8
0.8
0.6
0.6
0.4
0.2
0
-0.2
-0.4
Channel
Channel
Channel
Channel
-0.6
-0.8
0
1
2
3
Current Output INL (LSB)
Current Output INL (LSB)
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
0.4
0.2
0
-0.2
-0.4
Channel
Channel
Channel
Channel
-0.6
-0.8
-1
0
1
2
3
-1
0
32
64
96
128
Code
160
192
224
255
0
32
64
96
128
Code
160
192
224
255
Output range: 0 μA to 250 μA
Figure 6-32. Current Output INL vs Digital Input Code
1
1
0.8
0.8
0.6
0.6
0.4
0.2
0
-0.2
-0.4
Channel
Channel
Channel
Channel
-0.6
-0.8
0
1
2
3
Current Output INL (LSB)
Current Output INL (LSB)
Figure 6-31. Current Output INL vs Digital Input Code
32
64
96
128
Code
160
192
224
0.2
0
-0.2
-0.4
CH0
CH1
CH2
CH3
-0.6
-0.8
-1
0
0.4
-1
-40
255
-25
-10
5
MAX
MAX
MAX
MAX
20
35
50
65
Temperature (C)
CH0
CH1
CH2
CH3
80
95
MIN
MIN
MIN
MIN
110 125
Output range: 0 μA to –240 μA
Figure 6-34. Current Output INL vs Temperature
1
1
0.8
0.8
0.6
0.6
0.4
0.2
0
-0.2
-0.4
CH0
CH1
CH2
CH3
-0.6
-0.8
-1
1.8
2.725
MAX
MAX
MAX
MAX
3.65
Supply Voltage (V)
CH0
CH1
CH2
CH3
MIN
MIN
MIN
MIN
4.575
Figure 6-35. Current Output INL vs Supply Voltage
5.5
Current Output DNL (LSB)
Current Output INL (LSB)
Figure 6-33. Current Output INL vs Digital Input Code
0.4
0.2
0
-0.2
-0.4
Channel
Channel
Channel
Channel
-0.6
-0.8
0
1
2
3
-1
0
32
64
96
128
Code
160
192
224
255
Figure 6-36. Current Output DNL vs Digital Input Code
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
19
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.18 Typical Characteristics: Current Output (continued)
1
1
0.8
0.8
0.6
0.6
0.4
0.2
0
-0.2
-0.4
Channel
Channel
Channel
Channel
-0.6
-0.8
0
1
2
3
Current Output DNL (LSB)
Current Output DNL (LSB)
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
0.4
0.2
0
-0.2
-0.4
Channel
Channel
Channel
Channel
-0.6
-0.8
-1
0
1
2
3
-1
0
32
64
96
128
Code
160
192
224
255
0
32
Output range: 0 μA to 250 μA
64
96
128
Code
160
192
224
255
Output range: 0 μA to –240 μA
Figure 6-37. Current Output DNL vs Digital Input Code
Figure 6-38. Current Output DNL vs Digital Input Code
1
Current Output DNL (LSB)
0.8
0.6
0.4
0.2
0
-0.2
-0.4
CH0
CH1
CH2
CH3
-0.6
-0.8
-1
-40
-25
-10
5
MAX
MAX
MAX
MAX
20
35
50
65
Temperature (C)
CH0
CH1
CH2
CH3
80
95
MIN
MIN
MIN
MIN
110 125
Figure 6-40. Current Output DNL vs Supply Voltage
2
8
1.6
6.4
1.2
0.8
0.4
0
-0.4
-0.8
Channel
Channel
Channel
Channel
-1.2
-1.6
0
1
2
3
Current Output TUE (%FSR)
Current Output TUE (%FSR)
Figure 6-39. Current Output DNL vs Temperature
4.8
3.2
1.6
0
-1.6
-3.2
Channel
Channel
Channel
Channel
-4.8
-6.4
0
1
2
3
-8
-2
0
32
64
96
128
Code
160
192
224
255
0
32
64
96
128
Code
160
192
224
255
Output range: 0 μA to 250 μA
Figure 6-41. Current Output TUE vs Digital Input Code
20
Figure 6-42. Current Output TUE vs Digital Input Code
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.18 Typical Characteristics: Current Output (continued)
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
10
2
Current Output TUE (%FSR)
6
0
1
2
3
4
2
0
-2
-4
-6
1.6
Current Output TUE (%FSR)
Channel
Channel
Channel
Channel
8
1.2
0.8
0.4
0
-0.4
-0.8
Channel
Channel
Channel
Channel
-1.2
-1.6
-8
-2
-40
-10
0
32
64
96
128
Code
160
192
224
255
-25
-10
Output range: 0 μA to –240 μA
1.5
1.2
1.2
0.8
0.4
0
-0.4
-0.8
-1.2
Channel 0
Channel 1
3.65
Supply Voltage (V)
Channel 2
Channel 3
4.575
Current Output Offset Error (%FSR)
Current Output TUE (%FSR)
2
2.725
80
95
110 125
Figure 6-44. Current Output TUE vs Temperature
1.6
-2
1.8
20
35
50
65
Temperature (C)
DAC channels at midscale
Figure 6-43. Current Output TUE vs Digital Input Code
-1.6
5
0
1
2
3
0.9
0.6
0.3
0
-0.3
-0.6
Channel
Channel
Channel
Channel
-0.9
-1.2
-1.5
-40
5.5
-25
-10
5
20
35
50
65
Temperature (C)
80
95
0
1
2
3
110 125
DAC channels at midscale
Figure 6-46. Current Output Offset Error vs Temperature
1.5
1000
1.2
800
0.9
600
0.6
400
Current Output (A)
Current Output Gain Error (%FSR)
Figure 6-45. Current Output TUE vs Supply Voltage
0.3
0
-0.3
-0.6
Channel
Channel
Channel
Channel
-0.9
-1.2
-1.5
-40
-25
-10
5
20
35
50
65
Temperature (C)
80
95
0
1
2
3
110 125
Figure 6-47. Current Output Gain Error vs Temperature
200
0
-200
-400
CH0,
CH1,
CH2,
CH3,
-600
-800
DAC Code
DAC Code
DAC Code
DAC Code
=
=
=
=
0
0
0
0
CH0,
CH1,
CH2,
CH3,
DAC Code
DAC Code
DAC Code
DAC Code
=
=
=
=
255
255
255
255
-1000
0
0.5
1
1.5
2
2.5
3
3.5
Load Voltage (V)
4
4.5
5
5.5
Figure 6-48. Current Output vs Load Voltage
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
21
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.18 Typical Characteristics: Current Output (continued)
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
Trigger (1 V/div)
IOUT (Zoomed, 10A/div)
Settling Band (−1 LSB)
Settling Band (+1 LSB)
Trigger (1 V/div)
IOUT (Zoomed, 10 A/div)
Settling Band (−1 LSB)
Settling Band (+1 LSB)
0
10
20
30
40
50
0
10
20
30
40
50
Time (s)
Time (s)
Figure 6-49. Current Output Setting Time, Rising Edge
Figure 6-50. Current Output Setting Time, Falling Edge
VDD ( 1 V/div)
IOUT (40 A/div)
VDD (1 V/div)
IOUT (20 A/div)
0
500
1000
1500
Time (s)
2000
2500
3000
0
500
1000
DAC at mid scale (0 μA) stored in EEPROM
0
100
200
300
400 500 600
Time (s)
700
(100 A/div)
(100 A/div)
(100 A/div)
(0.4 A/div)
800
2500
3000
Figure 6-52. Current Output Power-Off Glitch
AC Power-Supply Rejection Ratio (LSB/V)
1
2
3
4
2000
DAC at mid scale (0 μA)
Figure 6-51. Current Output Power-On Glitch
Channel
Channel
Channel
Channel
1500
Time (s)
500
200
100
50
20
10
5
2
1
0.5
0.2
10
20 30 50
900 1000
100 200
500 1000 2000
Frequency (Hz)
10000
30000
Channel 4 is victim, all other channels are aggressors
Figure 6-53. Current Output Channel-to-Channel Crosstalk
22
Figure 6-54. Current Output AC PSRR vs Frequency
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.18 Typical Characteristics: Current Output (continued)
at TA = 25°C, VDD = 5.5 V, output range: ±250 μA (unless otherwise noted)
2
1
1.8
1.6
Noise Density (nA/Hz)
Noise Density (nA/Hz)
0.8
0.6
0.4
1.4
1.2
1
0.8
0.6
0.4
0.2
0.2
0
10
2030 50 100 200
500 1000
Frequency (Hz)
10000
0
10
100000
2030 50 100 200
500 1000
Frequency (Hz)
10000
100000
Output range: 0 μA to 250 μA
Figure 6-55. Current Output Noise Density
Figure 6-56. Current Output Noise Density
30
25
Noise Current (nA)
20
15
10
5
0
-5
-10
-15
-20
-25
0
1
2
Output range: 0 μA to 250 μA, f = 0.1 Hz to 10 Hz
Figure 6-57. Current Output Flicker Noise
3
4
5
6
Time (s)
7
8
9
10
f = 0.1 Hz to 10 Hz
Figure 6-58. Current Output Flicker Noise
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
23
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.19 Typical Characteristics: Comparator
at TA = 25°C, VDD = 5.5 V, external reference = 5.5 V, gain = 1x, 12-bit resolution, FBx pin in Hi-Z mode, and DAC outputs
unloaded (unless otherwise noted)
VOUT (1 V/div)
VFB (1 LSB/div)
0
2
4
6
8
10
VOUT (1 V/div)
VFB (1 LSB/div)
0
2
4
Time (s)
6
8
10
Time (s)
Comparator output in push-pull mode
Comparator output in push-pull mode
Figure 6-59. Comparator Response Time:
Low‑to‑High Transition
Figure 6-60. Comparator Response Time:
High‑to‑Low Transition
5
Comparator Offset Error (mV)
4
3
2
1
0
-1
-2
Channel
Channel
Channel
Channel
-3
-4
-5
-40
-25
-10
5
20
35
50
65
Temperature (C)
80
95
0
1
2
3
110 125
Figure 6-61. Comparator Offset Error vs Temperature
24
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
6.20 Typical Characteristics: General
1.22
1.21314
1.219
1.213126
1.218
1.213112
Internal Reference (V)
Internal Reference (V)
at TA = 25°C, VDD = 5.5 V, and DAC outputs unloaded (unless otherwise noted)
1.217
1.216
1.215
1.214
1.213
1.213098
1.213084
1.21307
1.213056
1.213042
1.212
1.213028
1.211
1.213014
1.21
-40
-25
-10
5
20
35
50
65
Temperature (C)
80
95
1.213
1.8
110 125
2.725
5.5
Figure 6-63. Internal Reference vs Supply Voltage
Figure 6-62. Internal Reference vs Temperature
30
24
21
18
15
12
9
6
VDD = 1.8 V
VDD = 3.3 V
VDD = 5.5 V
3
-25
-10
5
20
35
50
65
Temperature (C)
80
95
110 125
Deep-Sleep Mode PD Current (A)
3
27
Sleep Mode PD Current (A)
4.575
Internal reference
Internal reference
0
-40
3.65
Supply Voltage (V)
VDD = 1.8 V
VDD = 3.3 V
VDD = 5.5 V
2.5
2
1.5
1
0.5
0
-40
-25
-10
20
35
50
65
Temperature (C)
80
95
110 125
Deep-sleep mode
Sleep mode, internal reference disabled
Figure 6-64. Power-Down Current vs Temperature
5
Figure 6-65. Power-Down Current vs Temperature
5
Boot-up Time (ms)
4
3
2
1
0
0.5
3.5
6.5
9.5
12.5
External Capacitance on CAP Pin (F)
15
Figure 6-66. Boot-up Time vs Capacitance on CAP pin
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
25
DAC63004, DAC53004
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
www.ti.com
7 Detailed Description
7.1 Overview
The 12-bit DAC63004 and 10-bit DAC53004 (DACx3004) are a pin-compatible family of ultra-low-power,
quad-channel, buffered voltage-output and current-output, smart digital-to-analog converters (DACs). The DAC
channels are independently configurable as voltage output or current output. The DAC outputs change to Hi-Z
when VDD is off; a feature useful in voltage-margining applications. These smart DACs contain nonvolatile
memory (NVM), an internal reference, automatically detectable I2C and SPI interface, PMBus-compatibility in
I2C mode, a force-sense output, and a general-purpose input/output. These devices support Hi-Z power-down
modes by default, which can also be configured to 10 kΩ-GND or 100 kΩ-GND using the NVM. The DACx3004
have a power-on-reset (POR) circuit that makes sure all the registers start with default or user-programmed
settings using NVM. The DACx3004 operate with either an internal reference, external reference, or with a
power supply as the reference, and provide a full-scale output between 1.8 V and 5.5 V.
The DACx3004 devices support I2C standard mode (100 kbps), fast mode (400 kbps), and fast mode plus
(1 Mbps). The I2C interface can be configured with four target addresses using the A0 pin. These devices also
support specific PMBus commands such as turn on/off, margin high or low, and more. SPI mode supports
a three-wire interface by default, with up to a 50-MHz SCLK input. The GPIO input can be configured as
SDO in the NVM for SPI read capability. The GPIO input can also be configured as FAULT-DUMP, LDAC,
PD, PROTECT, RESET, and STATUS functions. These devices support deep-sleep mode in addition to sleep
(power-down) mode. Deep-sleep mode uses the GPIO pin for power-down and wake up, in which the device
draws a very-low power-down current of 3 μA. Together with ultra-low-power operation, the DACx3004 are
designed for battery-operated applications, such as land mobile radios, medical pulse oximeters, and laptops.
The DACx3004 also include digital slew rate control, and support standard waveform generation such as sine
and cosine, triangular, and sawtooth. These devices can generate pulse-width modulation (PWM) output with
the combination of the triangular or sawtooth waveform and the FB pin. The force-sense outputs of the DAC
channels can be used as programmable comparators. Comparator mode allows programmable hysteresis,
latching comparator, and window comparator. These features enable the DACx3004 to go beyond the limitations
of a conventional DAC that depends on a processor to function. As a result of processor-less operation and the
smart feature set, the DACx3004 are called smart DACs.
7.2 Functional Block Diagram
Figure 7-1. Functional Block Diagram
26
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.3 Feature Description
7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
The DACx3004 devices consist of string architecture with a voltage-output amplifier and an external FB pin and
voltage-to-current converter for each channel. Section 7.2 shows the DAC architecture within the block diagram,
which operates from a 1.8-V to 5.5-V power supply. The DAC has an internal voltage reference of 1.21 V. There
is an option to select an external reference on the VREF pin or the power supply as a reference. The voltage
output mode uses one of these three reference options. The current output mode uses an internal band gap to
generate the current outputs. Both the voltage- and current-output modes support multiple programmable output
ranges.
The DACx3004 devices support Hi-Z output when VDD is off, maintaining very low leakage current at the
output pins with up to 1.25 V of forced voltage. The DAC output pin also starts up in high-impedance mode
by default, making these devices an excellent choice for voltage margining and scaling applications. To change
the power-up mode to 10 kΩ-GND or 100 kΩ-GND, program the corresponding VOUT-PDN-X field in the
COMMON-CONFIG register and load these bits in the device NVM.
The DACx3004 devices support an independent comparator mode for each channel. The respective FBx pins
act as the inputs for the comparator. The DAC architecture supports inversion of the comparator output using
register settings. The comparator outputs can be push-pull or open-drain. The comparator mode supports
programmable hysteresis using margin-high and margin-low register fields, latching comparator, and window
comparator. The comparator outputs are accessible internally by the device.
The DACx3004 devices include a smart feature set to enable processor-less operation and high-integration. The
NVM enables a predictable start-up. The GPIO triggers the DAC output without the I2C interface in the absence
of a processor or when the processor or software fails. The integrated functions and the FBx pin enable PWM
output for control applications. The FBx pin enables this device to be used as a programmable comparator. The
digital slew-rate control and the Hi-Z power-down modes enable a hassle-free voltage margining and scaling
function.
7.3.2 Digital Input/Output
The DACx3004 have four digital IO pins that include I2C, SPI, PMBus, and GPIO interfaces. These devices
automatically detect I2C and SPI protocols at the first successful communication after power-on, and then
connect to the detected interface. After an interface protocol is connected, any change in the protocol is ignored.
The I2C interface uses the A0 pin to select from among four address options. The SPI interface is a 3-wire
interface by default. No readback capability is available in this mode. The GPIO pin can be configured in the
register map and then programmed in to the NVM as the SDO pin. The SPI readback mode is slower than the
write mode. The programming interface pins are:
• I2C: SCL, SDA, A0
• SPI: SCLK, SDI, SYNC, SDO/GPIO
The GPIO can be configured as multiple functions other than SDO. These are LDAC, PD, STATUS, PROTECT,
FAULT-DUMP, and RESET. All the digital pins are open-drain when used as outputs. Therefore, all the output
pins must be pulled up to the desired IO voltage using external resistors.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
27
DAC63004, DAC53004
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
www.ti.com
7.3.3 Nonvolatile Memory (NVM)
The DACx3004 contain nonvolatile memory (NVM) bits. These memory bits are user programmable and
erasable, and retain the set values in the absence of a power supply. All the register bits, as shown in the
highlighted gray cells in Table 7-20, can be stored in the NVM by setting NVM-PROG = 1 in the COMMONTRIGGER register. The NVM-PROG is an autoresetting bit. The default values for all the registers in the
DACx3004 are loaded from NVM as soon as a POR event is issued.
The DACx3004 also implement NVM-RELOAD bit in the COMMON-TRIGGER register. Set this bit to 1 for
the device to start an NVM-reload operation. After completion, the device autoresets the NVM-RELOAD bit to
0. During the NVM write or reload operation, all read/write operations to the device are blocked. Section 6.8
provides the timing specification for the NVM write cycle. The processor must wait for the specified duration
before resuming any read or write operation on the SPI or I2C interface.
7.3.4 Power Consumption
The power consumption of the DACx3004 in sleep mode and deep-sleep mode are provided in Section 6.20. In
normal operation, the total power consumption of the device depends on the number of channels powered on
and the output mode of each channel (voltage or current). In current-output mode, the IDD also depends on the
output range. The IDD calculation excludes the load current. For example, in the ±250 μA output mode with a
DAC setting of +125 μA, the total current drawn through the VDD pin is the total IDD plus 125 μA. The total IDD in
normal operation can be calculated using Equation 1.
where:
•
•
•
PNORMAL_MODE = VDD × IDD_SLEEP + IDD_REF + ∑3X = 0 VDD × IDD_X
(1)
IDD_SLEEP is the current through VDD in sleep mode when all the channels and internal reference are powered
down.
IDD_REF is the reference current, which is:
– either the current drawn by the reference input impedance when VDD is used as reference
– or the current drawn by the internal reference, if enabled
IDD_X is the current through VDD for every powered-on channel-X.
Note
When an external reference is used, the current is calculated mainly as the current sourced from
the external reference, which is equal to the reference voltage divided by the input impedance of the
VREF pin.
28
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.4 Device Functional Modes
7.4.1 Voltage-Output Mode
The voltage-output mode for each DAC channel can be entered by selecting the power-up option in the VOUTPDN-X fields in the COMMON-CONFIG register and simultaneously powering down the current output option
for the respective channels using the IOUT-PDN-X bits in the same register. Short the OUTx and FBx pins of
respective channels externally for closed-loop amplifier output. An open FBx pin saturates the amplifier output.
To achieve the desired voltage output, select the correct reference option, select the amplifier gain for the
required output range, and program the DAC code in the DAC-X-DATA register of the respective channels.
7.4.1.1 Voltage Reference and DAC Transfer Function
There are three voltage reference options possible with the DACx3004: internal reference, external reference,
and the power supply as reference, as shown in Figure 7-2. The DAC transfer function in the voltage-output and
comparator modes changes based on the voltage reference selection.
VDD
VREF
EN-INT-REF
Internal
Reference
DIS-MODE-IN
MUX
VOUT-GAIN-X
IOUT-RANGE-X
VOUT-PDN-X
DAC Ladder
Digital
IO
IOUT-PDN-X
VOUT-PDN-X
+
OUTx
–
10k/100k
IOUT-PDN-X
Internal
Bandgap
FBx
R1
R2
CMP-X-HIZ-IN-DIS or
VOUT-PDN-X (Hi-Z)
AGND
Figure 7-2. Voltage Reference Selection and Power-Down Logic
7.4.1.1.1 Internal Reference
The DACx3004 contain an internal reference that is disabled by default. To enable the internal reference, write
1 to bit EN-INT-REF in the COMMON-CONFIG register. The internal reference generates a fixed 1.21-V voltage
(typical). Use the VOUT-GAIN-X bit in the DAC-X-VOUT-CMP-CONFIG register to achieve gains of 1.5x, 2x, 3x,
or 4x for the DAC output voltage (VOUT). Equation 2 shows DAC transfer function using the internal reference.
where:
•
•
•
•
VOUT = DAC_DATA
× VREF × GAIN
N
(2)
2
N is the resolution in bits, 10 (DAC53004), or 12 (DAC63004).
DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA bit in the
DAC-X-DATA register. DAC_DATA ranges from 0 to 2N – 1.
VREF is the internal reference voltage = 1.21 V (typical).
GAIN = 1.5x, 2x, 3x, or 4x, based on VOUT-X-GAIN bits.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
29
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.4.1.1.2 External Reference
By default, the DACx3004 operate from an external reference input. The external reference option can also be
selected by configuring the VOUT-GAIN-X field in the DAC-X-VOUT-CMP-CONFIG register appropriately. Write
1 to the DIS-MODE-IN bit in the DEVICE-MODE-CONFIG register to minimize IDD. The external reference can
be between 1.7 V and VDD. Equation 3 shows DAC transfer function when the external reference is used. The
gain at the output stage of the DAC is always 1x in the external reference mode.
Note
The external reference must be less than VDD in both transient and steady-state conditions.
Therefore, the external reference must ramp up after VDD and ramp down before VDD.
where:
•
•
•
VOUT = DAC_DATA
× VREF
N
(3)
2
N is the resolution in bits, 10 (DAC53004), or 12 (DAC63004).
DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA field in the
DAC-X-DATA register. DAC_DATA ranges from 0 to 2N – 1.
VREF is the external reference voltage.
7.4.1.1.3 Power-Supply as Reference
The DACx3004 can operate with the power-supply pin (VDD) as a reference. Equation 4 shows DAC transfer
function when the power-supply pin is used as reference. The gain at the output stage is always 1x.
where:
•
•
•
•
VOUT = DAC_DATA
× VDD
N
(4)
2
N is the resolution in bits, either 10 (DAC53004), or 12 (DAC63004).
DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA bit in the
DAC-X-DATA register.
DAC_DATA ranges from 0 to 2N – 1.
VDD is used as the DAC reference voltage.
7.4.2 Current-Output Mode
To enter current-output mode for each DAC channel, disable the respective IOUT-PDN-X bits in the COMMONCONFIG register, and set the respective VOUT-PDN-X bits in the same register to Hi-Z power-down mode.
Select the desired current-output range by writing to the IOUT-RANGE-X bit in the DAC-X-IOUT-MISC-CONFIG
register. To minimize leakage in current-output mode, disconnect the FBx pin. For the best power-on glitch
performance, program the NVM with IOUT mode using the smallest output range before powering on the output
channel, and then immediately program the DAC code and desired output range. The transfer function of the
output current is shown in Equation 5.
where:
•
•
•
30
IOUT =
DAC_DATA × IMAX − IMIN
+ IMIN
28
(5)
DAC_DATA is the decimal equivalent of the binary code that is loaded to the DAC-X-DATA bit as specified in
Section 7.6.8. DAC_DATA ranges from 0 to 255.
IMAX is the signed maximum current in the IOUT-RANGE-X setting as specified in Section 7.6.5.
IMIN is the signed minimum current in the IOUT-RANGE-X setting as specified in Section 7.6.5.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.4.3 Comparator Mode
All the DAC channels can be configured as programmable comparators in the voltage-output mode. To enter
the comparator mode for a channel, write 1 to the CMP-X-EN bit in the respective DAC-X-VOUT-CMP-CONFIG
register. The comparator output can be configured as push-pull or open-drain using the CMP-X-OD-EN bit. To
enable the comparator output on the output pin, write 1 to the CMP-X-OUT-EN bit. To invert the comparator
output, write 1 to the CMP-X-INV-EN bit. The FBx pin has a finite impedance. By default, the FBx pin is in the
high-impedance mode. To disable high-impedance on the FBx pin, write 1 to the CMP-X-HIZ-IN-DIS bit. Table
7-1 shows the comparator output at the pin for different bit settings.
Note
In the Hi-Z input mode, the comparator input range is limited to:
• For GAIN = 1x, 1.5x, or 2x: VFB ≤ (VREF × GAIN) / 3
• For GAIN = 3x, or 4x: VFB ≤ (VREF × GAIN) / 6
Any higher input voltage is clipped.
Table 7-1. Comparator Output Configuration
CMP-X-EN
CMP-X-OUT-EN
CMP-X-OD-EN
CMP-X-INV-EN
0
X
X
X
Comparator not enabled
CMPX-OUT PIN
1
0
X
X
No output
1
1
0
0
Push-pull output
1
1
0
1
Push-pull and inverted output
1
1
1
0
Open-drain output
1
1
1
1
Open-drain and inverted output
Figure 7-3 shows the interface circuit when all the DAC channels are configured as comparators. The
programmable comparator operation is as shown in Figure 7-4. Individual comparator channels can be
configured in no-hysteresis, with-hysteresis, and window-comparator modes using the CMP-X-MODE bit in the
respective DAC-X-CMP-MODE-CONFIG register, as shown in Table 7-2.
VDD
10 k
0.1 μF
VDD
VREF
CMP3-OUT
+
-
CMP3
1.5 μF
CAP
CMP0
+
-
CMP0-OUT
FB3/AIN3
(0 V to VFS/3 or 0 V to VFS)
CMP2-OUT
FB0/AIN0
(0 V to VFS/3 or 0 V to VFS)
+
-
CMP1
CMP2
+
-
CMP1-OUT
FB1/AIN1
(0 V to VFS/3 or 0 V to VFS)
FB2/AIN2
(0 V to VFS/3 or 0 V to VFS)
AGND
SCL/SYNC
GPIO/SDO
A0/SDI
SDA/SCLK
VIO
10 k
Figure 7-3. Comparator Interface
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
31
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
DAC-X-DATA
FBx/AINx
OUT-X
CMP-X-INV-EN = 0
OUT-X
CMP-X-INV-EN = 1
Figure 7-4. Programmable Comparator Operation
Table 7-2. Comparator Mode Selection
CMP-X-MODE BIT FIELD
32
COMPARATOR CONFIGURATION
00
Normal comparator mode. No hysteresis or window operation.
01
Hysteresis comparator mode. DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers set the hysteresis.
10
Window comparator mode. DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers set the window
bounds.
11
Invalid setting
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.4.3.1 Programmable Hysteresis Comparator
Comparator mode provides hysteresis when the CMP-X-MODE bit is set to 01b, as shown in Table 7-2. The
hysteresis is provided by the DAC-X-MARGIN-HIGH and DAC-X-MARGIN-LOW registers, as shown in Figure
7-5.
When the DAC-X-MARGIN-HIGH is set to full-code or the DAC-X-MARGIN-LOW is set to zero-code, the
comparator works as a latching comparator that is, the output is latched after the threshold is crossed. The
latched output can be reset by writing to the corresponding RST-CMP-FLAG-X bit in the COMMON-DAC-TRIG
register. Figure 7-6 shows the behavior of a latching comparator with active low output and Figure 7-7 shows the
behavior of a latching comparator with active high output.
Note
The value of the DAC-X-MARGIN-HIGH register must be greater than the value of the DAC-XMARGIN-LOW register. The comparator output in the hysteresis mode can only be noninverting that
is, the CMP-X-INV-EN bit in the DAC-X-VOUT-CMP-CONFIG register must be set to 0. In latching
mode, for the reset to take effect, the input voltage must be within DAC-X-MARGIN-HIGH and DAC-XMARGIN-LOW.
DAC-X-MARGIN-HIGH
FBx/AINx
Hysteresis
DAC-X-MARGIN-LOW
OUT-X
CMP-X-INV-EN = 0
Figure 7-5. Programmable Hysteresis Without Latching Output
DAC-X-MARGIN-HIGH
FBx/AINx
DAC-X-MARGIN-LOW
(ZERO-CODE)
OUT-X
CMP-X-INV-EN = 0
RST-CMP-FLAG-X
Figure 7-6. Latching Comparator With Active Low Output
DAC-X-MARGIN-HIGH
(FULL-CODE)
FBx/AINx
DAC-X-MARGIN-LOW
OUT-X
CMP-X-INV-EN = 0
RST-CMP-FLAG-X
Figure 7-7. Latching Comparator With Active High Output
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
33
DAC63004, DAC53004
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
www.ti.com
7.4.3.2 Programmable Window Comparator
Window comparator mode is enabled by setting the CMP-X-MODE bit to 10b, as shown in Table 7-2. The
window bounds are set by the DAC-X-MARGIN-HIGH and the DAC-X-MARGIN-LOW registers, as shown in
Figure 7-8. The output of the window comparator for a given channel is indicated by the respective WIN-CMP-X
bit in the CMP-STATUS register. The comparator output (WIN-CMP-X) can be latched by writing 1 to the
WIN-LATCH-EN bit in the COMMON-CONFIG register. After being latched, the comparator output can be reset
using the corresponding RST-CMP-FLAG-X bit in the COMMON-DAC-TRIG register. For the reset to take effect,
the input must be within the window bounds.
DAC-X-MARGIN-HIGH
FBx/AINx
DAC-X-MARGIN-LOW
WIN-CMP-X
WIN-LATCH-EN = 0
WIN-CMP-X
WIN-LATCH-EN = 1
RST-CMP-FLAG-X
Figure 7-8. Window Comparator Operation
A single comparator is used per channel to check both the margin-high and margin-low limits of the window.
Therefore, the window comparator function has a finite response time as specified in Section 6.7. Also, the
static behavior of the WIN-CMP-X bit is not reflected at the output pins. Set the CMP-X-OUT-EN bit to 0. The
WIN-CMP-X bit must be read digitally using the communication interface. This bit can also be mapped to the
GPIO pin, as shown in Table 7-19.
•
•
•
Note
The value of the DAC-X-MARGIN-HIGH register must be greater than that of the DAC-X-MARGINLOW register.
Set the SLEW-RATE-X bit to 0000b (no-slew) and LOG-SLEW-EN-X bit to 0b in the DAC-X-FUNCCONFIG register to get the best response time from the window comparator.
The CMP-X-OUT-EN bit in the DAC-X-VOUT-CMP-CONFIG register can be set to 0b to eliminate
undesired toggling of the OUT pin.
7.4.4 Fault-Dump Mode
The DACx3004 provides a feature to save a few registers into the NVM when the FAULT-DUMP bit is triggered
or the GPIO mapped to fault-dump (as shown in Table 7-18) is triggered. This feature is useful in system-level
fault management to capture the state of the device or system just before a fault is triggered, to allow diagnosis
after the fault has occurred. The registers saved when fault-dump is triggered, are:
• CMP-STATUS[7:0]
• DAC-0-DATA[15:8]
• DAC-1-DATA[15:8]
• DAC-2-DATA[15:8]
• DAC-3-DATA[15:8]
Note
When the fault-dump cycle is in progress, any change in the data can corrupt the final outcome. Make
sure the comparator and the DAC codes are stable during the NVM write cycle.
Table 7-3 shows the storage format of the registers in the NVM.
34
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
Table 7-3. Fault-Dump NVM Storage Format
NVM ROWS
B31-B24
Row1
CMP-STATUS[7:0]
B23-B16
Row2
DAC-0-DATA[15:8]
B15-B8
B7-B0
Don't care
DAC-1-DATA[15:8]
DAC-2-DATA[15:8]
DAC-3-DATA[15:8]
The data captured in the NVM after the fault dump can be read in a specific sequence:
1. Set the EE-READ-ADDR bit to 0b in the COMMON-CONFIG register, to select row1 of the NVM.
2. Trigger the read of the selected NVM row by writing 1 to the READ-ONE-TRIG in the COMMON-TRIGGER
register; this bit autoresets. This action copies that data from the selected NVM row to SRAM addresses
0x9D (LSB 16 bits from the NVM) and 0x9E (MSB 16 bits from the NVM).
3. To read the SRAM data:
a. Write 0x009D to the SRAM-CONFIG register.
b. Read the data from the SRAM-DATA register to get the LSB 16 bits.
c. Write 0x009E to the SRAM-CONFIG register.
d. Read the data from the SRAM-DATA register again to get the MSB bits.
4. Set the EE-READ-ADDR bit to 1b in the COMMON-CONFIG register, to select row2 of the NVM. Repeat
steps 2 and 3.
7.4.5 Application-Specific Modes
This section provides the details of application-specific functional modes available in DACx3004.
7.4.5.1 Voltage Margining and Scaling
Voltage margining or scaling is a primary application for DACx3004. This section provides specific features
available for this application such as Hi-Z output, slew-rate control, PROTECT input, and PMBus compatibility.
7.4.5.1.1 High-Impedance Output and PROTECT Input
All the DAC output channels remain in high-impedance (Hi-Z) when VDD is off. Figure 7-9 shows a simplified
schematic of DACx3004 used in a voltage-margining application. The series resistor RS is needed in voltageoutput mode, but is optional in current-output mode. Almost all linear regulators and DC/DC converters have a
feedback voltage of ≤ 1.25 V. The low-leakage currents at the outputs are maintained for VFB of ≤ 1.25 V. Thus,
for all practical purposes, the DAC outputs appear as Hi-Z when VDD of the DAC is off in voltage margining
and scaling applications. This feature allows for seamless integration of the DACx3004 into a system without any
need for additional power-supply sequencing for the DAC.
VIN
VREG
VDD
R1
RS
PROTECT
ILEAK
DAC
VFB
1.25 V
ZOUT
R2
Linear
Regulator
or
DC/DC
Converter
Figure 7-9. High-Impedance (Hi-Z) Output and PROTECT Input
The DAC channels power down to Hi-Z at boot up. The outputs can power up with a preprogrammed code that
corresponds to the nominal output of the DC/DC converter or the linear regulator. This feature allows for smooth
power up and power down of the DAC without impacting the feedback loop of the DC/DC converter or the linear
regulator.
The GPIO pin of the DACx3004 can be configured as a PROTECT function, as shown in Table 7-18. PROTECT
takes the DAC outputs to a predictable state with a slewed or direct transition. This function is useful in systems
where a fault condition (such as a brownout), a subsystem failure, or a software crash requires that the DAC
outputs reach a predefined state without the involvement of a processor. The detected event can be fed to
the GPIO pin that is configured as the PROTECT input. The PROTECT function can also be triggered using
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
35
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
the PROTECT bit in the COMMON-TRIGGER register. Configure the behavior of the PROTECT function in the
PROTECT-CONFIG field in the DEVICE-MODE-CONFIG register, as shown in Table 7-4.
•
•
Note
After the PROTECT function is triggered, the write functionality is disabled on the communication
interface until the function is completed.
The PROTECT-FLAG bit in the CMP-STATUS register is set to 1 when the PROTECT function
is triggered. This bit can be polled by reading the CMP-STATUS register. After the PROTECT
function is complete, a read command on the CMP-STATUS register resets the PROTECT-FLAG
bit.
Table 7-4. PROTECT Function Configuration
PROTECT-CONFIG FIELD
FUNCTION
00
Switch to Hi-Z power-down (no slew).
01
Switch to DAC code stored in NVM (no slew) and then switch to Hi-Z power-down.
10
Slew to margin-low code and then switch to Hi-Z power-down.
11
Slew to margin-high code and then switch to Hi-Z power-down.
7.4.5.1.2 Programmable Slew-Rate Control
When the DAC data registers are written, the voltage on DAC output (VOUT) immediately transitions to the new
code following the slew rate and settling time specified in the Electrical Characteristics.
The slew rate control feature allows the user to control the rate at which the output voltage (VOUT) changes.
When this feature is enabled (using the SLEW-RATE-X[3:0] bits), the DAC output changes from the current
code to the code in the DAC-X-MARGIN-HIGH or DAC-X-MARGIN-LOW registers (when margin high or low
commands are issued to the DAC) using the step size and time-period per step set in CODE-STEP-X and
SLEW-RATE-X bits in the DAC-X-FUNC-CONFIG register:
• SLEW-RATE-X defines the time-period per step at which the digital slew updates.
• CODE-STEP-X defines the number of LSBs by which the output value changes at each update, for the
corresponding channels.
Table 7-5 and Table 7-6 show different settings available for CODE-STEP-X and SLEW-RATE-X. With the
default slew rate control setting of no-slew, the output changes immediately at a rate limited by the output drive
circuitry and the attached load.
When the slew rate control feature is used, the output changes happen at the programmed slew rate. This
configuration results in a staircase formation at the output as shown in Figure 7-10. Do not write to CODE-STEPX, SLEW-RATE-X, or DAC-X-DATA during the output slew operation. Equation 6 provides the equation for the
calculating the slew time (tSLEW).
36
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
MARGIN-HIGH
CODE-STEP
MARGIN-LOW
TIME PERIOD
tSLEW
Figure 7-10. Programmable Slew-Rate Control
where:
•
•
•
•
tSLEW =
SLEW_RATE × MARGIN_HIGH − MARGIN_LOW + 1
CODE_STEP
(6)
SLEW_RATE is the SLEW-RATE-X setting as specified in Table 7-6.
CODE_STEP is the CODE-STEP-X setting as specified in Table 7-5.
MARGIN_HIGH is the DAC-X-MAGIN-HIGH as specified in Section 7.6.2.
MARGIN_LOW is the DAC-X-MAGIN-LOW as specified in Section 7.6.3.
Table 7-5. Code Step
REGISTER
CODE-STEP-X[2]
CODE-STEP-X[1]
CODE-STEP-X[0]
CODE STEP SIZE
0
0
0
1 LSB (default)
0
0
1
2 LSB
0
1
0
3 LSB
0
1
1
4 LSB
1
0
0
6 LSB
1
0
1
8 LSB
1
1
0
16 LSB
1
1
1
32 LSB
DAC-X-FUNC-CONFIG
Table 7-6. Slew Rate
REGISTER
DAC-X-FUNC-CONFIG
SLEW-RATE-X[3]
SLEW-RATE-X[2]
SLEW-RATE-X[1]
SLEW-RATE-X[0]
TIME PERIOD
(PER STEP)
0
0
0
0
No slew (default)
0
0
0
1
4 µs
0
0
1
0
8 µs
0
0
1
1
12 µs
0
1
0
0
18 µs
0
1
0
1
27 µs
0
1
1
0
40.5 µs
0
1
1
1
60.75 µs
1
0
0
0
91.13 µs
1
0
0
1
136.69 µs
1
0
1
0
239.2 µs
1
0
1
1
418.61 µs
1
1
0
0
732.56 µs
1
1
0
1
1281.98 µs
1
1
1
0
2563.96 µs
1
1
1
1
5127.92 µs
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
37
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.4.5.1.3 PMBus Compatibility Mode
The PMBus protocol is an I2C-based communication standard for power-supply management. PMBus contains
standard command codes tailored to power supply applications. The DACx3004 implement some PMBus
commands such as Turn Off, Turn On, Margin Low, Margin High, Communication Failure Alert Bit (CML), as
well as PMBUS revision. Figure 7-11 shows typical PMBus connections. The EN-PMBUS bit in the INTERFACECONFIG register must be set to 1 to enable the PMBus protocol.
ALERT
PMBus-compatible device #1
DATA
ALERT
PMBus-compatible device #2
Control signal
DATA
Clock
CLOCK
ADDRESS
CONTROL
Data
WP
System Host
—
Bus Controller
Alert signal
WP
CLOCK
ADDRESS
CONTROL
Optional
Required
ALERT
PMBus-compatible device #3
WP
DATA
CLOCK
ADDRESS
CONTROL
Figure 7-11. PMBus Connections
38
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
Similar to I2C, PMBus is a variable length packet of 8-bit data bytes, each with a receiver acknowledge,
wrapped between a start and stop bit. The first byte is always a 7-bit target address followed by a write bit,
sometimes called the even address that identifies the intended receiver of the packet. The second byte is an
8-bit command byte, identifying the PMBus command being transmitted using the respective command code.
After the command byte, the transmitter either sends data associated with the command to write to the receiver
command register (from least significant byte to most significant byte, as shown in Table 7-7), or sends a new
start bit indicating the desire to read the data associated with the command register from the receiver. Then the
receiver transmits the data following the same least significant byte first format (see Table 7-8).
Table 7-7. PMBus Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
Address (A) byte
Section 7.5.2.2.1
Command byte
Section 7.5.2.2.2
Data byte - LSDB
Data byte - MSDB
(Optional)
DB [31:24]
DB [23:16]
DB [15:8]
DB [7:0]
ACK
Table 7-8. PMBus Read Sequence
S
MSB
…
R/W
(0)
ACK
ADDRESS BYTE
Section 7.5.2.2.1
From Controller
MSB
…
LSB
ACK
COMMAND BYTE
Section 7.5.2.2.2
Target
From Controller
Target
R/W
(1)
Sr
MSB …
Sr
ADDRESS BYTE
Section 7.5.2.2.1
From Controller
ACK
MSB
…
LSB
ACK
MSB
LSDB
Target
From Target
…
LSB
ACK
MSDB (Optional)
Controller
From Target
Controller
The DACx3004 I2C interface implements some of the PMBus commands. Table 7-9 shows the supported
PMBus commands that are implemented in DACx3004.The DAC uses DAC-X-MARGIN-LOW, DAC-X-MARGINHIGH bits, SLEW-RATE-X, and CODE-STEP-X bits for PMBUS-OPERATION-CMD-X. To access multiple
channels, write the PMBus page address as specified in Table 7-21 to the PMBUS-PAGE register first, followed
by a write to the channel-specific register.
Table 7-9. PMBus Operation Commands
REGISTER
PMBUS-OP-CMD-X
PMBUS-OPERATION-CMD-X[15:8]
DESCRIPTION
00h
Turn off
80h
Turn on
94h
Margin low
A4h
Margin high
The DACx3004 also implement PMBus features such as group command protocol and communication time-out
failure. The CML bit in the PMBUS-CML register indicates a communication fault in the PMBus. This bit is reset
by writing 1.
To get the PMBus version, read the PMBUS-VERSION register.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
39
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.4.5.2 Function Generation
The DACx3004 implement a continuous function or waveform generation feature. These devices can generate a
triangular wave, sawtooth wave, and sine wave independently for every channel.
7.4.5.2.1 Triangular Waveform Generation
The triangular waveform uses the DAC-X-MARGIN-LOW and DAC-X-MARGIN-HIGH registers for minimum and
maximum levels, respectively. The frequency of the waveform depends on the min and max levels, CODE-STEP
and SLEW-RATE settings as shown in Equation 7. An external RC load with a time-constant larger than
the slew-rate settings can be dominant over the internal frequency calculation. The CODE-STEP-X and SLEWRATE-X settings are available in the DAC-X-FUNC-CONFIG register. Writing 0b000 to the FUNC-CONFIG-X bit
field in the DAC-X-FUNC-CONFIG register selects triangular waveform.
f TRIANGLE_WAVE =
where:
•
•
•
•
2 × SLEW_RATE ×
1
MARGIN_HIGH − MARGIN_LOW + 1
CODE_STEP
(7)
SLEW_RATE is the SLEW-RATE-X setting as specified in Table 7-6.
CODE_STEP is the CODE-STEP-X setting as specified in Table 7-5.
MARGIN_HIGH is the DAC-X-MAGIN-HIGH as specified in Section 7.6.2.
MARGIN_LOW is the DAC-X-MAGIN-LOW as specified in Section 7.6.3.
7.4.5.2.2 Sawtooth Waveform Generation
The sawtooth and the inverse sawtooth waveforms use the DAC-X-MARGIN-LOW and DAC-X-MARGIN-HIGH
registers for minimum and maximum levels, respectively. The frequency of the waveform depends on the min
and max levels, CODE-STEP and SLEW-RATE settings as shown in Equation 8. An external RC load with a
time constant larger than the slew-rate settings can be dominant over the internal frequency calculation. The
CODE-STEP-X and SLEW-RATE-X settings are available in the DAC-X-FUNC-CONFIG register. Write 0b001
to the FUNC-CONFIG-X bit field in the DAC-X-FUNC-CONFIG register to select sawtooth waveform, and write
0b010 to select inverse sawtooth waveform.
f SAWTOOTH_WAVE =
where:
•
•
•
•
40
SLEW_RATE ×
1
MARGIN_HIGH − MARGIN_LOW + 1
CODE_STEP
(8)
SLEW_RATE is the SLEW-RATE-X setting as specified in Table 7-6.
CODE_STEP is the CODE-STEP-X setting as specified in Table 7-5.
MARGIN_HIGH is the DAC-X-MAGIN-HIGH as specified in Section 7.6.2.
MARGIN_LOW is the DAC-X-MAGIN-LOW as specified in Section 7.6.3.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.4.5.2.3 Sine Waveform Generation
The sine wave function uses 24 preprogrammed points per cycle. The frequency of the sine wave depends on
the SLEW-RATE settings as shown in Equation 9:
1
f SINE_WAVE = 24 × SLEW_RATE
(9)
where SLEW_RATE is the SLEW-RATE-X setting as specified in Table 7-6.
An external RC load with a time constant larger than the slew-rate settings can be dominant over the internal
frequency calculation. The SLEW-RATE-X setting is available in the DAC-X-FUNC-CONFIG register. Writing
0b100 to the FUNC-CONFIG-X bit field in the DAC-X-FUNC-CONFIG register selects sine wave. The codes
for the sine wave are fixed. Use the gain settings at the output amplifier for changing the full-scale output
using the internal reference option. The gain settings are accessible through the VOUT-GAIN-X bits in the
DAC-X-VOUT-CMP-CONFIG register. Table 7-10 shows the list of hard-coded discrete points for the sine wave
with 12-bit resolution and Figure 7-12 shows the pictorial representation of the sine wave. There are four phase
settings available for the sine wave that are selected using the PHASE-SEL-X bit in the DAC-X-FUNC-CONFIG
register.
Table 7-10. Sine Wave Data Points
SEQUENCE
12-BIT VALUE
SEQUENCE
12-BIT VALUE
0
0x800
12
0x800
1
0x9A8
13
0x658
2
0xB33
14
0x4CD
3
0xC87
15
0x379
4
0xD8B
16
0x275
5
0xE2F
17
0x1D1
6
0xE66
18
0x19A
7
0xE2F
19
0x1D1
8
0xD8B
20
0x275
9
0xC87
21
0x379
10
0xB33
22
0x4CD
11
0x9A8
23
0x658
5
6
7
4
8
3
9
2
10
1
0
11
TIME PERIOD
12
0
13
23
14
22
15
21
16
20
17
18
19
Figure 7-12. Sine Wave Generation
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
41
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.4.6 Device Reset and Fault Management
This section provides the details of power-on-reset (POR), software reset, and other diagnostics and faultmanagement features of DACx3004.
7.4.6.1 Power-On Reset (POR)
The DACx3004 family of devices includes a power-on reset (POR) function that controls the output voltage at
power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers
to initialize to default values, and communication with the device is valid only after a POR (boot-up) delay. The
default value for all the registers in the DACx3004 is loaded from NVM as soon as the POR event is issued.
When the device powers up, a POR circuit sets the device to the default mode. The POR circuit requires specific
VDD levels, as indicated in Figure 7-13, to make sure that the internal capacitors discharge and reset the device
at power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD drops
to less than 1.65 V, but remains greater than 0.7 V (shown as the undefined region), the device may or may
not reset under all specified temperature and power-supply conditions. In this case, initiate a POR. When VDD
remains greater than 1.65 V, a POR does not occur.
VDD (V)
5.5 V
No power-on reset
Spe cified supply
voltage range
1.71 V
1.65 V
Undefined
0.7 V
Power-on reset
0V
Figure 7-13. Threshold Levels for VDD POR Circuit
7.4.6.2 External Reset
An external reset to the device can be triggered through the GPIO pin or through the register map. To initiate
a device software reset event, write the reserved code 1010 to the RESET field in the COMMON-TRIGGER
register. A software reset initiates a POR event. The GPIO pin can be configured as a RESET pin as shown
in Table 7-18. This configuration must be programmed into the NVM so that the setting is not cleared after the
device reset. The RESET input must be a low pulse. The device starts the boot-up sequence after the falling
edge of the RESET input. The rising edge of the RESET input does not have any effect.
7.4.6.3 Register-Map Lock
The DACx3004 implement a register-map lock feature that prevents an accidental or unintended write to the
DAC registers. The device locks all the registers when the DEV-LOCK bit in the COMMON-CONFIG register is
set to 1. However, the software reset function through the COMMON-TRIGGER register is not blocked when
using I2C interface. To bypass the DEV-LOCK setting, write 0101 to the DEV-UNLOCK bits in the COMMONTRIGGER register.
42
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.4.6.4 NVM Cyclic Redundancy Check (CRC)
The DACx3004 implement a cyclic redundancy check (CRC) feature for the NVM to make sure that the data
stored in the NVM is uncorrupted. There are two types of CRC alarm bits implemented in DACx3004:
• NVM-CRC-FAIL-USER
• NVM-CRC-FAIL-INT
The NVM-CRC-FAIL-USER bit indicates the status of user-programmable NVM bits, and the NVM-CRC-FAILINT bit indicates the status of internal NVM bits The CRC feature is implemented by storing a 16-Bit CRC
(CRC-16-CCITT) along with the NVM data each time NVM program operation (write or reload) is performed and
during the device start up. The device reads the NVM data and validates the data with the stored CRC. The
CRC alarm bits (NVM-CRC-FAIL-USER and NVM-CRC-FAIL-INT in the GENERAL-STATUS register) report any
errors after the data are read from the device NVM. The alarm bits are set only at boot-up.
7.4.6.4.1 NVM-CRC-FAIL-USER Bit
A logic 1 on NVM-CRC-FAIL-USER bit indicates that the user-programmable NVM data are corrupt. During this
condition, all registers in the DAC are initialized with factory reset values, and any DAC registers can be written
to or read from. To reset the alarm bits to 0, issue a software reset (see Section 7.4.6.2) command, or cycle
power to the DAC. A software reset or power-cycle also reloads the user-programmable NVM bits. In case the
failure persists, reprogram the NVM.
7.4.6.4.2 NVM-CRC-FAIL-INT Bit
A logic 1 on NVM-CRC-FAIL-INT bit indicates that the internal NVM data are corrupt. During this condition, all
registers in the DAC are initialized with factory reset values, and any DAC registers can be written to or read
from. In case of a temporary failure, to reset the alarm bits to 0, issue a software reset (see Section 7.4.6.2)
command or cycle power to the DAC. A permanent failure in the NVM makes the device unusable.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
43
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.4.7 Power-Down Mode
The DACx3004 output amplifier and internal reference can be independently powered down through the ENINT-REF, VOUT-PDN-X, and IOUT-PDN-X bits in the COMMON-CONFIG register, as shown in Figure 7-2. At
power up, the DAC output and the internal reference are disabled by default. In power-down mode, the DAC
outputs (OUTx pins) are in a high-impedance state. To change this state to 10 kΩ-AGND or 100 kΩ-AGND in
voltage-output mode (at power up), use the VOUT-PDN-X bits. The power-down state for current-output mode is
always high-impedance.
The DAC power-up state can be programmed to any state (power-down or normal mode) using the NVM. Table
7-11 shows the DAC power-down bits. The individual channel power-down bits can be mapped to the GPIO
pin using the GPIO-CONFIG register. This function is called sleep mode. In this mode, the internal low-dropout
regulator (LDO) and the common functional blocks are still powered-on, and the device draws a maximum of 28
μA of current through the power supply.
Table 7-11. DAC Power-Down Bits
REGISTER
VOUT-PDN-X[1]
VOUT-PDN-X[0]
IOUT-PDN-X
0
0
1
Power up VOUT-X
0
1
1
Power down VOUT-X with 10 kΩ to AGND.
Power down IOUT-X to Hi-Z.
1
0
1
Power down VOUT-X with 100 kΩ to AGND.
Power down IOUT-X to Hi-Z.
1
1
1
Power down VOUT-X to Hi-Z.
Power down IOUT-X to Hi-Z (default).
1
1
0
Power down VOUT-X to Hi-Z.
Power up IOUT-X.
COMMON-CONFIG
DESCRIPTION
7.4.7.1 Deep-Sleep Mode
The DACx3004 provides a deep-sleep mode, where the internal LDO and most of the common functional blocks
are powered-down. The GPIO pin must be used to enter and exit this mode. The I2C or SPI interface does not
work during the deep-sleep mode. The steps to enter and exit the deep-sleep mode are:
1. Make sure that the GPIO pin is pulled high.
2. Write 1 to the DEEP-SLEEP-EN bit in the GPIO-CONFIG register.
3. Disable GP output and SDO by writing 0 to GPO-EN and SDO-EN bits.
4. Enable GPIO input mode by writing 1 to GPI-EN and 0b0000 to GPI-CONFIG bits.
5. To program these settings into the NVM, write 1 to the NVM-PROG bit in the COMMON-TRIGGER register.
6. A negative-edge trigger on the GPIO puts the device into the deep-sleep mode. The LDO takes
approximately 550 μs to switch off. The device remains in this mode as long as the signal is low.
7. To bring the device out of the deep-sleep mode, pull the GPIO pin high. The digital circuitry and the LDO
takes approximately 550 μs to switch on.
44
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.5 Programming
The DACx3004 are programmed through either a 3-wire SPI or 2-wire I2C interface. A 4-wire SPI mode is
enabled by mapping the GPIO pin as SDO. The SPI readback operates at a lower SCLK than the standard
SPI write operation. The type of interface is determined based on the first protocol to communicate after device
power up. After the interface type is determined, the device ignores any change in the type while the device is
on. The interface type can be changed after a power cycle.
7.5.1 SPI Programming Mode
An SPI access cycle for DACx3004 is initiated by asserting the SYNC pin low. The serial clock, SCLK, can be
a continuous or gated clock. SDI data are clocked on SCLK falling edges. The SPI frame for DACx3004 is 24
bits long. Therefore, the SYNC pin must stay low for at least 24 SCLK falling edges. The access cycle ends
when the SYNC pin is deasserted high. If the access cycle contains less than the minimum clock edges, the
communication is ignored. By default, the SDO pin is not enabled (three-wire SPI). In the three-wire SPI mode,
if the access cycle contains more than the minimum clock edges, only the first 24 bits are used by the device.
When SYNC is high, the SCLK and SDI signals are blocked, and SDO becomes Hi-Z to allow data readback
from other devices connected on the bus.
Table 7-12 and Figure 7-14 describe the format for the 24-bit SPI access cycle. The first byte input to SDI is the
instruction cycle. The instruction cycle identifies the request as a read or write command and the 7-bit address
that is to be accessed. The last 16 bits in the cycle form the data cycle.
Table 7-12. SPI Read/Write Access Cycle
BIT
FIELD
DESCRIPTION
23
R/W
Identifies the communication as a read or write command to the address register: R/W = 0 sets a write
operation. R/W = 1 sets a read operation
22-16
A[6:0]
Register address: specifies the register to be accessed during the read or write operation
15-0
DI[15:0]
Data cycle bits: If a write command, the data cycle bits are the values to be written to the register with
address A[6:0]. If a read command, the data cycle bits are don't care values.
SYNC
1
8
9
24
1
8
9
24
D15
D0
SCLK
Write command
D23
SDI
D16
HiZ
Any command
D15
D0
D23
D16
Write command echo
HiZ
SDO
D16
D23
D15
HiZ
D0
Figure 7-14. SPI Write Cycle
Read operations require that the SDO pin is first enabled by setting the SDO-EN bit in the INTERFACE-CONFIG
register. This configuration is called four-wire SPI. A read operation is initiated by issuing a read command
access cycle. After the read command, a second access cycle must be issued to get the requested data. The
output data format is shown in Table 7-13 and Figure 7-15. Data are clocked out on the SDO pin either on the
falling edge or rising edge of SCLK according to the FSDO bit, as shown in Figure 6-3.
Table 7-13. SDO Output Access Cycle
BIT
FIELD
23
R/W
22-16
A[6:0]
15-0
DI[15:0]
DESCRIPTION
Echo R/W from previous access cycle
Echo register address from previous access cycle
Readback data requested on previous access cycle
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
45
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
SYNC
1
8
9
24
1
8
9
24
D15
D0
SCLK
Any command
Read command
D23
SDI
D16
D15
D23
D0
HiZ
D16
Read Data
HiZ
SDO
D16
D23
D15
HiZ
D0
Figure 7-15. SPI Read Cycle
The daisy-chain operation is also enabled with the SDO pin. In daisy-chain mode, multiple devices are
connected in a chain with the SDO pin of one device is connected to SDI pin of the following device, as shown
in Figure 7-16. The SPI host drives the SDI pin of the first device in the chain. The SDO pin of the last device
in the chain is connected to the POCI pin of the SPI host. In four-wire SPI mode, if the access cycle contains
multiples of 24 clock edges, only the last 24 bits are used by the device first device in the chain. If the access
cycle contains clock edges that are not in multiples of 24, the SPI packet is ignored by the device. Figure 7-17
describes the packet format for the daisy-chain write cycle.
VIO
VIO
C
VIO
B
TI SPI Device
RPULL-UP
RPULL-UP
TI SPI Device
SDO
SDI
A
RPULL-UP
TI SPI Device
SDO
SDI
SDO
SDI
SCLK
SCLK
SCLK
SYNC
SYNC
SYNC
Figure 7-16. SPI Daisy-Chain Connection
SYNC
1
8
9
24
25
48
49
72
SCLK
Device A command
SDI-C
D23
SDO-C
D16
D15
Device B command
D0
D23 – D1
Device C command
D0
Device A command
D23 – D1
D0
Device B command
Figure 7-17. SPI Daisy-Chain Write Cycle
46
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.5.2 I2C Programming Mode
The DACx3004 devices have a 2-wire serial interface (SCL and SDA), and one address pin (A0), as shown
in the pin diagram, Figure 5-1. The I2C bus consists of a data line (SDA) and a clock line (SCL) with pullup
structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect
to the I2C bus through the open drain I/O pins, SDA and SCL.
The I2C specification states that the device that controls communication is called a controller, and the devices
that are controlled by the controller are called targets. The controller generates the SCL signal. The controller
also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus
to indicate the start or stop of a data transfer. Device addressing is completed by the controller. The controller
on an I2C bus is typically a microcontroller or digital signal processor (DSP). The DACx3004 family operates as
a target on the I2C bus. A target acknowledges controller commands, and upon controller control, receives or
transmits data.
Typically, the DACx3004 family operates as a target receiver. A controller writes to the DACx3004, a target
receiver. However, if a controller requires the DACx3004 internal register data, the DACx3004 operate as a
target transmitter. In this case, the controller reads from the DACx3004. According to I2C terminology, read and
write refer to the controller.
The DACx3004 family supports the following data transfer modes:
•
•
•
Standard mode (100 kbps)
Fast mode (400 kbps)
Fast mode plus (1.0 Mbps)
The data transfer protocol for standard and fast modes is exactly the same; therefore, both modes are referred
to as F/S-mode in this document. The fast mode plus protocol is supported in terms of data transfer speed,
but not output current. The low-level output current would be 3 mA; similar to the case of standard and fast
modes. The DACx3004 family supports 7-bit addressing. The 10-bit addressing mode is not supported. The
device supports the general call reset function. Sending the following sequence initiates a software reset within
the device: start or repeated start, 0x00, 0x06, stop. The reset is asserted within the device on the rising edge of
the ACK bit, following the second byte.
Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a ninth clock
cycle generates and detects an acknowledge signal. An acknowledge is when the SDA line is pulled low during
the high period of the ninth clock cycle. A not-acknowledge is when the SDA line is left high during the high
period of the ninth clock cycle, as shown in Figure 7-18.
Data output
by transmitter
Not acknowledge
Data output
by receiver
Acknowledge
1
SCL from
controller
2
8
9
S
Clock pulse for
acknowledgement
Start
condition
Figure 7-18. Acknowledge and Not Acknowledge on the I2C Bus
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
47
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.5.2.1 F/S Mode Protocol
The following steps explain a complete transaction in F/S mode.
1. The controller initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 7-19. All I2C-compatible devices
recognize a start condition.
2. The controller then generates the SCL pulses, and transmits the 7-bit address and the read/write direction
bit (R/W) on the SDA line. During all transmissions, the controller makes sure that data are valid. A valid
data condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown
in Figure 7-20. All devices recognize the address sent by the controller and compare the address to the
respective internal fixed address. Only the target device with a matching address generates an acknowledge
by pulling the SDA line low during the entire high period of the 9th SCL cycle, as shown in Figure 7-18.
When the controller detects this acknowledge, the communication link with a target has been established.
3. The controller generates further SCL cycles to transmit (R/W bit 0) or receive (R/W bit 1) data to the target.
In either case, the receiver must acknowledge the data sent by the transmitter. The acknowledge signal can
be generated by the controller or by the target, depending on which is the receiver. The 9-bit valid data
sequences consists of eight data bits and one acknowledge-bit, and can continue as long as necessary.
4. To signal the end of the data transfer, the controller generates a stop condition by pulling the SDA line from
low-to-high while the SCL line is high, as shown in Figure 7-19. This action releases the bus and stops the
communication link with the addressed target. All I2C-compatible devices recognize the stop condition. Upon
receipt of a stop condition, the bus is released, and all target devices then wait for a start condition followed
by a matching address.
SDA
SDA
SCL
SCL
S
Start
condition
P
Stop
condition
Figure 7-19. Start and Stop Conditions
48
Data line stable
Data valid
Change of data
allowed
Figure 7-20. Bit Transfer on the I2C Bus
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.5.2.2 I2C Update Sequence
For a single update, the DACx3004 require a start condition, a valid I2C address byte, a command byte, and two
data bytes, as listed in Table 7-14.
Table 7-14. Update Sequence
MSB
....
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
ACK
MSB
...
LSB
Address (A) byte
Section 7.5.2.2.1
Command byte
Section 7.5.2.2.2
Data byte - MSDB
Data byte - LSDB
DB [31:24]
DB [23:16]
DB [15:8]
DB [7:0]
ACK
After each byte is received, the DACx3004 family acknowledges the byte by pulling the SDA line low during the
high period of a single clock pulse, as shown in Figure 7-21. These four bytes and acknowledge cycles make up
the 36 clock cycles required for a single update to occur. A valid I2C address byte selects the DACx3004.
Recognize
START or
REPEATED
START
condition
Recognize
STOP or
REPEATED
START
condition
Generate ACKNOWLEDGE
signal
P
SDA
MSB
Address
SCL
Sr
Acknowledgement
signal from target
1
R/W
7
8
9
1
2-8
9
Sr
or
P
S
or
Sr
ACK
START or
REPEATED
START
condition
ACK
REPEATED
START or
STOP
condition
Figure 7-21. I2C Bus Protocol
The command byte sets the operating mode of the selected DACx3004 device. For a data update to occur
when the operating mode is selected by this byte, the DACx3004 device must receive two data bytes: the most
significant data byte (MSDB) and least significant data byte (LSDB). The DACx3004 device performs an update
on the falling edge of the acknowledge signal that follows the LSDB.
When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 10 kSPS. Using fast mode
plus (clock = 1 MHz), the maximum DAC update rate is limited to 25 kSPS. When a stop condition is received,
the DACx3004 device releases the I2C bus and awaits a new start condition.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
49
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.5.2.2.1 Address Byte
The address byte, as shown in Table 7-15, is the first byte received from the controller device following the start
condition. The first four bits (MSBs) of the address are factory preset to 1001. The next three bits of the address
are controlled by the A0 pin. The A0 pin input can be connected to VDD, AGND, SCL, or SDA. The A0 pin is
sampled during the first byte of each data frame to determine the address. The device latches the value of the
address pin, and consequently responds to that particular address according to Table 7-16.
Table 7-15. Address Byte
COMMENT
—
MSB
AD6
AD5
AD4
AD3
General address
1
0
0
1
Broadcast address
1
0
0
0
LSB
AD2
AD1
AD0
See Table 7-16
(target address column)
1
1
R/W
0 or 1
1
0
Table 7-16. Address Format
TARGET ADDRESS
A0 PIN
000
AGND
001
VDD
010
SDA
011
SCL
The DACx3004 supports broadcast addressing, which is used for synchronously updating or powering down
multiple DACx3004 devices. When the broadcast address is used, the DACx3004 responds regardless of the
address pin state. Broadcast is supported only in write mode.
7.5.2.2.2 Command Byte
Table 7-21 lists the command byte in the ADDRESS column.
50
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.5.2.3 I2C Read Sequence
To read any register the following command sequence must be used:
1. Send a start or repeated start command with a target address and the R/W bit set to 0 for writing. The device
acknowledges this event.
2. Send a command byte for the register to be read. The device acknowledges this event again.
3. Send a repeated start with the target address and the R/W bit set to 1 for reading. The device acknowledges
this event.
4. The device writes the MSDB byte of the addressed register. The controller must acknowledge this byte.
5. Finally, the device writes out the LSDB of the register.
The broadcast address cannot be used for reading.
Table 7-17. Read Sequence
S
MSB
…
R/W
(0)
ACK
ADDRESS BYTE
Section 7.5.2.2.1
From Controller
MSB
…
LSB
ACK
COMMAND BYTE
Section 7.5.2.2.2
Target
From Controller
Target
R/W
(1)
Sr
MSB …
Sr
ADDRESS BYTE
Section 7.5.2.2.1
From Controller
ACK
MSB
…
LSB
ACK
MSDB
Target
From Target
MSB
…
LSB
ACK
LSDB
Controller
From Target
Controller
7.5.3 General-Purpose Input/Output (GPIO) Modes
Together with I2C and SPI, the DACx3004 also support a GPIO that can be configured in the NVM for multiple
functions. This pin allows for updating the DAC output channels and reading status bits without using the
programming interface, thus enabling processor-less operation. In the GPIO-CONFIG register, write 1 to the
GPI-EN bit to set the GPIO pin as an input, or write 1 to the GPO-EN bit to set the pin as output. There
are global and channel-specific functions mapped to the GPIO pin. For channel-specific functions, select the
channels using the GPI-CH-SEL field in the GPIO-CONFIG register. Table 7-18 lists the functional options
available for the GPIO as input and Table 7-19 lists the options for the GPIO as output. Some of the GP input
operations are edge-triggered after the device boots up. After the power supply ramps up, the device registers
the GPI level and executes the associated command. This feature allows the user to configure the initial output
state at power-on. By default, the GPIO pin is not mapped to any operation. When the GPIO pin is mapped to
a specific input function, the corresponding software bit functionality is disabled to avoid a race condition. When
used as a RESET input, the GPIO pin must transmit an active-low pulse for triggering a device reset. All other
constraints of the functions are applied to the GPIO-based trigger.
Note
Pull the GPIO pin to high or low when not used. When the GPIO pin is used as RESET, the
configuration must be programmed into the NVM. Otherwise, the setting is cleared after the device
resets.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
51
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
Table 7-18. General-Purpose Input Function Map
REGISTER
BIT FIELD
CHANNELS
0000
All
0010
All
0011
As per GPI-CH-SEL
0100
As per GPI-CH-SEL
0101
GPIO-CONFIG
GPI-CONFIG
GPIO EDGE /
LEVEL
VALUE
All
0111
All
1000
As per GPI-CH-SEL. Both
the SYNC-CONFIG-X and
the GPI-CH-SEL must be
configured for every channel.
1001
As per GPI-CH-SEL
1010
As per GPI-CH-SEL
1011
1100
All
1101
All
Others
NA
Falling-edge
Trigger DEEP-SLEEP mode.
Rising-edge
Bring the device out of deep-sleep.
Falling-edge
Trigger FAULT-DUMP
Rising-edge
No effect
Falling-edge
IOUT power-down
Rising-edge
IOUT power-up
Falling-edge
VOUT power-down. Pulldown
resistor as per the VOUT-PDN-X
setting
Rising-edge
VOUT power-up
Falling-edge
Trigger PROTECT function
Rising-edge
No effect
Falling-edge
Trigger CLR function
Rising-edge
No effect
Falling-edge
Trigger LDAC function
Rising-edge
No effect
Falling-edge
Stop function generation
Rising-edge
Start function generation
Falling-edge
Trigger margin-low
Rising-edge
Trigger margin-high
Low pulse
All
FUNCTION
Trigger device RESET. The RESET
configuration must be programmed
into the NVM.
Rising-edge
No effect
Falling-edge
Allows NVM programming
Rising-edge
Blocks NVM programming
Falling-edge
Allows register map update
rising-edge
Blocks register map write except
a write to the DEV-UNLOCK field
through I2C or SPI and to the
RESET field through I2C
NA
Not applicable
Table 7-19. General-Purpose Output (STATUS) Function Map
REGISTER
GPIO-CONFIG
52
BIT FIELD
GPO-CONFIG
VALUE
FUNCTION
0001
NVM-BUSY
0100
DAC-0-BUSY
0101
DAC-1-BUSY
0110
DAC-2-BUSY
0111
DAC-3-BUSY
1000
WIN-CMP-0
1001
WIN-CMP-1
1010
WIN-CMP-2
1011
WIN-CMP-3
Others
Not applicable
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6 Register Map
Table 7-20. Register Map
REGISTER(1) (2)
MOST SIGNIFICANT DATA BYTE (MSDB)
BIT15
BIT14
BIT13
BIT12
BIT11
LEAST SIGNIFICANT DATA BYTE (LSDB)
BIT10
BIT9
BIT8
NOP
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
DAC-X-MARGINHIGH
DAC-X-MARGIN-HIGH
X
DAC-X-MARGINLOW
DAC-X-MARGIN-LOW
X
DAC-X-VOUTCMP-CONFIG
X
DAC-X-IOUT-MISCCONFIG
X
DAC-X-CMPMODE-CONFIG
DAC-X-FUNCCONFIG
VOUT-X-GAIN
IOUT-X-RANGE
X
CLR-SEL-X
BRDCONFIG-X
DEV-LOCK
EE-READADDR
EN-INT-REF
VOUT-PDN-3
DEV-UNLOCK
IOUT-PDN-3
VOUT-PDN-0
IOUT-PDN-0
X
VOUT-PDN-2
RESET
TRIG-MARLO-0
TRIG-MARHI-0
STARTFUNC-0
RST-CMPFLAG-1
TRIG-MARLO-1
TRIG-MARHI-1
STARTFUNC-1
GENERAL-STATUS
NVM-CRCFAIL-INT
NVM-CRCFAIL-USER
X
DACBUSY-3
DACBUSY-2
DACBUSY-1
DACBUSY-0
NVM-BUSY
CMP-STATUS
X
GF-EN
DEEPSLEEP-EN
RESERVED
PROTECTFLAG
GPO-EN
DIS-MODEIN
RESERVED
X
TIMEOUTEN
X
FAULTDUMP
PROTECT
READ-ONE- NVM-PROG
TRIG
NVMRELOAD
RST-CMPFLAG-2
TRIG-MARLO-2
TRIG-MARHI-2
STARTFUNC-2
RST-CMPFLAG-3
TRIG-MARLO-3
TRIG-MARHI-3
STARTFUNC-3
CMPFLAG-2
CMPFLAG-1
CMPFLAG-0
DEVICE-ID
WIN-CMP-3
PROTECT-CONFIG
X
WIN-CMP-2
WIN-CMP-1
WIN-CMP-0
CMPFLAG-3
GPI-CONFIG
RESERVED
EN-PMBUS
GPI-EN
X
X
FAST-SDOEN
X
SDO-EN
SRAM-ADDR
SRAM-DATA
DAC-X-DATA-8BIT
BRDCAST-DATA
X
BRDCAST-DATA
PMBUS-PAGE
PMBUS-VERSION
CLR
X
DAC-X-DATA-8BIT
PMBUS-CML
VOUT-PDN-1
GPI-CH-SEL
SRAM-DATA
PMBUS-OP-CMD
IOUT-PDN-2
LDAC
GPO-CONFIG
SRAM-CONFIG
(1)
(2)
IOUT-PDN-1
DAC-X-DATA
WINLATCH-EN
CMP-X-EN
FUNC-GEN-CONFIG-BLOCK-X
RST-CMPFLAG-0
INTERFACECONFIG
CMP-X-HIZ- CMP-X-INVIN-DIS
EN
X
COMMON-DACTRIG
DEVICE-MODECONFIG
CMP-XOUT-EN
X
CMP-X-MODE
SYNCCONFIG-X
COMMONTRIGGER
GPIO-CONFIG
CMP-X-ODEN
X
DAC-X-DATA
COMMON-CONFIG
BIT0
NOP
X
PMBUS-PAGE
NA
PMBUS-OPERATION-CMD-X
X
NA
CML
X
PMBUS-VERSON
NA
NA
The highlighted gray cells indicate the register bits or fields that are stored in the NVM.
X = Don't care.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
53
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
Table 7-21. Register Names
I2C/SPI
54
PMBUS PAGE ADDR
PMBUS REGISTER
ADDR
00h
FFh
01h
00h
ADDRESS
REGISTER NAME
SECTION
D0h
NOP
Section 7.6.1
25h
DAC-0-MARGIN-HIGH
Section 7.6.2
02h
00h
26h
DAC-0-MARGIN-LOW
Section 7.6.3
03h
FFh
D1h
DAC-0-VOUT-CMP-CONFIG
Section 7.6.4
04h
FFh
D2h
DAC-0-IOUT-MISC-CONFIG
Section 7.6.5
05h
FFh
D3h
DAC-0-CMP-MODE-CONFIG
Section 7.6.6
06h
FFh
D4h
DAC-0-FUNC-CONFIG
Section 7.6.7
07h
01h
25h
DAC-1-MARGIN-HIGH
Section 7.6.1
08h
01h
26h
DAC-1-MARGIN-LOW
Section 7.6.2
09h
FFh
D5h
DAC-1-VOUT-CMP-CONFIG
Section 7.6.3
0Ah
FFh
D6h
DAC-1-IOUT-MISC-CONFIG
Section 7.6.4
0Bh
FFh
D7h
DAC-1-CMP-MODE-CONFIG
Section 7.6.5
0Ch
FFh
D8h
DAC-1-FUNC-CONFIG
Section 7.6.6
0Dh
02h
25h
DAC-2-MARGIN-HIGH
Section 7.6.1
0Eh
02h
26h
DAC-2-MARGIN-LOW
Section 7.6.2
0Fh
FFh
D9h
DAC-2-VOUT-CMP-CONFIG
Section 7.6.3
10h
FFh
DAh
DAC-2-IOUT-MISC-CONFIG
Section 7.6.4
11h
FFh
DBh
DAC-2-CMP-MODE-CONFIG
Section 7.6.5
12h
FFh
DCh
DAC-2-FUNC-CONFIG
Section 7.6.6
13h
03h
25h
DAC-3-MARGIN-HIGH
Section 7.6.1
14h
03h
26h
DAC-3-MARGIN-LOW
Section 7.6.2
15h
FFh
DDh
DAC-3-VOUT-CMP-CONFIG
Section 7.6.3
16h
FFh
DEh
DAC-3-IOUT-MISC-CONFIG
Section 7.6.4
17h
FFh
DFh
DAC-3-CMP-MODE-CONFIG
Section 7.6.5
18h
FFh
E0h
DAC-3-FUNC-CONFIG
Section 7.6.6
19h
00h
21h
DAC-0-DATA
Section 7.6.8
1Ah
01h
21h
DAC-1-DATA
Section 7.6.8
1Bh
02h
21h
DAC-2-DATA
Section 7.6.8
1Ch
03h
21h
DAC-3-DATA
Section 7.6.8
1Fh
FFh
E3h
COMMON-CONFIG
Section 7.6.9
20h
FFh
E4h
COMMON-TRIGGER
Section 7.6.10
21h
FFh
E5h
COMMON-DAC-TRIG
Section 7.6.11
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
Table 7-21. Register Names (continued)
I2C/SPI
PMBUS PAGE ADDR
PMBUS REGISTER
ADDR
REGISTER NAME
SECTION
22h
FFh
E6h
GENERAL-STATUS
Section 7.6.12
23h
FFh
E7h
CMP-STATUS
Section 7.6.13
24h
FFh
E8h
GPIO-CONFIG
Section 7.6.14
25h
FFh
E9h
DEVICE-MODE-CONFIG
Section 7.6.15
ADDRESS
26h
FFh
EAh
INTERFACE-CONFIG
Section 7.6.16
2Bh
FFh
EFh
SRAM-CONFIG
Section 7.6.17
2Ch
FFh
F0h
SRAM-DATA
Section 7.6.18
40h
NA
NA
DAC-0-DATA-8BIT
Section 7.6.19
41h
NA
NA
DAC-1-DATA-8BIT
Section 7.6.19
42h
NA
NA
DAC-2-DATA-8BIT
Section 7.6.19
43h
NA
NA
DAC-3-DATA-8BIT
Section 7.6.19
50h
FFh
F1h
BRDCAST-DATA
Section 7.6.20
NA
All pages
00h
PMBUS-PAGE
Section 7.6.21
NA
00h
01h
PMBIS-OP-CMD-0
Section 7.6.22
NA
01h
01h
PMBUS-OP-CMD-1
Section 7.6.22
NA
02h
01h
PMBUS-OP-CMD-2
Section 7.6.22
NA
03h
01h
PMBUS-OP-CMD-3
Section 7.6.22
NA
All pages
78h
PMBUS-CML
Section 7.6.23
NA
All pages
98h
PMBUS-VERSION
Section 7.6.24
Table 7-22. Access Type Codes
Access Type
Code
Description
X
X
Don't care
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default value
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
55
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.1 NOP Register (address = 00h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = D0h
Figure 7-22. NOP Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
1
0
1
0
NOP
R-0h
Table 7-23. NOP Register Field Descriptions
Bit
Field
Type
Reset
Description
15-0
NOP
R
0000h
No operation
7.6.2 DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
PMBus page address = 00h, 01h, 02h, 03h, PMBus register address = 25h
Figure 7-23. DAC-X-MARGIN-HIGH Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
DAC-X-MARGIN-HIGH[11:0]
DAC-X-MARGIN-HIGH[9:0]
X
R/W-0h
X-0h
Table 7-24. DAC-X-MARGIN-HIGH Register Field Descriptions
Bit
15-4
Field
Type
Reset
Description
DAC-X-MARGIN-HIGH[11:0]
DAC-X-MARGIN-HIGH[9:0]
R/W
000h
Margin-high code for DAC output
Data are in straight-binary format. MSB left-aligned.
Use the following bit-alignment:
DAC63004: {DAC-X-MARGIN-HIGH[11:0]}
DAC53004: {DAC-X-MARGIN-HIGH[9:0], X, X}
X = Don't care bits.
3-0
X
X
0
Don't care
7.6.3 DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
PMBus page address = 00h, 01h, 02h, 03h, PMBus register address = 26h
Figure 7-24. DAC-X-MARGIN-LOW Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
DAC-X-MARGIN-LOW[11:0]
DAC-X-MARGIN-LOW[9:0]
X
R/W-0h
X-0h
Table 7-25. DAC-X-MARGIN-LOW Register Field Descriptions
Bit
15-4
Field
Type
Reset
Description
DAC-X-MARGIN-LOW[11:0]
DAC-X-MARGIN-LOW[9:0]
R/W
000h
Margin-low code for DAC output
Data are in straight-binary format. MSB left-aligned.
Use the following bit-alignment:
DAC63004: {DAC-X-MARGIN-LOW[11:0]}
DAC53004: {DAC-X-MARGIN-LOW[9:0], X, X}
X = Don't care bits.
3-0
56
X
X
0
Don't care
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.4 DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = D1h, D5h, D9h, DDh
Figure 7-25. DAC-X-VOUT-CMP-CONFIG Register (X = 0, 1, 2, 3)
15
14
2
1
0
X
13
12
VOUT-GAIN-X
11
10
9
8
X
7
6
5
CMP- CMPX-OD- X-OUTEN
EN
4
3
CMP-XHIZ-INDIS
CMPX-INVEN
CMPX-EN
X-0h
R/W-0h
X-0h
R/W-0h R/W-0h
R/W-0h
R/W-0h R/W-0h
Table 7-26. DAC-X-VOUT-CMP-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
X
X
0h
Don't care
12-10
VOUT-GAIN-X
R/W
0h
000: Gain = 1x, external reference on VREF pin
001: Gain = 1x, VDD as reference
010: Gain = 1.5x, internal reference
011: Gain = 2x, internal reference
100: Gain = 3x, internal reference
101: Gain = 4x, internal reference
Others: Invalid
X
X
0h
Don't care
4
CMP-X-OD-EN
R/W
0
0: Set OUTx pin as push-pull
1: Set OUTx pin as open-drain in comparator mode (CMP-X-EN =
1 and CMP-X-OUT-EN = 1)
3
CMP-X-OUT-EN
R/W
0
0: Generate comparator output but consume internally
1: Bring comparator output to the respective OUTx pin
2
CMP-X-HIZ-IN-DIS
R/W
0
0: FBx input has high-impedance. Input voltage range is limited.
1: FBx input is connected to resistor divider and has finite
impedance. Input voltage range is same as full-scale.
1
CMP-X-INV-EN
R/W
0
0: Don't invert the comparator output
1: Invert the comparator output
0
CMP-X-EN
R/W
0
0: Disable comparator mode
1: Enable comparator mode. Current-output must be in powerdown. Voltage-output mode must be enabled.
9-5
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
57
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.5 DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = D2h, D6h, DAh, DEh
Figure 7-26. DAC-X-IOUT-MISC-CONFIG Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
X
IOUT-RANGE-X
X
X-0h
R/W-0h
X-0h
3
2
1
0
1
0
Table 7-27. DAC-X-IOUT-MISC-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-13
X
X
0h
Don't care
12-9
IOUT-RANGE-X
R/W
0000
0000: 0 μA to 25 μA
0001: 0 μA to 50 μA
0010: 0 μA to 125 μA
0011: 0 μA to 250 μA
0100: 0 μA to ‒24 μA
0101: 0 μA to ‒48 μA
0110: 0 μA to ‒120 μA
0111: 0 μA to ‒240 μA
1000: ‒25 μA to +25 μA
1001: ‒50 μA to +50 μA
1010: ‒125 μA to +125 μA
1011: ‒250 μA to +250 μA
Others: Invalid
8-0
X
X
000h
Don't care
7.6.6 DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = D3h, D7h, DBh, DFh
Figure 7-27. DAC-X-CMP-MODE-CONFIG Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
X
CMP-X-MODE
X
X-0h
R/W-0h
X-0h
3
2
Table 7-28. DAC-X-CMP-MODE-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-12
X
X
00h
Don't care
11-10
CMP-X-MODE
R/W
00
00: No hysteresis or window function
01: Hysteresis provided using DAC-X-MARGIN-HIGH and DACX-MARGIN-LOW registers
10: Window comparator mode with DAC-X-MARGIN-HIGH and
DAC-X-MARGIN-LOW registers setting window bounds
11: Invalid
X
X
000h
Don't care
9-0
58
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.7 DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = D4h, D8h, DCh, E0h
Figure 7-28. DAC-X-FUNC-CONFIG Register (X = 0, 1, 2, 3)
15
14
13
CLR-SEL-X
SYNCCONFIG-X
BRDCONFIG-X
12
11
10
9
8
FUNC-GEN-CONFIG-BLOCK
7
6
5
4
R/W-0h
R/W-0h
R/W-0h
R/W-0h
3
2
1
0
Table 7-29. DAC-X-FUNC-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
CLR-SEL-X
R/W
0
0: Clear DAC-X to zero-scale
1: Clear DAC-X to mid-scale
14
SYNC-CONFIG-X
R/W
0
0: DAC-X output updates immediately after a write command
1: DAC-X output updates with LDAC pin falling-edge or when the
LDAC bit in the COMMON-TRIGGER register is set to 1
13
BRD-CONFIG-X
R/W
0
0: Don't update DAC-X with broadcast command
1: Update DAC-X with broadcast command
Table 7-30. Linear-Slew Mode: FUNC-GEN-CONFIG-BLOCK Field Descriptions
Field
Type
Reset
Description
12-11
Bit
PHASE-SEL-X
R/W
0
00: 0°
01: 120°
10: 240°
11: 90°
10-8
FUNC-CONFIG-X
R/W
0
000: Triangular wave
001: Sawtooth wave
010: Inverse sawtooth wave
100: Sine wave
111: Disable function generation
Others: Invalid
7
LOG-SLEW-EN-X
R/W
0
0: Enable linear slew
6-4
CODE-STEP-X
R/W
0
CODE-STEP for linear slew mode:
000: 1-LSB
001: 2-LSB
010: 3-LSB
011: 4-LSB
100: 6-LSB
101: 8-LSB
110: 16-LSB
111: 32-LSB
3-0
SLEW-RATE-X
R/W
0
SLEW-RATE for linear slew mode:
0000: No slew for margin-high and margin-low. Invalid for
waveform generation.
0001: 4 µs/step
0010: 8 µs/step
0011: 12 µs/step
0100: 18 µs/step
0101: 27.04 µs/step
0110: 40.48 µs/step
0111: 60.72 µs/step
1000: 91.12 µs/step
1001: 136.72 µs/step
1010: 239.2 µs/step
1011: 418.64 µs/step
1100: 732.56 µs/step
1101: 1282 µs/step
1110: 2563.96 µs/step
1111: 5127.92 µs/step
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
59
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
Table 7-31. Logarithmic-Slew Mode: FUNC-GEN-CONFIG-BLOCK Field Descriptions
Bit
Field
Type
Reset
Description
12-11
PHASE-SEL-X
R/W
0
00: 0°
01: 120°
10: 240°
11: 90°
10 - 8
FUNC-CONFIG-X
R/W
0
000: Triangular wave
001: Sawtooth wave
010: Inverse sawtooth wave
100: Sine wave
111: Disable function generation
Others: Invalid
7
LOG-SLEW-EN-X
R/W
0
1: Enable logarithmic slew.
In logarithmic slew mode, the DAC output moves from the DACX-MARGIN-LOW code to the DAC-X-MARGIN-HIGH code, or
vice versa, in 3.125% steps.
When slewing in the positive direction, the next step is (1 +
0.03125) times the current step.
When slewing in the negative direction, the next step is (1 ‒
0.03125) times the current step.
When DAC-X-MARGIN-LOW is 0, the slew starts from code 1.
The time interval for each step is defined by RISE-SLEW-X and
FALL-SLEW-X.
6-4
RISE-SLEW-X
R/W
0
SLEW-RATE for logarithmic slew mode (DAC-X-MARGIN-LOW to
DAC-X-MARGIN-HIGH):
000: 4 µs/step
001: 12 µs/step
010: 27.04 µs/step
011: 60.72 µs/step
100: 136.72 µs/step
101: 418.64 µs/step
110: 1282 µs/step
111: 5127.92 µs/step
3-1
FALL-SLEW-X
R/W
0
SLEW-RATE for logarithmic slew mode (DAC-X-MARGIN-HIGH
to DAC-X-MARGIN-LOW):
000: 4 µs/step
001: 12 µs/step
010: 27.04 µs/step
011: 60.72 µs/step
100: 136.72 µs/step
101: 418.64 µs/step
110: 1282 µs/step
111: 5127.92 µs/step
X
X
0
Don't care
0
60
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.8 DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
PMBus page address = 00h, 01h, 02h, 03h, PMBus register address = 21h
Figure 7-29. DAC-X-DATA Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
DAC-X-DATA[11:0]
DAC-X-DATA[9:0]
X
R/W-0h
X-0h
0
Table 7-32. DAC-X-DATA Register Field Descriptions
Bit
Field
Type
Reset
Description
15-4
DAC-X-DATA[11:0]
DAC-X-DATA[9:0]
R/W
000h
Data for DAC output
Data are in straight-binary format. MSB left-aligned. MSB leftaligned. Use the following bit-alignment:
DAC63004: {DAC-X-DATA[11:0]}
DAC53004: {DAC-X-DATA[9:0], X, X}
X = Don't care bits.
3-0
X
X
0h
Don't care
7.6.9 COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
PMBus page address = FFh, PMBus register address = E3h
Figure 7-30. COMMON-CONFIG Register
15
14
13
12
WINLATCHEN
DEVLOCK
EE-READADDR
EN-INTREF
VOUT-PDN-3
IOUTPDN-3
VOUT-PDN-2
IOUTPDN-2
VOUT-PDN-1
IOUTPDN-1
VOUT-PDN-0
IOUTPDN-0
R/W-0h
R/W-0h
R/W-11b
R/W-1b
R/W-11b
R/W-1b
R/W-11b
R/W-1b
R/W-11b
R/W-1b
R/W-0h R/W-0h
11
10
9
8
7
6
5
4
3
2
1
0
Table 7-33. COMMON-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
WIN-LATCH-EN
R/W
0
0: Non-latching window-comparator output
1: Latching window-comparator output
14
DEV-LOCK
R/W
0
0: Device not locked
1: Device locked, the device locks all the registers. To set this
bit back to 0 (unlock device), write to the unlock code to the DEVUNLOCK field in the COMMON-TRIGGER register first, followed
by a write to the DEV-LOCK bit as 0.
13
EE-READ-ADDR
R/W
0
0: Fault-dump read enable at address 0x00
1: Fault-dump read enable at address 0x01
12
EN-INT-REF
R/W
0
0: Disable internal reference
1: Enable internal reference. This bit must be set before using
internal reference gain settings.
R/W
11
00: Power-up VOUT-X
01: Power-down VOUT-X with 10 KΩ to AGND
10: Power-down VOUT-X with 100 KΩ to AGND
11: Power-down VOUT-X with Hi-Z to AGND
R/W
1
0: Power-up IOUT-X
1: Power-down IOUT-X
11-10, 8-7, VOUT-PDN-X
5-4, 2-1
9, 6, 3, 0
IOUT-PDN-X
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
61
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E4h
Figure 7-31. COMMON-TRIGGER Register
15
14
13
12
11
10
9
DEV-UNLOCK
RESET
R/W-0h
R/W-0h
8
7
6
5
4
3
2
1
0
LDAC
CLR
X
FAULTDUMP
PROTECT
READONETRIG
NVMPROG
NVMRELOAD
X-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h R/W-0h
Table 7-34. COMMON-TRIGGER Register Field Descriptions
Bit
62
Field
Type
Reset
Description
15-12
DEV-UNLOCK
R/W
0000
0101: Device unlocking password
Others: Don't care
11 - 8
RESET
W
0000
1010: POR reset triggered. This bit self-resets.
Others: Don't care
7
LDAC
R/W
0
0: LDAC operation not triggered
1: LDAC operation triggered if the respective SYNC-CONFIG-X
bit in the DAC-X-FUNC-CONFIG register is 1. This bit self-resets.
6
CLR
R/W
0
0: DAC registers and outputs unaffected
1: DAC registers and outputs set to zero-code or mid-code based
on the respective CLR-SEL-X bit in the DAC-X-FUNC-CONFIG
register. This bit self-resets.
5
X
X
0
Don't care
4
FAULT-DUMP
R/W
0
0: Fault-dump is not triggered
1: Triggers fault-dump sequence. This bit self-resets.
3
PROTECT
R/W
0
0: PROTECT function not triggered
1: Trigger PROTECT function. This bit is self-resetting.
2
READ-ONE-TRIG
R/W
0
0: Fault-dump read not triggered
1: Read one row of NVM for fault-dump. This bit self-resets.
1
NVM-PROG
R/W
0
0: NVM write not triggered
1: NVM write triggered. This bit self-resets.
0
NVM-RELOAD
R/W
0
0: NVM reload not triggered
1: Reload data from NVM to register map. This bit self-resets.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E5h
Figure 7-32. COMMON-DAC-TRIG Register
15
14
13
RESETCMPFLAG-0
TRIGMARLO-0
TRIGMARHI-0
W-0h
W-0h
W-0h
12
11
10
9
START- RESETFUNC-0 CMPFLAG-1
TRIGMARLO-1
TRIGMARHI-1
R/W-0h
W-0h
W-0h
W-0h
8
7
6
5
START- RESETFUNC-1 CMPFLAG-2
TRIGMARLO-2
TRIGMARHI-2
R/W-0h
W-0h
W-0h
W-0h
4
3
2
1
0
START- RESETFUNC-2 CMPFLAG-2
TRIGMARLO-3
TRIGMARHI-3
STARTFUNC-3
R/W-0h
W-0h
W-0h
R/W-0h
W-0h
Table 7-35. COMMON-DAC-TRIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15, 11, 7, RESET-CMP-FLAG-X
3
W
0
0: Latching-comparator output unaffected
1: Reset latching-comparator and window-comparator output.
This bit self-resets.
14, 10, 6, TRIG-MAR-LO-X
2
W
0
0: Don't care
1: Trigger margin-low command. This bit self-resets.
13, 9, 5, 1 TRIG-MAR-HI-X
W
0
0: Don't care
1: Trigger margin-high command. This bit self-resets.
12, 8, 4, 0 START-FUNC-X
R/W
0
0: Stop function generation
1: Start function generation as per FUNC-GEN-CONFIG-X in the
DAC-X-FUNC-CONFIG register.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
63
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
PMBus page address = FFh, PMBus register address = E6h
Figure 7-33. GENERAL-STATUS Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NVMCRCFAIL-INT
NVMCRCFAILUSER
X
DAC-3BUSY
DAC-2BUSY
DAC-1BUSY
DAC-0BUSY
X
DEVICE-ID
VERSION-ID
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
X-0h
R
R-0h
Table 7-36. GENERAL-STATUS Register Field Descriptions
64
Bit
Field
Type
Reset
Description
15
NVM-CRC-FAIL-INT
R
0
0: No CRC error in OTP
1: Indicates a failure in OTP loading. A software
reset or power-cycle can bring the device out of
this condition in case of temporary failure.
14
NVM-CRC-FAIL-USER
R
0
0: No CRC error in NVM loading
1: Indicates a failure in NVM loading. The register
settings are corrupted. The device allows all
operations during this error condition. Reprogram
the NVM to get original state. A software reset
brings the device out of this temporary error
condition.
13
X
R
0
Don't care
12
DAC-3-BUSY
R
0
0: DAC-3 channel can accept commands
1: DAC-3 channel does not accept commands
11
DAC-2-BUSY
R
0
0: DAC-2 channel can accept commands
1: DAC-2 channel does not accept commands
10
DAC-1-BUSY
R
0
0: DAC-1 channel can accept commands
1: DAC-1 channel does not accept commands
9
DAC-0-BUSY
R
0
0: DAC-0 channel can accept commands
1: DAC-0 channel does not accept commands
8
X
R
0
Don't care
7-2
DEVICE-ID
R
DAC53004: 05h
DAC63004: 04h
Device identifier
1-0
VERSION-ID
R
00
Version identifier
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.13 CMP-STATUS Register (address = 23h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E7h
Figure 7-34. CMP-STATUS Register
15
14
13
12
11
10
9
X
8
7
6
5
4
3
2
1
0
PROTECT- WIN- WIN- WIN- WIN- CMP- CMP- CMP- CMPFLAG
CMP-3 CMP-2 CMP-1 CMP-0 FLAG- FLAG- FLAG- FLAG3
2
1
0
X-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
Table 7-37. CMP-STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
X
X
0
Don't care
PROTECT-FLAG
R
0
0: PROTECT operation not triggered.
1: PROTECT function is completed or in progress. This bit resets
to 0 when read.
7, 6, 5, 4
WIN-CMP-X
R
0
Window comparator output from respective channels. The output
is latched or unlatched based on the WINDOW-LATCH-EN
setting in the COMMON-CONFIG register.
3, 2, 1, 0
CMP-FLAG-X
R
0
Synchronized comparator output from respective channels.
15-9
8
7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E8h
Figure 7-35. GPIO-CONFIG Register
15
14
13
GF-EN
DEEP- GPO-EN
SLEEPEN
R/W-0h
R/W-0h
12
11
10
9
8
7
6
5
4
3
2
1
0
GPO-CONFIG
GPI-CH-SEL
GPI-CONFIG
GPI-EN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
Table 7-38. GPIO-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15
GF-EN
R/W
0
0: Glitch filter disabled for GP input. This setting provides faster
response.
1: Glitch filter enabled for GP input. This setting introduces
additional propagation delay but provides robustness.
14
DEEP-SLEEP-EN
R/W
0
0: Deep-sleep mode disabled
1: Deep-sleep mode enabled for GP input
13
GPO-EN
R/W
0
0: Disable output mode for GPIO pin
1: Enable output mode for GPIO pin
GPO-CONFIG
R/W
0000
STATUS function setting. The GPIO pin is mapped to the
following register bits as output:
0001: NVM-BUSY
0100: DAC-0-BUSY
0101: DAC-1-BUSY
0110: DAC-2-BUSY
0111: DAC-3-BUSY
1000: WIN-CMP-0
1001: WIN-CMP-1
1010: WIN-CMP-2
1011:WIN-CMP-3
Others: Invalid
12-9
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
65
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
Table 7-38. GPIO-CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
8-5
GPI-CH-SEL
R/W
0000
Each bit corresponds to a DAC channel. 0b is disabled and 1b is
enabled.
GPI-CH-SEL[0]: Channel 0
GPI-CH-SEL[1]: Channel 1
GPI-CH-SEL[2]: Channel 2
GPI-CH-SEL[3]: Channel 3
Example: when GPI-CH-SEL is 0101, both channel-0 and
channel-2 are enabled and both channel-1 and channel-3 are
disabled.
4-1
GPI-CONFIG
R/W
0000
GPIO pin input configuration. Global settings act on the entire
device. Channel-specific settings are dependent on the channel
selection by the GPI-CH-SEL bits:
0000: DEEP-SLEEP (global). GPIO falling-edge triggers deepsleep mode, GPIO rising-edge takes the device out of deep-sleep
mode.
0010: FAULT-DUMP (global). GPIO falling-edge triggers faultdump, GPIO = 1 has no effect.
0011: IOUT power-up, down (channel-specific). GPIO falling-edge
triggers power-down, GPIO rising-edge triggers power-up.
0100: VOUT power-up/down (channel-specific). The output load
is as per the VOUT-PDN-X setting. GPIO falling-edge triggers
power-down, GPIO rising-edge triggers power-up.
0101: PROTECT input (global). GPIO falling-edge asserts
PROTECT function, GPIO = 1 has no effect.
0111: CLR input (global). GPIO = 0 asserts CLR function, GPIO =
1 has no effect.
1000: LDAC input (channel-specific). GPIO falling-edge asserts
LDAC function, GPIO = 1 has no effect. Both the SYNC-CONFIGX and the GPI-CH-SEL must be configured for every channel.
1001: Start, stop function generation (channel-specific). GPIO
falling-edge stops function generation. GPIO rising-edge starts
function generation.
1010: Trigger margin-high, low (channel-specific). GPIO fallingedge triggers margin-low. GPIO rising-edge triggers margin-high.
1011: RESET input (global). The falling-edge of the GPIO pin
asserts the RESET function. The RESET input must be a pulse.
The GPIO rising-edge brings the device out of reset. The RESET
configuration must be programmed into the NVM. Otherwise the
setting will be cleared after the device reset.
1100: NVM write-protection (global). GPIO falling-edge allows
NVM programming. GPIO rising-edge blocks NVM programming.
1101: Register-map lock (global). GPIO falling-edge allows
update to the register map. GPIO rising-edge blocks any register
map update except a write to the DEV-UNLOCK field through I2C
or SPI and to the RESET field through I2C.
Others: Not applicable
0
66
GPI-EN
R/W
0
0: Disable input mode for GPIO pin
1: Enable input mode for GPIO pin
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = E9h
Figure 7-36. DEVICE-MODE-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RESERVED
DISMODE-IN
RESERVED
PROTECTCONFIG
RESERVED
X
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
X-0h
1
0
Table 7-39. DEVICE-MODE-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R/W
00
Always write 0b00
DIS-MODE-IN
R/W
0
Write 1 to this bit for low-power consumption.
RESERVED
R/W
0
Always write 0b000
9-8
PROTECT-CONFIG
R/W
00
00: Switch to Hi-Z power-down (no slew)
01: Switch to DAC code stored in NVM (no slew) and then switch
to Hi-Z power-down
10: Slew to margin-low code and then switch to Hi-Z power-down
11: Slew to margin-high code and then switch to Hi-Z power-down
7-5
RESERVED
R/W
0
Always write 0b000
4-0
X
R/W
00h
Don't care
15-14
13
12-10
7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
Figure 7-37. INTERFACE-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
X
SDOEN
X
TIMEOUTEN
X
EN-PMBUS
X
FSDOEN
X-0h
R/W-0h
X-0h
R/W-0h
X-0h
R/W-0h
X-0h R/W-0h
Table 7-40. INTERFACE-CONFIG Register Field Descriptions
Bit
15-13
12
11-9
8
7-3
Field
Type
Reset
Description
X
X
0h
Don't care
TIMEOUT-EN
R/W
0
0: I2C timeout disabled
1: I2C timeout enabled
X
X
0h
Don't care
EN-PMBUS
R/W
0
0: PMBus disabled
1: Enable PMBus
X
X
00h
Don't care
2
FSDO-EN
R/W
0
0: Fast SDO disabled
1: Fast SDO enabled
1
X
X
0
Don't care
0
SDO-EN
R/W
0
0: SDO disabled
1: SDO enabled on GPIO pin
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
67
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
PMBus page address = FFh, PMBus register address = EFh
Figure 7-38. SRAM-CONFIG Register
15
14
13
12
11
10
9
8
7
6
5
4
3
X
SRAM-ADDR
X-0h
R/W-0h
2
1
0
Table 7-41. SRAM-CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
X
X
0h
Don't care
7-0
SRAM-ADDR
R/W
0h
8-bit SRAM address. Writing to this register field configures the
SRAM address to be accessed next. This address automatically
increments after a write to the SRAM.
7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
PMBus page address = FFh, PMBus register address = F0h
Figure 7-39. SRAM-DATA Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SRAM-DATA
R/W-0h
Table 7-42. SRAM-DATA Register Field Descriptions
Bit
15-0
68
Field
Type
Reset
Description
SRAM-ADDR
R/W
0h
16-bit SRAM data. This data is written to or read from the address
configured in the SRAM-CONFIG register.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.19 DAC-X-DATA-8BIT Register (address = 40h, 41h, 42h, 43h) [reset = 0000h]
PMBus page address = Not applicable, PMBus register address = Not applicable
Figure 7-40. DAC-X-DATA-8BIT Register
15
14
13
12
11
10
9
8
7
6
5
4
3
DAC-X-DATA-8BIT[7:0]
X
R/W-0h
X-0h
2
1
0
Table 7-43. DAC-X-DATA-8BIT Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
DAC-X-DATA-8BIT[7:0]
R/W
00h
8-bit data for current output. This register provides faster update
rate in the I2C mode. Data are in straight-binary format
7-0
X
X
00h
Not applicable
7.6.20 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
PMBus page address = FFh, PMBus register address = F1h
Figure 7-41. BRDCAST-DATA Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
BRDCAST-DATA[11:0]
BRDCAST-DATA[9:0]
X
R/W-0h
X-0h
0
Table 7-44. BRDCAST-DATA Register Field Descriptions
Bit
Field
Type
Reset
Description
15-4
BRDCAST-DATA[11:0]
BRDCAST-DATA[9:0]
R/W
000h
Broadcast code for all DAC channels
Data are in straight-binary format. MSB left-aligned. Use the
following bit-alignment:
DAC63004: {BRDCAST-DATA[11:0]}
DAC53004: {BRDCAST-DATA[9:0], X, X}
X = Don't care bits.
The BRD-CONFIG-X bit in the DAC-X-FUNC-CONFIG register
must be enabled for the respective channels.
3-0
X
X
0h
Don't care.
7.6.21 PMBUS-PAGE Register [reset = 0300h]
PMBus page address = X, PMBus register address = 00h
Figure 7-42. PMBUS-PAGE Register
15
14
13
12
11
10
9
8
7
6
5
4
3
PMBUS-PAGE
X
R/W-03h
X-00h
2
1
0
Table 7-45. PMBUS_OPERATION Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
PMBUS-PAGE
R/W
03h
8-bit PMBus page address as specified in Table 7-21.
7-0
X
X
00h
Not applicable
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
69
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
7.6.22 PMBUS-OP-CMD-X Register [reset = 0000h]
PMBus page address = 00h, 01h, 02h, 03h, PMBus register address = 01h
Figure 7-43. PMBUS-OP-CMD-X Register (X = 0, 1, 2, 3)
15
14
13
12
11
10
9
8
7
6
5
4
3
PMBUS-OPERATION-CMD-X
X
R/W-00h
X-00h
2
1
0
Table 7-46. PMBUS-OP-CMD-X Register Field Descriptions
Bit
Field
Type
Reset
Description
15-8
PMBUS-OPERATION-CMD-X
R/W
00h
PMBus operation commands:
00h: Turn off
80h: Turn on
A4h: Margin high, DAC output margins high to DAC-X-MARGINHIGH code
94h: Margin low, DAC output margins low to DAC-X-MARGINLOW code
7-0
X
X
00h
Not applicable
7.6.23 PMBUS-CML Register [reset = 0000h]
PMBus page address = X, PMBus register address = 78h
Figure 7-44. PMBUS-CML Register
15
14
13
12
11
10
9
8
7
6
5
4
3
X
CML
X
N/A
X-00h
R/W-0h
X-0h
X-00h
2
1
0
Table 7-47. PMBUS-CML Register Field Descriptions
Bit
15-10
Field
Type
Reset
Description
X
X
00h
Don't care
9
CML
R/W
0
0: No communication fault
1: PMBus communication fault for write with incorrect number of
clocks, read before write command, invalid command address,
and invalid or unsupported data value; reset this bit by writing 1.
8
X
X
0h
Don't care
7-0
X
X
00h
Not applicable
7.6.24 PMBUS-VERSION Register [reset = 2200h]
PMBus page address = X, PMBus register address =98h
Figure 7-45. PMBUS-VERSION Register
15
14
13
12
11
10
9
8
7
6
5
4
3
PMBUS-VERSION
X
R-22h
X-00h
2
1
0
Table 7-48. PMBUS-VERSION Register Field Descriptions
Bit
70
Field
Type
Reset
Description
15-8
PMBUS-VERSION
R
22h
PMBus version
7-0
X
X
00h
Not applicable
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The DACx3004 are quad-channel buffered, force-sense output, voltage-output and current-output smart DACs
that include an NVM and internal reference, and available in a tiny 3-mm × 3-mm package. In voltage-output
mode, short the OUTx and FBx pins for each channel. In current-output mode, leave the FBx pins unconnected.
The FBx pins function as inputs in comparator mode. The external reference must not exceed VDD, either during
transient or steady-state conditions. For the best Hi-Z output performance, use a pullup resistor on the VREF
pin to VDD. In case the VDD remains floating during the off condition, place a 100-kΩ resistor to AGND for
proper detection of the VDD off condition. All the digital outputs are open drain; use external pullup resistors on
these pins. The interface protocol is detected at power-on, and the device locks to the protocol as long as VDD
is on. In I2C mode, when allocating the I2C addresses in the system, consider the broadcast address as well.
I2C timeout can be enabled for robustness. SPI mode is 3-wire by default. Configure the GPIO pin as SDO in
the NVM for SPI readback capability. The SPI clock speed in readback mode is slower than that in write mode.
Power-down mode sets the DAC outputs in Hi-Z by default. Change the configuration appropriately for different
power-down settings. The DAC channels can also power-up with a programmed DAC code in the NVM.
8.2 Typical Application
A power-supply margining and scaling circuit is used to trim, scale, or test the output of a power converter.
This example circuit is used to test a system by margining the power supplies for adaptive voltage scaling or to
program a desired value at the output. Adjustable power supplies, such as low-dropout regulators (LDOs) and
DC/DC converters, provide a feedback or adjust the input that is used to set the desired output. A precision
voltage-output DAC is the best choice for controlling the power-supply output linearly. Figure 8-1 shows a control
circuit for a switch-mode power supply (SMPS) using the DACx3004. Typical applications of power-supply
margining are communications equipment, enterprise servers, test and measurement, and general-purpose
power-supply modules.
VDD
10 kΩ
0.1 μ
VREF
CAP
1.5 μF
LDO
L
IN
PH
SMPS / LDO
VOUT
BOOT
CL
CB
SENSE
Internal
Reference
R1
VFB
R3
R2
R3
GND
R3
Power-supply: 0 - 3
R3
NVM
VOUT/
IOUT
DAC
REG
DAC
BUF
VOUT/
IOUT
DAC
REG
DAC
BUF
VOUT/
IOUT
DAC
REG
DAC
BUF
VOUT/
IOUT
DAC
REG
DAC
BUF
Output Configuration
Logic
SCL/SYNC
Digital Interface
VIN
SDA/SCLK
A0/SDI
PROTECT
DACx3004
AGND
Figure 8-1. Voltage Margining and Scaling
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
71
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
8.2.1 Design Requirements
Table 8-1. Design Parameters
PARAMETER
VALUE
Power-supply nominal output
3.3 V
Reference voltage of the converter (VFB)
0.6 V
Margin
±10% (that is, 2.97 V to 3.63 V)
DAC output range
1.8 V
Nominal current through R1 and R2
100 µA
8.2.2 Detailed Design Procedure
The DACx3004 features a Hi-Z power-down mode that is set by default at power-up, unless the device is
programmed otherwise using the NVM. When the DAC output is at Hi-Z, the current through R3 is zero and the
SMPS is set at the nominal output voltage of 3.3 V. To have the same nominal condition when the DAC powers
up, bring up the device at the same output as VFB (that is 0.6 V). This configuration makes sure there is no
current through R3 even at power-up. Calculate R1 as (VOUT – VFB) / 100 µA = 27 kΩ.
To achieve ±10% margin-high and margin-low conditions, the DAC must sink or source additional current
through R1. Calculate the current from the DAC (IMARGIN) using Equation 10 as 12 µA.
where
•
•
•
IMARGIN =
VOUT × 1 + MARGIN − VFB
− INOMINAL
R1
(10)
IMARGIN is the margin current sourced or sinked from the DAC.
MARGIN is the percentage margin value divided by 100.
INOMINAL is the nominal current through R1 and R2.
To calculate the value of R3, first decide the DAC output range, and make sure to avoid the codes near
zero-scale and full-scale for safe operation in the linear region. A DAC output of 20 mV is a safe consideration as
the minimum output, and (1.8 V – 0.6 V – 20 mV = 1.18 V) as the maximum output. When the DAC output is at
20 mV, the power supply goes to margin high, and when the DAC output is at 1.18 V, the power supply goes to
margin low. Calculate the value of R3 using Equation 11 as 48.3 kΩ. Choose a standard resistor value and adjust
the DAC outputs. Choosing R3 = 47 kΩ makes the DAC margin high code as 1.164 V and the DAC margin low
code as 36 mV.
R3 =
VDAC − VFB
IMARGIN
(11)
When the DACx3004 are set in the current-output mode, the series resistor R3 is not required. Set the DAC
output at the current-output range of –25 µA to +25 µA, and set the DAC code appropriately to achieve a margin
current of ±12 µA.
The DACx3004 have a slew-rate feature that is used to toggle between margin high, margin low, and nominal
outputs with a defined slew rate. See Section 7.6.7 for the slew-rate setting details.
Note
The DAC-X-MARGIN-HIGH register value in DACx3004 results in the margin-low value at the power
supply output. Similarly, the DAC-X-MARGIN-LOW register value in DACx3004 results in the marginhigh value at the power-supply output.
72
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
The pseudocode for getting started with a power-supply control application is as follows:
//SYNTAX: WRITE , ,
//Write DAC code for nominal output (repeat for all DAC channels)
//For a 1.8-V output range, the 10-bit hex code for 0.6 V is 0x155. With 16-bit left alignment,
this becomes 0x5540
WRITE DAC_DATA(0x19), 0x55, 0x40
//Power-up voltage output on all channels, enables internal reference WRITE COMMON-CONFIG(0x1F),
0x12, 0x49
//Set channel 0 gain setting to 1.5x internal reference (1.8 V)
WRITE DAC-0-VOUT-CMP-CONFIG(0x3), 0x08, 0x00
//Set channel 1 gain setting to 1.5x internal reference (1.8 V)
WRITE DAC-1-VOUT-CMP-CONFIG(0x9), 0x08, 0x00
//Set channel 2 gain setting to 1.5x internal reference (1.8 V)
WRITE DAC-2-VOUT-CMP-CONFIG(0xF), 0x08, 0x00
//Set channel 3 gain setting to 1.5x internal reference (1.8 V)
WRITE DAC-3-VOUT-CMP-CONFIG(0x15), 0x08, 0x00
//Configure GPI for Margin-High, Low trigger for all channels
WRITE GPIO-CONFIG(0x24), 0x01, 0xF5
//Set slew rate and code step (repeat for all channels)
//CODE_STEP: 2 LSB, SLEW_RATE: 60.72 µs/step
WRITE DAC-0-FUNC-CONFIG(0x06), 0x00, 0x17
//Write DAC margin high code (repeat for all channels)
//For a 1.8-V output range, the 10-bit hex code for 1.164 V is 0x296. With 16-bit left alignment,
this becomes 0xA540
WRITE DAC-0-MARGIN-HIGH(0x01), 0xA5, 0x40
//Write DAC margin low code (repeat for all channels)
//For a 1.8-V output range, the 10-bit hex code for 36 mV is 0x14. With 16-bit left alignment, this
becomes 0x0500
WRITE DAC-0-MARGIN-LOW(0x02), 0x05, 0x00
//Save settings to NVM
WRITE COMMON-TRIGGER(0x20), 0x00, 0x02
8.2.3 Application Curves
Figure 8-2. Power-Supply Margin High
Figure 8-3. Power-Supply Margin Low
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
73
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
9 Power Supply Recommendations
The DACx3004 family of devices does not require specific power-supply sequencing. These devices require a
single power supply, VDD. However, make sure the external voltage reference is applied after VDD. Use a 0.1-µF
decoupling capacitor for the VDD pin. Use a bypass capacitor with a value approximately 1.5 µF for the CAP pin.
10 Layout
10.1 Layout Guidelines
The DACx3004 pin configuration separates the analog, digital, and power pins for an optimized layout. For signal
integrity, separate the digital and analog traces, and place decoupling capacitors close to the device pins.
10.2 Layout Example
Figure 10-1. Layout Example
Note: The ground and power planes have been omitted for clarity. Connect the thermal pad to ground.
74
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
DAC63004, DAC53004
www.ti.com
SLASEX2A – APRIL 2021 – REVISED DECEMBER 2021
11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
PMBus™ is a trademark of SMIF, Inc..
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: DAC63004 DAC53004
75
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2023
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
DAC53004RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D53004
Samples
DAC53004RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D53004
Samples
DAC63004RTER
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D63004
Samples
DAC63004RTET
ACTIVE
WQFN
RTE
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
D63004
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
