DAC7545JU

DAC7545 DA C75 DAC 7 54 45 5 SBAS150A – AUGUST 1987 – REVISED FEBRUARY 2003 CMOS 12-Bit Multiplying DIGITAL-TO-ANALOG CONVERTER Microprocessor Compatible FEATURES DESCRIPTION ● ● ● ● ● ● ● ● The DAC7545 is a low-cost, CMOS, 12-bit, four-quadrant multiplying, digital-to-analog converter (DAC) with input data latches. The input data is loaded into the DAC as a 12-bit data word. The data flows through to the DAC when both the chip select (CS ) and the write (WR) pins are at a logic low. FOUR-QUADRANT MULTIPLICATION LOW-GAIN TC: 2ppm/°C typ MONOTONICITY ENSURED OVER TEMPERATURE SINGLE 5V TO 15V SUPPLY TTL/CMOS LOGIC COMPATIBLE LOW OUTPUT LEAKAGE: 10nA max LOW OUTPUT CAPACITANCE: 70pF max DIRECT REPLACEMENT FOR THE AD7545, PM-7545 Laser-trimmed thin-film resistors and excellent CMOS voltage switches provide true 12-bit integral and differential linearity. The device operates on a single +5V to +15V supply and is available in an SO-20 package; devices are specified over the commercial temperature range. The DAC7545 is well suited for battery-powered or other lowpower applications because the power dissipation is less than 0.5mW when used with CMOS logic inputs and VDD = +5V. RFB 20 VREF 19 12-Bit Multiplying DAC 12 WR 17 CS 16 Input Data Latches 1 OUT 1 2 AGND 18 3 VDD DGND 12 DB11-DB0 (Pins 4-15) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 1987-2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) TA = +25°C, unless otherwise noted. VDD to DGND ........................................................................... –0.3V, +17 Digital Input to DGND ............................................................... –0.3V, VDD VRFB, VREF, to DGND ........................................................................ ±25V VPIN 1 to DGND ........................................................................ –0.3V, VDD AGND to DGND ........................................................................ –0.3V, VDD Power Dissipation: Any Package to +75°C .................................... 450mW Derates above +75°C by ................................ 6mW/°C Operating Temperature: Commercial J, K, L, and GL ........................................... –40°C to +85°C Storage Temperature ...................................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. NOTE: (1) Stresses above those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT DAC7545 " DAC7545 " SPECIFIED RELATIVE GAIN ERROR (LSB) PACKAGE TEMPERATURE ACCURACY (LSB) VDD = +5V PACKAGE-LEAD DESIGNATOR(1) RANGE ±2 ±1 ±1/2 ±1/2 ±20 ±10 ±5 ±2 SO-20 " SO-20 " DW " DW " PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY –40°C to +85°C DAC7545JU DAC7545JU " DAC7545KU DAC7545KU –40°C to +85°C DAC7545LU DAC7545LU " DAC7545GLU DAC7545GLU Rails, Rails, Rails, Rails, 38 38 38 38 NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN CONNECTIONS Top View SO OUT 1 1 20 RFB AGND 2 19 VREF DGND 3 18 VDD (MSB) DB11 4 17 WR DB10 5 DB9 6 15 DB0 (LSB) DB8 7 14 DB1 DB7 8 13 DB2 DB6 9 12 DB3 DB5 10 11 DB4 DAC7545 16 CS WRITE CYCLE TIMING DIAGRAM CS tCS tCH VDD Mode Selection 0 WR tWR VDD tDS Data In (DB0-DB11) 2 VIH VIL Write Mode Data Valid tDH CS and WR low, DAC responds Data Bus (DB0-DB11) inputs. 0 VDD 0 Hold Mode Either CS or WR high, data bus to (DB0-DB11) is locked out; DAC holds last data present when WR or CS assumed high state. NOTES: VDD = +5V, tR = tF = 20ns. VDD = +15V, tR = tF = 40ns. All inputs signal rise and fall times measured from 10% to 90% of VDD. Timing measurement reference level is (VIH + VIL)/2. DAC7545 www.ti.com SBAS150A ELECTRICAL CHARACTERISTICS VREF = +10V, VOUT 1 = 0V, and ACOM = DCOM, unless otherwise specified. DAC7545 VDD = +5V VDD = +15V GRADE TA = +25°C TMAX-TMIN(1) TA = +25°C TMAX-TMIN(1) All J K L GL J K L GL J K L GL 12 ±2 ±1 ±1/2 ±1/2 ±4 ±1 ±1 ±1 ±20 ±10 ±5 ±2 12 ±2 ±1 ±1/2 ±1/2 ±4 ±1 ±1 ±1 ±20 ±10 ±6 ±3 12 ±2 ±1 ±1/2 ±1/2 ±4 ±1 ±1 ±1 ±25 ±15 ±10 ±6 12 ±2 ±1 ±1/2 ±1/2 ±4 ±1 ±1 ±1 ±25 ±15 ±10 ±7 Gain Temperature Coefficient(3) (∆Gain/∆Temperature) All ±5 ±5 ±10 ±10 DC Supply Rejection(3) (∆Gain/∆VDD) Output Leakage Current at Out 1 All J, K, L, GL 0.015 10 0.03 50 0.01 10 0.02 50 %/% nA All 2 2 2 2 µs 300 400 5 5 250 250 5 5 PARAMETER STATIC PERFORMANCE Resolution Accuracy Differential Nonlinearity Gain Error (with internal RFB)(2) DYNAMIC PERFORMANCE Current Settling Time(3) UNITS TEST CONDITIONS/COMMENTS Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB 10-Bit Monotonic, TMIN to TMAX 10-Bit Monotonic, TMIN to TMAX 12-Bit Monotonic, TMIN to TMAX 12-Bit Monotonic, TMIN to TMAX DAC register loaded with FFFH. Gain error is adjustable using the circuits in Figures 2 and 3. ppm/°C Typical Value is 2ppm/°C for VDD = +5 ∆VDD ± 5% DB0-DB11 = 0V; WR, CS = 0V To 1/2 LSB. Out 1 Load = 100Ω DAC output measured from falling edge of WR. CS = 0V. Propagation Delay(3) (from digital input change to 90% of final analog output) Glitch Energy AC Feedback at IOUT 1 All All REFERENCE INPUT Input Resistance (pin 19 to AGND) All 7 25 7 25 7 25 7 25 kΩ(6) kΩ AC OUTPUTS Output Capacitance(3): COUT 1 COUT 2 All All 70 200 70 200 70 200 70 200 pF pF DB0-DB11 = 0V; WR, CS = 0V DB0-DB11 = VDD; WR, CS = 0V DIGITAL INPUTS VIH (Input HIGH Voltage) VIL (Input LOW Voltage) IIN (Input Current)(7) Input Capacitance(3): DB0-DB11 WR, CS All All All All All 2.4 0.8 ±1 5 20 2.4 0.8 ±10 5 20 13.5 1.5 ±1 5 20 13.5 1.5 ±10 5 20 V(6) V µA pF pF VIN = 0V or VDD VIN = 0V VIN = 0V SWITCHING CHARACTERISTICS(8) Chip Select to Write Setup Time, tCS All All All Data Setup Time, tDS All Data Hold Time, tDH All 380 270 0 400 280 210 150 10 180 120 0 160 100 90 60 10 200 150 0 240 170 120 80 10 ns(6) ns(5) ns(6) ns(6) ns(5) ns(6) ns(5) ns(6) See Timing Diagram Chip Select to Write Hold Time, tCH Write Pulse Width, tWR 280 200 0 250 175 140 100 10 All All All 2 100 10 2 500 10 2 100 10 2 500 10 mA µA µA(5) All Digital Inputs VIL or VIH All Digital Inputs 0V or VDD All Digital Inputs 0V or VDD All ns Out 1 Load = 100Ω. CEXT = 13pF(4) nV-s(5) VREF = ACOM mVp-p(5) VREF = ±10V, 10kHz Sine Wave Input Resistance TC = 300ppm/°C(5) tCS ≥ tWR, tCH ≥ 0 POWER SUPPLY, IDD NOTES: (1) Temperature ranges—J, K, L, and GL: –40°C to +85°C. (2) This includes the effect of 5ppm max, gain TC. (3) Ensured but not tested. (4) DB0-DB11 = 0V to VDD or VDD to 0V. (5) Typical. (6) Minimum. (7) Logic inputs are MOS gates. Typical input current (+25°C) is less than 1nA. (8) Sample tested at +25°C to ensure compliance. DAC7545 SBAS150A www.ti.com 3 DISCUSSION OF SPECIFICATIONS MONOTONICITY RELATIVE ACCURACY This term (also known as end point linearity) describes the transfer function of analog output to digital input code. Relative accuracy describes the deviation from a straight line after zero and full-scale have been adjusted. Monotonicity assures that the analog output will increase or stay the same for increasing digital input codes. The DAC7545 is ensured monotonic to 12 bits, except the J grade is specified to be 10-bit monotonic. POWER-SUPPLY REJECTION Power-supply rejection is the measure of the sensitivity of the output (full-scale) to a change in the power-supply voltage. DIFFERENTIAL NONLINEARITY Differential nonlinearity is the deviation from an ideal 1LSB change in the output, for adjacent input code changes. A differential nonlinearity specification of 1LSB ensures monotonicity. GAIN ERROR Gain error is the difference in measure of full-scale output versus the ideal DAC output; the ideal output for the DAC7545 is –(4095/4096)(VREF). Gain error can be adjusted to zero using external trims, see the Applications section. OUTPUT LEAKAGE CURRENT The current that appears at OUT 1 with the DAC loaded with all zeros. MULTIPLYING FEEDTHROUGH ERROR The AC output error due to capacitive feedthrough from VREF to OUT 1 with the DAC loaded with all zeros; this test is performed using a 10kHz sine wave. OUTPUT CURRENT SETTLING TIME CIRCUIT DESCRIPTION Figure 1 shows a simplified schematic of the DAC portion of the DAC7545. The current from the VREF pin is switched from OUT 1 to AGND by the FET switch. This circuit architecture keeps the resistance at the reference pin constant and equal to RLDR, so the reference can be provided by either a voltage or current, AC or DC, positive or negative polarity, and have a voltage range up to ±20V even with VDD = 5V. The RLDR is equal to R and is typically 11kW. The output capacitance of the DAC7545 is code dependent and varies from a minimum value (70pF) at code 000h to a maximum (200pF) at code FFFh. The input buffers are CMOS inverters, designed so that when the DAC7545 is operated from a 5V supply (VDD), the logic threshold is TTL-compatible. Being simple CMOS inverters, there is a range of operation where the inverters operate in the linear region and thus draw more supply current than normal. Minimizing this transition time through the linear region and insuring that the digital inputs are operated as close to the rails as possible will minimize the supply drain current. The time required for the output to settle within ±0.5 LSB of final value from a change in code of all zeros to all ones, or all ones to all zeros. R VREF R R R PROPAGATION DELAY 2R The delay of the internal circuitry is measured as the time from a digital code change to the point at which the output reaches 90% of final value. 2R 2R 2R 2R RFB OUT 1 DIGITAL-TO-ANALOG GLITCH IMPULSE AGND The area of the glitch energy measured in nanovolt-seconds. Key contributions to glitch energy are internal circuitry timing differences and charge injected from digital logic. The measurement is performed with VREF = GND, an OPA600 as the output op amp, and G1 (phase compensation) = 0pF. 4 DB11 (MSB) DB10 DB9 DB0 (LSB) FIGURE 1. Simplified DAC Circuit of the DAC7545. DAC7545 www.ti.com SBAS150A APPLICATIONS tance. Eliminating this capacitor will result in excessive ringing and an increase in glitch energy, therefore, this capacitor must be as small as possible to minimize settling time. UNIPOLAR OPERATION Figure 2 shows the DAC7545 connected for unipolar operation. The high-grade DAC7545 is specified for a 1LSB gain error, so gain adjust is typically not needed; however, the resistors shown are for adjusting full-scale errors. The value of R1 should be minimized to reduce the effects of mismatching temperature coefficients between the internal and external resistors. A range of adjustment of 1.5 times the desired range will be adequate. For example, for a DAC7545JP, the gain error is specified to be ±25LSB, therefore, a range of adjustment of ±37LSB will be adequate. Equation 1 results in a value of 458W for the potentiometer (use 500Ω). R1 = RLADDER (3 • Gain Error) 4096 VDD VREF R1 BIPOLAR OPERATION Figure 3 and Table II illustrate the recommended circuit and code relationship for bipolar operation. The DAC function uses offset binary code. The inverter, U1, on the MSB line converts binary two’s complement input code to offset binary code. If the inversion is done in software, U1 can be omitted. (1) BINARY CODE RFB ANALOG OUTPUT MSB LSB 1111 1111 1111 1000 0000 0000 0000 0000 0001 0000 0000 0000 R2 +5V VIN The circuit of Figure 2 can be used with input voltages up to ±20V as long as the output amplifier is biased to handle the excursions. Table I represents the analog output for four codes into the DAC for Figure 2. C1 33pF TABLE I. Unipolar Codes. VOUT OUT 1 –VIN (4095/4096) –VIN (2048/4096) = –1/2VIN –VIN (1/4096) 0V OPA604 DAC7545 AGND DGND DATA INPUT MSB LSB 0111 1111 1111 0000 0000 0001 0000 0000 0000 1111 1111 1111 1000 0000 0000 DB0-DB11 FIGURE 2. Unipolar Binary Operation. R3, R4, and R5 must match within 0.01% and must be the same type of resistors (preferably wire-wound or metal foil), so that the temperature coefficients match; mismatch of R3 value to R4 causes both offset and full-scale error. Mismatch of R5 to R4 and R3 causes full-scale error. The capacitor across the feedback resistor is used to compensate for the phase shift due to stray capacitances of the circuit board, the DAC output capacitance, and op amp input capaci- R2 R4 20kΩ +5V 18 VDD 19 20 C1 33pF RFB OPA604 or 1/2 OPA2604 1 OUT 1 VREF R1 DAC7545 DB11 DB10-DB0 R3 10kΩ R5 20kΩ VOUT AGND 2 4 11 U1 (see text) +VIN (2047/2048) +VIN (1/2048) 0V –VIN (1/2048) –VIN (2048/2048) TABLE II. Binary Two’s Complement Code Table for Circuit of Figure 3. The addition of R1 will cause a negative gain error. To compensate for this error, R2 must be added. The value of R2 should be one-third the value of R1. VIN ANALOG OUTPUT R6 5kΩ 10% OPA604 or 1/2 OPA2604 Analog Common 12 Data Input FIGURE 3. Bipolar Operation (binary two’s complement code). DAC7545 SBAS150A www.ti.com 5 DIGITALLY-CONTROLLED GAIN BLOCK Figure 4 shows a circuit for a digitally-controlled gain block. The feedback for the op amp is made up of the FET switch and the R-2R ladder. The input resistor to the gain block is the RFB of the DAC7545. As the FET switch is in the feedback loop, a zero code into the DAC will result in the op amp having no feedback, and a saturated op amp output. VOUT = –VIN DB11 2 + DB10 4 + DB9 8 + ••• + DB0 4096 INTERFACING TO MICROPROCESSORS RFB +5V 16 20 OUT 1 18 19 DAC7545 The DAC7545 can be directly interfaced to either an 8- or 16bit microprocessor through its 12-bit wide data latch using the CS and WR controls. AGND DGND VOUT Unused digital inputs must be connected to VDD or to DGND, this prevents noise from triggering the high impedance digital input. It is suggested that the unused digital inputs also be given a path to ground or VDD through a 1mW resistor to prevent the accumulation of static charge if the PC card is unplugged from the system. In addition, in systems where the AGND to DGND connection is on a backplane, it is recommended that two diodes be connected in inverse parallel between AGND and DGND. VIN DB0-DB11 WR CS 17 reference applications and low-bandwidth requirement; the OPA37 has low VOS and does not require an offset trim. For wide bandwidth, high slew rate, or fast-settling applications, the OPA604 or 1/2 OPA2604 are recommended. NOTE: There must be at least 1LSB loaded in the DAC or the amp will saturate due to the lack of feedback. An 8-bit processor interface is shown in Figure 5. It uses two memory addresses: one for the lower 8 bits and one for the upper 4 bits of data into the DAC via the latch. OPA111 A15 A0 Address Bus FIGURE 4. Digitally Controlled Gain Block. Address Decode APPLICATION HINTS CMOS DACs, such as the DAC7545, exhibit a code-dependent out resistance. The effect of this is a code-dependent differential nonlinearity at the amplifier output that depends on the offset voltage, VOS, of the amplifier. Thus linearity depends upon the potential of OUT 1 and AGND being exactly equal to each other. Usually the DAC is connected to an external op amp with the noninverting input connected to AGND. The op amp selected should have a low input bias current and low VOS and VOS drift over temperature. The op amp offset voltage should be less than (25 • 10–6)(VREF) over operating conditions. Suitable op amps are the OPA37 and the OPA627 for fixed 6 CPU Q0(1) CS CS Q1(2) 4 Latch 4 DB11 DB8 DAC7545 WR WR WR 8 DB7 DB0 DB7 DB0 8-Bit Data Bus NOTES: (1) Q0 = decoded address for DAC. (2) Q1 = decoded address for latch. FIGURE 5. 8-Bit Processor Interface. DAC7545 www.ti.com SBAS150A PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DAC7545GLU OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 DAC7545GLU DAC7545GLUG4 OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 DAC7545GLU DAC7545JU OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 DAC7545JU DAC7545KU OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 DAC7545KU DAC7545KUG4 OBSOLETE SOIC DW 20 TBD Call TI Call TI -40 to 85 DAC7545KU (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 TYP 9.97 SEATING PLANE PIN 1 ID AREA A 0.1 C 20 1 13.0 12.6 NOTE 3 18X 1.27 2X 11.43 10 11 B 7.6 7.4 NOTE 4 20X 0.51 0.31 0.25 C A B 2.65 MAX 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.3 0.1 1.27 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 11 10 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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