DAC7554IDGSR

DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 12-BIT, QUAD, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • DESCRIPTION 2.7-V to 5.5-V Single Supply 12-Bit Linearity and Monotonicity Rail-to-Rail Voltage Output Settling Time: 5 µs (Max) Ultralow Glitch Energy: 0.1 nVs Ultralow Crosstalk: –100 dB Low Power: 880 µA (Max) Per-Channel Power Down: 2 µA (Max) Power-On Reset to Zero Scale SPI-Compatible Serial Interface: Up to 50 MHz Simultaneous or Sequential Update Specified Temperature Range: –40°C to 105°C Small 10-Lead MSOP Package The DAC7554 is a quad-channel, voltage-output DAC with exceptional linearity and monotonicity. Its proprietary architecture minimizes undesired transients such as code to code glitch and channel to channel crosstalk. The low-power DAC7554 operates from a single 2.7-V to 5.5-V supply. The DAC7554 output amplifiers can drive a 2-kΩ, 200-pF load rail-to-rail with 5-µs settling time; the output range is set using an external voltage reference. The 3-wire serial interface operates at clock rates up to 50 MHz and is compatible with SPI, QSPI, Microwire, and DSP interface standards. The outputs of all DACs may be updated simultaneously or sequentially. The parts incorporate a power-on-reset circuit to ensure that the DAC outputs power up to zero volts and remain there until a valid write cycle to the device takes place. The parts contain a power-down feature that reduces the current consumption of the device to under 1 µA. APPLICATIONS • • • • • Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Control The small size and low-power operation makes the DAC7554 ideally suited for battery-operated portable applications. The power consumption is typically 3.5 mW at 5 V, 1.65 mW at 3 V, and reduces to 1 µW in power-down mode. The DAC7554 is available in a 10-lead MSOP package and is specified over –40°C to 105°C. FUNCTIONAL BLOCK DIAGRAM VDD SCLK SYNC REFIN Input Register DAC Register String DAC A Buffer VOUTA Input Register DAC Register String DAC B Buffer VOUTB Input Register DAC Register String DAC C Buffer VOUTC Input Register DAC Register String DAC D Buffer VOUTD Interface Logic DIN Power-On Reset DAC7554 Power-Down Logic GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004, Texas Instruments Incorporated DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING DAC7554 10 MSOP DGS –40°C TO 105°C D754 ORDERING NUMBER TRANSPORT MEDIA DAC7554IDGS 80-piece Tube DAC7554IDGSR 2500-piece Tape and Reel ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VDD to GND –0.3 V to 6 V Digital input voltage to GND –0.3 V to VDD + 0.3 V Vout to GND –0.3 V to VDD+ 0.3 V Operating temperature range –40°C to 105°C Storage temperature range –65°C to 150°C Junction temperature (TJ Max) (1) 2 150°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, REFIN = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 12 Relative accuracy Differential nonlinearity Specified monotonic by design ±1 LSB ±0.08 ± 0.5 LSB ±12 mV Offset error Zero-scale error Bits ±0.35 ±12 All zeroes loaded to DAC register Gain error Full-scale error mV ±0.15 %FSR ±0.5 %FSR Zero-scale error drift 7 µV/°C Gain temperature coefficient 3 ppm of FSR/°C PSRR OUTPUT VDD = 5 V 0.75 mV/V CHARACTERISTICS (2) Output voltage range Output voltage settling time 0 RL = 2 kΩ; 0 pF < CL < 200 pF Slew rate REFIN V 5 µs 1 Capacitive load stability RL = ∞ 470 RL = 2 kΩ Digital-to-analog glitch impulse 1 LSB change around major carry Channel-to-channel crosstalk 1-kHz full-scale sine wave, outputs unloaded V/µs pF 1000 0.1 nV-s –100 dB Digital feedthrough 0.1 nV-s Output noise density (10-kHz offset frequency) 70 nV/rtHz –85 dB Total harmonic distortion FOUT = 1 kHz, FS = 1 MSPS, BW = 20 kHz 1 Ω VDD = 5 V 50 mA VDD = 3 V 20 Coming out of power-down mode, VDD = 5 V 15 Coming out of power-down mode, VDD = 3 V 15 DC output impedance Short-circuit current Power-up time µs LOGIC INPUTS (2) ±1 µA 0.3 VDD V 3 pF 5.5 V 700 880 µA 550 830 0.2 2 0.05 2 Input current VIN_L, Input low voltage VDD = 5 V VIN_H, Input high voltage VDD = 3 V 0.7 VDD V Pin capacitance POWER REQUIREMENTS VDD 2.7 IDD(normal operation) VDD = 3.6 V to 5.5 V DAC active and excluding load current VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V IDD (all power-down modes) VDD = 3.6 V to 5.5 V VIH = VDD and VIL = GND VDD = 2.7 V to 3.6 V Reference input impedance 25 µA kΩ POWER EFFICIENCY IOUT/IDD (1) (2) ILOAD = 2 mA, VDD = 5 V 93% Linearity tested using a reduced code range of 48 to 4048; output unloaded. Specified by design and characterization, not production tested. 3 DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TIMING CHARACTERISTICS (1) (2) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS t1 (3) SCLK cycle time t2 SCLK HIGH time t3 SCLK LOW time t4 SYNC falling edge to SCLK falling edge setup time t5 Data setup time t6 Data hold time t7 SCLK falling edge to SYNC rising edge t8 Minimum SYNC HIGH time (1) (2) (3) MIN VDD = 2.7 V to 3.6 V 20 VDD = 3.6 V to 5.5 V 20 VDD = 2.7 V to 3.6 V 10 VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 10 VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 4 VDD = 3.6 V to 5.5 V 4 VDD = 2.7 V to 3.6 V 5 VDD = 3.6 V to 5.5 V 5 VDD = 2.7 V to 3.6 V 4.5 VDD = 3.6 V to 5.5 V 4.5 VDD = 2.7 V to 3.6 V 0 VDD = 3.6 V to 5.5 V 0 VDD = 2.7 V to 3.6 V 20 VDD = 3.6 V to 5.5 V 20 All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Serial Write Operation timing diagram Figure 1. Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. t1 SCLK t8 t2 t3 t4 t7 SYNC t5 DIN LD1 t6 LD0 SEL1 SEL0 D11 D1 D0 Figure 1. Serial Write Operation 4 TYP X MAX UNITS ns ns ns ns ns ns ns ns DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 PIN DESCRIPTION DGS Package (Top View) VOUTA VOUTB GND VOUTC VOUTD 1 10 2 9 3 8 4 7 5 6 REFIN SYNC VDD DIN SCLK Terminal Functions TERMINAL NO. DESCRIPTION NAME 1 VOUTA Analog output voltage from DAC A 2 VOUTB Analog output voltage from DAC B 3 GND Ground 4 VOUTC Analog output voltage from DAC C 5 VOUTD Analog output voltage from DAC D 6 SCLK Serial clock input 7 DIN Serial data input 8 VDD Analog voltage supply input 9 SYNC Frame synchronization input. The falling edge of the FS pulse indicates the start of a serial data frame shifted out to the DAC7554 10 REFIN Analog input. External reference 5 DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 1 Channel B VDD = 5 V Linearity Error − LSB VREF = 4.096 V 0.5 0 −0.5 −0.5 −1 −1 0.5 0 −0.25 −0.5 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 0.25 0 −0.25 −0.5 0 4096 1536 2048 2560 Digital Input Code 3072 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 3584 4096 1 VREF = 4.096 V Channel D VDD = 5 V Linearity Error − LSB Linearity Error − LSB 1024 Figure 3. Channel C 0.5 0 −0.5 −1 VREF = 4.096 V VDD = 5 V 0.5 0 −0.5 −1 Differential Linearity Error − LSB Differential Linearity Error − LSB 512 Figure 2. 1 0.5 0.25 0 −0.25 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 Digital Input Code Figure 4. 6 VDD = 5 V 0 0.5 0.25 VREF = 4.096 V 0.5 Differential Linearity Error − LSB Differential Linearity Error − LSB Linearity Error − LSB Channel A 2560 3072 3584 4096 −0.5 0 512 1024 1536 2048 2560 Digital Input Code Figure 5. 3072 3584 4096 DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 1 VREF = 2.5 V VDD = 2.7 V Linearity Error − LSB Linearity Error − LSB Channel A 0.5 0 −0.5 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 4096 −0.5 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 4096 1 Channel C VREF = 2.5 V Channel D VDD = 2.7 V Linearity Error − LSB Linearity Error − LSB 0 Figure 7. 0.5 0 −0.5 −1 VREF = 2.5 V VDD = 2.7 V 0.5 0 −0.5 −1 Differential Linearity Error − LSB Differential Linearity Error − LSB VDD = 2.7 V Figure 6. 1 0.5 0.25 0 −0.25 −0.5 VREF = 2.5 V −1 Differential Linearity Error − LSB Differential Linearity Error − LSB −1 Channel B 0.5 0 512 1024 1536 2048 2560 Digital Input Code Figure 8. 3072 3584 4096 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Input Code Figure 9. 7 DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE 10 10 VDD = 5 V, VREF = 4.096 V VDD = 2.7 V, VREF = 2.5 V Channel C 5 Channel D 0 Channel B Zero−Scale Error − mV Zero−Scale Error − mV Channel A Channel A 5 Channel C Channel D 0 Channel B −5 −40 −10 20 50 −5 −40 80 TA − Free-Air Temperature − °C 80 Figure 11. FULL-SCALE ERROR vs FREE-AIR TEMPERATURE FULL-SCALE ERROR vs FREE-AIR TEMPERATURE 5 VDD = 2.7 V, VREF = 2.5 V Channel A Channel C Channel D 0 Channel B −5 −10 20 50 80 TA − Free-Air Temperature − °C Figure 12. 8 50 Figure 10. VDD = 5 V, VREF = 4.096 V −10 −40 20 TA − Free-Air Temperature − °C Channel C Channel A Full−Scale Error − mV Full−Scale Error − mV 5 −10 Channel D 0 Channel B −5 −10 −40 −10 20 50 80 TA − Free-Air Temperature − °C Figure 13. DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) SINK CURRENT AT NEGATIVE RAIL SOURCE CURRENT AT POSITIVE RAIL 0.2 5.50 Typical for All Channels VDD = 2.7 V, Vref = 2.5 V 0.15 VO − Output Voltage − V VO − Output Voltage − V Typical for All Channels 0.1 VDD = 5.5 V, Vref = 4.096 V VDD = Vref = 5.5 V 5.40 5.30 0.05 DAC Loaded with 000h 0 0 5 10 ISINK − Sink Current − mA DAC Loaded with FFFh 5.20 15 0 5 10 ISOURCE − Source Current − mA Figure 14. Figure 15. SOURCE CURRENT AT POSITIVE RAIL SUPPLY CURRENT vs DIGITAL INPUT CODE 15 700 2.7 Typical for All Channels I DD − Supply Current − µ A VO − Output Voltage − V 600 2.6 VDD = Vref = 2.7 V 2.5 500 VDD = 5.5 V, Vref = 4.096 V VDD = 2.7 V, Vref = 2.5 V 400 300 200 100 All Channels Powered, No Load DAC Loaded with FFFh 2.4 0 5 10 ISOURCE − Source Current − mA Figure 16. 15 0 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Input Code Figure 17. 9 DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 800 700 VDD = 5.5 V, Vref = 4.096 V 600 VDD = 2.7 V, Vref = 2.5 V 500 All DACs Powered, No Load, Vref = 2.5 V 650 I DD − Supply Current − µ A I DD − Supply Current − µ A 700 400 300 200 600 550 500 450 100 All Channels Powered, No Load 0 −40 −10 20 50 80 TA − Free-Air Temperature − °C 400 2.7 110 3.8 4.1 4.5 4.8 5.2 5.5 Figure 18. Figure 19. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION - 5.5 V 2000 VDD = 5.5 V, Vref = 4.096 V TA = 25
C, SCL Input (All Other Inputs = GND) 1800 1500 f − Frequency − Hz I DD − Supply Current − µ A 3.4 VDD − Supply Voltage − V 2200 VDD = 5.5 V, Vref = 4.096 V 1400 1000 1000 500 600 VDD = 2.7 V, Vref = 2.5 V 200 0 0 1 2 3 4 VLOGIC − Logic Input Voltage − V Figure 20. 10 3.1 5 282 339 395 452 508 565 621 678 734 791 IDD − Current Consumption − A Figure 21. DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V TOTAL ERROR - 5 V 2000 VDD = 5 V, Vref = 4.096 V, TA = 25
C Channel B Output VDD = 2.7 V, Vref = 2.5 V 6 Channel C Output 4 Total Error - mV f − Frequency − Hz 1500 1000 Channel A Output 2 0 −2 500 Channel D Output −4 0 −6 0 280 327 373 420 467 513 560 607 653 700 IDD − Current Consumption − A 6 TOTAL ERROR - 2.7 V EXITING POWER-DOWN MODE 5 VDD = 5 V, Vref = 4.096 V, Power-Up Code 4000 4 Channel C Output Channel B Output 0 −2 VO − Output Voltage − V Total Error - mV Figure 23. Channel A Output 2 1024 1536 2048 2560 3072 3584 4095 Digital Input Code Figure 22. VDD = 2.7 V, Vref = 2.5 V, TA = 25
C 4 512 3 2 1 −4 Channel D Output −6 0 512 1024 1536 2048 2560 3072 3584 4095 Digital Input Code Figure 24. 0 t − Time − 4 s/div Figure 25. 11 DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) LARGE-SIGNAL SETTLING TIME - 5 V LARGE-SIGNAL SETTLING TIME - 2.7 V 5 3 Vref = 2.5 V VDD = 2.7 V, Output Loaded With 200 pF to GND Code 41 to 4055 VDD = 5 V, Vref = 4.096 V Output Loaded With 200 pF to GND Code 41 to 4055 VO − Output Voltage − V VO − Output Voltage − V 4 3 2 2 1 1 0 0 t − Time − 5 s/div Figure 27. MIDSCALE GLITCH WORST-CASE GLITCH VO - VO - (5 mV/Div) (5 mV/Div) Figure 26. Trigger Pulse Trigger Pulse Time - (400 nS/Div) Figure 28. 12 t − Time − 5 s/div Time - (400 nS/Div) Figure 29. DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS (continued) CHANNEL-TO-CHANNEL CROSSTALK FOR A FULL-SCALE SWING VO - VO - (5 mV/Div) (5 mV/Div) DIGITAL FEEDTHROUGH ERROR Trigger Pulse Trigger Pulse Time - (400 nS/Div) Time - (400 nS/Div) Figure 30. Figure 31. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY THD − Total Harmonic Distortion − dB −40 VDD = 5 V, Vref = 4.096 V −1 dB FSR Digital Input, Fs = 1 Msps Measurement Bandwidth = 20 kHz −50 −60 −70 THD −80 2nd Harmonic −90 −100 3rd Harmonic 0 1 2 3 4 5 6 7 8 Output Frequency (Tone) − kHz 9 10 Figure 32. 13 DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 3-Wire Serial Interface The DAC7554 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface. Table 1. Serial Interface Programming CONTROL 14 DATA BITS LD1 LD0 Sel1 Sel0 DB11-DB0 0 0 0 0 data 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 DAC(s) FUNCTION A Input register updated data B Input register updated data C Input register updated 1 data D Input register updated 0 0 data A DAC register updated, output updated 1 0 1 data B DAC register updated, output updated 1 1 0 data C DAC register updated, output updated 0 1 1 1 data D DAC register updated, output updated 1 0 0 0 data A Input register and DAC register updated, output updated 1 0 0 1 data B Input register and DAC register updated, output updated 1 0 1 0 data C Input register and DAC register updated, output updated 1 0 1 1 data D Input register and DAC register updated, output updated 1 1 0 0 data A-D Input register updated 1 1 0 1 data A-D DAC register updated, output updated 1 1 1 0 data A-D Input register and DAC register updated, output updated 1 1 data -- 1 1 Sel1 Sel0 Power-Down Mode - See Table 2 0 0 Channel A 0 1 Channel B 1 0 Channel C 1 1 Channel D LD1 LD0 FUNCTION 0 0 Single channel store. The selected input register is updated. 0 1 Single channel DAC update. The selected DAC register is updated with input register information. 1 0 Single channel update. The selected input and DAC register is updated. 1 1 Depends on the Sel1 and Sel0 Bits CHANNEL SELECT DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 POWER-DOWN MODE In power-down mode, the DAC outputs are programmed to one of three output impedances, 1 kΩ, 100 kΩ, or floating. Table 2. Power-Down Mode Control EXTENDED CONTROL DATA BITS FUNCTION LD1 LD0 Sel1 Sel0 DB11 DB10 DB9 DB8 DB7 DB6-DB0 1 1 1 1 0 0 0 0 0 X PWD Hi-Z (selected channel = A) 1 1 1 1 0 0 0 0 1 X PWD 1 kΩ (selected channel = A) 1 1 1 1 0 0 0 1 0 X PWD 100 kΩ (selected channel = A) 1 1 1 1 0 0 0 1 1 X PWD Hi-Z (selected channel = A) 1 1 1 1 0 0 1 0 0 X PWD Hi-Z (selected channel = B) 1 1 1 1 0 0 1 0 1 X PWD 1 kΩ (selected channel = B) 1 1 1 1 0 0 1 1 0 X PWD 100 kΩ (selected channel = B) 1 1 1 1 0 0 1 1 1 X PWD Hi-Z (selected channel = B) 1 1 1 1 0 1 0 0 0 X PWD Hi-Z (selected channel = C) 1 1 1 1 0 1 0 0 1 X PWD 1 kΩ (selected channel = C) 1 1 1 1 0 1 0 1 0 X PWD 100 kΩ (selected channel = C) 1 1 1 1 0 1 0 1 1 X PWD Hi-Z (selected channel = C) 1 1 1 1 0 1 1 0 0 X PWD Hi-Z (selected channel = D) 1 1 1 1 0 1 1 0 1 X PWD 1 kΩ (selected channel = D) 1 1 1 1 0 1 1 1 0 X PWD 100 kΩ (selected channel = D) 1 1 1 1 0 1 1 1 1 X PWD Hi-Z (selected channel = D) 1 1 1 1 1 X X 0 0 X PWD Hi-Z (all channels) 1 1 1 1 1 X X 0 1 X PWD 1 kΩ (all channels) 1 1 1 1 1 X X 1 0 X PWD 100 kΩ (all channels) 1 1 1 1 X X 1 1 X PWD Hi-Z (all channels) 1 DB11 ALL CHANNELS FLAG 0 See DB7–DB10 1 DB10 and DB9 are Don't Care DB10 DB9 0 0 Channel Select Channel A 0 1 Channel B 1 0 Channel C 1 1 Channel D DB8 DB7 0 0 Power-down Hi-Z 0 1 Power-down 1 kΩ 1 0 Power-down 100 kΩ 1 1 Power-down Hi-Z Power-Down Mode 15 DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 THEORY OF OPERATION D/A SECTION DAC External Reference Input The architecture of the DAC7554 consists of a string DAC followed by an output buffer amplifier. Figure 33 shows a generalized block diagram of the DAC architecture. There is a single reference input pin for the four DACs. The reference input is unbuffered. The user can have a reference voltage as low as 0.25 V and as high as VDD because there is no restriction due to headroom and footroom of any reference amplifier. REFIN _ Ref + Resistor String Ref − DAC Register VOUT + Power-On Reset GND Figure 33. Typical DAC Architecture The input coding to the DAC7554 is unsigned binary, which gives the ideal output voltage as: VOUT = REFIN × D/4096 Where D = decimal equivalent of the binary code that is loaded to the DAC register which can range from 0 to 4095. To Output Amplifier REFIN R R R It is recommended to use a buffered reference in the external circuit (e.g., REF3140). The input impedance is typically 25 kΩ. R GND Figure 34. Typical Resistor String On power up, all internal registers are cleared and all channels are updated with zero-scale voltages. Until valid data is written, all DAC outputs remain in this state. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. In order not to turn on ESD protection devices, VDD should be applied before any other pin is brought high. Power Down The DAC7554 has a flexible power-down capability as described in Table 2. Individual channels could be powered down separately or all channels could be powered down simultaneously. During a power-down condition, the user has flexibility to select the output impedance of each channel. During power-down operation, each channel can have either 1-kΩ, 100-kΩ, or Hi-Z output impedance to ground. SERIAL INTERFACE RESISTOR STRING The resistor string section is shown in Figure 34. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is specified monotonic. The DAC7554 architecture uses four separate resistor strings to minimize channel-to-channel crosstalk. OUTPUT BUFFER AMPLIFIERS The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with up to 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/µs with a half-scale settling time of 3 µs with the output unloaded. 16 The DAC7554 is controlled over a versatile 3-wire serial interface, which operates at clock rates up to 50 MHz and is compatible with SPI, QSPI, Microwire, and DSP interface standards. 16-Bit Word and Input Shift Register The input shift register is 16 bits wide. DAC data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK, as shown in the Figure 1 timing diagram. The 16-bit word, illustrated in Table 1, consists of four control bits followed by 12 bits of DAC data. The data format is straight binary with all zeroes corresponding to 0-V output and all ones corresponding to full-scale output (VREF – 1 LSB). Data is loaded MSB first (Bit 15) where the first two bits (LD1 and LD0) determine if the input register, DAC register, or both are updated with shift register input data. Bit 13 and bit 12 (Sel1 and Sel0) determine whether the data is for DAC A, DAC B, DAC C, DAC D, or all DACs. All channels are updated when bits 15 and 14 (LD1 and LD0) are high. DAC7554 www.ti.com The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC to SCLK falling edge setup time, t4. After SYNC goes low, serial data is shifted into the device's input shift register on the falling edges of SCLK for 16 clock pulses. Any data and clock pulses after the sixteenth falling edge of SCLK are ignored. No further serial data transfer occurs until SYNC is taken high and low again. SYNC may be taken high after the falling edge of the sixteenth SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t7. After the end of serial data transfer, data is automatically transferred from the input shift register to the input register of the selected DAC. If SYNC is taken high before the sixteenth falling edge of SCLK, the data transfer is aborted and the DAC input registers are not updated. INTEGRAL AND DIFFERENTIAL LINEARITY The DAC7554 uses precision thin-film resistors providing exceptional linearity and monotonicity. Integral linearity error is typically within (+/-) 0.35 LSBs, and differential linearity error is typically within (+/-) 0.08 LSBs. GLITCH ENERGY The DAC7554 uses a proprietary architecture that minimizes glitch energy. The code-to-code glitches are so low, they are usually buried within the wide-band noise and cannot be easily detected. The DAC7554 glitch is typically well under 0.1 nV-s. Such low glitch energy provides more than 10X improvement over industry alternatives. CHANNEL-TO-CHANNEL CROSSTALK The DAC7554 architecture is designed to minimize channel-to-channel crosstalk. The voltage change in one channel does not affect the voltage output in another channel. The DC crosstalk is in the order of a few microvolts. AC crosstalk is also less than –100 dBs. This provides orders of magnitude improvement over certain competing architectures. SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 can exceed 1 MSPS if the waveform to be generated consists of small voltage steps between consecutive DAC updates. To obtain a high dynamic range, REF3140 (4.096 V) or REF02 (5.0 V) are recommended for reference voltage generation. Generating ±5-V, ±10-V, and ± 12-V Outputs For Precision Industrial Control Industrial control applications can require multiple feedback loops consisting of sensors, ADCs, MCUs, DACs, and actuators. Loop accuracy and loop speed are the two important parameters of such control loops. Loop Accuracy: In a control loop, the ADC has to be accurate. Offset, gain, and the integral linearity errors of the DAC are not factors in determining the accuracy of the loop. As long as a voltage exists in the transfer curve of a monotonic DAC, the loop can find it and settle to it. On the other hand, DAC resolution and differential linearity do determine the loop accuracy, because each DAC step determines the minimum incremental change the loop can generate. A DNL error less than –1 LSB (non-monotonicity) can create loop instability. A DNL error greater than +1 LSB implies unnecessarily large voltage steps and missed voltage targets. With high DNL errors, the loop looses its stability, resolution, and accuracy. Offering 12-bit ensured monotonicity and ± 0.08 LSB typical DNL error, 755X DACs are great choices for precision control loops. Loop Speed: Many factors determine control loop speed. Typically, the ADC's conversion time, and the MCU's computation time are the two major factors that dominate the time constant of the loop. DAC settling time is rarely a dominant factor because ADC conversion times usually exceed DAC conversion times. DAC offset, gain, and linearity errors can slow the loop down only during the start-up. Once the loop reaches its steady-state operation, these errors do not affect loop speed any further. Depending on the ringing characteristics of the loop's transfer function, DAC glitches can also slow the loop down. With its 1 MSPS (small-signal) maximum data update rate, DAC7554 can support high-speed control loops. Ultra-low glitch energy of the DAC7554 significantly improves loop stability and loop settling time. APPLICATION INFORMATION Generating Industrial Voltage Ranges: Waveform Generation For control loop applications, DAC gain and offset errors are not important parameters. This could be exploited to lower trim and calibration costs in a high-voltage control circuit design. Using a quad operational amplifier (OPA4130), and a voltage reference (REF3140), the DAC7554 can generate the wide voltage swings required by the control loop. Due to its exceptional linearity, low glitch, and low crosstalk, the DAC7554 is well suited for waveform generation (from DC to 10 kHz). The DAC7554 large-signal settling time is 5 µs, supporting an update rate of 200 KSPS. However, the update rates 17 DAC7554 www.ti.com SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004  Vtail DAC7554 R1 REF3140 R2 Vref _ REFIN DAC7554 Vdac +  V out  V ref R2
1 Din  V tail R2 4096 R1 R1 VOUT OPA4130 Figure 35. Low-cost, Wide-swing Voltage Generator for Control Loop Applications The output voltage of the configuration is given by: (1) Fixed R1 and R2 resistors can be used to coarsely set the gain required in the first term of the equation. Once R2 and R1 set the gain to include some minimal over-range, a DAC7554 channel could be used to set the required offset voltages. Residual errors are not an issue for loop accuracy because offset and gain errors could be tolerated. One DAC7554 channel can provide the Vtail voltage, while the other three DAC7554 channels can provide Vdac voltages to help generate three high-voltage outputs. For ±5-V operation: R1=10 kΩ, R2 = 15 kΩ, Vtail = 3.33 V, Vref = 4.096 V For ±10-V operation: R1=10 kΩ, R2 = 39 kΩ, Vtail = 2.56 V, Vref = 4.096 V For ±12-V operation: R1=10 kΩ, R2 = 49 kΩ, Vtail = 2.45 V, Vref = 4.096 V 18 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DAC7554IDGS ACTIVE VSSOP DGS 10 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 105 D754 DAC7554IDGSR ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 105 D754 DAC7554IDGSRG4 ACTIVE VSSOP DGS 10 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 105 D754 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of