DAC7558IRHBRG4

DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 12-BIT, OCTAL, ULTRALOW GLITCH, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER FEATURES • • • • • • • • • • • • • • • • • DESCRIPTION 2.7-V to 5.5-V Single Supply 12-Bit Linearity and Monotonicity Rail-to-Rail Voltage Output Settling Time: 5 µs (Max) Ultralow Glitch Energy: 0.1 nVs Ultralow Crosstalk: –100 dB Low Power: 1.8 mA (Max) Per-Channel Power Down: 2 µA (Max) Power-On Reset to Zero Scale and Mid Scale SPI-Compatible Serial Interface: Up to 50 MHz Simultaneous or Sequential Update Asynchronous Clear Binary and Twos-Complement Capability Daisy-Chain Operation 1.8-V to 5.5-V Logic Compatibility Specified Temperature Range: –40°C to 105°C Small, 5-mm x 5-mm, 32-Lead QFN Package The DAC7558 is a 12-bit, octal-channel, voltage output DAC with exceptional linearity and monotonicity. Its proprietary architecture minimizes undesired transients such as code to code glitch and channel to channel crosstalk. The low-power DAC7558 operates from a single 2.7-V to 5.5-V supply. The DAC7558 output amplifiers can drive a 2-kΩ, 200-pF load rail-to-rail with 5-µs settling time; the output range is set using an external voltage reference. The 3-wire serial interface operates at clock rates up to 50 MHz and is compatible with SPI, QSPI, Microwire™, and DSP interface standards. The outputs of all DACs may be updated simultaneously or sequentially. The parts incorporate a power-on-reset circuit to ensure that the DAC outputs power up to zero volts and remain there until a valid write cycle to the device takes place. The parts contain a power-down feature that reduces the current consumption of the device to under 2 µA. The small size and low-power operation makes the DAC7558 ideally suited for battery-operated portable applications. The power consumption is typically 7.5 mW at 5 V, 3.7 mW at 3 V, and reduces to 1 µW in power-down mode. APPLICATIONS • • • • • Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Control The DAC7558 is available in a 32-lead QFN package and is specified over –40°C to 105°C. FUNCTIONAL BLOCK DIAGRAM VDD IOVDD VREF1 VREF2 VFBA − Input Register DAC Register String DAC A VOUTA + SCLK Interface Logic SYNC VFBH SDIN − SDO Input Register DAC Register String DAC H Power-On Reset DCEN RST RSTSEL AGND VOUTH + Power-Down Logic DGND VREF3 VREF4 PD Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Microwire is a trademark of National Semiconductor Corp.. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT DAC7558 (1) PACKAGE 32 QFN PACKAGE DESIGNATOR RHB SPECIFIED TEMPERATURE RANGE –40°C TO 105°C PACKAGE MARKING D758 ORDERING NUMBER TRANSPORT MEDIA DAC7558IRHBT 250-piece Tape and Reel DAC7558IRHBR 3000-piece Tape and Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VDD , IOVDD to GND –0.3 V to 6 V Digital input voltage to GND –0.3 V to VDD + 0.3 V Vout to GND –0.3 V to VDD+ 0.3 V Operating temperature range –40°C to 105°C Storage temperature range –65°C to 150°C Junction temperature (TJ Max) (1) 2 150°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 ELECTRICAL CHARACTERISTICS VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (1) Resolution 12 Relative accuracy Differential nonlinearity Specified monotonic by design Bits ±0.35 ±1 LSB ±0.08 ±0.5 LSB ±12 mV ±12 mV Offset error Zero-scale error All zeroes loaded to DAC register Gain error VDD = 5 V, VREF = 4.096 V ±0.15 %FSR Full-scale error VDD = 5 V, VREF = 4.096 V ±0.5 %FSR Zero-scale error drift Gain temperature coefficient PSRR VDD = 5 V 7 µV/°C 3 ppm of FSR/°C 0.75 mV/V OUTPUT CHARACTERISTICS (2) Output voltage range Output voltage settling time 0 RL = 2 kΩ; 0 pF < CL < 200 pF 5 Slew rate Capacitive load stability VREF RL = ∞ RL = 2 kΩ Digital-to-analog glitch impulse 1 LSB change around major carry Channel-to-channel crosstalk 1-kHz full-scale sine wave, outputs unloaded V µs 1.8 V/µs 470 pF 1000 0.1 nV-s –100 dB Digital feedthrough 0.1 nV-s Output noise density (10-kHz offset frequency) 120 nV/rtHz –85 dB 1 Ω VDD = 5 V 50 mA VDD = 3 V 20 Coming out of power-down mode, VDD = 5 V 15 Coming out of power-down mode, VDD = 3 V 15 Total harmonic distortion FOUT = 1 kHz, FS = 1 MSPS, BW = 20 kHz DC output impedance Short-circuit current Power-up time µs REFERENCE INPUT VREF Input range 0 VDD Reference input impedance VREF1 through VREF4 shorted together 12.5 Reference current VREF = VDD = 5 V, VREF1 through VREF4 shorted together 400 650 VREF = VDD = 3 V, VREF1 through VREF4 shorted together 240 425 V kΩ µA LOGIC INPUTS (2) Input current VIN_L, Input low voltage IOVDD ≥ 2.7 V VIN_H, Input high voltage IOVDD ≥ 2.7 V Pin capacitance (1) (2) ±1 µA 0.3 IOVDD V 3 pF 0.7 IOVDD V Linearity tested using a reduced code range of 30 to 4065; output unloaded. Specified by design and characterization, not production tested. For 1.8 V < IOVDD < 2.7 V, it is recommended that VIH = IOVDD , VIL = GND. 3 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 ELECTRICAL CHARACTERISTICS (Continued) VDD = 2.7 V to 5.5 V, VREF = VDD, RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS VDD, IOVDD (1) IDD(normal operation) VDD = 3.6 V to 5.5 V VDD = 2.7 V to 3.6 V 2.7 5.5 V 1.1 1.8 mA 1 1.7 0.2 2 0.05 2 DAC active and excluding load current VIH = IOVDD and VIL = GND IDD (all power-down modes) VDD = 3.6 V to 5.5 V VIH = IOVDD and VIL = GND VDD = 2.7 V to 3.6 V POWER EFFICIENCY IOUT/IDD (1) 4 ILOAD = 2 mA, VDD = 5 V IOVDD operates down to 1.8 V with slightly degraded timing, as long as VIH = IOVDD and VIL = GND. 93% µA DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TIMING CHARACTERISTICS (1) (2) VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND; all specifications –40°C to 105°C, unless otherwise specified PARAMETER TEST CONDITIONS t1 (3) SCLK cycle time t2 SCLK HIGH time t3 SCLK LOW time t4 SYNC falling edge to SCLK falling edge setup time t5 Data setup time t6 Data hold time t7 SCLK falling edge to SYNC rising edge t8 Minimum SYNC HIGH time t9 SCLK falling edge to SDO valid t10 CLR pulse width low (1) (2) (3) MIN VDD = 2.7 V to 3.6 V 20 VDD = 3.6 V to 5.5 V 20 VDD = 2.7 V to 3.6 V 10 VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 10 VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 4 VDD = 3.6 V to 5.5 V 4 VDD = 2.7 V to 3.6 V 5 VDD = 3.6 V to 5.5 V 5 VDD = 2.7 V to 3.6 V 4.5 VDD = 3.6 V to 5.5 V 4.5 VDD = 2.7 V to 3.6 V 0 VDD = 3.6 V to 5.5 V 0 VDD = 2.7 V to 3.6 V 20 VDD = 3.6 V to 5.5 V 20 VDD = 2.7 V to 3.6 V 10 VDD = 3.6 V to 5.5 V 10 VDD = 2.7 V to 3.6 V 10 VDD = 3.6 V to 5.5 V 10 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Serial Write Operation timing diagram Figure 1. Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V. t1 SCLK t8 t2 t3 t4 t7 SYNC t5 SDIN D23 t6 D22 D21 D20 D19 D1 D0 Input Word n SDO D0 t9 D23 Undefined CLR D23 Input Word n+1 D22 D0 Input Word n t10 Figure 1. Serial Write Operation 5 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 PIN DESCRIPTION VOUTE VFBE VOUTF VFBF VFBG VOUTH VOUTG VFBH RHB PACKAGE (TOP VIEW) 24 23 22 21 20 19 18 17 25 16 VREF3 DCEN 26 15 SYNC VREF4 DGND RSTSEL 11 IOVDD RST 31 10 SDO VREF1 32 1 9 8 VREF2 2 3 4 5 6 7 VFBD 12 30 VOUTD AGND VFBB SDIN 29 VFBC VOUTC SCLK 13 VOUTB 14 28 VOUTA 27 VFBA PD VDD Terminal Functions TERMINAL NO. 6 DESCRIPTION NAME 1 VFBA DAC A amplifier sense input 2 VOUTA Analog output voltage from DAC A 3 VOUTB Analog output voltage from DAC B 4 VFBB DAC B amplifier sense input 5 VFBC DAC C amplifier sense input 6 VOUTC Analog output voltage from DAC C 7 VOUTD Analog output voltage from DAC D 8 VFBD DAC D amplifier sense input 9 VREF2 Positive reference voltage input for DAC C and DAC D 10 SDO Serial data output 11 IOVDD I/O voltage supply input 12 DGND Digital ground 13 SDIN Serial data input 14 SCLK Serial clock input 15 SYNC Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out to the DAC7558. 16 VREF3 Positive reference voltage input for DAC E and DAC F 17 VFBE DAC E amplifier sense input 18 VOUTE Analog output voltage from DAC E 19 VOUTF Analog output voltage from DAC F 20 VFBF DAC F amplifier sense input 21 VFBG DAC G amplifier sense input 22 VOUTG Analog output voltage from DAC G 23 VOUTH Analog output voltage from DAC H 24 VFBH DAC H amplifier sense input DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 PIN DESCRIPTION (continued) Terminal Functions (continued) (1) 25 VREF4 Positive reference voltage input for DAC G and DAC H 26 DCEN Daisy-chain enable 27 PD Power down 28 VDD Analog voltage supply input 29 AGND (1) Analog ground 30 RSTSEL Reset select. If this pin is low, input coding is binary; if high, then 2s compliment. 31 RST Asynchronous reset. Active low. If RST pin is low, all DAC channels reset either to zero scale (RSTSEL = 0) or to midscale (RSTSEL = 1). 32 VREF1 Positive reference voltage input for DAC A and DAC B Thermal pad should be connected to AGND. TYPICAL CHARACTERISTICS LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 VREF = 4.096 V VDD = 5 V Linearity Error − LSB Channel A 0.5 0 −0.5 0.25 0 −0.25 −0.5 Channel B VREF = 4.096 V VDD = 5 V 0.5 0 −0.5 −1 −1 0.5 0 512 1024 1536 2048 2560 Digital Input Code Figure 2. 3072 3584 4096 Differential Linearity Error − LSB Differential Linearity Error − LSB Linearity Error − LSB 1 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Input Code Figure 3. 7 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vsDIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 VREF = 4.096 V VDD = 5 V Linearity Error − LSB Channel C 0.5 0 −0.5 −1 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 3072 3584 4096 Differential Linearity Error − LSB Differential Linearity Error − LSB Linearity Error − LSB 1 Channel D VREF = 4.096 V 0.5 0 −0.5 −1 0.5 0.25 0 −0.25 −0.5 0 512 1024 Digital Input Code 2560 3072 Figure 5. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 VDD = 5 V Linearity Error − LSB VREF = 4.096 V 0.5 0 −0.5 −1 0.5 0.25 0 −0.25 −0.5 1024 1536 2048 2560 3072 3584 4096 Differential Linearity Error − LSB Linearity Error − LSB Differential Linearity Error − LSB 8 2048 Figure 4. Channel E 512 1536 3584 4096 Digital Input Code 1 0 VDD = 5 V Channel F VREF = 4.096 V VDD = 5 V 0.5 0 −0.5 −1 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 Digital Input Code Digital Input Code Figure 6. Figure 7. 2560 3072 3584 4096 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 Channel G VREF = 4.096 V VDD = 5 V Linearity Error − LSB 1 Linearity Error − LSB LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 0.5 0 −0.5 −0.25 Linearity Error − LSB 512 1024 1536 2048 2560 3072 3584 4096 VDD = 5 V 0 −0.5 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 3072 3584 Digital Input Code Digital Input Code Figure 8. Figure 9. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE Channel A VREF = 2.5 V 4096 1 VDD = 2.7 V Linearity Error − LSB 0 Differential Linearity Error − LSB 0 0.5 0 −0.5 Channel B VREF = 2.5 V VDD = 2.7 V 0.5 0 −0.5 −1 −1 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 Digital Input Code Figure 10. 3072 3584 4096 Differential Linearity Error − LSB Differential Linearity Error − LSB 0.25 1 Differential Linearity Error − LSB VREF = 4.096 V −1 −1 0.5 −0.5 Channel H 0.5 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 4096 Figure 11. 9 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 1 Channel C VREF = 2.5 V VDD = 2.7 V Linearity Error − LSB Linearity Error − LSB 1 0.5 0 −0.5 VREF = 2.5 V 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 3072 3584 4096 Differential Linearity Error − LSB 0.5 0 −0.5 0.5 0.25 0 −0.25 −0.5 0 512 1024 Digital Input Code 3072 3584 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 0 −0.5 −1 0.5 0.25 0 −0.25 1024 1536 2048 2560 Digital Input Code 4096 1 VDD = 2.7 V Linearity Error − LSB VREF = 2.5 V Figure 14. 10 2560 Figure 13. 0.5 512 2048 Figure 12. Channel E 0 1536 Digital Input Code 3072 3584 4096 Differential Linearity Error − LSB Differential Linearity Error − LSB Linearity Error − LSB 1 −0.5 VDD = 2.7 V −1 −1 Differential Linearity Error − LSB Channel D 0.5 Channel F VREF = 2.5 V VDD = 2.7 V 0.5 0 −0.5 −1 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 Digital Input Code Figure 15. 3072 3584 4096 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE VREF = 2.5 V 1 VDD = 2.7 V Linearity Error − LSB Channel G 0.5 0 −0.5 Channel H VREF = 2.5 V VDD = 2.7 V 0.5 0 −0.5 −1 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 4096 0.5 0.25 0 −0.25 −0.5 0 512 1024 1536 2048 2560 Figure 16. Figure 17. ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE ZERO-SCALE ERROR vs FREE-AIR TEMPERATURE 3584 4096 4 VDD = 2.7 V, VREF = 2.5 V CHE VDD = 5 V, VREF = 4.096 V CHE Zero-Scale Error − mV 2 CHD 0 CHF 2 0 CHD −2 −2 CHF CHA, B, C, G, H −4 −40 3072 Digital Input Code 4 Zero-Scale Error − mV Differential Linearity Error − LSB −1 Differential Linearity Error − LSB Linearity Error − LSB 1 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE −10 20 CHA, B, C, G, H 50 TA − Free-Air Temperature −
C Figure 18. 80 −4 −40 −10 20 50 80 TA − Free-Air Temperature −
C Figure 19. 11 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) GAIN ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs FREE-AIR TEMPERATURE 0.1 0.1 VDD = 5 V, VREF = 4.096 V VDD = 2.7 V, VREF = 2.5 V 0.05 Gain Error − % FSR Gain Error − % FSR 0.05 CHE 0 CHD −0.05 CHA 0 CHD −0.05 CHA, B, C, F, G, H −0.1 −40 −10 20 50 CH B, C, E, F, G, H −0.1 −40 80 TA − Free-Air Temperature −
C Figure 20. Figure 21. INTEGRAL LINEARITY ERROR (MINIMUM) vs FREE-AIR TEMPERATURE INTEGRAL LINEARITY ERROR (MAXIMUM) vs FREE-AIR TEMPERATURE 1 1 VDD = 5 V, VREF = 4.096 V 0.5 0 CH A, B, C, D, E, F, G, H −0.5 −10 20 50 80 TA − Free-Air Temperature −
C Figure 22. 12 Linearity Error (max) − LSB Linearity Error (min) − LSB VDD = 5 V, VREF = 4.096 V −1 −40 −10 20 50 80 TA − Free-Air Temperature −
C 0.5 0 CH A, B, C, D, E, F, G, H −0.5 −1 −40 −10 20 50 TA − Free-Air Temperature −
C Figure 23. 80 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) SINK CURRENT AT NEGATIVE RAIL SOURCE CURRENT AT POSITIVE RAIL 0.2 5.50 0.15 Typical for all Channels VO − Output Voltage − V VO − Output Voltage − V Typical for all Channels VDD = 2.7 V, VREF = 2.5 V 0.1 0.05 5.40 DAC Loaded With FFFH VDD = VREF = 5.5 V 5.30 VDD = 5.5 V, VREF = 4.096 V DAC Loaded With 000H 0 0 5 10 5.20 15 0 5 ISINK − Sink Current − mA 10 15 ISOURCE − Sink Current − mA Figure 24. Figure 25. SOURCE CURRENT AT POSITIVE RAIL SUPPLY CURRENT vs DIGITAL INPUT CODE 1400 2.7 Typical for all Channels VDD = 5.5 V, VREF = 4.096 V I DD − Supply Current − µ A VO − Output Voltage − V 1200 2.6 2.5 DAC Loaded With FFFH VDD = VREF = 2.7 V 1000 VDD = 2.7 V, VREF = 2.5 V 800 600 400 200 All Channels Powered, No Load 0 2.4 0 5 10 ISOURCE − Sink Current − mA Figure 26. 15 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Input Code Figure 27. 13 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 1600 1600 All Channels Powered, No Load All DACs Powered, No Load, VREF = 2.5 V 1400 1400 I DD − Supply Current − µ A I DD − Supply Current − µ A VDD = 5.5 V, VREF = 4.096 V 1200 VDD = 2.7 V, VREF = 2.5 V 1000 800 600 400 1200 1000 800 600 200 All Channels Powered, No Load 0 −40 −10 20 50 80 TA − Free-Air Temperature −
C 400 2.7 110 3.4 3.8 4.1 4.5 4.8 5.2 5.5 VDD − Supply Voltage − V Figure 28. Figure 29. SUPPLY CURRENT vs LOGIC INPUT VOLTAGE HISTOGRAM OF CURRENT CONSUMPTION - 5.5 V 2200 4000 TA = 25
C, SCL Input (All Other Inputs = GND) VDD = 5.5 V, VREF = 4.096 V 1800 VDD = 5.5 V, VREF = 4.096 V 3000 f − Frequency − Hz I DD − Supply Current − µ A 3.1 1400 1000 2000 1000 600 VDD = 2.7 V, VREF = 2.5 V 200 0 1 2 3 4 VLOGIC − Logic Input Voltage − V Figure 30. 14 5 0 600 700 800 900 1000 1100 1200 1300 1400 1500 IDD − Current Consumption −
A Figure 31. DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) HISTOGRAM OF CURRENT CONSUMPTION - 2.7 V TOTAL ERROR - 5 V 0.005 4000 3500 VDD = 2.7 V, VREF = 2.5 V E 0.0025 Output Error − V 3000 f − Frequency − Hz VDD = 5 V, VREF = 4.096, TA = 25
C 2500 2000 1500 D 0 A −0.0025 1000 B, C, F, G, H 500 0 600 700 800 900 1000 1100 1200 1300 1400 1500 −0.005 0 Figure 32. 1024 1536 2048 2560 3072 3584 4095 Figure 33. TOTAL ERROR - 2.7 V EXITING POWER-DOWN MODE 0.005 5 VDD = 5 V, VREF = 4.096 V, Powerup to Code 4000 VDD = 2.7 V, VREF = 2.5 V, TA = 25
C 0.0025 D 0 A 4 VO − Output Voltage − V E Output Error − V 512 Digital Input Code IDD − Current Consumption −
A 3 2 −0.0025 B, C, F, G, H −0.005 0 512 1024 1536 2048 2560 3072 3584 4095 Digital Input Code Figure 34. 1 0 t − Time − 4
s/div Figure 35. 15 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) LARGE-SIGNAL SETTLING TIME - 5 V LARGE-SIGNAL SETTLING TIME - 2.7 V 3 5 VO − Output Voltage − V VO − Output Voltage − V 4 3 2 1 2 1 VDD = 2.5 V, Output Loaded With 200 pF to GND, Code 41 to 4055 VDD = 5 V, Output Loaded With 200 pF to GND, Code 41 to 4055 0 0 t − Time − 5
s/div t − Time − 5
s/div Figure 36. Figure 37. MIDSCALE GLITCH WORST-CASE GLITCH Trigger Pulse 16 VDD = 5 V, VREF = 4.096 V VO − Output Voltage VO − Output Voltage VDD = 5 V, VREF = 4.096 V Trigger Pulse t − Time − 400 nS/div t − Time − 400 nS/div Figure 38. Figure 39. DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 TYPICAL CHARACTERISTICS (continued) DIGITAL FEEDTHROUGH ERROR CHANNEL-TO-CHANNEL CROSSTALK FOR A FULL-SCALE SWING VDD = 5 V, VREF = 4.096 V VO − Output Voltage VO − Output Voltage VDD = 5 V, VREF = 4.096 V Trigger Pulse Trigger Pulse t − Time − 400 nS/div t − Time − 400 nS/div Figure 40. Figure 41. TOTAL HARMONIC DISTORTION vs OUTPUT FREQUENCY −40 Total Harmonic Distortion − dB VDD = 5 V, VREF = 4.096 V − 1dB FSR Digital Input, Fs = 1 Msps Measurement Bandwidth = 20 kHz −50 −60 −70 THD −80 2nd Harmonic −90 3rd Harmonic −100 0 1 2 3 4 5 6 7 Output Frequency − kHz 8 9 10 Figure 42. 17 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 3-Wire Serial Interface The DAC7558 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface. Table 1. Serial Interface Programming DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15–DB4 DB3–DB0 A1 A0 LD1 LD0 SEL2 SEL1 SEL0 PWD MSB–LSB Don't Care 0 0 0 0 0 0 0 0 Data X Write to buffer A with data 0 0 0 0 1 0 Data X Write to buffer B with data 0 0 0 1 0 0 Data X Write to buffer C with data 0 0 0 1 1 0 Data X Write to buffer D with data 0 0 1 0 0 0 Data X Write to buffer E with data 0 0 1 0 1 0 Data X Write to buffer F with data 0 0 1 1 0 0 Data X Write to buffer G with data 0 0 1 1 1 0 Data X Write to buffer H with data 0 1 (000, 001, 010, 011, 100, 101, 110, 111) 0 Data X Write to buffer with data and load DAC (selected by DB19, DB18, and DB17) 1 0 (000, 001, 010, 011, 100, 101, 110, 111) 0 Data X Write to buffer with data and load DAC (selected by DB19, DB18, and DB17) and load all other DACs with buffer data 1 1 0 0 0 0 Data X Load DACs A and B with current buffer data 1 1 0 0 1 0 Data X Load DACs A, B, C, and D with current buffer data 1 1 0 1 0 0 Data X Load DACs A, B, C, D, E, and F with current buffer data 1 1 0 1 1 0 Data X Load DACs A, B, C, D, E, F, G, and H with current buffer data 1 1 1 0 0 0 Data X Write to buffer with new data and load DACs A and B simultaneously 1 1 1 0 1 0 Data X Write to buffer with new data and load DACs A, B, C, and D simultaneously 1 1 1 1 0 0 Data X Write to buffer with new data and load DACs A, B, C, D, E, and F simultaneously 1 1 1 1 1 0 Data X Write to buffer with new data and load DACs A, B, C, D, E, F, G, and H simultaneously (Both A1 and A0 should be set to zero for normal device operation. DAC(s) do not respond if any other combination is used) X 0 (000, 001, 010, 011, 100, 101, 110, 111) 1 (000, 001, 010, 011, 100, 101, 110, 111) 1 See Table 2 1 See Table 2 and Table 3 X X X 18 DESCRIPTION Write to buffer and load DAC with Power-Down command to individual channel (selected by DB19, DB18, and DB17) Write to buffer and load DACs with Power-Down command to multiple channels (selected by DB19, DB18, and DB17) DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 THEORY OF OPERATION D/A SECTION OUTPUT BUFFER AMPLIFIERS The architecture of the DAC7558 consists of a string DAC followed by an output buffer amplifier. Figure 43 shows a generalized block diagram of the DAC architecture. The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It is capable of driving a load of 2 kΩ in parallel with up to 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is 1 V/µs with a half-scale settling time of 3 µs with the output unloaded. VREF 100 k
100 k
VFB 50 k
_ Ref + Resistor String Ref − DAC Register VOUT + GND Figure 43. Typical DAC Architecture The input coding to the DAC7558 is unsigned binary, which gives the ideal output voltage as: VOUT = VREF× D/4096 Where D = decimal equivalent of the binary code that is loaded to the DAC register which can range from 0 to 4095. To Output Amplifier VREF R R R R GND Figure 44. Typical Resistor String RESISTOR STRING The resistor string section is shown in Figure 44. It is simply a string of resistors, each of value R. The DAC7558 uses eight separate resistor strings. Each VREFx input pin provides the external reference voltage for two resistor strings. A resistor string has 100 kΩ total resistance to ground, including a 50 kΩ divide-by-two resistor. Since each VREFx pin connects to two resistor strings, the resistance seen by each VREFx pin is approximately 50 kΩ. The divide-by-two function provided by the resistor string is compensated by a gain-of-two amplifier configuration. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is specified monotonic. The DAC7558 architecture uses eight separate resistor strings to minimize channel-to-channel crosstalk. DAC External Reference Input Four separate reference pins are provided for eight DACs, providing maximum flexibility. VREF1 serves DAC A and DAC B, VREF2 serves DAC C and DAC D, VREF3 serves DAC E and DAC F, and VREF4 serves DAC G and DAC H. VREF1 through VREF4 can be externally shorted together for simplicity. It is recommended to use a buffered reference in the external circuit (e.g., REF3140). The input impedance is typically 50 kΩ for each reference input pin. Amplifier Sense Input The DAC7558 contains eight amplifier feedback input pins, VFBA ... VFBH. For voltage output operation, VFBA ... VFBH must externally connect to VOUTA ... VOUTH respectively. For better DC accuracy, these connections should be made at load points. The VFBA ... VFBH pins are also useful for a variety of applications, including digitally controlled current sources. Each feedback input pin is internally connected to the DAC amplifier's negative input terminal through a 100-kΩ resistor; and, the amplifier's negative input terminal internally connects to ground through another 100-kΩ resistor (See Figure 43). This forms a gain-of-two, non-inverting amplifier configuration. Overall gain remains one because the resistor string has a divide-by-two configuration. The resistance seen at each VFBx pin is approximately 200 kΩ to ground. Power-On Reset On power up, all internal registers are cleared and all channels are updated with zero-scale voltages. Until valid data is written, all DAC outputs remain in this state. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. In order not to turn on ESD protection devices, VDD should be applied before any other pin is brought high. During power up, all digital input pins should be set at logic-low voltages. Shortly after power up, if RSTSEL pin is low, then all DAC outputs are at their zero-scale voltages. If RSTSEL pin is brought high, then all DAC outputs are at their mid-scale voltages. 19 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 Power Down The DAC7558 has a flexible power-down capability as described in Table 2 and Table 3. Individual channels can be powered down separately, or multiple channels can be powered down simultaneously. During a power-down condition, the user has flexibility to select the output impedance of each channel. If the PD pin is brought low, then all channels can simultaneously be powered down, with the output at high impedance state (High-Z). The DAC7558 has DB16 as a power-down flag. If this flag is set, then DB11 and DB10 select one of the three power-down modes of the device as described in Table 2. Table 2. DAC7558 Power-Down Modes DB11 DB10 OPERATING MODE 0 0 PWD Hi-Z 0 1 PWD 1 kΩ 1 0 PWD 100 kΩ 1 1 PWD Hi-Z brought low. The RST signal resets all internal registers, and therefore behaves like the Power-On Reset. The DAC7558 updates at the first rising edge of the SYNC signal that occurs after the RST pin is brought back to high. If the RSTSEL pin is high, RST signal going low resets all outputs to midscale. If the RSTSEL pin is low, RST signal going low resets all outputs to zero-scale. Input Data Format Selection DAC7558 can use unsigned binary (USB) or binary twos complement (BTC) input data formats. Format selection is done by the RSTSEL pin. If the RSTSEL is kept low, the 12-bit input data is assumed to have USB format, and any asynchronous clear operation generates zero-scale outputs. If the RSTSEL pin is kept high, the 12-bit input data is assumed to have BTC format and any asynchronous clear operation generates mid-scale outputs. SERIAL INTERFACE The DAC7558 can also be powered down using the PD pin. When the PD pins is brought low, all channels simultaneously power down and all outputs become high impedance. When the PD pin is brought high, the device resumes its state before the power down condition. The DAC7558 is controlled over a versatile 3-wire serial interface, which operates at clock rates up to 50 MHz and is compatible with SPI, QSPI, Microwire, and DSP interface standards. The DAC7558 also has an option to power down individual channels, or multiple channels simultaneously selected by DB20. If DB20 = 0, then the user can power down the selected individual channels. If DB20 = 1, then the user can power down the multiple channels simultaneously as explained in Table 3. Power-down mode is selected by DB11 and DB10. The input shift register is 24 bits wide. DAC data is loaded into the device as a 24-bit word under the control of a serial clock input, SCLK, as shown in the Figure 1 timing diagram. The 24-bit word, illustrated in Table 1, consists of 8 control bits, followed by 12 data bits and 4 don't care bits. Data format is straight binary (RSTSEL pin = 0) or binary twos complement (RSTSEL = 1), where the most significant DAC data bit is DB15. Data is loaded MSB first (DB23) where the first two bits (DB23 and DB22) should be set to zero for DAC7558 to work. The DAC7558 does not respond to any other combination other than 00. DB21 and DB20 (LD1 and LD0) determine if the input register, DAC register, or both are updated with shift register input data. DB19, DB18, and DB17 (SEL2, SEL1, and SEL0) bits select the desired DAC(s). DB16 is the power-down bit. If DB16 = 0, then it is a normal operation, if DB16 = 1, then DB11 and DB10 determine the power-down mode (Hi-Z, 1 kΩ, or 100 kΩ). DB20 bit also gives the user the option of powering down either a single channel or multiple channels at the same time. See Power Down section for more details. Table 3. DAC7558 Power-Down Modes for Multiple Channels DB19 DB18 DB17 0 0 0 OPERATING MODE PWD Channel A-B 0 0 1 PWD Channel A-C 0 1 0 PWD Channel A-D 0 1 1 PWD Channel A-E 1 0 0 PWD Channel A-F 1 0 1 PWD Channel A-G 1 1 0 PWD Channel A-H 1 1 1 PWD Channel A-H Asynchronous Clear The DAC7558 output is asynchronously set to zero-scale voltage immediately after the RST pin is 20 24-Bit Word and Input Shift Register The SYNC input is a level-triggered input that acts as a frame-synchronization signal and chip enable. Data can only be transferred into the device while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC-to-SCLK DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 falling-edge setup time, t4. After SYNC goes low, serial data is shifted into the device's input shift register on the falling edges of SCLK for 24 clock pulses. Any data and clock pulses after the twenty-fourth falling edge of SCLK are ignored. No further serial data transfer occurs until SYNC is taken high and low again. SYNC may be taken high after the falling edge of the twenty-fourth SCLK pulse, observing the minimum SCLK Loop falling-edge to SYNC rising-edge time, t7. After the end of serial data transfer, data is automatically transferred from the input shift register to the input register of the selected DAC. If SYNC is taken high before the twenty-fourth falling edge of SCLK, the data transfer is aborted and the DAC input registers are not updated. When DCEN is low, the SDO pin is brought to a Hi-Z state. The first 24 data bits that follow the falling edge of SYNC are stored in the shift register. The rising edge of SYNC that follows the 24th data bit updates the DAC(s). If SYNC is brought high before the 24th data bit, no action occurs. In daisy-chain mode (DCEN = 1) the DAC7558 requires a falling SCLK edge after the rising SYNC, in order to initialize the serial interface for the next update. When DCEN is high, data can continuously be shifted into the shift register, enabling the daisy-chain operation. The SDO pin becomes active and outputs SDIN data with 24 clock-cycle delay. A rising edge of SYNC loads the shift register data into the DAC(s). The loaded data consists of the last 24 data bits received into the shift register before the rising edge of SYNC. If daisy-chain operation is not needed, DCEN should permanently be tied to a logic-low voltage. Daisy-Chain Operation When the DCEN pin is brought high, daisy chaining is enabled. Serial data output (SDO) pin is provided to daisy-chain multiple DAC7558 devices in a system. As long as SYNC is high or DCEN is low the SDO pin is in a high-impedance state. When SYNC is brought low the output of the internal shift register is tied to the SDO pin. As long as SYNC is low and DCEN is high, SDO duplicates the SDIN signal with 24-cycle delay. To support multiple devices in a daisy-chain, SCLK and SYNC signals are shared across all devices and SDO of one DAC7558 should be tied to the SDIN of the next DAC7558. For n devices in such a daisy chain, 24n SCLK cycles are required to shift the entire input data stream. After 24n SCLK falling edges are received (following a falling SYNC), the data stream becomes complete, and SYNC can be brought high to update n devices simultaneously. SDO operation is specified at a maximum SCLK speed of 10 MHz. Daisy-chain operation is also possible between octal-channel DAC7558, dual-channel DAC7552, and single-channel DAC7551 devices. Dasy chaining enables communication with any number of DAC channels using a single serial interface. As long as the correct number of bits are shifted using a daisy-chain setting, a rising edge of SYNC properly updates all chips in the system. Following a rising edge of SYNC, all devices on the daisy chain respond according to the control bits they receive. IOVDD and Level Shifters The DAC7558 can be used with different logic families that require a wide range of supply voltages (from 1.8 V to 5.5 V). To enable this useful feature, the IOVDD pin must be connected to the logic supply voltage of the system. All DAC7558 digital input and output pins are equipped with level-shifter circuits. Level shifters at the input pins ensure that external logic high voltages are translated to the internal logic high voltage, with no additional power dissipation. Similarly, the level shifter for the SDO pin translates the internal logic high voltage (AVDD) to the external logic high level (IOVDD). For single supply operation, the IOVDD pin can be tied to the AVDD pin. INTEGRAL AND DIFFERENTIAL LINEARITY The DAC7558 uses precision thin-film resistors providing exceptional linearity and monotonicity. Integral linearity error is typically within (+/-) 0.35 LSBs, and differential linearity error is typically within (+/-) 0.08 LSBs. GLITCH ENERGY The DAC7558 uses a proprietary architecture that minimizes glitch energy. The code-to-code glitches are so low, they are usually buried within the wide-band noise and cannot be easily detected. The DAC7558 glitch is typically well under 0.1 nV-s. Such low glitch energy provides more than 10X improvement over industry alternatives. CHANNEL-TO-CHANNEL CROSSTALK The DAC7558 architecture is designed to minimize channel-to-channel crosstalk. The voltage change in one channel does not affect the voltage output in another channel. The DC crosstalk is in the order of a few microvolts. AC crosstalk is also less than –100 dBs. This provides orders of magnitude improvement over certain competing architectures. 21 DAC7558 www.ti.com SLAS435A – MAY 2005 – REVISED DECEMBER 2005 APPLICATION INFORMATION Waveform Generation Due to its exceptional linearity, low glitch, and low crosstalk, the DAC7558 is well suited for waveform generation (from DC to 10 kHz). The DAC7558 large-signal settling time is 5 µs, supporting an update rate of 200 KSPS. However, the update rates can exceed 1 MSPS if the waveform to be generated consists of small voltage steps between consecutive DAC updates. To obtain a high dynamic range, REF3140 (4.096 V) or REF02 (5.0 V) are recommended for reference voltage generation. Generating ±5-V, ±10-V, and ± 12-V Outputs For Precision Industrial Control Industrial control applications can require multiple feedback loops consisting of sensors, ADCs, MCUs, DACs, and actuators. Loop accuracy and loop speed are the two important parameters of such control loops. Loop Accuracy: In a control loop, the ADC has to be accurate. Offset, gain, and the integral linearity errors of the DAC are not factors in determining the accuracy of the loop. As long as a voltage exists in the transfer curve of a monotonic DAC, the loop can find it and settle to it. On the other hand, DAC resolution and differential linearity do determine the loop accuracy, because each DAC step determines the minimum incremental change the loop can generate. A DNL error less than –1 LSB (non-monotonicity) can create loop instability. A DNL error greater than +1 LSB implies unnecessarily large voltage steps and missed voltage targets. With high DNL errors, the loop looses its stability, resolution, and accuracy. Offering 12-bit ensured monotonicity and ± 0.08 LSB typical DNL error, 755X DACs are great choices for precision control loops. Loop Speed: Many factors determine control loop speed. Typically, the ADC's conversion time, and the MCU's computation time are the two major factors that dominate the time constant of the loop. DAC settling time is rarely a dominant factor because ADC conversion times usually exceed DAC conversion times. DAC offset, gain, and linearity errors can slow the loop down only during the start-up. Once the loop reaches its steady-state operation, these errors do not affect loop speed any further. Depending on the 22 ringing characteristics of the loop's transfer function, DAC glitches can also slow the loop down. With its 1 MSPS (small-signal) maximum data update rate, DAC7558 can support high-speed control loops. Ultra-low glitch energy of the DAC7558 significantly improves loop stability and loop settling time. Generating Industrial Voltage Ranges: For control loop applications, DAC gain and offset errors are not important parameters. This could be exploited to lower trim and calibration costs in a high-voltage control circuit design. Using a quad operational amplifier (OPA4130), and a voltage reference (REF3140), the DAC7558 can generate the wide voltage swings required by the control loop. Vtail DAC7558 R1 REF3140 R2 Vref _ REFIN DAC7558 Vdac + VOUT OPA4130 Figure 45. Low-cost, Wide-swing Voltage Generator for Control Loop Applications The output voltage of the configuration is given by:   V OUT  V REF R2
1 Din  V tail R2 4096 R1 R1 (1) Fixed R1 and R2 resistors can be used to coarsely set the gain required in the first term of the equation. Once R2 and R1 set the gain to include some minimal over-range, four DAC7558 channels could be used to precisely set the required offset voltages. Residual errors are not an issue for loop accuracy because offset and gain errors could be tolerated. Four DAC7558 channels can provide the Vtail voltages to minimize offset error, while the other four DAC7558 channels provide Vdac voltages to generate four high-voltage outputs. For ±5-V operation: R1=10 kΩ, R2 = 15 kΩ, Vtail = 3.33 V, VREF = 4.096 V For ±10-V operation: R1=10 kΩ, R2 = 39 kΩ, Vtail = 2.56 V, VREF = 4.096 V For ±12-V operation: R1=10 kΩ, R2 = 49 kΩ, Vtail = 2.45 V, VREF = 4.096 V PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DAC7558IRHBR ACTIVE VQFN RHB 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 D758 DAC7558IRHBT ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 D758 DAC7558IRHBTG4 ACTIVE VQFN RHB 32 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 105 D758 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of