D AC
7
512
DAC7571
www.ti.com
SLAS374D – FEBRUARY 2003 – REVISED JANUARY 2014
+2.7 V to +5.5 V, I2C INTERFACE (RECEIVE ONLY), VOLTAGE OUTPUT,
12-BIT DIGITAL-TO-ANALOG CONVERTER
Check for Samples: DAC7571
FEATURES
1
•
•
•
•
•
•
•
2
•
•
•
•
DESCRIPTION
Micropower Operation: 140 µA @ 5 V
Power-On Reset to Zero
+2.7-V to +5.5-V Power Supply
Specified Monotonic by Design
Settling Time: 10 µs to ±0.003%FS
I2C™ Interface up to 3.4 Mbps
On-Chip Output Buffer Amplifier, Rail-to-Rail
Operation
Double-Buffered Input Register
Address Support for up to Two DAC7571s
Small 6-Lead SOT Package
Operation From –40°C to 105°C
The DAC7571 is a low-power, single channel, 12-bit
buffered voltage output DAC. Its on-chip precision
output amplifier allows rail-to-rail output swing to be
achieved. The DAC7571 utilizes an I2C compatible
two wire serial interface that operates at clock rates
up to 3.4 Mbps with address support of up to two
DAC7571s on the same data bus.
The output voltage range of the DAC is set to VDD.
The DAC7571 incorporates a power-on-reset circuit
that ensures that the DAC output powers up at zero
volts and remains there until a valid write to the
device takes place. The DAC7571 contains a powerdown feature, accessed via the internal control
register, that reduces the current consumption of the
device to 50 nA at 5 V.
APPLICATIONS
•
•
•
•
•
The low power consumption of this part in normal
operation makes it ideally suited for portable battery
operated equipment. The power consumption is less
than 0.7 mW at VDD = 5 V reducing to 1 µW in powerdown mode.
Process Control
Data Acquisition Systems
Closed-Loop Servo Control
PC Peripherals
Portable Instrumentation
The DAC7571 is available in a 6-lead SOT 23
package.
VDD
GND
Power-On
Reset
Ref (+) REF(-)
12-Bit
DAC
DAC
Register
I2C
Control
Logic
A0
SCL
Output
Buffer
Power Down
Control Logic
VOUT
Resistor
Network
SDA
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
I2C is a trademark of Philips Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2014, Texas Instruments Incorporated
DAC7571
SLAS374D – FEBRUARY 2003 – REVISED JANUARY 2014
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DESIGNATO
R
DAC7571
SOT23-6
DBV
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
–40°C to +105°C
D771
ORDERING
NUMBER
TRANSPORT MEDIA
DAC7571IDBVT
250-Piece Small Tape and Reel
DAC7571IDBVR
3000-Piece Tape and Reel
PIN CONFIGURATIONS
(TOP VIEW)
1
2
3
D771
VOUT
GND
VDD
6
5
4
PIN DESCRIPTION (SOT23-6)
A0
SCL
SDA
(BOTTOM VIEW)
5
4
YMLL
6
1
2
3
PIN
NAME
1
VOUT
Analog output voltage from DAC
2
GND
Ground reference point for all
circuitry on the part
3
VDD
Analog Voltage Supply Input
4
SDA
Serial Data Input
5
SCL
Serial Clock Input
6
A0
LOT
TRACE
CODE:
Lot Trace Code
DESCRIPTION
Device Address Select
Year (3 = 2003); Month (1–9 = JAN–SEP; A=OCT,
B=NOV, C=DEC); LL – Random code generated
when assembly is requested
ABSOLUTE MAXIMUM RATINGS (1)
UNITS
VDD to GND
–0.3 V to +6 V
Digital Input voltage to GND
–0.3 V to +VDD +0.3 V
VOUT to GND
–0.3 V to +VDD +0.3 V
Operating temperature range
–40°C to +105°C
Storage temperature range
–65°C to +150°C
Junction temperature range (TJ max)
+150°C
Power dissipation
(TJmax - TA)R ΘJA
Thermal impedance, R ΘJA
240°C/W
Lead temperature, soldering
(1)
Vapor phase (60 s)
215°C
Infrared (15 s)
220°C
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to +105°C unless otherwise noted.
PARAMETER
CONDITIONS
DAC7571
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE (1)
Resolution
12
Relative accuracy
(1)
2
Bits
±0.195
% of FSR
Linearity calculated using a reduced code range of 48 to 4047; output unloaded.
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SLAS374D – FEBRUARY 2003 – REVISED JANUARY 2014
ELECTRICAL CHARACTERISTICS (continued)
VDD = +2.7 V to +5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications –40°C to +105°C unless otherwise noted.
PARAMETER
CONDITIONS
Differential nonlinearity
DAC7571
MIN
TYP
Assured monotonic by design
±1
Zero code error
Full-scale error
MAX
All ones loaded to DAC register
UNITS
LSB
5
20
mV
–0.15
–1.25
% of FSR
±1.25
% of FSR
Gain error
Zero code error drift
±7
µV/°C
Gain temperature coefficient
±3
ppm of FSR/°C
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time
0
1
V/µs
470
pF
RL = 2 kΩ
1000
pF
1 LSB Change around major carry
20
nV-s
0.5
nV-s
Digital feedthrough
DC output impedance
VDD = +5 V
Short-circuit current
LOGIC INPUTS
µs
RL =∞
Capacitive load stability
Power-up time
V
10
8
Slew rate
Code change glitch impulse
VDD
1/4 Scale to 3/4 scale change (400H to C00H)
1
Ω
50
mA
VDD = +3 V
20
mA
Coming out of power-down mode, VDD = +5 V
2.5
µs
Coming out of power-down mode, VDD = +3 V
5
µs
(3)
Input current
VINL, Input low voltage
VDD = +3 V
VINH, Input high voltage
VDD = +5 V
±1
µA
0.3 × VDD
V
0.7 × VDD
V
Pin capacitance
3
pF
5.5
V
POWER REQUIREMENTS
VDD
2.7
IDD (normal operation)
DAC active and excluding load current
VDD = +3.6 V to +5.5 V
VIH = VDD and VIL = GND
135
200
µA
VDD = +2.7 V to +3.6 V
VIH = VDD and VIL = GND
115
160
µA
IDD (all power-down modes)
VDD = +3.6 V to +5.5 V
VIH = VDD and VIL = GND
0.2
1
µA
VDD = +2.7 V to +3.6 V
VIH = VDD and VIL = GND
0.05
1
µA
ILOAD = 2 mA, VDD = +5 V
93
POWER EFFICIENCY
IOUT/IDD
(2)
(3)
%
Specified by design and characterization, not production tested.
Specified by design and characterization, not production tested.
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TIMING CHARACTERISTICS
SYMBOL
fSCL
PARAMETER
SCL Clock Frequency
TEST CONDITIONS
MAX
UNITS
Standard mode
MIN
100
kHz
Fast mode
400
kHz
High-speed mode, CB - 100pF max
3.4
MHz
1.7
MHz
High-Speed mode, CB - 400pF max
tBUF
Bus Free Time Between a STOP
and START Condition
tHD; tSTA
Hold Time (Repeated) START
Condition
tLOW
tHIGH
tSU; tSTA
tSU; tDAT
tHD; tDAT
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Setup Time
Data Hold Time
Standard mode
4.7
µs
Fast mode
1.3
µs
Standard mode
4.0
µs
Fast mode
600
ns
High-speed mode
160
ns
Standard mode
4.7
µs
Fast mode
1.3
µs
High-speed mode, CB - 100pF max
160
ns
High-speed mode, CB - 400pF max
320
ns
Standard mode
4.0
µs
Fast mode
600
ns
High-speed mode, CB - 100pF max
60
ns
High-speed mode, CB - 400pF max
120
ns
Standard mode
4.7
µs
Fast mode
600
ns
High-speed mode
160
ns
Standard mode
250
ns
Fast mode
100
ns
High-speed mode
10
ns
Standard mode
0
3.45
µs
Fast mode
0
0.9
µs
High-speed mode, CB - 100pF max
0
70
ns
High-speed mode, CB - 400pF max
0
150
ns
1000
ns
20 + 0.1CB
300
ns
High-speed mode, CB - 100pF max
10
40
ns
High-speed mode, CB - 400pF max
20
80
ns
1000
ns
300
ns
Standard mode
tRCL
Rise Time of SCL Signal
Fast mode
Standard mode
tRCL1
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge BIT
Fast mode
20 + 0.1CB
High-speed mode, CB - 100pF max
10
80
ns
High-speed mode, CB - 400pF max
20
160
ns
300
ns
Standard mode
tFCL
Fall Time of SCL Signal
20 + 0.1CB
300
ns
High-speed mode, CB - 100pF max
Fast mode
10
40
ns
High-speed mode, CB - 400pF max
20
80
ns
Standard mode
tRDA
Rise Time of SDA Signal
1000
ns
20 + 0.1CB
300
ns
High-speed mode, CB - 100pF max
10
80
ns
High-speed mode, CB - 400pF max
20
160
ns
Fast mode
Standard mode
tFDA
4
Fall Time of SDA Signal
TYP
300
ns
20 + 0.1CB
300
ns
High-speed mode, CB - 100pF max
10
80
ns
High-speed mode, CB - 400pF max
20
160
ns
Fast mode
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SLAS374D – FEBRUARY 2003 – REVISED JANUARY 2014
TIMING CHARACTERISTICS (continued)
SYMBOL
tSU; tSTO
CB
PARAMETER
Setup Time for STOP Condition
MIN
Standard mode
4.0
µs
Fast mode
600
ns
High-speed mode
160
ns
Capacitive Load for SDA and SCL
tSP
Pulse Width of Spike Suppressed
VNH
Noise Margin at the HIGH Level
for Each Connected Device
(Including Hysteresis)
VNL
TEST CONDITIONS
Noise Margin at the LOW Level for
Each Connected Device
(Including Hysteresis)
TYP
MAX
UNITS
400
pF
Fast mode
50
ns
High-speed mode
10
ns
Standard mode
Fast mode
0.2VDD
V
0.1VDD
V
High-speed mode
Standard mode
Fast mode
High-speed mode
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TYPICAL CHARACTERISTICS: VDD = +5 V
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
CODE (+25 ° C )
LE − LSB
8
6
4
2
0
−2
−4
−6
−8
8
6
4
2
0
−2
−4
−6
−8
1
1
0.5
0.5
DLE − LSB
DLE − LSB
LE − LSB
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
CODE (-40°C)
0
−0.5
0
−0.5
−1
−1
0
512
1024
1536
2048
2560
3072
3584
0
4096
512
1024
Digital Input Code
1536 2048 2560
Digital Input Code
Figure 1.
4096
TYPICAL TOTAL UNADJUSTED ERROR
8
6
4
2
0
−2
−4
−6
−8
Output Error −mV
LE − LSB
3584
Figure 2.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
CODE (+105° C)
16
8
0
−8
−16
0
512
1024
1
DLE − LSB
3072
1536
2048
2560
3072
3584 4096
Digital Input Code
0.5
0
−0.5
−1
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 3.
Figure 4.
ZERO-SCALE ERROR
vs
TEMPERATURE
FULL-SCALE ERROR
vs
TEMPERATURE
30
30
20
20
Zero-Scale Error − mV
Zero-Scale Error − mV
0
10
0
−10
0
−10
−20
−20
−30
−50
10
−30
−10
10
30
50
T − Temperature − _C
70
90
110
−30
−50
Figure 5.
6
−30
−10
10
30
50
T − Temperature − _C
70
90
110
Figure 6.
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SLAS374D – FEBRUARY 2003 – REVISED JANUARY 2014
TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
IDD HISTOGRAM
SOURCE AND SINK CURRENT CAPABILITY
2500
5
DAC Loaded with FFFH
4
1500
3
VOUT (V)
f − Frequency − Hz
2000
1000
2
500
DAC Loaded with 000H
200
190
180
170
160
150
140
130
120
110
90
100
80
1
0
0
IDD − Supply Current − mA
0
5
10
15
ISOURCE/SINK (mA)
Figure 7.
Figure 8.
SUPPLY CURRENT
vs
CODE
SUPPLY CURRENT
vs
TEMPERATURE
300
250
400
I DD − Supply Current − µ A
I DD − Supply Current − µA
500
200
300
150
200
100
100
0
000H
200H
600H
A00H
CODE
E00H
50
0
−50
FFFH
−30
−10
10
30
50
70
90
110
T − Temperature − _C
Figure 9.
Figure 10.
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
POWER-DOWN CURRENT
vs
SUPPLY VOLTAGE
300
90
80
200
70
150
IDD (nA)
I DD − Supply Current − µ A
100
250
100
60
+105°C
50
–40°C
40
30
50
20
0
2.7
3.2
3.7
4.2
4.7
VDD − Supply Voltage − V
5.2
5.7
+25°C
10
0
2.7
3.2
3.7
4.2
4.7
5.2
5.7
VDD (V)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
FULL-SCALE SETTLING TIME
2500
CLK (5V/div)
IDD (µA)
2000
1500
VOUT (1V/div)
1000
Full-Scale Code Change
000H to FFFH
Output Loaded with
2kΩ and 200pF to GND
500
0
0
1
2
3
4
Time (1µs/div)
5
VLOGIC (V)
Figure 13.
Figure 14.
FULL-SCALE SETTLING TIME
HALF-SCALE
SETTLING
HALF-SCALE
SETTLING
TIME TIME
CLK (5V/div)
CLK (5V/div)
VOUT (1V/div)
Full-Scale Code Change
FFFH to 000H
Output Loaded with
2kΩ and 200pF to GND
Half-Scale Code Change
400H to C00H
Output Loaded with
2kΩ and 200pF to GND
VOUT (1V/div)
Time (1µs/div)
Time (1µs/div)
Figure 15.
Figure 16.
HALF-SCALE SETTLING TIME
POWER-ON RESET TO 0V
CLK (5V/div)
Half-Scale Code Change
C00H to 400H
Output Loaded with
2kΩ and 200pF to GND
Loaded with 2kΩ to VDD.
VDD (1V/div)
VOUT (1V/div)
VOUT (1V/div)
Time (20µs/div)
Time (1µs/div)
Figure 17.
8
Figure 18.
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TYPICAL CHARACTERISTICS: VDD = +5 V (continued)
At TA = +25°C, +VDD = +5 V, unless otherwise noted.
EXITING POWER-DOWN
(800HLoaded)
CODE CHANGE GLITCH
Loaded with 2kΩ
and 200pF to GND.
Code Change:
800H to 7FFH.
VOUT (1V/div)
VOUT (20mV/div)
CLK (5V/div)
Time (5µs/div)
Time (0.5µs/div)
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS: VDD = +2.7 V
At TA = +25°C, +VDD = +2.7V, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
CODE (+25 °C)
LE − LSB
8
6
4
2
0
−2
−4
−6
−8
8
6
4
2
0
−2
−4
−6
−8
1
1
0.5
0.5
DLE − LSB
DLE − LSB
LE − LSB
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
CODE (-40 °C)
0
−0.5
−1
0
512
1024
1536
2048
2560
3072
3584
0
−0.5
−1
4096
0
512
1024
Digital Input Code
1536
Figure 21.
3584
4096
ABSOLUTE ERROR
8
Output Error − mV
LE − LSB
0.5
0
−8
0
−0.5
−1
0
512
−16
1024
1536
2048
2560
3072
3584
4096
512
1024
1536
2048
2560
3072
Digital Input Code
Figure 23.
Figure 24.
ZERO-SCALE ERROR
vs
TEMPERATURE
FULL-SCALE ERROR
vs
TEMPERATURE
30
30
20
20
10
0
−10
−20
−30
−50
0
Digital Input Code
Full-Scale Error − mV
DLE − LSB
3072
16
8
6
4
2
0
−2
−4
−6
−8
1
Zero-Scale Error − mV
2560
Figure 22.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs
CODE (+105 °C)
3584 4096
10
0
−10
−20
−30
−10
10
30
50
70
90
110
−30
−50
−30
−10
10
30
50
70
90
110
T − Temperature − _C
T − Temperature − _C
Figure 25.
10
2048
Digital Input Code
Figure 26.
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TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7V, unless otherwise noted.
IDD HISTOGRAM
2500
SOURCE
AND
CAPABILITY
SOURCE
ANDSINK
SINKCURRENT
CURRENT CAPABILITY
3
VDD = +3V
DAC Loaded with FFFH
2
1500
VOUT (V)
f − Frequency − Hz
2000
1000
1
500
200
190
180
170
160
150
140
130
120
110
100
90
80
DAC Loaded with 000H
0
0
IDD − Supply Current − mA
0
5
10
15
ISOURCE/SINK (mA)
Figure 27.
Figure 28.
SUPPLY CURRENT
vs
CODE
SUPPLY CURRENT
vs
9
TEMPERATURE
300
I DD − Supply Current − µ A
500
f − Frequency − Hz
400
300
200
100
0
000H 02FH 200H 400H 600H 800H A00 C00H E00H FCFH FFFH
IDD − Supply Current
− mA
H
250
200
150
100
50
0
−50
−30
−10
10
30
50
70
90
110
T − Temperature − _C
Figure 29.
Figure 30.
SUPPLY CURRENT
vs
LOGIC INPUT VOLTAGE
FULL
SCALE SETTLING
SETTLINGTIME
TIME
FULL-SCALE
2500
CLK (2.7V/div)
IDD (µA)
2000
1500
1000
500
VOUT (1V/div)
0
0
1
2
3
4
5
Full-Scale Code Change
000H to FFFH
Output Loaded with
2kΩ and 200pF to GND
Time (1µs/div)
VLOGIC (V)
Figure 31.
Figure 32.
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TYPICAL CHARACTERISTICS: VDD = +2.7 V (continued)
At TA = +25°C, +VDD = +2.7V, unless otherwise noted.
FULL SCALE SETTLING TIME
HALF SCALE SETTLING TIME
CLK (2.7V/div)
CLK (2.7V/div)
Full-Scale Code Change
FFFH to 000H
Output Loaded with
2kΩ and 200pF to GND
VOUT (1V/div)
VOUT (1V/div)
Time (1µs/div)
Half-Scale Code Change
400H to C00H
Output Loaded with
2kΩ and 200pF to GND
Time (1µs/div)
Figure 33.
Figure 34.
HALF SCALE SETTLING TIME
POWER ON
RESET
POWER-ON
RESET
to 0V 0 V
CLK (2.7V/div)
Half-Scale Code Change
C00H to 400H
Output Loaded with
2kΩ and 200pF to GND
VOUT (1V/div)
Time (20µs/div)
Time (1µs/div)
Figure 35.
Figure 36.
EXITING-POWER DOWN (800HLoaded)
CODE CHANGE GLITCH
Loaded with 2kΩ
and 200pF to GND.
Code Change:
800H to 7FFH.
VOUT (1V/div)
VOUT (20mV/div)
CLK (2.7V/div)
Time (5µs/div)
Time (0.5µs/div)
Figure 37.
12
Figure 38.
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THEORY OF OPERATION
D/A SECTION
The architecture of the DAC7571 consists of a string DAC followed by an output buffer amplifier. Figure 39
shows a block diagram of the DAC architecture.
VDD
REF (+)
Resistor
String
DAC Register
VOUT
Output
Amplifier
REF (-)
GND
Figure 39. R-String DAC Architecture
The input coding to the DAC7571 is unsigned binary, which gives the ideal output voltage as:
D
V OUT + VDD
4096
where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 4095.
RESISTOR STRING
The resistor string section is shown in Figure 40. It is simply a string of resistors, each of value R. The code
loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the
output amplifier by closing one of the switches connecting the string to the amplifier. It is ensured monotonic
because it is a string of resistors. The negative tap of the resistor string is tied to GND. The positive tap of the
resistor string is tied to VDD.
VDD
R
To Output
Amplifier
R
R
R
GND
Figure 40. Resistor String
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OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range
of 0 V to VDD. It is capable of driving a load of 2kΩ in parallel with 1000 pF to GND. The source and sink
capabilities of the output amplifier can be seen in the typical characteristics. The slew rate is 1V/µs with a halfscale settling time of 8 µs with the output unloaded.
I2C Interface
The DAC7571 uses an I2C interface as defined by Philips Semiconductor to receive data in slave mode (see I2CBus Specification, Version 2.1, January 2000). The DAC7571 supports the following data transfer modes,
described in the I2C-Bus Specification: Standard Mode (100 kbit/s), Fast Mode (400 kbit/s) and High-Speed
Mode (3.4 Mbit/s). Ten-bit addressing and general call addressing are not supported.
For simplicity, standard mode and fast mode are referred to as F/S-mode and high-speed mode is referred to as
HS-mode.
The 2-wire I2C serial bus protocol operates as follows:
• The Master initiates data transfer by establishing a Start condition. The Start condition is defined when a highto-low transition occurs on the SDA line while SCL is high, as shown in Figure 41. The byte following the start
condition is the address byte consisting of the 7-bit slave address followed by the W bit.
SDA
SDA
SCL
SCL
S
P
Start
Condition
Stop
Condition
Figure 41. START and STOP Conditions
•
The addressed Slave responds by pulling the SDA pin low during the ninth clock pulse, termed the
Acknowledge bit (see Figure 42). At this stage all other devices on the bus remain idle while the selected
device waits for data to be written to its shift register.
Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
8
S
9
Clock Pulse for
Acknowledgement
START
Condition
Figure 42. Acknowledge on the I2C Bus
•
14
Data is transmitted over the serial bus in sequences of nine clock cycles (8 data bits followed by an
acknowledge bit. The transitions on the SDA line must occur during the low period of SCL and remain stable
during the high period of SCL (see Figure 43).
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SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
Figure 43. Bit Transfer on the I2C Bus
•
When all data bits have been written, a Stop condition is established (see Figure 44). In writing to the
DAC7571, the master must pull the SDA line high during the tenth clock pulse to establish a Stop condition.
Recognize START or
REPEATED START
Condition
Recognize STOP or
REPEATED START
Condition
Generate ACKNOWLEDGE
Signal
P
SDA
MSB
Acknowledgement
Signal From Slave
Sr
Address
R/W
SCL
S
or
Sr
1
2
START or
Repeated START
Condition
7
8
9
ACK
1
2
3-8
9
ACK
Sr
or
P
Clock Line Held Low While
Interrupts are Serviced
STOP or
Repeated START
Condition
Figure 44. Bus Protocol
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Standard-and Fast-Mode:
S SLAVE ADDRESS R/W A
Ctrl/MS-Byte
A LS-Byte
A/A
P
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
”0” (write)
From Master to DAC7571
DAC7571 I2C-SLAVE ADDRESS:
From DAC7571 to Master
MSB
A =
A =
S =
Sr =
P =
LSB
1
Acknowledge (SDA LOW)
Not Acknowledge (SDA HIGH)
START Condition
Repeated START Condition
STOP Condition
0
0
1
1
0
A0
R/W
‘0’ = Write to DAC7571
‘1’ = Not Supported
Factory Preset
A0 = I2C Address Pin
High-Speed-Mode (HS-Mode):
F/S-Mode
S
HS-Mode
HS-Master Code
A Sr Slave Address
R/W A
Ctrl/MS-Byte
HS-Mode Master Code:
A/A
P
HS-Mode Continues
Sr Slave Address
MSB
LSB
0
0
0
1
X
X
R/W
Ctrl/MS-Byte:
LS-Byte:
MSB
0
A LS-Byte
Data Transferred
(n* Words + Acknowledge)
Word = 16 Bit
”0” (write)
0
F/S-Mode
0
PD1 PD2
D11
D10
D9
LSB
MSB
D8
D7
LSB
D6
D5
D4
D3
D2
D1
D0
D11 − D0 = Data Bits
Figure 45. Master Transmitter Addressing DAC7571 as a Slave Receiver With a 7-Bit Address
ADDRESS BYTE
MSB
1
0
0
1
1
0
A0
R/W
0
The address byte is the first byte received by the DAC7571 following the START condition from the master
device. The first five bits (MSBs) of the slave address are factory preset to 100110. The next bit of the address
byte is the device select bit, A0. In order for DAC7571 to respond, the logic state of address bit A0 should match
the logic state of address pin A0. A maximum of two devices with the same preset code can therefore be
connected on the same bus at one time. The A0 Address Input can be connected to VDD or digital ground, or can
be actively driven by TTL or CMOS logic levels. The device address is set by the state of the A0 pin upon powerup of the DAC7571. The last bit of the address byte (R/W) should always be zero (receive only I2C interface).
Following the START condition, the DAC7571 monitors the SDA bus, checking the device type identifier being
transmitted. Upon receiving the 100110 code, the appropriate device select bit and the R/W bit, the DAC7571
outputs an acknowledge signal on the SDA line. Upon receipt of a broadcast address 10010000, the DAC7571
responds regardless of the state of the A0 pin.
16
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MASTER TRANSMITTER WRITING TO A SLAVE RECEIVER (DAC7571) IN STANDARD/FAST
MODES
I2C protocol starts when the bus is idle, that is, when SDA and SCL lines are stable high. The master then pulls
the SDA line low while SCL is still high indicting that serial data transfer has started. This is called a start
condition, and can only be asserted by the master. After the start condition, the master generates the serial clock
and puts out an address byte. While generating the bit stream, the master ensures the timing for valid data. For
each valid I2C bit, the SDA line should remain stable during the entire high period of the SCL line. The address
byte consists of 7 address bits (1001 100, assuming A0=0) and a direction bit (R/W=0). After sending the
address byte, the master generates a ninth SCL pulse and monitors the state of the SDA line during the high
period of this ninth clock cycle.
The SDA line being pulled low by a receiver during the high period of this 9th clock cycle is called an
acknowledge signal. If the master receives an acknowledge signal, it knows that a DAC7571 successfully
matched the address which the master sent. Upon the receipt of this acknowledge, the master knows that the
communication link with a DAC7571 has been established and more data can be sent. The master continues by
sending a Control/MS-byte, which sets DAC7571 operation mode and specifies the first 4 MSBs of data. After
sending the Control/MS-byte, the master expects an acknowledge signal from the DAC7571. Upon the receipt of
the acknowledge, the master sends an LS-byte that represents the 8 least significant bits of DAC7571's 12-bit
conversion data. After receiving the LS-byte, the DAC7571 sends an acknowledge. At the falling edge of the
acknowledge signal, following the LS-byte, the DAC7571 performs a digital to analog conversion. For further
DAC updates, the master can keep repeating Control/MS-byte and LS-byte sequences expecting an
acknowledge after each byte. After the required number of digital to analog conversions is complete, the master
can break the communication link with the DAC7571 by pulling the SDA line from low to high while SCL line is
high. This is called a stop condition. A stop condition brings the bus back to idle (SDA and SCL both high). A
stop condition indicates that communication with the DAC7571 has ended. All devices on the bus, including the
DAC7571, waits for a new start condition followed by a matching address byte. DAC7571 stays in a programmed
state until the receipt of a stop condition.
Table 1. Write Sequence in Standard/Fast Modes
Transmitter
MSB
6
5
4
3
Master
Master
1
0
0
0
0
PD1
1
Comment
Begin Sequence (1)
1
Write Addressing (LSB=0, R/W =
0)
0
A0
0
PD0
D11
D10
D9
D8
Writing Control/MS-Byte
D2
D1
D0
Writing LS-Byte
DAC7571 Acknowledges
D7
D6
D5
D4
D3
DAC7571
DAC7571 Acknowledges
Master
Stop or Repeated Start (2)
(1)
(2)
LSB
DAC7571 Acknowledges
DAC7571
Master
1
Start
DAC7571
Master
2
Done
Once DAC7571 is addressed, high-byte-low-byte sequences can repeat until a stop condition is received.
Use repeated start to secure bus operation and loop back to the stage of write addressing for next Write.
POWER-ON RESET
The DAC7571 contains a power-on reset circuit that controls the output voltage during power-up. On power-up,
the DAC register is filled with zeros and the output voltage is 0 V. It remains at a zero-code output until a valid
write sequence is made to the DAC. This is useful in applications where it is important to know the state of the
DAC output while it is in the process of powering up.
POWER-DOWN MODES
The DAC7571 contains four separate modes of operation. These modes are programmable via two bits (PD1
and PD0). Table 2 shows how the state of these bits correspond to the mode of operation.
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Table 2. Modes of Operation for the DAC7571
PD1
PD0
0
0
OPERATING MODE
Normal Operation
0
1
1kΩ to AGND, PWD
1
0
100kΩ to AGND, PWD
1
1
High Impedance, PWD
When both bits are set to 0, the device works normally with normal power consumption of 150 µA at 5V.
However, for the three power-down modes, the supply current falls to 200 nA at 5V (50 nA at 3 V). Not only does
the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor
network of known values. This has the advantage that the output impedance of the device is known while in
power-down mode. There are three different options: The output is connected internally to AGND through a 1 kΩ
resistor, a 100 kΩ resistor, or it is left open-circuited (high impedance). The output stage is illustrated in
Figure 46.
Amplifier
Resistor
String DAC
VOUT
Powerdown
Circuitry
Resistor
Network
Figure 46. Output Stage During Power-Down
All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time required to exit power down is typically 2.5 µs for AVDD =
5 V and 5 µs for AVDD = 3 V. See the Typical Characteristics for more information.
CURRENT CONSUMPTION
The DAC7571 typically consumes 150 µA at VDD = 5 V and 120 µA at VDD = 3 V. Additional current consumption
can occur due to the digital inputs if VIH
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