DAC
®
761
DAC
DAC7611
1
761
1
12-Bit Serial Input
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● LOW POWER: 2.5mW
● FAST SETTLING: 7µs to 1 LSB
● 1mV LSB WITH 4.095V FULL-SCALE
RANGE
● COMPLETE WITH REFERENCE
The DAC7611 is a 12-bit digital-to-analog converter
(DAC) with guaranteed 12-bit monotonicity performance over the industrial temperature range. It requires a single +5V supply and contains an input shift
register, latch, 2.435V reference, DAC, and high speed
rail-to-rail output amplifier. For a full-scale step, the
output will settle to 1 LSB within 7µs. The device
consumes 2.5mW (0.5mA at 5V).
● 12-BIT LINEARITY AND MONOTONICITY
OVER INDUSTRIAL TEMP RANGE
The synchronous serial interface is compatible with a
wide variety of DSPs and microcontrollers. Clock
(CLK), serial data in (SDI), and load strobe (LD)
comprise the serial interface. In addition, two control
pins provide a chip select (CS) function and an asynchronous clear (CLR) input. The CLR input can be
used to ensure that the DAC7611 output is 0V on
power-up or as required by the application.
● ASYNCHRONOUS RESET TO 0V
● 3-WIRE INTERFACE: Up to 20MHz Clock
● ALTERNATE SOURCE TO DAC8512
APPLICATIONS
● PROCESS CONTROL
● DATA ACQUISITION SYSTEMS
The DAC7611 is available in an 8-lead SOIC or 8-pin
plastic DIP package and is fully specified over the
industrial temperature range of –40°C to +85°C.
● CLOSED-LOOP SERVO-CONTROL
● PC PERIPHERALS
● PORTABLE INSTRUMENTATION
VDD
DAC7611
Ref
12-Bit DAC
VOUT
12
CLR
DAC Register
LD
CS
CLK
12
Serial Shift Register
SDI
GND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
© 1997 Burr-Brown Corporation
SBAS075
PDS-1402A
1
Printed in U.S.A. April, 1998
DAC7611
SPECIFICATIONS
ELECTRICAL
At TA = –40°C to +85°C, and VDD = +5V, unless otherwise noted.
DAC7611P, U
PARAMETER
ACCURACY
Resolution
Relative Accuracy(1)
Differential Nonlinearity
Zero-Scale Error
Full Scale Voltage
ANALOG OUTPUT
Output Current
Load Regulation
Capacitive Load
Short Circuit Current
Short Circuit Duration
DAC7611PB, UB
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Guaranteed Monotonic
Code 000H
Code FFFH
12
–2
–1
–1
4.079
±1/2
±1/2
+1
4.095
+2
+1
+3
4.111
✻
–1
–1
✻
4.087
±1/4
±1/4
✻
4.095
+1
+1
✻
4.103
Bits
LSB
LSB
LSB
V
Code 800H
RLOAD ≥ 402Ω, Code 800H
No Oscillation
±5
GND or VDD
DIGITAL INPUT
Data Format
Data Coding
Logic Family
Logic Levels
VIH
VIL
IIH
IIL
±7
1
500
±70
Indefinite
✻
3
✻
✻
✻
✻
✻
✻
2.4
✻
✻
✻
0.8
±10
±10
POWER SUPPLY
VDD
IDD
Power Dissipation
Power Supply Sensitivity
To ±1 LSB of Final Value
+4.75
TEMPERATURE RANGE
Specified Performance
–40
+5.0
0.5
2.5
0.001
+5.25
1
5
0.004
✻
+85
✻
✻
✻
✻
✻
V
V
µA
µA
µs
nV-s
nV-s
✻
✻
✻
7
15
2
VIH = 5V, VIL = 0V, No Load, at Code 000H
VIH = 5V, VIL = 0V, No Load
∆VDD = ±5%
mA
LSB
pF
mA
✻
✻
✻
Serial
Straight Binary
TTL
DYNAMIC PERFORMANCE
Settling Time(2) (tS)
DAC Glitch
Digital Feedthrough
✻
✻
✻
✻
✻
V
mA
mW
%/%
✻
°C
✻ Same specification as for DAC7611P, U.
NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where
the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC7611
2
PIN CONFIGURATION
PIN DESCRIPTION
Top View
DIP
VDD
1
CS
2
CLK
3
SDI
4
8
DAC7611
VOUT
7
GND
6
CLR
5
LD
PIN
LABEL
DESCRIPTION
1
VDD
Power Supply
2
CS
Chip Select (active LOW).
3
CLK
Synchronous Clock for the Serial Data Input.
4
SDI
Serial Data Input. Data is clocked into the internal
serial register on the rising edge of CLK.
5
LD
Loads the Internal DAC Register. NOTE: The DAC
register is a transparent latch and is transparent
when LD is LOW (regardless of the state of CS or
CLK).
6
CLR
Asynchronous Input to Clear the DAC Register.
When CLR is strobbed LOW, the DAC register is set
to 000H and the output voltage to 0V.
7
GND
Ground
8
VOUT
Voltage Output. Fixed output voltage range of approximately 0V to 4.095V (1mV/LSB). The internal
reference maintains this output range over time,
temperature, and power supply variations (within
the values defined in the specifications section).
PIN CONFIGURATION
Top View
SOIC
VDD
1
CS
2
CLK
3
SDI
4
DAC7611
8
VOUT
7
GND
6
CLR
5
LD
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ABSOLUTE MAXIMUM RATINGS(1)
VDD to GND .......................................................................... –0.3V to 6V
Digital Inputs to GND ............................................. –0.3V to VDD + 0.3V
VOUT to GND ........................................................... –0.3V to VDD + 0.3V
Power Dissipation ........................................................................ 325mW
Thermal Resistance, θJA ............................................................ 150°C/W
Maximum Junction Temperature ................................................. +150°C
Operating Temperature Range ...................................... –40°C to +85°C
Storage Temperature Range ........................................ –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................. +300°C
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
NONLINEARITY
(LSB)
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
DAC7611P
DAC7611U
±2
±2
±1
±1
–40°C to +85°C
–40°C to +85°C
8-Pin DIP
8-Lead SOIC
006
182
±1
±1
±1
±1
"
"
"
DAC7611PB
DAC7611UB
"
"
"
–40°C to +85°C
–40°C to +85°C
8-Pin DIP
8-Lead SOIC
006
182
"
"
"
"
"
"
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
DAC7611P
DAC7611U
DAC7611U/2K5
DAC7611PB
DAC7611UB
DAC7611UB/2K5
Rails
Rails
Tape and Reel
Rails
Rails
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7611/2K5” will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
®
3
DAC7611
EQUIVALENT INPUT LOGIC
ESD protection
diodes to VDD
and GND
DAC
Switches
12
CLR
Force to 000H
DAC
Register
LD
Latched
Transparent
12
Data
SDI
Serial Shift Register
CS
CLK
®
DAC7611
4
TIMING DIAGRAMS
(MSB)
SDI
(LSB)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CLK
tCSS
tCSH
CS
tLD1
tLD2
LD
tDS
tDH
SDI
tCL
tCH
CLK
tLDW
LD
tCLRW
CLR
tS
FS
VOUT
ZS
TIMING SPECIFICATIONS
LOGIC TRUTH TABLE
CS(1) CLK(1)
CLR
LD
tS
±1 LSB
Error Band
SERIAL SHIFT
REGISTER
TA = –40°C to +85°C and V DD = +5V.
DAC REGISTER
H
X
H
H
No Change
No Change
L
L
H
H
No Change
No Change
L
H
H
H
No Change
No Change
SYMBOL
DESCRIPTION
tCH
Clock Width HIGH
MIN TYP MAX UNITS
30
tCL
Clock Width LOW
30
ns
Load Pulse Width
20
ns
ns
L
↑
H
H
Advanced One Bit
No Change
tLDW
↑
L
H
H
Advanced One Bit
No Change
tDS
Data Setup
15
ns
H(2)
X
H
↓
No Change
Changes to Value of
Serial Shift Register
tDH
Data Hold
15
ns
tCLRW
Clear Pulse Width
30
ns
H(2)
X
H
L(3)
No Change
Transparent
tLD1
Load Setup
15
ns
H
X
L
X
No Change
Loaded with 000H
Load Hold
10
ns
H
X
↑
tLD2
H
No Change
Latched with 000H
↑ Positive Logic Transition; ↓ Negative Logic Transition; X = Don’t Care.
NOTES: (1) CS and CLK are interchangeable. (2) A HIGH value is suggested
in order to avoid to “false clock” from advancing the shift register and changing
the DAC voltage. (3) If data is clocked into the serial register while LD is LOW,
the DAC output voltage will change, reflecting the current value of the serial
shift register.
tCSS
Select
30
ns
tCSH
Deselect
20
ns
NOTE: All input control signals are specified with tR = tF = 5ns (10% to 90%
of +5V) and timed from a voltage level of 1.6V. These parameters are
guaranteed by design and are not subject to production testing.
®
5
DAC7611
TYPICAL PERFORMANCE CURVES
At TA = +25°, and VDD = 5V, unless otherwise specified.
PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT
OUTPUT SWING vs LOAD
1k
5
100
RL tied to AGND
Data = FFFH
Delta VOUT (mV)
Output Voltage (V)
4
3
2
25°C
10
1
RL tied to +5V
Data = 000H
1
85°C (mV)
–40°C
0.1
Data = 000H
0.01
0.001
0
10
100
1k
10k
100k
0.01
0.1
1
10
100
Current (mA)
Load Resistance (Ω)
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
BROADBAND NOISE
4.0
No Load
Supply Current (mA)
Noise Voltage (500µV/div)
3.2
Code = FFFH
BW = 2MHz
2.4
1.6
0.8
0
0
Time (2ms/div)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Logic Voltage (V)
POWER SUPPLY REJECTION vs FREQUENCY
MINIMUM SUPPLY VOLTAGE vs LOAD
70
5.0
Data = FFFH
VDD = 5V
±200mV AC
60
4.8
VDD Minimum (V)
50
PSR (dB)
∆VFS = 1 LSB
Data = FFFH
40
30
20
4.6
4.4
4.2
10
0
10
100
1k
10k
100k
4.0
0.010
1M
Frequency (Hz)
®
DAC7611
0.100
1.000
Output Load Current (mA)
6
10.000
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE
SUPPLY CURRENT vs TEMPERATURE
80
4.0
Positive
Current
Limit
Supply Current (mA)
40
VLOGIC = 2.4V
Data = FFFH
No Load
3.5
Data = 800H
Output tied to ISOURCE
20
0
–20
–40
Negative
Current
Limit
–60
3.0
2.5
2.0
VDD = 5.25V
VDD = 5.0V
1.5
1.0
0.5
–80
VDD = 4.75V
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–50
–25
0
25
50
75
100
Output Voltage (V)
Temperature (°C)
MIDSCALE GLITCH PERFORMANCE
MIDSCALE GLITCH PERFORMANCE
125
LD
VOUT (10mV/div)
VOUT (10mV/div)
LD
VOUT
VOUT
800H to 7FFH
7FFH to 800H
Time (500ns/div)
Time (500ns/div)
LARGE-SIGNAL SETTLING TIME
RISE TIME DETAIL
CL = 110pF
RL = No Load
Output Voltage (1mV/div)
LD
1V/div
Output Current (mA)
60
VOUT
LD
Time (20µs/div)
VOUT
Time (10µs/div)
®
7
DAC7611
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
FALL TIME DETAIL
OUTPUT VOLTAGE NOISE vs FREQUENCY
10.000
Noise (µV/√Hz)
Output Voltage (1mV/div)
Data = FFFH
VOUT
LD
1.000
0.100
0.010
Time (10µs/div)
10
100
1k
10k
100k
Frequency (Hz)
LONG-TERM DRIFT ACCELERATED BY BURN-IN
5
TOTAL UNADJUSTED ERROR HISTOGRAM
60
120 Units
T.U.E = ΣINL = ZS + FS
Sample Size = 300 Units
TA = +25°C
50
3
2
1
min
0
avg
–1
Number of Units
Output Voltage Change (mV)
4
max
–2
–3
40
30
20
10
–4
–5
0
200
400
600
800
1000
0
–12
1200
–8
–4
0
4
8
12
Hours of Operation at +150°C
FULL-SCALE VOLTAGE vs TEMPERATURE
ZERO-SCALE VOLTAGE vs TEMPERATURE
4.115
3
4.105
2
Zero-Scale (mV)
Full-Scale Output (V)
No Load
Sample Size = 300
Avg + 3σ
4.110
4.100
4.095
Avg
4.090
4.085
1
0
4.080
Avg – 3σ
4.075
–1
–50
–25
0
25
50
75
100
125
–50
Temperature (°C)
0
25
50
Temperature (°C)
®
DAC7611
–25
8
75
100
125
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°, and VDD = 5V, unless otherwise specified.
LINEARITY ERROR vs DIGITAL CODE
(at +25°C)
2.0
1.5
1.5
Linearity Error (LSBs)
2.0
1.0
0.5
0
–0.5
–1.0
1.0
0.5
0
–0.5
–1.0
–1.5
–1.5
–2.0
–2.0
0
512
1024
1536
2048
2560
3072
3584
0
4096
512
1024
1536
2048
2560
3072
3584
4096
Code
Code
LINEARITY ERROR vs DIGITAL CODE
(at –40°C)
2.0
1.5
Linearity Error (LSBs)
Linearity Error (LSBs)
LINEARITY ERROR vs DIGITAL CODE
(at +85°C)
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
512
1024
1536
2048
2560
3072
3584
4096
Code
®
9
DAC7611
OPERATION
clear input (CLR) is provided to simplify start-up or periodic
resets. Table I shows the relationship between input code
and output voltage.
The digital data into the DAC7611 is double-buffered. This
means that new data can be entered into the DAC without
disturbing the old data and the analog output of the converter. At some point after the data has been entered into the
serial shift register, this data can be transferred into the DAC
register. This transfer is accomplished with a HIGH to LOW
transition of the LD pin. However, the LD pin makes the
DAC register transparent. If new data is shifted into the shift
register while LD is LOW, the DAC output voltage will
change as each new bit is entered. To prevent this, LD must
be returned HIGH prior to shifting in new serial data.
At any time, the contents of the DAC register can be set to
000H (analog output equals 0V) by taking the CLR input
LOW. The DAC register will remain at this value until CLR
is returned HIGH and LD is taken LOW to allow the
contents of the shift register to be transferred to the DAC
register. If LD is LOW when CLR is taken LOW, the DAC
register will be set to 000H and the analog output driven to
0V. When CLR is returned HIGH, the DAC register will be
set to the current value in the serial shift register and the
analog output will respond accordingly.
The DAC7611 is a 12-bit digital-to-analog converter (DAC)
complete with a serial-to-parallel shift register, DAC register, laser-trimmed 12-bit DAC, on-board reference, and a
rail-to-rail output amplifier. Figure 1 shows the basic operation of the DAC7611.
INTERFACE
Figure 1 shows the basic connection between a
microcontroller and the DAC7611. The interface consists of
a serial clock (CLK), serial data (SDI), and a load strobe
signal (LD). In addition, a chip select (CS) input is available
to enable serial communication when there are multiple
serial devices. The data format is Straight Binary and is
loaded MSB-first into the shift registers. An asynchronous
DAC7611 Full-Scale Range = 4.095V
Least Significant Bit = 1mV
DIGITAL INPUT CODE
STRAIGHT BINARY
ANALOG OUTPUT
(V)
FFFH
801H
800H
7FFH
000H
DESCRIPTION
+4.095
+2.049
+2.048
+2.047
0
Full Scale
Midscale + 1 LSB
Midscale
Midscale – 1 LSB
Zero Scale
DIGITAL-TO-ANALOG CONVERTER
The internal DAC section is a 12-bit voltage output
device that swings between ground and the internal reference voltage. The DAC is realized by a laser-trimmed
R-2R ladder network which is switched by N-channel
MOSFETs. The DAC output is internally connected to
the rail-to-rail output operational amplifier.
TABLE I. Digital Input Code and Corresponding Ideal
Analog Output.
+5V
DAC7611
1
VDD
VOUT
8
2
CS
GND
7
Serial Clock
3
CLK
CLR
6
Serial Data
4
SDI
LD
5
10µF
From
µC
+
0.1µF
0V to
+4.095V
OUTPUT AMPLIFIER
A precision, low-power amplifier buffers the output of the
DAC section and provides additional gain to achieve a 0 to
4.095V range. The amplifier has low offset voltage, low
noise, and a set gain of 1.682V/V (4.095/2.435). See Figure
2 for an equivalent circuit schematic of the analog portion of
the DAC7611.
Load Strobe
FIGURE 1. Basic Operation of the DAC7611.
R-2R DAC
2R
Output Amplifier
R
Buffer
Bandgap
Reference
2R
R2
2.435V
R
R1
2R
R
2R
2R
FIGURE 2. Simplified Schematic of Analog Portion.
®
DAC7611
10
The output amplifier has a 7µs typical settling time to ±1
LSB of the final value. Note that there are differences in the
settling time for negative-going signals versus positivegoing signals.
The DAC7611 power supply should be bypassed as shown
in Figure 1. The bypass capacitors should be placed as close
to the device as possible, with the 0.1uF capacitor taking
priority in this regard. The Power Supply Rejection vs
Frequency graph in the Typical Performance Curves section
shows the PSRR performance of the DAC7611. This should
be taken into account when using switching power supplies
or DC/DC converters.
The rail-to-rail output stage of the amplifier provides the
full-scale range of 0V to 4.095V while operating on a supply
voltage as low as 4.75V. In addition to its ability to drive
resistive loads, the amplifier will remain stable while driving
capacitive loads of up to 500pF. See Figure 3 for an equivalent circuit schematic of the amplifier’s output driver and the
Typical Performance Curves section for more information
regarding settling time, load driving capability, and output
noise.
In addition to offering guaranteed performance with VDD in
the 4.75V to 5.25V range, the DAC7611 will operate with
reduced performance down to 4.5V. Operation between
4.5V and 4.75V will result in longer settling time, reduced
performance, and current sourcing capability. Consult the
VDD vs Load Current graph in the Typical Performance
Curves section for more information.
APPLICATIONS
VDD
POWER AND GROUNDING
P-Channel
The DAC7611 can be used in a wide variety of situations—
from low power, battery operated systems to large-scale
industrial process control systems. In addition, some applications require better performance than others, or are particularly sensitive to one or two specific parameters. This
diversity makes it difficult to define definite rules to follow
concerning the power supply, bypassing, and grounding.
The following discussion must be considered in relation to
the desired performance and needs of the particular system.
A precision analog component requires careful layout, adequate bypassing, and a clean, well-regulated power supply.
As the DAC7611 is a single-supply, +5V component, it will
often be used in conjunction with digital logic,
microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the
higher the switching speed, the more difficult it will be to
achieve good performance.
Because the DAC7611 has a single ground pin, all return
currents, including digital and analog return currents, must
flow through this pin. The GND pin is also the ground
reference point for the internal bandgap reference. Ideally,
GND would be connected directly to an analog ground
plane. This plane would be separate from the ground connection for the digital components until they are connected
at the power entry point of the system (see Figure 4).
VOUT
N-Channel
AGND
FIGURE 3. Simplified Driver Section of Output Amplifier.
POWER SUPPLY
A BiCMOS process and careful design of the bipolar and
CMOS sections of the DAC7611 result in a very low power
device. Bipolar transistors are used where tight matching
and low noise are needed to achieve analog accuracy, and
CMOS transistors are used for logic, switching functions
and for other low power stages.
If power consumption is critical, it is important to keep the
logic levels on the digital inputs (SDI, CLK, CS, LD, CLR)
as close as possible to either VDD or ground. This will keep
the CMOS inputs (see “Supply Current vs Logic Input
Voltages” in the Typical Performance Curves) from shunting current between VDD and ground. Thus, CMOS logic
levels rather than TTL logic levels, are strongly recommended for driving the DAC7611.
The power applied to VDD should be well regulated and lownoise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between VDD and VOUT.
®
11
DAC7611
OFFSET ERROR MEASUREMENT
As with most DACs, the DAC7611 can have an offset error
(or zero scale error) which is either negative or positive. If
the error is positive, the output voltage for an input code of
000H will be greater than 0V. If the error is negative, the
output voltage is below 0V. However, since the DAC7611 is
a single-supply device and cannot swing below ground, the
output voltage will be 0V, giving the impression that the
offset error is zero.
Since measuring the offset error on a DAC is such a
common task, a method is needed to reliably measure the
offset error of the DAC7611. This can easily be done as
shown in Figure 5. The resistor between VOUT and a negative voltage provides the output amplifier some ability to
swing below ground.
As with the GND connection, VDD should be connected to
a +5V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the
power entry point. In addition, the 10µF and 0.1µF capacitors shown in Figure 4 are strongly recommended and
should be installed as close to VDD and ground as possible.
In some situations, additional bypassing may be required
such as a 100µF electrolytic capacitor or even a “Pi” filter
made up of inductors and capacitors—all designed to essentially lowpass filter the +5V supply, removing the high
frequency noise (see Figure 4).
Digital Circuits
+5V
Power
Supply
+5V
+5V
GND
DAC7611
GND
+
100µF
+
VDD
0.1µF
10µF
GND
Optional
Other
Analog
Components
FIGURE 4. Suggested Power and Ground Connections for a DAC7611 Sharing a +5V Supply with a Digital System.
+5V
DAC7611
10µF
+
1
VDD
VOUT
8
2
CS
GND
7
3
CLK
CLR
6
4
SDI
LD
5
0.1µF
i ≤ 200µA
R
–V
FIGURE 5. Offset Error Measurement Circuit.
®
DAC7611
12
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
DAC7611P
NRND
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
DAC7611PB
NRND
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
DAC7611PBG4
NRND
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
DAC7611PG4
NRND
PDIP
P
8
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
DAC7611U
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7611U/2K5
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7611U/2K5G4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7611UB
ACTIVE
SOIC
D
8
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7611UB/2K5
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7611UB/2K5G4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7611UBG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
DAC7611UG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
75
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jul-2009
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DAC7611U/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
DAC7611UB/2K5
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC7611U/2K5
SOIC
D
8
2500
346.0
346.0
29.0
DAC7611UB/2K5
SOIC
D
8
2500
346.0
346.0
29.0
Pack Materials-Page 2
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