DAC7678SRGET

DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 12-Bit, Octal-Channel, Ultra-Low Glitch, Voltage Output, Two-Wire Interface Digital-to-Analog Converter with 2.5V Internal Reference Check for Samples: DAC7678 FEATURES APPLICATIONS • • • • • • • 1 23 • • • • • • • • Relative Accuracy: – 1 LSB INL Glitch Energy: 0.15nV-s Internal Reference: – 2.5V Reference Voltage (disabled by default) – ±5mV Initial Accuracy (max) – 5ppm/°C Temperature Drift (typ) – 25ppm/°C Temperature Drift (max) – 20mA Sink/Source Capability Power-On Reset to Zero Scale or Midscale – Devices in the TSSOP Package Reset to Zero Scale – Devices in the QFN Package Reset to Zero Scale or Midscale Ultra-Low Power Operation: 0.13mA/Channel at 5V (without internal reference current) Wide Power-Supply Range: +2.7V to +5.5V 2-Wire Serial Interface ( I2C™ compatible) On-Chip Output Buffer Amplifier with Rail-toRail Operation Temperature Range: –40°C to +125°C AVDD VREFIN/VREFOUT DAC7678 SCL 2.5V Reference Input Control Logic Data Buffer H DAC Register H 12-Bit DAC VOUTH Data Buffer G DAC Register G 12-Bit DAC VOUTG Data Buffer F DAC Register F 12-Bit DAC VOUTF Data Buffer E DAC Register E 12-Bit DAC VOUTE Data Buffer D DAC Register D 12-Bit DAC VOUTD Data Buffer C DAC Register C 12-Bit DAC VOUTC Data Buffer B DAC Register B 12-Bit DAC VOUTB Data Buffer A DAC Register A 12-Bit DAC VOUTA Buffer Control Register Control Power-Down Control Logic SDA Control Logic ADDR0 ADDR1 LDAC RSTSEL CLR Portable Instrumentation Closed-Loop Servo-Control Process Control Data Acquisition Systems Programmable Attenuation PC Peripherals DESCRIPTION The DAC7678 is a low-power, voltage-output, octal channel, 12-bit digital-to-analog converter (DAC). The DAC7678 includes a 2.5V internal reference (disabled by default), giving a full-scale output voltage range of 5V. The internal reference has an initial accuracy of ±5mV and can source up to 20mA at the VREFIN/VREFOUT pin. The device is monotonic, provides very good linearity, and minimizes undesired code-to-code transient voltages (glitch). The DAC7678 uses a versatile, 2-wire serial interface that is I2C-compatible and operates at clock rates of up to 3.4MHz. Multiple devices can share the same bus. The DAC7678 incorporates a power-on-reset circuit that ensures the DAC output powers up to either zero-scale or mid-scale until a valid code is written to the device. These devices contain a power-down feature, accessed over the serial interface that reduces the current consumption of the device to typically 0.42μA at 5V. Power consumption (including internal reference) is typically 3.56mW at 3V, reducing to 0.68μW in power-down mode. The low power consumption, internal reference, and small footprint make this device ideal for portable, batteryoperated equipment. The DAC7678 is drop-in and functionally compatible with DAC5578, DAC6578, and DAC7578. All devices are available in a 4x4 QFN-24 package and a TSSOP-16 package. RELATED DEVICES 8-BIT 10-BIT 12-BIT Pin- and Function-Compatible (w/internal reference) — — DAC7678 Pin- and Function-Compatible DAC5578 DAC6578 DAC7578 GND 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. 2 2 3 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010–2014, Texas Instruments Incorporated DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT MAXIMUM RELATIVE ACCURACY (LSB) MAXIMUM DIFFERENTIAL NONLINEARITY (LSB) MAXIMUM REFERENCE DRIFT (ppm/°C) DAC7678 ±1 ±0.25 25 (1) PACKAGELEAD PACKAGE DESIGNATOR TSSOP-16 PW QFN-24 RGE SPECIFIED TEMPERATURE RANGE PACKAGE MARKING –40°C to +125°C DAC7678 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. DAC7678 UNIT –0.3 to +6 V Digital input voltage to GND –0.3 to +AVDD + 0.3 V VOUT to GND –0.3 to +AVDD + 0.3 V VREFIN/VREFOUT to GND AVDD to GND –0.3 to +AVDD + 0.3 V Operating temperature range –40 to +125 °C Storage temperature range –65 to +150 °C +150 °C (TJ max – TA)/θJA W Junction temperature range (TJ max) Power dissipation (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. THERMAL INFORMATION THERMAL METRIC (1) DAC7678 PW (16 PINS) RGE (24 PINS) θJA Junction-to-ambient thermal resistance 111.9 33.7 θJCtop Junction-to-case (top) thermal resistance 33.3 16.9 θJB Junction-to-board thermal resistance 52.4 7.4 ψJT Junction-to-top characterization parameter 2 0.5 ψJB Junction-to-board characterization parameter 51.2 7.1 θJCbot Junction-to-case (bottom) thermal resistance n/a 1.7 (1) 2 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 ELECTRICAL CHARACTERISTICS At AVDD = 2.7V to 5.5V, External Reference Used, and over –40°C to +125°C, unless otherwise noted. PARAMETER TEST CONDITIONS DAC7678 MIN TYP MAX UNIT STATIC PERFORMANCE (1) Resolution 12 Bits Relative accuracy Measured by the line passing through codes 30 and 4050 ±0.3 ±1 LSB Differential nonlinearity 12-bit monotonic ±0.1 ±0.25 LSB Offset error Extrapolated from two-point line (2), unloaded 0.5 ±4 Offset error drift Full-scale error DAC register loaded with all '1's ±0.03 Full-scale error drift Zero-code error ±0.2 % of FSR μV/°C 2 DAC register loaded with all '0's 1 Zero-code error drift Gain error mV μV/°C 3 4 mV μV/°C 2 Extrapolated from two-point line (2), unloaded ±0.01 Gain temperature coefficient ±0.15 % of FSR ppm of FSR/°C ±1 OUTPUT CHARACTERISTICS (3) Output voltage range Output voltage settling time 0 DACs unloaded, 1/4 scale to 3/4 scale RL = 1MΩ, CL = 470 pF Slew rate Capacitive load stability RL = ∞ AVDD V μs 7 μs 12 0.75 V/μs 470 pF RL = 2kΩ 1000 pF Code change glitch impulse 1LSB change around major carry 0.15 nV-s Digital feedthrough SCL toggling 1.5 nV-s Power-on glitch RL = ∞ Channel-to-channel dc crosstalk 3 mV Full-scale swing on adjacent channel 0.1 LSB DC output impedance At midscale input 4.5 Ω Short-circuit current DAC outputs shorted to GND 25 mA Power-up time (including settling time) Coming out of power-down mode, AVDD = 5V 50 μs DAC output noise density TA = +25°C, at zero-code input, fOUT = 1kHz 20 nV/√Hz DAC output noise TA = +25°C, at midscale input, 0.1Hz to 10Hz (external reference used) 3 μVPP AC PERFORMANCE (3) (1) (2) (3) Linearity calculated using a reduced code range; output unloaded. 12-bit: 30 and 4050 Specified by design or characterization; not production tested. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 3 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At AVDD = 2.7V to 5.5V, External Reference Used, and over –40°C to +125°C, unless otherwise noted. PARAMETER DAC7678 TEST CONDITIONS MIN TYP MAX UNIT INTERNAL REFERENCE Output voltage TA = +25°C 2.495 2.5 2.505 Initial accuracy TA = +25°C –5 ±0.1 5 mV 5 25 ppm/°C Output voltage temperature drift (4) Output voltage noise TA = +25°C, f = 0.1Hz to 10Hz 15 Output voltage noise density (high-frequency noise) TA = +25°C, f = 1kHz, CL = 0μF 250 TA = +25°C, f = 1MHz, CL = 0μF 50 Load regulation (5) Output current load capability Thermal hysteresis (5) Internal reference current consumption External reference current 500 μV/mA 200 μV/mA ±20 mA 80 μV/V TA = +25°C, time = 0 to 2160 hours 100 ppm First cycle 200 ppm 50 ppm AVDD = 5.5V 420 μA AVDD = 3.6V 400 μA 60 μA Additional cycles External VREF = 2.5V (when internal reference is disabled), all eight channels active VREFIN/VREFOUT pin reference input range Reference input impedance nV/√Hz Sinking, TA = +25°C TA = +25°C Long-term stability/drift (aging) (5) μVPP Sourcing, TA = +25°C (4) Line regulation V 0 Reference disabled AVDD 42 V kΩ LOGIC INPUTS (4) Input current μA ±1 VINL Logic input LOW voltage 2.7V ≤ AVDD ≤ 5.5V GND–0.3 0.3×AVDD VINH Logic input HIGH voltage 2.7V ≤ AVDD ≤ 5.5V 0.7×AVDD AVDD+0.3 V 3 pF Pin capacitance 1.5 V POWER REQUIREMENTS AVDD IDD 2.7 (6) 5.5 V Normal mode, internal reference switched off AVDD = 3.6V to 5.5V, VINH = AVDD and VINL = GND 1.02 1.4 mA AVDD = 2.7V to 3.6V, VINH = AVDD and VINL = GND 0.86 1.3 mA Normal mode, internal reference switched on AVDD = 3.6V to 5.5V, VINH = AVDD and VINL = GND 1.49 2.2 mA AVDD = 2.7V to 3.6V, VINH = AVDD and VINL = GND 1.32 2 mA AVDD = 3.6V to 5.5V, VINH = AVDD and VINL = GND 0.42 6 μA AVDD = 2.7V to 3.6V, VINH = AVDD and VINL = GND 0.25 4.7 μA Normal mode, internal reference switched off AVDD = 3.6V to 5.5V, VINH = AVDD and VINL = GND 3.67 7.7 mW AVDD = 2.7V to 3.6V, VINH = AVDD and VINL = GND 2.32 4.68 mW Normal mode, internal reference switched on AVDD = 3.6V to 5.5V, VINH = AVDD and VINL = GND 5.36 12.1 mW AVDD = 2.7V to 3.6V, VINH = AVDD and VINL = GND 3.56 7.2 mW AVDD = 3.6V to 5.5V, VINH = AVDD and VINL = GND 1.51 33 μW AVDD = 2.7V to 3.6V, VINH = AVDD and VINL = GND 0.68 16.92 μW +125 °C All power-down modes Power dissipation (6) All power-down modes TEMPERATURE RANGE Specified performance (4) (5) (6) 4 –40 Specified by design or characterization; not production tested. Explained in more detail in the Application Information section of this data sheet. Input code = midscale, no load. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 PIN CONFIGURATIONS PW PACKAGE TSSOP-16 (TOP VIEW) 2 15 SDA AVDD 3 14 GND VOUTA 4 13 VOUTB VOUTC 5 12 VOUTE 6 11 20 19 NC 1 18 2 17 GND VOUTD VOUTA 3 16 VOUTB VOUTF VOUTC 4 15 VOUTD VOUTE 5 14 VOUTF VOUTG 6 13 VOUTH VOUTH DAC7678 (Thermal pad) 1 NC (1) 8 9 10 11 12 CLR NC 7 ADDR1 CLR ADDR0 9 21 RSTSEL 8 10 22 VREFIN/VREFOUT VREFIN/VREFOUT 7 23 AVDD DAC7678 VOUTG 24 SDA ADDR0 TWOC SCL SCL 16 NC 1 LDAC LDAC NC RGE PACKAGE QFN-24 (TOP VIEW) It is recommended to connect the thermal pad to GND for better thermal dissipation. PIN DESCRIPTIONS 16-PIN 24-PIN NAME 1 22 LDAC DESCRIPTION 2 11 ADDR0 3 2 AVDD Power-supply input, 2.7V to 5.5V 4 3 VOUTA Analog output voltage from DAC A 5 4 VOUTC Analog output voltage from DAC C 6 5 VOUTE Analog output voltage from DAC E 7 6 VOUTG Analog output voltage from DAC G 8 8 VREFIN/ VREFOUT Load DACs. Three-state address input 0 Positive reference input or reference output of 2.5V, if internal reference used. 9 12 CLR 10 13 VOUTH Asynchronous clear input Analog output voltage from DAC H 11 14 VOUTF Analog output voltage from DAC F 12 15 VOUTD Analog output voltage from DAC D 13 16 VOUTB Analog output voltage from DAC B 14 17 GND Ground reference point for all circuitry on the device 15 19 SDA Serial data input. Data are clocked into or out of the input register. This pin is a bidirectional, opendrain data line that should be connected to the supply voltage with an external pull-up resistor. 16 20 SCL Serial clock input. Data can be transferred at rates up to 3.4MHz. Schmitt-trigger logic input. — 1 NC Not internally connected. — 7 NC Not internally connected. — 9 RSTSEL Reset select pin. RSTSEL high resets device to mid-scale; RSTSEL low resets device to zero-scale. — 10 ADDR1 Three-state address input 1 — 18 NC — 21 TWOC — 23 NC Not internally connected. — 24 NC Not internally connected. Not internally connected. Twos complement select. If the TWOC pin is pulled high, the DAC registers use twos complement format; if TWOC is pulled low, the DAC registers use straight binary format. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 5 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com TIMING DIAGRAM tLOW Low Byte Ack Cycle tR tHD:STA tF SCL tHD:STA tHIGH tSU:STA tSU:STO tSU:DAT tHD:DAT SDA tBUF P S S P t1 LDAC1 t3 t2 LDAC2 t4 CLR (1) Asynchronous LDAC update mode. For more information and details, see the LDAC Functionality section (2) Synchronous LDAC update mode. For more information and details, see the LDAC Functionality section Figure 1. Serial Write Operation TIMING REQUIREMENTS At AVDD = 2.7 V to 5.5 V and –40°C to +125°C range (unless otherwise noted). STANDARD MODE PARAMETER MIN MAX SCL frequency, fSCL FAST MODE MIN 0.1 Bus free time between STOP and START conditions, tBUF MAX MIN 0.4 4.7 1.3 Hold time after repeated start, tHDSTA HIGH SPEED MODE UNIT MAX 3.4 MHz µs 4 0.6 0.16 µs 4.7 0.6 0.16 µs STOP condition setup time, tSUSTO 4 0.6 0.16 µs Data hold time, tHDDAT 0 0 0 ns Repeated Start setup time, tSUSTA Data setup time, tSUDAT 250 100 10 ns SCL clock LOW period, tLOW 4700 1300 160 ns SCL clock HIGH period, tHIGH 4000 600 60 ns Clock/Data fall time, tF 300 300 160 Clock/Data rise time, tR 1000 300 160 LDAC pulse width LOW time, t1 40 10 ns ns 1.2 µs SCL falling edge to LDAC falling edge for asynchronous LDAC update, t2 20 5 0.6 µs LDAC falling edge to SCL falling edge for synchronous LDAC update, t3 360 90 10.5 µs 40 10 1.2 µs CLR pulse width LOW time, t4 6 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS: INTERNAL REFERENCE At TA = 25°C, unless otherwise noted INTERNAL REFERENCE VOLTAGE vs TEMPERATURE LONG-TERM STABILITY DRIFT 2.505 22 Devices Shown 2.503 150 2.502 100 2.501 50 2.500 2.499 0 -50 2.498 -100 2.497 -150 2.496 -200 2.495 -40 -25 -10 5 19 Devices Shown 200 Drift - ppm Reference Voltage - V 2.504 250 20 35 50 65 T - Temperature - °C 80 95 110 -250 125 0 240 480 Figure 2. 720 960 1200 1440 t - Time - Hours 1680 1920 2160 Figure 3. INTERNAL REFERENCE VOLTAGE vs SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs LOAD CURRENT 2.505 2.515 2.504 2.510 TA = 125°C Reference Voltage - V Reference Voltage - V 2.503 2.502 TA = 25°C 2.501 2.500 TA = -40°C 2.499 2.498 TA = 125°C TA = 25°C 2.505 TA = -40°C 2.500 2.495 2.497 2.496 2.495 2.7 3.1 3.5 4.3 3.9 Supply Voltage - V 4.7 5.1 5.5 2.490 -20 -15 -10 -5 0 5 Load Current - mA 10 Figure 4. Figure 5. INTERNAL REFERENCE NOISE DENSITY vs FREQUENCY INTERNAL REFERENCE NOISE 0.1 Hz to 10 Hz 15 20 350 Reference Unbuffered CREF = 0 mF 300 Vnoise - 5 mV/div Voltage Noise - nV/ÖHz 250 200 150 - 15 mV Peak-to-peak 100 50 0 10 100 1000 f - Frequency - Hz 10000 100000 Figure 6. t - Time - 2s/div Figure 7. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 7 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 channels) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 channels) 0.25 1.0 All Eight Channels Shown, AVDD = 5.5 V, Internal Reference = 2.5 V 0.6 0.15 0.4 0.10 0.2 0.0 -0.2 -0.4 -0.8 CHB CHF CHD CHH 0.00 -0.05 -0.15 0 1.00 512 1024 1536 2048 2560 Digital Input Code 3072 3584 DNL CHA DNL CHB DNL CHC DNL CHD -0.20 -1.0 -0.25 4096 0 512 1536 2048 2560 Digital Input Code 3072 3584 Figure 9. LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (–40°C) 4096 0.25 0.60 AVDD = 5.5 V, 0.20 Internal Reference = 2.5 V, Typical Channel Shown 0.15 0.40 0.10 DNL - Error - LSB 0.20 0.00 -0.20 0.05 0.00 -0.05 -0.40 -0.10 -0.60 -0.15 -0.80 -0.20 -1.00 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 -0.25 4096 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 Figure 10. Figure 11. LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE(+25°C) 4096 0.25 1.00 AVDD = 5.5 V, Internal Reference = 2.5 V, Typical Channel Shown 0.80 0.60 0.20 0.15 AVDD = 5.5 V, Internal Reference = 2.5 V, Typical Channel Shown 0.10 DNL - Error - LSB 0.40 0.20 0.00 -0.20 0.05 0.00 -0.05 -0.40 -0.10 -0.60 -0.15 -0.80 -0.20 -1.00 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 4096 -0.25 0 Figure 12. 8 1024 DNL CHE DNL CHF DNLCHG DNLCHH Figure 8. AVDD = 5.5 V, Internal Reference = 2.5 V, Typical Channel Shown 0.80 INL - Error - LSB 0.05 -0.10 CHA CHE CHC CHG -0.6 INL - Error - LSB All Eight Channels Shown AVDD = 5.5 V, Internal Reference = 2.5 V 0.20 DNL - Error - LSB INL - Error - LSB 0.8 512 1024 1536 2048 2560 Digital Input Code 3072 3584 4096 Figure 13. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted LINEARITY ERROR vs DIGITAL INPUT CODE (+125°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+125°C) 0.25 1.00 AVDD = 5.5 V, 0.80 Internal Reference = 2.5 V, Typical Channel Shown 0.60 0.15 0.10 DNL - Error - LSB INL - Error - LSB 0.40 0.20 0.00 -0.20 0.05 0.00 -0.05 -0.40 -0.10 -0.60 -0.15 -0.80 -0.20 -1.00 0 AVDD = 5.5 V, Internal Reference = 2.5 V, Typical Channel Shown 0.20 512 1024 1536 2048 2560 Digital Input Code 3072 3584 -0.25 4096 0 512 1024 1536 2048 2560 Digital Input Code Figure 14. LINEARITY ERROR vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE AVDD = 5.5 V, Internal Reference = 2.5 V AVDD = 5.5 V, Internal Reference = 2.5 V 0.20 0.15 INL MAX 0.10 DNL - Error - LSB 0.40 INL - Error - LSB 4096 0.25 0.60 0.20 0.00 INL MIN -0.20 DNL MAX 0.05 0.00 -0.10 -0.60 -0.15 -0.80 -0.20 -25 -10 5 20 35 50 65 T - Temperature -°C 80 95 110 125 DNL MIN -0.05 -0.40 -1.00 -40 3584 Figure 15. 1.00 0.80 3072 -0.25 -40 -25 5 -10 20 35 50 65 T - Temperature -°C 80 Figure 16. Figure 17. POWER SUPPLY CURRENT vs TEMPERATURE OFFSET ERROR vs TEMPERATURE 95 110 125 4 1.40 AVDD = 5.5 V, External Reference = 5 V 3 AVDD = 5.5 V, Internal Reference = 2.5 V 2 1.20 Offset Error - mV Power-Supply Current - mA 1.30 1.10 1.00 1 0 -1 -2 0.90 -3 0.80 -40 -25 -10 5 20 35 50 65 T - Temperature -°C 80 95 110 125 -4 -40 -25 Figure 18. -10 5 20 35 50 65 T - Temperature -°C 80 Ch A Ch C Ch E Ch G Ch B Ch D Ch F Ch H 95 110 125 Figure 19. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 9 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted POWER SUPPLY CURRENT vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 0.20 2.20 AVDD = 5.5 V, Internal Reference = 2.5 V 0.15 2.00 AVDD = 5.5 V, Internal Reference = 2.5 V 0.10 Full Scale Error - %FSR Power Supply Current - mA 2.10 1.90 1.80 1.70 1.60 1.50 0.05 0.00 -0.05 -0.10 DAC A DAC C DAC E DAC G -0.15 1.40 1.30 -40 -25 -10 5 20 35 50 65 T - Temperature -°C 80 95 110 -0.20 -40 125 -25 -10 5 20 35 50 65 T - Temperature -°C Figure 20. POWER-DOWN CURRENT vs TEMPERATURE 110 125 GAIN ERROR vs TEMPERATURE 0.15 AVDD = 5.5 V, Internal Reference = 2.5 V 5.50 AVDD = 5.5 V, Internal Reference = 2.5 V 5.00 0.10 4.50 Gain Error - %FSR 4.00 3.50 3.00 2.50 2.00 0.05 0.00 -0.05 1.50 1.00 DAC A DAC C DAC E DAC G -0.10 0.50 0.00 -40 -25 -10 5 20 35 50 65 T - Temperature -°C 80 95 110 -0.15 -40 125 -25 -10 5 20 35 50 65 T - Temperature -°C 80 Figure 22. Figure 23. SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 5.00 DAC B DAC D DAC F DAC H 95 110 125 0.60 Channel C 0.50 AVDD = 5.5 V, Internal Reference Enabled, DAC Loaded with 000h Channel C Output Voltage - V 4.95 Output Voltage - V 95 Figure 21. 6.00 Power Supply Current - mA 80 DAC B DAC D DAC F DAC H 4.90 0.40 0.30 0.20 4.85 AVDD = 5.5 V, Internal Reference Enabled, DAC Loaded with FFFh 0.10 4.80 0 2 4 6 8 10 0.00 0 ISOURCE - mA Figure 24. 10 1 2 3 4 5 6 Isink - mA 7 8 9 10 Figure 25. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 5.00 0.60 Channel D 0.50 AVDD = 5.5 V, Internal Reference Enabled, DAC Loaded with 000h Channel D Output Voltage - V Output Voltage - V 4.95 4.90 0.40 0.30 0.20 4.85 AVDD = 5.5 V, Internal Reference Enabled, DAC Loaded with FFFh 4.80 0 1 2 3 4 5 6 ISOURCE - mA 7 8 9 0.10 0.00 0 10 1 2 3 4 5 6 ISINK - mA 7 Figure 26. Figure 27. SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 5.00 9 10 9 10 0.60 Channel H 0.50 AVDD = 5.5 V, Internal Reference Enabled, DAC Loaded with 000h Channel H Output Voltage - V 4.95 Output Voltage - V 8 4.90 0.40 0.30 0.20 4.85 AVDD = 5.5 V, Internal Reference Enabled, DAC Loaded with FFFh 4.80 0 1 2 3 4 5 6 ISOURCE - mA 7 8 9 0.10 0.00 0 10 1 2 3 4 5 6 ISINK - mA 7 8 Figure 28. Figure 29. POWER SUPPLY CURRENT vs DIGITAL INPUT CODE POWER SUPPLY CURRENT vs DIGITAL INPUT CODE 2.20 1.40 2.10 1.20 Power Supply Current - mA Power Supply Current - mA 2.00 1.90 1.80 1.70 1.60 1.50 1.40 AVDD = 5.5 V, Internal Reference Enabled, Code Loaded to all Eight DAC Channels 1.30 1.20 1.10 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 1.00 0.80 0.60 0.40 AVDD = 5.5 V, External Reference = 5 V, Internal Reference Disabled, Code Loaded to all Eight DAC Channels 0.20 4096 0.00 0 Figure 30. 512 1024 1536 2048 2560 Digital Input Code 3072 3584 4096 Figure 31. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 11 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted POWER SUPPLY CURRENT vs POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT vs POWER SUPPLY VOLTAGE 2.20 1.40 AVDD = 2.7 V to 5.5 V, Internal Reference Enabled AVDD = 2.7 V to 5.5 V, Internal Reference Disabled 1.30 Power Supply Current - mA Power Supply Current - mA 2.00 1.80 1.60 1.40 1.20 1.10 1.00 0.90 0.80 1.20 0.70 1.00 2.7 3.1 3.5 4.3 4.7 3.9 AVDD - Supply Voltage - V 5.1 0.60 2.7 5.5 3.5 3.9 4.3 4.7 AVDD - Supply Voltage - V Figure 32. Figure 33. POWER DOWN CURRENT vs POWER SUPPLY VOLTAGE POWER-SUPPLY CURRENT HISTOGRAM 0.45 5.1 5.5 16 AVDD = 2.7 V to 5.5 V 0.40 14 0.35 0.25 0.20 0.15 10 8 6 0.10 4 0.05 2 1.70 1.66 1.68 1.60 1.62 1.64 1.56 1.58 1.52 1.54 5.5 1.48 1.50 5.1 1.44 1.46 4.7 1.38 4.3 1.40 1.42 3.9 AVDD - Supply Voltage - V 1.34 1.36 3.5 1.30 0 3.1 1.32 0.00 2.7 AVDD = 5.5 V, Internal Reference = 2.5 V 12 0.30 % of Population Power Supply Current - mA 3.1 IDD - Supply Current - mA Figure 34. Figure 35. POWER-SUPPLY CURRENT HISTOGRAM 14 AVDD = 5.5 V, 12 External Reference = 5 V % of Population 10 8 6 4 2 0.90 0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 1.12 1.13 1.14 1.15 0 IDD - Supply Current - mA Figure 36. 12 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted FULL-SCALE SETTLING TIME: 5V RISING EDGE FULL-SCALE SETTLING TIME: 5V FALLING EDGE AVDD = 5.5 V, From Code FFFh to 000h Internal Reference Enabled Zoomed Rising Edge 100 mV/div Zoomed Falling Edge 100 mV/div Falling Edge 2 V/div Rising Edge 2 V/div Trigger Pulse 5 V/div AVDD = 5.5 V, From Code 000h to FFFh, Internal Reference Enabled Trigger Pulse 5 V/div t - Time - 5 ms/div t - Time - 5 ms/div Figure 37. Figure 38. HALF-SCALE SETTLING TIME: 5V RISING EDGE HALF-SCALE SETTLING TIME: 5V FALLING EDGE AVDD = 5.5 V, From Code 400h to C00h Internal Reference Enabled AVDD = 5.5 V, From Code C00h to 400h Internal Reference Enabled Zoomed Rising Edge 100 mV/div Zoomed Falling Edge 100 mV/div Falling Edge 2 V/div Rising Edge 2 V/div Trigger Pulse 5 V/div Trigger Pulse 5 V/div t - Time - 5 ms/div t - Time - 5 ms/div Figure 39. Figure 40. CLOCK FEEDTHROUGH 400 kHz, MIDSCALE POWER-ON GLITCH RESET TO ZERO SCALE AVDD = 5.5 V, Clock Feedthrough Impulse ~1.5 nV-s Internal Reference Enabled AVDD = 5.5 V, DAC Unloaded, DAC at Zero Scale VOUT - 2 mV/div VOUT - 5 mV/div SCL - 5 V/div ~2 mVPP AVDD - 2 V/div t - Time - 10 ms/div t - Time - 1 ms/div Figure 41. Figure 42. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 13 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted POWER-ON GLITCH RESET-TO-MID SCALE POWER-OFF GLITCH AVDD = 5.5 V, DAC Unloaded, DAC at Zero Scale AVDD = 5.5 V, DAC Unloaded, DAC at Zero Scale VOUT - 2 V/div VOUT - 1 mV/div AVDD - 2 V/div AVDD - 2 V/div t - Time - 20 ms/div t - Time - 10 ms/div Figure 43. Figure 44. GLITCH ENERGY: 5V 1LSB STEP, RISING EDGE GLITCH ENERGY: 5V 1LSB STEP, FALLING EDGE AVDD = 5.5 V, From Code 800h to 801h VOUT - 500 mV/div AVDD = 5.5 V, From Code 801h to 800h LDAC Clock Feed-Through VOUT - 500 mV/div LDAC Clock Feed-Through LDAC - Trigger Pulse 5 V/div LDAC - Trigger Pulse 5 V/div t - Time - 2 ms/div t - Time - 2 ms/div Figure 45. Figure 46. DAC OUTPUT NOISE DENSITY vs FREQUENCY INTERNAL REFERENCE ENABLED DAC OUTPUT NOISE DENSITY vs FREQUENCY INTERNAL REFERENCE DISABLED 800 300 AVDD = 5.5 V, DAC Output Unloaded, Internal Reference = 2.5 V 700 Voltage Noise - nV/Ö Hz Full Scale 600 Voltage Noise - nV/ÖHz AVDD = 5.5 V, DAC Output Unloaded, External Reference = 5 V 250 500 400 Mid Scale 300 200 200 150 Full Scale 100 Mid Scale 50 100 0 20 Zero Scale Zero Scale 100 1000 10000 f - Frequency - Hz 100000 0 20 Figure 47. 14 100 1000 f - Frequency - Hz 10000 100000 Figure 48. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS: DAC at AVDD = 5.5 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted VOUT - 1 mV/div DAC OUTPUT NOISE 0.1 Hz to 10 Hz ~3 mVPP t - Time - 2 s/div Figure 49. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 15 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS: DAC AT AVDD = 3.6 V At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted POWER SUPPLY CURRENT vs TEMPERATURE POWER SUPPLY CURRENT vs DIGITAL INPUT CODE 1.30 1.30 1.20 1.10 Power Supply Current - mA Power Supply Current - mA 1.20 AVDD = 3.6 V, External Reference = 3.3 V 1.10 1.00 0.90 0.80 1.00 0.90 0.80 0.70 0.60 0.50 0.40 AVDD = 3.6 V, External Reference = 3.3 V, Internal Reference Disabled, Code Loaded to all Eight DAC Channels 0.30 0.20 0.10 0.70 -40 -25 -10 5 20 35 50 65 T - Temperature -°C 80 95 110 0.00 125 0 512 1024 Figure 50. 1536 2048 2560 Digital Input Code 3072 3584 4096 Figure 51. POWER SUPPLY CURRENT HISTOGRAM 14 AVDD = 3.6 V, External Reference = 3.3 V 12 % of Population 10 8 6 4 0 0.765 0.775 0.785 0.795 0.805 0.815 0.825 0.835 0.845 0.855 0.865 0.875 0.885 0.895 0.905 0.915 0.925 0.935 0.945 0.955 0.965 0.975 2 IDD - Supply Current - mA Figure 52. 16 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 Channels) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (All 8 Channels) 1.00 0.25 AVDD = 2.7 V, External Reference = 2.5 V AVDD = 2.7 V, External Reference = 2.5 V 0.20 0.60 0.15 0.40 0.10 DNL - Error - LSB INL - Error - LSB 0.80 0.20 0.00 -0.20 0.05 0.00 -0.05 -0.10 -0.40 -0.60 CHA CHB CHC CHD -0.80 -1.00 0 -0.15 CHE CHF CHG CHH DNL CHA DNL CHB DNL CHC DNL CHD -0.20 -0.25 512 1024 1536 2048 2560 Digital Input Code 3072 3584 0 4096 512 1024 1536 2048 2560 Digital Input Code Figure 53. 3584 4096 DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (-40°C) 1.00 0.25 AVDD = 2.7 V, 0.80 External Reference = 2.5 V AVDD = 2.7 V, 0.20 External Reference = 2.5 V 0.60 0.15 0.40 0.10 DNL - Error - LSB INL - Error - LSB 3072 Figure 54. LINEARITY ERROR vs DIGITAL INPUT CODE (-40°C) 0.20 0.00 -0.20 0.05 0.00 -0.05 -0.40 -0.10 -0.60 -0.15 -0.80 -0.20 -0.25 -1.00 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 0 4096 1536 2048 2560 Digital Input Code 3072 3584 LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+25°C) 0.25 AVDD = 2.7 V, 0.80 External Reference = 2.5 V 0.20 0.60 0.15 0.40 0.10 0.20 0.00 -0.20 0.00 -0.60 -0.15 -0.80 -0.20 1024 1536 2048 2560 Digital Input Code 3072 3584 4096 AVDD = 2.7 V, External Reference = 2.5 V -0.05 -0.10 -1.00 4096 0.05 -0.40 512 1024 Figure 56. 1.00 0 512 Figure 55. DNL - Error - LSB INL - Error - LSB DNL CHE DNL CHF DNL CHG DNL CHH -0.25 0 Figure 57. 512 1024 1536 2048 2560 Digital Input Code 3072 3584 4096 Figure 58. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 17 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE (+125°C) 1.00 0.25 AVDD = 2.7 V, 0.80 External Reference = 2.5 V 0.20 0.60 0.15 0.40 0.10 DNL - Error - LSB INL - Error - LSB LINEARITY ERROR vs DIGITAL INPUT CODE (+125°C) 0.20 0.00 -0.20 0.05 0.00 -0.05 -0.40 -0.10 -0.60 -0.15 -0.80 -0.20 -1.00 AVDD = 2.7 V, External Reference = 2.5 V -0.25 0 512 1024 1536 2048 2560 Digital Input Code 3072 3584 4096 0 512 1024 1536 2048 2560 Digital Input Code Figure 59. LINEARITY ERROR vs TEMPERATURE DIFFERENTIAL LINEARITY ERROR vs TEMPERATURE AVDD = 2.7 V, External Reference = 2.5 V 0.15 INL MAX 0.20 0.00 INL MIN -0.20 0.05 0.00 -0.10 -0.60 -0.15 -0.80 -0.20 -10 5 20 35 50 65 T - Temperature -°C 80 95 110 125 DNL MIN -0.05 -0.40 -25 DNL MAX 0.10 DNL - Error - LSB INL - Error - LSB AVDD = 2.7 V, External Reference = 2.5 V 0.20 0.40 -0.25 -40 -25 -10 5 20 35 50 65 T - Temperature -°C Figure 61. 95 110 125 OFFSET ERROR vs TEMPERATURE 1.30 4 AVDD = 2.7 V, 1.20 External Reference = 2.5 V 3 AVDD = 2.7 V, External Reference = 2.5 V 2 1.10 Offset Error - mV Power-Supply Current - mA 80 Figure 62. POWER-SUPPLY CURRENT vs TEMPERATURE 1.00 0.90 1 0 -1 0.80 -2 0.70 0.60 -40 DAC A DAC C DAC E DAC G -3 -25 -10 5 20 35 50 65 T - Temperature -°C 80 95 110 125 -4 -40 -25 Figure 63. 18 4096 0.25 0.60 -1.00 -40 3584 Figure 60. 1.00 0.80 3072 -10 5 20 35 50 65 T - Temperature -°C 80 DAC B DAC D DAC F DAC H 95 110 125 Figure 64. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted POWER-DOWN CURRENT vs TEMPERATURE FULL-SCALE ERROR vs TEMPERATURE 0.20 AVDD = 2.7 V, 4.20 External Reference = 2.5 V 3.90 3.60 AVDD = 2.7 V, External Reference = 2.5 V 0.15 0.10 Full-Scale Error - %FSR Power Supply Current - mA 4.70 4.50 3.30 3.00 2.70 2.40 2.10 1.80 1.50 1.20 0.05 0.00 -0.05 -0.10 DAC A DAC C DAC E DAC G 0.90 0.60 0.30 0.00 -40 -0.15 -25 -10 5 20 35 50 65 T - Temperature -°C 80 95 110 -0.20 -40 125 -25 -10 5 20 35 50 65 T - Temperature -°C Figure 65. 80 95 DAC B DAC D DAC F DAC H 110 125 9 10 Figure 66. GAIN ERROR vs TEMPERATURE 0.15 AVDD = 2.7 V, External Reference = 2.5 V Gain Error - %FSR 0.10 0.05 0.00 -0.05 DAC A DAC C DAC E DAC G -0.10 -0.15 -40 -25 -10 5 20 35 50 65 T - Temperature -°C 80 95 DAC B DAC D DAC F DAC H 110 125 Figure 67. SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 2.500 0.60 AVDD = 2.7 V, External Reference = 2.5 V, DAC Loaded with FFFh 2.495 Channel A 2.490 AVDD = 2.7 V, External Reference = 2.5 V, DAC Loaded with 000h 0.50 Channel A Output Voltage - V Output Voltage - V 2.485 2.480 2.475 2.470 2.465 0.40 0.30 0.20 2.460 2.455 0.10 2.450 2.445 0.00 0 1 2 3 4 5 6 ISOURCE - mA 7 8 9 10 0 Figure 68. 1 2 3 4 5 6 ISINK - mA 7 8 Figure 69. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 19 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 2.500 0.60 AVDD = 2.7 V, External Reference = 2.5 V, DAC Loaded with FFFh 2.495 Channel B AVDD = 2.7 V, External Reference = 2.5 V, DAC Loaded with 000h 0.50 2.490 Channel B Output Voltage - V Output Voltage - V 2.485 2.480 2.475 2.470 0.40 0.30 0.20 2.465 2.460 0.10 2.455 2.450 0 0.00 1 2 3 4 5 6 ISOURCE - mA 7 8 9 0 10 1 2 3 4 Figure 70. 5 6 ISINK - mA 7 8 9 10 9 10 Figure 71. SOURCE CURRENT AT POSITIVE RAIL SINK CURRENT AT NEGATIVE RAIL 2.500 0.60 AVDD = 2.7 V, External Reference = 2.5 V, DAC Loaded with FFFh 2.495 Channel G AVDD = 2.7 V, External Reference = 2.5 V, DAC Loaded with 000h 0.50 2.490 Channel G Output Voltage - V Output Voltage - V 2.485 2.480 2.475 2.470 0.40 0.30 0.20 2.465 2.460 0.10 2.455 2.450 0 0.00 1 2 3 4 5 6 ISOURCE - mA 7 8 9 10 3 4 5 6 ISINK - mA 7 8 POWER SUPPLY CURRENT vs DIGITAL INPUT CODE POWER SUPPLY CURRENT HISTOGRAM 18 AVDD = 2.7 V, 16 External Reference = 2.5 V 14 0.90 % of Population Power Supply Current - mA 1.00 2 Figure 73. AVDD = 2.7 V, External Reference = 2.5 V, Internal Reference Disabled, Code Loaded to all Eight DAC Channels 1.10 1 Figure 72. 1.30 1.20 0 0.80 0.70 0.60 0.50 0.40 0.30 12 10 8 6 4 0.20 2 0.90 0.88 0.89 0.85 0.86 0.87 IDD - Supply Current - mA Figure 74. 20 0.83 0.84 4096 0.81 0.82 3584 0.79 0.80 3072 0.77 0.78 1536 2048 2560 Digital Input Code 0.74 1024 0.75 0.76 512 0.72 0.73 0 0.70 0 0.00 0.71 0.10 Figure 75. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted FULL-SCALE SETTLING TIME: 2.7V RISING EDGE FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE AVDD = 2.7 V, From Code FFFh to 000h External Reference = 2.5 V AVDD = 2.7 V, From Code 000h to FFFh External Reference = 2.5 V Zoomed Rising Edge 100 mV/div Zoomed Falling Edge 100 mV/div Falling Edge 2 V/div Rising Edge 2 V/div Trigger Pulse 5 V/div Trigger Pulse 5 V/div t - Time - 5 ms/div t - Time - 5 ms/div Figure 76. Figure 77. HALF-SCALE SETTLING TIME: 2.7V RISING EDGE HALF-SCALE SETTLING TIME: 2.7V FALLING EDGE AVDD = 2.7 V, From Code 400h to C00h External Reference = 2.5 V AVDD = 2.7 V, From Code C00h to 400h External Reference = 2.5 V Zoomed Falling Edge 100 mV/div Zoomed Rising Edge 100 mV/div Falling Edge 2 V/div Rising Edge 2 V/div Trigger Pulse 5 V/div Trigger Pulse 5 V/div t - Time - 5 ms/div t - Time - 5 ms/div Figure 78. Figure 79. CLOCK FEEDTHROUGH 400 kHz, MIDSCALE POWER-ON GLITCH RESET TO ZERO SCALE AVDD = 2.7 V, Clock Feedthrough Impulse ~ 0.5n V-s External Reference = 2.5 V VOUT - 2 mV/div ~ 1.8 mVPP AVDD = 2.7 V, External Reference = 2.5 V, DAC = Zero Scale, DACs unloaded VOUT - 5 mV/div AVDD - 2 V/div SCL - 5 V/div t - Time - 10 ms/div t - Time - 1 ms/div Figure 80. Figure 81. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 21 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com TYPICAL CHARACTERISTICS: DAC AT AVDD = 2.7 V (continued) At TA = 25°C, external reference used, DAC output not loaded, and all DAC codes in straight binary data format, unless otherwise noted POWER-ON GLITCH RESET TO MIDSCALE POWER-OFF GLITCH AVDD = 2.7 V, External Reference = 2.5 V, DAC = Mid Scale, DACs Unloaded VOUT - 2 mV/div AVDD = 2.7 V, DAC = Zero Scale VOUT - 1 mV/div AVDD - 2 V/div AVDD - 2 V/div t - Time - 10 ms/div t - Time - 20 ms/div Figure 82. Figure 83. GLITCH ENERGY: 2.7V 1LSB STEP, RISING EDGE GLITCH ENERGY: 2.7V 1LSB STEP, FALLING EDGE AVDD = 2.7 V, From Code 800h to 801h External Reference = 2.5 V VOUT - 500 mV/div VOUT - 500 mV/div LDAC Clock Feed-Through LDAC Clock Feed-Through LDAC - Trigger Pulse 5 V/div LDAC - Trigger Pulse 5 V/div t - Time - 2 ms/div t - Time - 2 ms/div Figure 84. 22 AVDD = 2.7 V, From Code 801h to 800h External Reference = 2.5 V Figure 85. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) The DAC7678 architecture consists of eight string DACs each followed by an output buffer amplifier. The DAC7678 also includes an internal 2.5V reference with a maximum 25ppm/°C temperature drift performance, offering a 5V, full-scale output voltage. Figure 86 shows a principal block diagram of the DAC architecture. VREFIN/VREFOUT 150kW will be un-shorted if external reference is used. Thus the overall gain will be one and allows the user to provide an external reference value of 0 to AVDD. If internal reference is used RDIVIDER is shorted and the overall gain will be two. VREF RDIVIDER VREF 2 150kW 178kW DAC Register REF(+) Resistor String REF(-) R VOUTX To Output Amplifier (2x Gain) R Figure 86. Device Architecture For the TSSOP package, the input coding to the DAC7678 is straight binary. For the QFN package, the TWOC pin controls the code format. When using the internal reference, the ideal output voltage is given by Equation 1: DIN VOUT = ´ 2 ´ VREFOUT 4096 (1) R When using an external reference, the ideal output voltage is given by Equation 2: DIN VOUT = ´ VREFIN 4096 (2) Where: DIN = decimal equivalent of the binary code that is loaded to the DAC register. It can range from 0 to 4095. VREFOUT = internal reference voltage of 2.5V (typ), supplied at the VREFIN/VREFOUT pin. VREFIN = external reference voltage of 0V to 5V (typ), supplied at the VREFIN/VREFOUT pin. RESISTOR STRING The resistor string circuitry is shown in Figure 87. It is a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. It is monotonic because it is a string of resistors. RDIVIDER R Figure 87. Resistor String OUTPUT AMPLIFIER The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving a maximum output range of 0V to AVDD. It is capable of driving a load of 2kΩ in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the Typical Characteristics. The typical slew rate is 0.75V/μs, with a typical full-scale settling time of 7μs with the output unloaded. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 23 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com INTERNAL REFERENCE which consists of 8 bit Address Byte plus 24 bit serial command as shown in Table 1. During the time that the internal reference is disabled, the DAC functions normally using an external reference. However, when switching to the external reference the internal gain is dynamically switched to one. Therefore appropriate value of external reference should be used per the desired output voltage. At this point, the internal reference is disconnected from the VREFIN/VREFOUT pin (3-state output). Do not attempt to drive the VREFIN/VREFOUT pin externally and internally at the same time indefinitely. There are two modes that allow communication with the internal reference: Regular/Static and Flexible. In Flexible mode DB14 needs to be set to '1' as shown in Table 17. The DAC7678 includes a 2.5V internal reference that is disabled by default. The internal reference is externally available at the VREFIN/VREFOUT pin. A minimum 100nF capacitor is recommended between the reference output and GND for noise filtering. The internal reference of the DAC7678 is a bipolartransistor based precision bandgap voltage reference. Figure 88 shows the basic bandgap topology. Transistors Q1 and Q2 are biased such that the current density of Q1 is greater than that of Q2. The difference of the two base-emitter voltages (VBE1 – VBE2) has a positive temperature coefficient and is forced across resistor R1. This voltage is gained up and added to the base-emitter voltage of Q2, which has a negative temperature coefficient. The resulting output voltage is virtually independent of temperature. The short-circuit current is limited by design to approximately 100mA. Regular/Static Mode (see Table 1 and Table 2) Enabling Internal Reference: To enable the internal reference, write the 24-bit serial command shown in Table 1 after properly addressing the device. When performing a power cycle to reset the device, the internal reference is switched off (default mode). In the default mode, the internal reference is powered down until a valid write sequence is applied to power up the internal reference. Setting DB4 to '1' turns on the internal reference.If the internal reference is powered up, it automatically powers down when all DACs power down in any of the power-down modes (see Table 17 and Power Down Modes section). The internal reference automatically powers up when any DAC is powered up. VREF Reference Disable Q1 Q2 R1 Disabling Internal Reference: R2 To disable the internal reference, address the device by writing the 8-bit address byte and then writing the 24-bit serial command shown in Table 1. When performing a power cycle to reset the device, the internal reference is put back into the default mode (switched off). Figure 88. Simplified Schematic of the Bandgap Reference SPACER Enable/Disable Internal Reference The internal reference in the DAC7678 is disabled by default for debugging, evaluation purposes, or when using an external reference. The internal reference can be powered up and powered down using a serial command that requires a 32-bit write sequence, Table 1. Write Sequence for Enabling Internal Reference (Static Mode) (Internal Reference Powered On) COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT BYTE C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 X X X X X X X X X X X X X X X 1 X X X X Table 2. Write Sequence for Disabling Internal Reference (Static Mode) (Internal Reference Powered Off) COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT BYTE C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 X X X X X X X X X X X X X X X 0 X X X X 24 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 Flexible Mode (see Table 3, Table 4, Table 5 and Table 6) internal reference operating mode. When performing a power cycle to reset the device, the internal reference is switched off (default mode). In the default mode, the internal reference remains powered down until a valid write sequence is applied to power up the internal reference. When the internal reference is powered up in flexible mode, it remains powered up, regardless of the state of the DACs. Enabling Internal Reference: Method 1) To enable the internal reference, write the 24-bit serial command shown in Table 3 after properly addressing the device. When performing a power cycle to reset the device, the internal reference is switched off (default mode). In the default mode, the internal reference is powered down until a valid write sequence is applied to power up the internal reference. If the internal reference is powered up, it automatically powers down when all DACs power down in any of the power-down modes (see the Power Down Modes section). The internal reference powers up automatically when any DAC is powered up. Disabling Internal Reference: To disable the internal reference, write the 24-bit serial command shown in Table 5 after properly addressing the device. When performing a power cycle to reset the device, the internal reference is switched off (default mode). When the internal reference is operated in Flexible mode, Static mode is disabled and does not work. To switch from Flexible mode to Static mode, use the command shown in Table 6. Method 2) To always enable the internal reference, write the 24-bit serial command shown in Table 4 after properly addressing the device. When the internal reference is always enabled, any power-down command to the DAC channels does not change the Table 3. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Powered On) COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT BYTE C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 X X X X X 1 0 0 X X X X X X X X X X X X Table 4. Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Always Powered On) COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT BYTE C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 X X X X X 1 0 1 X X X X X X X X X X X X Table 5. Write Sequence for Disabling Internal Reference (Flexible Mode) (Internal Reference Always Powered Down) COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT BYTE C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 X X X X X 1 1 0 X X X X X X X 0 X X X X Table 6. Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT BYTE C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 1 X X X X X 0 X X X X X X X X X X X X X X Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 25 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com TWO-WIRE, I2C-COMPATIBLE INTERFACE The I2C™ is a 2-wire serial interface developed by Philips Semiconductor (see I2C™-Bus Specification, Rev. 03, June 2007). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C™ compatible devices connect to the I2C™ bus through open drain I/O pins, SDA and SCL. The I2C specification states that the device that controls communication is called a master, and the devices that are controlled by the master are called slaves. The master device generates the SCL signal. The master device also generates special timing conditions (start condition, repeated start condition, and stop condition) on the bus to indicate the start or stop of a data transfer. Device addressing is also done by the master. The master device on an I2C bus is usually a microcontroller or a digital signal processor (DSP). The DAC7678 on the other hand, operates as a slave device on the I2C bus. A slave devcie acknowledges master's commands and upon master's control, either receives or transmits data. SDA Other than specific timing signals, the I2C interface works with serial bytes. At the end of each byte, a 9th clock cycle is used to generate/detect an acknowledge signal, Acknowledge is when the SDA line is pulled low during the high period of the 9th clock cycle. A not-acknowledge is when the SDA line is left high during the high period of the 9th clock cycle as shown in Figure 90. Data Output by Transmitter Not Acknowledge Data Output by Receiver Acknowledge SCL from Master 1 2 8 9 S START Condition Clock Pulse for Acknowledgement Figure 90. Acknowledge and Not Acknowledge on the I2C Bus SDA SCL SCL S P Start Condition Stop Condition Figure 89. Start and Stop Conditions The DAC7678 normally operates as a slave receiver. A master device writes to the DAC7678, a slave receiver. However, if a master device inquires the DAC7678 internal register data, the DAC7678 operates as a slave transmitter. In this case, the master device reads from the DAC7678, a slave transmitter. According to I2C™ terminology, read and write are with respect to the master device. The DAC7678 works as a slave and supports the following data transfer modes, as defined in the I2C™ -Bus Specification: • Standard mode (100 kbps) • Fast mode (400 kbps) • Fast mode+ (1.0Mbps) and • High-Speed mode (3.4 Mbps) The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The fast mode+ protocol is supported in terms of data transfer speed but not output current. The low-level output current would be 3mA similar to the case of standard 26 and fast modes. The protocol for high-speed mode is different from the F/S-mode, and it is referred to as HS-mode. The DAC7678 supports 7-bit addressing. The 10-bit addressing and general call address are not supported. F/S Mode Protocol • The master initiates data transfer by generating a start condition. The start condition is when a highto-low transition occcurs on the SDA line while SCL is high, as shown in Figure 90. All I2Ccompatible devices recognize a start condition. • The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit (R/W) on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse, as shown in Figure 91. All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge by pulling the SDA line low during the entire high period of the ninth SCL cycle, as shown in Figure 90 by pulling the SDA line low during the entire high period of the 9th SCL cycle. Upon detecting this acknowledge, the master knows the communication link with a slave has been established. • The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So the acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. The 9-bit valid data sequences, consisting of 8-data bits and 1-bit acknowledge can continue as long as Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com • SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 89). This action releases the bus and stops the communication link with the addressed slave. All I2C-compatible devices recognize the stop condition. Upon receipt of a stop condition, the bus is released, and all slave devices then wait for a start condition followed by a matching address. • all devices must recognize it and switch their internal setting to support 3.4Mbps operation. The master then generates a repeated start condition (a repeated start condition has the same timing as the start condition). After this repeated start condition, the protocol is the same as F/Smode, except that transmission speeds up to 3.4Mbps are allowed. A stop condition ends HS mode and switches all the internal settings of the slave devices to support F/S-mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in H/S-mode. SDA DAC7678 I2C UPDATE SEQUENCE SCL Data Line Stable; Data Valid For a single update, the DAC7678 requires a start condition, a valid I2C address, a command and access (CA) byte, and two data bytes, the most significant data byte (MSDB) and least significant data byte (LSDB), as shown in Table 7. Change of Data Allowed Figure 91. Bit Transfer on the I2C Bus HS Mode Protocol • When the bus is idle, both the SDA and SCL lines are pulled high by the pull-up resistors. • The master generates a start condition followed by a valid serial byte containing H/S master code 00001XXX. This transmission is made in F/S mode at no more than 1.0 Mbps. No device is allowed to acknowledge the H/S master code, but After each byte is received, the DAC7678 acknowledges by pulling the SDA line low during the high period of a single clock pulse, as shown in Figure 92. These four bytes and acknowledge cycles make up the 36 clock cycles required for a single update to occur. A valid I2C address selects the DAC7678. Recognize START or REPEATED START Condition Recognize STOP or REPEATED START Condition Generate ACKNOWLEDGE Signal P SDA Acknowledgement Signal From Slave MSB Sr Address R/W SCL 1 2 S or Sr START or REPEATED START Condition 7 8 9 1 2 ACK Clock Line Held Low While Interrupts are Serviced 3 - 8 9 ACK Sr or P REPEATED START or STOP Condition Figure 92. I2C Bus Protocol Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 27 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com Table 7. Update Sequence MSB ··· LSB MSB ··· LSB MSB ACK ··· LSB ACK MSB ··· LSB ACK ACK Address (A) Byte Command/Access Byte MSDB LSDB DB[32:24] DB[23:16] DB[15:8] DB[7:0] SPACING The CA byte sets the operational mode of the selected DAC7678. When the operational mode is selected by this byte, the DAC7678 must receive two data bytes, the most significant data byte (MSDB) and least significant data byte (LSDB), for data update to occur. The DAC7678 performs an update on the falling edge of the acknowledge signal that follows the LSDB. maximum DAC update rate is limited to 22.22kSPS. Using the Fast mode plus (clock = 1MHz), the maximum DAC update rate is limited to 55.55kSPS. When a stop condition is received, the DAC7678 releases the I2C bus and awaits a new start condition. Address (A) Byte The address byte, as shown in Table 8, is the first byte received following the START condition from the master device. The first four bits (MSBs) of the address are factory preset to 1001. The next 3 bits of the address are controlled by the ADDR pin(s). The ADDR pin(s) inputs can be connected to AVDD, GND, or left floating. The device address should be determined before device power up. During power up the device latches the values of the address pins and consequently will respond to that particular address according to Table 9 and Table 10. When using the QFN package (DAC7678RGE), up to 8 devices can be connected to the same I2C bus. When using the TSSOP package (DAC7678PW), up to 3 devices can be connected to the same I2C bus. The CA byte does not have to be resent until a change in operational mode is required. The bits of the control byte continuously determine the type of update performed. Thus, for the first update, the DAC7678 requires a start condition, a valid I2C address, the CA byte, and two data bytes (MSDB and LSDB). For all consecutive updates, the DAC7678 needs only an MSDB and LSDB, as long as the CA byte command remains the same. When using the I2C HS mode (clock = 3.4MHz), each 12-bit DAC update other than the first update can be done within 18 clock cycles (MSDB, acknowledge signal, LSDB, acknowledge signal) at 188.88kSPS. When using Fast mode (clock = 400kHz), the Table 8. Address Byte MSB AD6 1 LSB AD5 0 AD4 0 AD3 1 AD2 AD1 AD0 See Table 9 or Table 10 Slave Address column R/W 0 or 1 Table 9. Address Format For QFN-24 (RGE) Package SLAVE ADDRESS ADDR1 ADDR0 1001 000 0 0 1001 001 0 1 1001 010 1 0 1001 011 1 1 1001 100 Float 0 1001 101 Float 1 1001 110 0 Float 1001 111 1 Float Not supported Float Float Table 10. Address Format For TSSOP-16 (PW) Package 28 SLAVE ADDRESS ADDR0 1001 000 0 1001 010 1 1001 100 Float Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 Command and Access (CA) Byte The Command and Access Byte, as shown in Table 11, controls which command is executed and which register is being accessed when writing to or reading from the DAC7678. See Table 12 for a list of write and read commands. Table 11. Command and Access Byte MSB C3 LSB C2 C1 Command bits C0 A3 A2 A1 Access bits A0 Table 12. Command and Access Byte Format (1) C3 C2 C1 C0 A3 A2 A1 A0 DESCRIPTION Write Sequences 0 0 0 0 A3 A2 A1 A0 Write to DAC input register channel n 0 0 0 1 A3 A2 A1 A0 Select to update DAC register channel n 0 0 1 0 A3 A2 A1 A0 Write to DAC input register channel n, and update all DAC registers (global software LDAC) 0 0 1 1 A3 A2 A1 A0 Write to DAC input register channel n, and update DAC register channel n 0 1 0 0 X X X X Power down/on DAC 0 1 0 1 X X X X Write to clear code register 0 1 1 0 X X X X Write to LDAC register 0 1 1 1 X X X X Software reset 1 0 0 0 X X X X Write to internal reference register 1 0 0 1 X X X X Write to additional internal reference register Read Sequences 0 0 0 0 A3 A2 A1 A0 Read from DAC input register channel n 0 0 0 1 A3 A2 A1 A0 Read from DAC register channel n 0 1 0 0 X X X X Read from DAC power down register 0 1 0 1 X X X X Read from clear code register 0 1 1 0 X X X X Read from LDAC register 1 0 0 0 X X X X Read from internal reference register 1 0 0 1 X X X X Read from additional internal reference register Access Sequences C3 C2 C1 C0 0 0 0 0 DAC channel A C3 C2 C1 C0 0 0 0 1 DAC channel B C3 C2 C1 C0 0 0 1 0 DAC channel C C3 C2 C1 C0 0 0 1 1 DAC channel D C3 C2 C1 C0 0 1 0 0 DAC channel E C3 C2 C1 C0 0 1 0 1 DAC channel F C3 C2 C1 C0 0 1 1 0 DAC channel G C3 C2 C1 C0 0 1 1 1 DAC channel H C3 C2 C1 C0 1 1 1 1 All DAC channels, broadcast update (1) Any sequences other than the ones listed are invalid; improper use can cause incorrect device functionality. Most Significant Data Byte (MSDB) and Least Significant Data Byte (LSDB) The MSDB and LSDB contain the data that are Table 13. MSDB passed to the register(s) specified by the CA byte, as MSB shown in Table 13 and Table 14. See Table 17 for a complete list of write sequences and Table 18 for a DB15 DB14 DB13 DB12 DB11 DB10 complete list of read sequences. The DAC7678 Most Significant Data Byte (MSDB) updates at the falling edge of the acknowledge signal that follows the LSDB[0] bit. LSB DB9 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DB8 29 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com Broadcast Address Byte 4. Then the device writes the MSDB byte of the addressed register. The master should acknowledge this byte. Finally, the device writes out the LSDB of the register as shown in Table 16. Broadcast addressing, see Table 15, is also supported by DAC7678. Broadcast addressing can be used for synchronously updating or powering down multiple DAC7678 devices. DAC7678 is designed to work with other members of the DACx578 family to support multichannel synchronous update. Using the broadcast address, DAC7678 responds regardless of the states of the address pins. Broadcast is supported only in write mode (Master writes to DAC7678). An alternative reading method allows for reading back the value of the last register written. The sequence is a start/repeated start with slave address and the R/W bit set to '1', and the two bytes of the last register are read out. Note that it is not possible to use the broadcast address for reading. 2 DAC7678 I C READ SEQUENCE Table 14. LSDB To read any register the following command sequence should be used: 1. Send a start or repeated start command with a slave address and the R/W bit set to '0' for writing. The device will acknowledge this event. 2. Then send a command byte for the register to be read. The device will acknowledge this event again. 3. Then send a repeated start with the slave address and the R/W bit set to '1' for reading. The device will also acknowledge this event. MSB DB7 LSB DB6 DB5 DB4 DB3 DB2 DB1 DB0 Least Significant Data Byte (LSDB) Table 15. Broadcast Address Byte MSB LSB 1 0 0 0 1 1 1 0 Table 16. Read Sequence S MSB … R/W(0) ACK Address Byte From master 30 MSB … LSB ACK Command/Access Byte Slave From master Sr Sr Slave MSB … R/W(1) ACK Address Byte From master MSB … LSB ACK MSDB slave Submit Documentation Feedback From Slave MSB … LSB ACK LSDB Master From Slave Master Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 Table 17. Control Matrix for Write Commands COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DESCRIPTION C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write to DAC Input Register 0 0 0 0 0 0 0 0 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel A 0 0 0 0 0 0 0 1 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel B 0 0 0 0 0 0 1 0 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel C 0 0 0 0 0 0 1 1 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel D 0 0 0 0 0 1 0 0 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel E 0 0 0 0 0 1 0 1 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel F 0 0 0 0 0 1 1 0 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel G 0 0 0 0 0 1 1 1 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel H 0 0 0 0 1 X X X X X X X Invalid code, no action performed 0 0 0 0 1 1 1 1 X X X X Broadcast mode–write to all DAC channels X X X X X X X X X Data[11:4] X X X Data[3:0] Select to Update DAC Register 0 0 0 1 0 0 0 0 X X X X X X X X X X X X X X X X Selects DAC channel A to be updated 0 0 0 1 0 0 0 1 X X X X X X X X X X X X X X X X Selects DAC channel B to be updated 0 0 0 1 0 0 1 0 X X X X X X X X X X X X X X X X Selects DAC channel C to be updated 0 0 0 1 0 0 1 1 X X X X X X X X X X X X X X X X Selects DAC channel D to be updated 0 0 0 1 0 1 0 0 X X X X X X X X X X X X X X X X Selects DAC channel E to be updated 0 0 0 1 0 1 0 1 X X X X X X X X X X X X X X X X Selects DAC channel F to be updated 0 0 0 1 0 1 1 0 X X X X X X X X X X X X X X X X Selects DAC channel G to be updated 0 0 0 1 0 1 1 1 X X X X X X X X X X X X X X X X Selects DAC channel H to be updated 0 0 0 1 1 X X X X X X X X X X X X X X X X X X X Invalid code, no action performed 0 0 0 1 1 1 1 1 X X X X X X X X X X X X X X X X Broadcast mode–selects all DAC channels to be updated Write to DAC Input Registers and Update DAC Register (Individual Software LDAC) 0 0 1 1 0 0 0 0 Data[11:4] Data[3:0] X X X X Write to DAC input register for channel A and update channel A DAC register 0 0 1 1 0 0 0 1 Data[11:4] Data[3:0] X X X X Write to DAC input register for channel B and update channel B DAC register 0 0 1 1 0 0 1 0 Data[11:4] Data[3:0] X X X X Write to DAC input register for channel C and update channel C DAC register 0 0 1 1 0 0 1 1 Data[11:4] Data[3:0] X X X X Write to DAC input register for channel D and update channel D DAC register 0 0 1 1 0 1 0 0 Data[11:4] Data[3:0] X X X X Write to DAC input register for channel E and update channel E DAC register 0 0 1 1 0 1 0 1 Data[11:4] Data[3:0] X X X X Write to DAC input register for channel F and update channel F DAC register 0 0 1 1 0 1 1 0 Data[11:4] Data[3:0] X X X X Write to DAC input register for channel G and update channel G DAC register 0 0 1 1 0 1 1 1 Data[11:4] Data[3:0] X X X X Write to DAC input register for channel H and update channel H DAC register 0 0 1 1 1 X X X X X X X Invalid code, no action performed 0 0 1 1 1 1 1 1 X X X X Broadcast mode–write to all input registers and update all DAC registers X X X X X X X X X Data[11:4] X Data[3:0] X X Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 31 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com Table 17. Control Matrix for Write Commands (continued) COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DESCRIPTION C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Write to Select DAC Input Register and Update All DAC Registers (Global Software LDAC) 0 0 1 0 0 0 0 0 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel A and update all DAC registers 0 0 1 0 0 0 0 1 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel B and update all DAC registers 0 0 1 0 0 0 1 0 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel C and update all DAC registers 0 0 1 0 0 0 1 1 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel D and update all DAC registers 0 0 1 0 0 1 0 0 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel E and update all DAC registers 0 0 1 0 0 1 0 1 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel F and update all DAC registers 0 0 1 0 0 1 1 0 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel G and update all DAC registers 0 0 1 0 0 1 1 1 Data[11:4] Data[3:0] X X X X Write to DAC input register of channel H and update all DAC registers 0 0 1 0 1 X X X X X X X Invalid code, no action performed 0 0 1 0 1 1 1 1 X X X X Broadcast mode–write to all input registers and update all DAC registers X X X X X X X X X X Data[11:4] X X Data[3:0] Power-Down Register 0 1 0 0 X X X X X PD1 PD0 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X 0 1 0 0 X X X X X 0 0 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X Each DAC bit set to '1' powers on selected DACs 0 1 0 0 X X X X X 0 1 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X Each DAC bit set to '1' powers down selected DACs. VOUT connected to GND through 1kΩ pulldown resistor 0 1 0 0 X X X X X 1 0 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X Each DAC bit set to '1' powers down selected DACs. VOUT connected to GND through 100kΩ pull-down resistor 0 1 0 0 X X X X X 1 1 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X Each DAC bit set to '1' powers down selected DACs. VOUT is High Z Clear Code Register 0 1 0 1 X X X X X X X X X X X X X X CL1 CL0 X X X X 0 1 0 1 X X X X X X X X X X X X X X 0 0 X X X X Write to clear code register, CLR pin will clear to zero scale 0 1 0 1 X X X X X X X X X X X X X X 0 1 X X X X Write to clear code register, CLR pin will clear to midscale 0 1 0 1 X X X X X X X X X X X X X X 1 0 X X X X Write to clear code register, CLR pin will clear to full scale 0 1 0 1 X X X X X X X X X X X X X X 1 1 X X X X Write to clear code register disables CLR pin 1 0 X X X X DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X X X X X X X When all DAC bits are set to '1', selected DACs ignore the LDAC pin. When all DAC bits are set to '0', selected DAC registers update according to the LDAC pin. LDAC Register 0 32 1 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 Table 17. Control Matrix for Write Commands (continued) COMMAND AND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DESCRIPTION C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Software Reset 0 1 1 1 X X X X 0 0 X X X X X X X X X X X X X X Software reset (default). Equivalent to power-on reset (POR). 0 1 1 1 X X X X 0 1 X X X X X X X X X X X X X X Software reset that sets device into High-Speed mode 0 1 1 1 X X X X 1 0 X X X X X X X X X X X X X X Software reset that maintains High-Speed mode state Internal Reference in Regular/Static Mode 1 0 0 0 X X X X X X X X X X X X X X X AR X X X X 1 0 0 0 X X X X X X X X X X X X X X X 0 X X X X Disable internal reference (Regular/Static mode) X X X Enable internal reference (Regular/Static mode). If any DACs are powered on, the reference is on. If all DACS are powered down, then reference is off. X 1 0 0 0 X X X X X X X X X X X X X X X 1 Internal Reference in Flexible Mode 1 0 0 1 X X X X X TR2 TR1 TR0 X X X X X X X X X X X X 1 0 0 1 X X X X X 1 0 0 X X X X X X X X X X X X Reference powers down when all DACs power down. Reference powers on when any DACs are powered on. 1 0 0 1 X X X X X 1 0 1 X X X X X X X X X X X X Reference is powered on regardless of DAC power state 1 0 0 1 X X X X X 1 1 0 X X X X X X X X X X X X Reference is powered down regardless of DAC power state 1 0 0 1 X X X X X 0 X X X X X X X X X X X X X X Reference follows Regular/Static mode reference register Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 33 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com Table 18. Control Matrix for Read Commands COMMAND ACCESS BYTE MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE DESCRIPTION C3 C2 C1 C0 A3 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Input Register 0 0 0 0 0 0 0 0 Data[11:4] Data[3:0] X X X X Read from DAC input register channel A 0 0 0 0 0 0 0 1 Data[11:4] Data[3:0] X X X X Read from DAC input register channel B 0 0 0 0 0 0 1 0 Data[11:4] Data[3:0] X X X X Read from DAC input register channel C 0 0 0 0 0 0 1 1 Data[11:4] Data[3:0] X X X X Read from DAC input register channel D 0 0 0 0 0 1 0 0 Data[11:4] Data[3:0] X X X X Read from DAC input register channel E 0 0 0 0 0 1 0 1 Data[11:4] Data[3:0] X X X X Read from DAC input register channel F 0 0 0 0 0 1 1 0 Data[11:4] Data[3:0] X X X X Read from DAC input register channel G 0 0 0 0 0 1 1 1 Data[11:4] Data[3:0] X X X X Read from DAC input register channel H 0 0 0 0 1 X X X X X X X Invalid code X X X X X X X X X X X X DAC Register 0 0 0 1 0 0 0 0 Data[11:4] Data[3:0] X X X X Read DAC A DAC register 0 0 0 1 0 0 0 1 Data[11:4] Data[3:0] X X X X Read DAC B DAC register 0 0 0 1 0 0 1 0 Data[11:4] Data[3:0] X X X X Read DAC C DAC register 0 0 0 1 0 0 1 1 Data[11:4] Data[3:0] X X X X Read DAC D DAC register 0 0 0 1 0 1 0 0 Data[11:4] Data[3:0] X X X X Read DAC E DAC register 0 0 0 1 0 1 0 1 Data[11:4] Data[3:0] X X X X Read DAC F DAC register 0 0 0 1 0 1 1 0 Data[11:4] Data[3:0] X X X X Read DAC G DAC register 0 0 0 1 0 1 1 1 Data[11:4] Data[3:0] X X X X Read DAC H DAC register 0 0 0 1 1 X X X X X X X X X X X X X X X X X X X Invalid code 0 X X X X 0 0 0 0 0 0 PD1 PD0 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A 0 1 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL1 CL0 1 0 X X X X 0 0 0 0 0 0 0 0 DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AR Read reference register X X 0 0 0 0 0 0 0 0 0 0 0 0 0 TR2 TR1 TR0 Read additional reference register Power Down Register 0 1 0 Read power down register Clear Code Register 0 1 Read clear code register LDAC Register 0 1 Read LDAC register Internal Reference in Regular/Static Mode 1 0 0 0 X X Internal Reference in Flexible Mode 1 34 0 0 1 X X Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 POWER-ON RESET TO ZERO-SCALE OR MID-SCALE The DAC7678 contains a power-on reset (POR) circuit that controls the output voltage during poweron. For devices housed in the TSSOP package, at power-on, all DAC registers are filled with zeros and the output voltages of all DAC channels are set to zero-scale. For devices housed in the QFN package, all DAC registers are set to have all DAC channels power on depending of the state of the RSTSEL pin. The RSTSEL pin value is read at power-on and should be set prior to or simultaneously with AVDD. For RSTSEL set to AVDD, the DAC channels are loaded with midscale code. If RSTSEL is set to ground, the DAC channels are loaded with zero-scale code. All DAC channels remain in this state until a valid write sequence and load command are sent to the respective DAC channel. The power-on reset function is useful in applications where it is important to know the output state of each DAC while the device is in the process of powering on. The internal reference is powered off/down by default, and remains that way until a valid reference-change command is executed. LDAC FUNCTIONALITY The DAC7678 offers both software and hardware simultaneous updates and control functions. The DAC double-buffered architecture is designed so that new data can be entered for each DAC without disturbing the analog outputs. The DAC7678 data updates can be performed either in synchronous or asynchronous mode. In synchronous mode, data are updated on the falling edge of the acknowledge signal that follows LSDB. For synchronous mode updates, the LDAC pin is not required and must be connected to GND permanently. In asynchronous mode, the LDAC pin is used as a negative-edge-triggered timing signal for asynchronous DAC updates. Multiple single-channel updates can be performed in order to set different channel buffers to desired values and then make a falling edge on the LDAC pin. The data buffers of all the channels must be loaded with the desired data before an LDAC falling edge. After a high-to-low LDAC transition, all DACs are simultaneously updated with the last contents of the corresponding data buffers. If the contents of a data buffer are not changed by the serial interface, the corresponding DAC output remains unchanged after the LDAC trigger. Alternatively, all DAC outputs can be updated simultaneously using the built-in LDAC software function. The LDAC register offers additional flexibility and control, giving the ability to select which DAC channel(s) should be updated simultaneously when the hardware LDAC pin is being brought low. The LDAC register is loaded with an 8-bit word (DB15 to DB8) using control bits C3, C2, C1, and C0. The default value for each bit, and therefore each DAC channel, is zero and the external LDAC pin operates in normal mode. If the LDAC register bit for a selected DAC channel is set to '1', that DAC channel ignores the external LDAC pin and updates only through the software LDAC command. If, however, the LDAC register bit is set to '0', the DAC channel is controlled by the external LDAC pin. This combination of a software and hardware simultaneous update function is particularly useful in applications where only selective DAC channels are to be updated simultaneously, while keeping the other channels unaffected and updating those channels synchronously. POWER-DOWN MODES The DAC7678 has two separate sets of power-down commands. One set is for the DAC channels and the other set is for the internal reference. For more information on powering down the reference see the Enable/Disable Internal Reference section. DAC Power-Down Commands The DAC7678 uses four modes of operation. These modes are accessed by using control bits C3, C2, C1, and C0. The control bits must be set to '0100'. When the control bits are set correctly, the four different power-down modes are software programmable by setting bits PD0 (DB13) and PD1 (DB14) in the control register. Table 19 shows how to control the operating mode with data bits PD0 (DB13) and PD1 (DB14). The DAC7678 treats the powerdown condition as data; all the operational modes are still valid for power down. It is possible to broadcast a power-down condition to all the DAC7678s in a system. It is also possible to power-down a channel and update data on other channels. Furthermore, it is possible to write to the DAC register/buffer of the DAC channel that is powered down. When the DAC channel is then powered on, it will contain this new value. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 35 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com When both the PD0 and PD1 bits are set to '0', the device works normally with its typical consumption of 1.49 mA at 5.5V. The reference is included with the operation of all eight channels. However, for the three power-down modes, the supply current falls to 0.42 µA at 5.5V (0.25 µA at 2.7V). Not only does the supply current fall, but the output stage also switches internally from the output amplifier to a resistor network of known values as shown in Figure 93. The advantage of this switching is that the output impedance of the device is known while it is in powerdown mode. As described in Table 19, there are three different power-down options. VOUT can be connected internally to GND through a 1kΩ resistor, a 100kΩ resistor, or open-circuited (High-Z). In other words, C3, C2, C1, and C0 = '0100' and DB14 and DB13 = '11' represent a power-down condition with High-Z output impedance for a selected channel. DB14 and DB13 = '01' represents a power-down condition with 1kΩ output impedance and '10' represents a power-down condition with 100kΩ output impedance. Table 19. DAC Operating Modes PD1 (DB14) PD0 (DB13) 0 0 Power on selected DACs 0 1 Power down selected DACs, 1kΩ to GND 1 0 Power down selected DACs, 100kΩ to GND 1 1 Power down selected DACs, High-Z to GND The DAC7678 contains a clear code register. The clear code register can be accessed via the serial interface (I2C) and is user configurable. Bringing the CLR pin low clears the contents of all DAC registers and all DAC buffers and replaces the code with the code determined by the clear code register. The clear code register can be written to by applying the commands shown in Table 17. The default setting of the clear code register sets the output of all DAC channels to 0V when the CLR pin is brought low. The CLR pin is falling-edge triggered; therefore, the device exits clear code mode on the falling edge of the acknowledge signal that follows LSDB of the next write sequence. If the CLR pin is executed (brought low) during a write sequence, this write sequence is aborted and the DAC registers and DAC buffers are cleared as described above. When performing a software reset of the device, the clear code register is reset to the default mode (DB5 = '0', DB4 = '0'). Setting the clear code register to DB4 = '1' and DB5 = '1' ignores any activity on the external CLR pin. SOFTWARE RESET FUNCTION DAC OPERATING MODES SPACER Resistor String DAC CLEAR CODE REGISTER AND CLR PIN The DAC7678 contains a software reset feature. When the software reset feature is executed, the device (all DAC channels) are reset to the power-on reset code. All registers inside the device are reset to the respective default settings. The DAC7678 has an additional feature of switching straight to high speed mode after reset. Table 20 shows all the different modes of the software reset function. Table 20. Software Reset Modes VOUTX Amplifier Power-Down Circuitry Resistor Network DB15 DB14 OPERATING MODES 0 0 Default Software reset. Equivalent to Poweron-Reset x 1 Software reset and set part in High Speed Mode 1 0 Software reset and maintain High Speed Mode state Figure 93. Output Stage During Power-Down 36 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 OPERATING EXAMPLES: DAC7678 For the following examples X = don’t care; value can be either '0' or '1'. I2C Standard and Fast mode examples (ADDR0 and LDAC pin tied low) (TSSOP package) Example 1: Write Mid Scale to Data Buffer A and Update Channel A Output Start Address S 1001 0000 Command and Access Byte ACK MSDB ACK 0000 0000 LSDB ACK 1000 0000 Stop ACK 0000 XXXX P Channel A updates to Mid Scale after the falling edge of the last ACK cycle SPACER Example 2: Power-Down Channel B, C, and H with Hi-Z Output Start Address S 1001 0000 Command and Access Byte ACK MSDB ACK 0100 XXXX LSDB ACK X111 0000 Stop ACK 110X XXXX P SPACER Example 3: Read-back the value of the input register of Channel G Start Address S 1001 0000 ACK Command and Access Byte ACK Repeated Start Address Sr 1001 0001 0000 0110 MSDB (from DAC7678) ACK ACK XXXX XXXX LSDB (from DAC7678) XXXX 0000 SPACER Example 4: Write multiple bytes of data to Channel F Write Full Scale and then Quarter Scale to Channel F Start Address S 1001 0000 ACK Command and Access Byte MSDB ACK 0000 0101 LSDB ACK 1111 1111 ACK* 1111 XXXX MSDB LSDB ACK 0100 0000 ACK** 0000 XXXX Stop P Channel F updates to Full Scale after the falling edge of the 4th ACK* cycle and then Channel F updates to quarter scale after falling edge of the last ACK** cycle. I2C High Speed mode example (ADDR0 and LDAC pin tied low) (TSSOP package) SPACER Example 5: Write Mid Scale and then Full Scale to all DAC channels Start HS Master Code S 0000 1000 NOT ACK Repeated Start Address Sr 1001 0000 ACK Command and Access Byte 0011 1111 ACK MSDB 1000 0000 ACK LSDB 0000 XXXX ACK MSDB 1111 1111 ACK LSDB ACK 1111 XXXX Stop P All Channels update to Mid Scale after the falling edge of the 4th ACK cycle and then all Channels update to Full scale after falling edge of the last ACK cycle. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 37 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com APPLICATION INFORMATION INTERNAL REFERENCE Where: The internal reference of the DAC7678 does not require an external load capacitor for stability because it is stable with any capacitive load. However, for improved noise performance, an external load capacitor of 100nF or larger connected to the VREFIN/VREFOUT output is recommended. Figure 94 shows the typical connections required for operation of the DAC7678 internal reference. A supply bypass capacitor at the AVDD input is also recommended. VREF_MAX = maximum reference voltage observed within temperature range TRANGE. VREF_MIN = minimum reference voltage observed within temperature range TRANGE. VREF = 2.5V, target value for reference output voltage. The internal reference features an exceptional maximum drift coefficient of 25ppm/°C from –40°C to 125°C. Temperature drift results are summarized in the Typical Characteristics. DAC7678 Noise Performance AVDD 1 LDAC SCL 16 2 ADDR0 SDA 15 3 AVDD GND 14 4 VOUTA VOUTB 13 5 VOUTC VOUTD 12 6 VOUTE VOUTF 11 7 VOUTG VOUTH 10 8 VREFIN/VREFOUT 1mF CLR Typical 0.1Hz to 10Hz voltage noise can be seen in Figure 7, Internal Reference Noise. Additional filtering can be used to improve output noise levels, although care should be taken to ensure the output impedance does not degrade the ac performance. The output noise spectrum at VREFIN/VREFOUT without any external components is depicted in Figure 6, Internal Reference Noise Density vs Frequency. Internal reference noise impacts the DAC output noise; see the DAC Noise Performance section for more details. 9 Load Regulation 100nF Figure 94. Typical Connections for Operating the DAC7678 Internal Reference Supply Voltage The internal reference features an extremely low dropout voltage. It can be operated with a supply of only 5mV above the reference output voltage in an unloaded condition. For loaded conditions, refer to the Load Regulation section. The stability of the internal reference with variations in supply voltage (line regulation, dc PSRR) is also exceptional. Within the specified supply voltage range of 2.7V to 5.5V, the variation at VREFIN/VREFOUT is less than 100 µV/V; see the Typical Characteristics. Load regulation is defined as the change in reference output voltage as a result of changes in load current. The load regulation of the internal reference is measured using force and sense contacts as shown in Figure 5. The force and sense lines reduce the impact of contact and trace resistance, resulting in accurate measurement of the load regulation contributed solely by the internal reference. Measurement results are summarized in the Typical Characteristics. Force and sense lines should be used for applications that require improved load regulation. Output Pin Contact and Trace Resistance VOUT Force Line IL Temperature Drift The internal reference is designed to exhibit minimal drift error, defined as the change in reference output voltage over varying temperature. The drift is calculated using the box method described by Equation 3: æ VREF_MAX - VREF_MIN ö 6 Drift Error = ç ÷ ´ 10 (ppm/°C) ´ V T REF RANGE è ø Sense Line Meter Load Figure 95. Accurate Load Regulation of the DAC7678 Internal Reference (3) 38 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 Long-Term Stability Long-term stability/aging refers to the change of the output voltage of a reference over a period of months or years. This effect lessens as time progresses (see Figure 3, the typical long-term stability curve). The typical drift value for the internal reference is 100ppm from 0 hours to 2160 hours. This parameter is characterized by powering-up 19 units and measuring them at regular intervals for a period of 2160 hours. Thermal Hysteresis Thermal hysteresis for a reference is defined as the change in output voltage after operating the device at 25°C, cycling the device through the operating temperature range, and returning to 25°C. Hysteresis is expressed by Equation 4: æ |VREF_PRE - VREF_POST VHYST = ç ç VREF_NOM è |ö ÷ ´ 106 (ppm/°C) ÷ ø æ æD VO UT = ç VREF ´ Gain ´ ç IN ç è 2n è ö æ R1 + R 2 ö æ R2 ö ö ÷ - VREF ´ ç ÷´ç R ÷÷ ø è è R1 ø ø÷ 1 ø (5) Where: DIN = decimal equivalent of the binary code that is loaded to the DAC register. It can range from 0 to 4095 (12 bit) n = resolution in bits Gain = 1 when External Reference is used and 2 when internal reference is used. æ 10 ´ DIN ö VOUT = ç ÷ - 5V è ø 2n (6) This result has an output voltage range of ±5V with 000h corresponding to a -5V output and FFFh corresponding to a +5V output for the 12 bit DAC7678. (4) V Where: VHYST = thermal hysteresis VREF_PRE = output voltage measured at 25°C pretemperature cycling VREF_POST = output voltage measured after the device cycles through the temperature range of –40°C to 125°C, and returns to 25°C. R2 10kW AV EXT REF DD +6V R1 10kW OPA703 AVDD VREFIN/ VREFOUT 10mF DAC NOISE PERFORMANCE ±5V VOUT DAC7678 0.1mF -6V GND Serial Interface Typical noise performance for the DAC7678 with the internal reference enabled is shown in Figure 47. Output noise spectral density at the VOUTX pin versus frequency is depicted in Figure 47 for full-scale, midscale, and zero-scale input codes. The typical noise density for midscale code is 290nV/√Hz at 1kHz and 117nV/√Hz at 100 kHz when internal reference is enabled. The typical noise density reduces to 104nV/√Hz at 1kHz for mid scale code with external reference as shown in Figure 48. Highfrequency noise can be improved by filtering the reference noise. Integrated output noise between 0.1Hz and 10Hz is close to 3µVPP (midscale), as shown in Figure 49. BIPOLAR OPERATION USING THE DAC7678 The DAC7678 family of products is designed for single-supply operation, but a bipolar output range is also possible using the circuit in Figure 96. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier. The output voltage for any input code can be calculated with Equation 5. Figure 96. Bipolar Output Range Using External Reference at 5V MICROPROCESSOR INTERFACING A basic connection diagram to the SCL and SDA pins of the DAC7678 is shown in Figure 97. The DAC7678 interfaces directly to standard mode, fast mode and high speed mode of 2-Wire compatible serial interfaces. The DAC7678 does not perform clock stretching (pulling SCL low), as a result it is not necessary to provide for this function unless other devices on the same bus require this function. Pull-up resistors are required on both the SDA and SCL lines as the bus-drivers are open-drain. The size of these pull-up resistors depends on the operating speed and capacitance of the bus lines. Higher value resistors consume less power but increase transition time on the bus limiting the bus speed. Long bus lines have higher capacitance and require smaller pull-up resistors to compensate. The resistors should not be too small; if they are, bus drivers may not be able to pull the bus lines low. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 39 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com CONNECTING MULTIPLE DEVICES VDD Pull-Up Resistors 1kW to 10kW (typ) Microcontroller or Microprocessor 2 with I C Port SCL SDA 1 LDAC SCL 16 2 ADDR0 SDA 15 3 AVDD 4 VOUTA 5 VOUTC VOUTD 12 6 VOUTE VOUTF 11 7 VOUTG VOUTH 10 8 VREFIN/VREFOUT GND 14 DAC7678 Top View Multiple devices of DAC7678 family can be connected on the same bus. Using the address pin, the DAC7678 can be set to one of three different I2C addresses for the TSSOP package and one of eight addresses for the QFN package. An example showing three DAC7678 devices in TSSOP package is shown if Figure 98. Note that only one set of pullup resistors is needed per bus. The pull-up resistor values may need to be lowered slightly to compensate for the additional bus capacitance due to multiple devices and increased bus length. VOUTB 13 CLR Leave Floating VDD 9 Pull-Up Resistors 1kW to 10kW (typ) Microcontroller or Microprocessor Figure 97. Typical Connections of the DAC7678 2 with I C Port 1 LDAC SCL 16 2 ADDR0 SDA 15 3 AVDD 4 VOUTA 5 VOUTC 6 VOUTE VOUTF 11 7 VOUTG VOUTH 10 8 VREFIN/VREFOUT GND 14 DAC7678 Top View VOUTB 13 VOUTD 12 CLR 9 SCL SDA VDD 1 LDAC SCL 16 1 LDAC SCL 16 2 ADDR0 SDA 15 2 ADDR0 SDA 15 3 AVDD 4 VOUTA 5 VOUTC 6 VOUTE 7 VOUTG 8 VREFIN/VREFOUT DAC7678 Top View GND 14 3 AVDD VOUTB 13 4 VOUTA VOUTD 12 5 VOUTC VOUTF 11 6 VOUTE VOUTF 11 VOUTH 10 7 VOUTG VOUTH 10 8 VREFIN/VREFOUT CLR 9 GND 14 DAC7678 Top View VOUTB 13 VOUTD 12 CLR 9 Figure 98. Typical Connections of the Multiple DAC7678 on the Same Bus 40 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 PARAMETER DEFINITIONS With the increased complexity of many different specifications listed in product data sheets, this section summarizes selected specifications related to digital-to-analog converters. STATIC PERFORMANCE Static performance parameters are specifications such as differential nonlinearity (DNL) or integral nonlinearity (INL). These are dc specifications and provide information on the accuracy of the DAC. They are most important in applications where the signal changes slowly and accuracy is required. Resolution Generally, the DAC resolution can be expressed in different forms. Specifications such as IEC 60748-4 recognize the numerical, analog, and relative resolution. The numerical resolution is defined as the number of digits in the chosen numbering system necessary to express the total number of steps of the transfer characteristic, where a step represents both a digital input code and the corresponding discrete analogue output value. The most commonly-used definition of resolution provided in data sheets is the numerical resolution expressed in bits. Least Significant Bit (LSB) The least significant bit (LSB) is defined as the smallest value in a binary coded system. The value of the LSB can be calculated by dividing the full-scale output voltage by 2n, where n is the resolution of the converter. Most Significant Bit (MSB) The most significant bit (MSB) is defined as the largest value in a binary coded system. The value of the MSB can be calculated by dividing the full-scale output voltage by 2. Its value is one-half of full-scale. Relative Accuracy or Integral Nonlinearity (INL) Relative accuracy or integral nonlinearity (INL) is defined as the maximum deviation between the real transfer function and a straight line passing through the endpoints of the ideal DAC transfer function. INL is measured in LSBs. Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is defined as the maximum deviation of the real LSB step from the ideal 1LSB step. Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart. If the DNL is less than 1LSB, the DAC is said to be monotonic. Full-Scale Error Full-scale error is defined as the deviation of the real full-scale output voltage from the ideal output voltage while the DAC register is loaded with the full-scale code (0xFFF). Ideally, the output should be AVDD – 1 LSB. The full-scale error is expressed in percent of full-scale range (%FSR). Offset Error The offset error is defined as the difference between actual output voltage and the ideal output voltage in the linear region of the transfer function. This difference is calculated by using a straight line defined by two codes (code 30 and 4050). Since the offset error is defined by a straight line, it can have a negative or positive value. Offset error is measured in mV. Zero-Code Error The zero-code error is defined as the DAC output voltage, when all '0's are loaded into the DAC register. Zero-scale error is a measure of the difference between actual output voltage and ideal output voltage (0V). It is expressed in mV. It is primarily caused by offsets in the output amplifier. Gain Error Gain error is defined as the deviation in the slope of the real DAC transfer characteristic from the ideal transfer function. Gain error is expressed as a percentage of full-scale range (%FSR). Full-Scale Error Drift Full-scale error drift is defined as the change in fullscale error with a change in temperature. Full-scale error drift is expressed in units of µV/°C. Offset Error Drift Offset error drift is defined as the change in offset error with a change in temperature. Offset error drift is expressed in µV/°C. Zero-Code Error Drift Zero-code error drift is defined as the change in zerocode error with a change in temperature. Zero-code error drift is expressed in µV/°C. Gain Temperature Coefficient The gain temperature coefficient is defined as the change in gain error with changes in temperature. The gain temperature coefficient is expressed in ppm of FSR/°C. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 41 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com Power-Supply Rejection Ratio (PSRR) Power-supply rejection ratio (PSRR) is defined as the ratio of change in output voltage to a change in supply voltage for a full-scale output of the DAC. The PSRR of a device indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is measured in decibels (dB). Monotonicity Monotonicity is defined as a slope whose sign does not change. If a DAC is monotonic, the output changes in the same direction or remains at least constant for each step increase (or decrease) in the input code. DYNAMIC PERFORMANCE Dynamic performance parameters are specifications such as settling time or slew rate, which are important in applications where the signal rapidly changes and/or high frequency signals are present. Slew Rate The output slew rate (SR) of an amplifier or other electronic circuit is defined as the maximum rate of change of the output voltage for all possible input signals. æ DVOUT (t ) ö SR = max ç ÷ Dt è ø Where ΔVOUT(t) is the output produced by the amplifier as a function of time t. Output Voltage Settling Time Settling time is the total time (including slew time) for the DAC output to settle within an error band around its final value after a change in input. Settling times are specified to within ±0.003% (or whatever value is specified) of full-scale range (FSR). Code Change/Digital-to-Analog Glitch Energy Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nanovolt-seconds (nV-s), and is measured when the digital input code is changed by 1LSB at the major carry transition. Digital Feed-through Digital feed-through is defined as impulse seen at the output of the DAC from the digital inputs of the DAC. It is measured when the DAC output is not updated. It is specified in nV-s, and measured with a full-scale code change on the data bus; that is, from all '0's to all '1's and vice versa. 42 Channel-to-Channel DC Crosstalk Channel-to-channel dc crosstalk is defined as the dc change in the output level of one DAC channel in response to a change in the output of another DAC channel. It is measured with a full-scale output change on one DAC channel while monitoring another DAC channel remains at midscale. It is expressed in LSB. DAC Output Noise Density Output noise density is defined as internallygenerated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. DAC Output Noise DAC output noise is defined as any voltage deviation of DAC output from the desired value (within a particular frequency band). It is measured with a DAC channel kept at midscale while filtering the output voltage within a band of 0.1Hz to 10Hz and measuring its amplitude peaks. It is expressed in terms of peak-to-peak voltage (Vpp). Full-Scale Range (FSR) Full-scale range (FSR) is the difference between the maximum and minimum analog output values that the DAC is specified to provide; typically, the maximum and minimum values are also specified. For an n-bit DAC, these values are usually given as the values matching with code 0 and 2n–1. LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC7678 offers single-supply operation, and is often used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it is to keep digital noise from appearing at the output. As a result of the single ground pin of the DAC7678, all return currents(including digital and analog return currents for the DAC) must flow through a single point. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system. The power applied to AVDD should be well-regulated and low noise. Switching power supplies and dc/dc converters often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 DAC7678 www.ti.com SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 analog output. As with the GND connection, AVDD should be connected to a power-supply plane or trace that is separate from the connection for digital logic until they are connected at the power-entry point. In addition, a 1µF to 10µF capacitor and 0.1µF bypass capacitor are strongly recommended. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors – all designed to essentially low-pass filter the supply and remove the high-frequency noise. Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 43 DAC7678 SBAS493C – FEBRUARY 2010 – REVISED JANUARY 2014 www.ti.com REVISION HISTORY Changes from Original (February 2010) to Revision A • Page Changed the data sheet From: Product Preview status To : Production ............................................................................. 1 Changes from Revision A (August 2010) to Revision B Page • Changed in Table 17, Power-Down Register section, bit DB12 through bit DB5 values have been reversed .................. 32 • Changed in Table 18, Power-Down Register section, bit DB7 through bit DB0 values have been reversed .................... 34 Changes from Revision B (July 2012) to Revision C Page • Changed the formatting so the title would straddle 2 columns, paragraph in first column and Table 13 in second column. lso formatted Table 14 and 15 to be 2 column. .................................................................................................... 29 • Changed "to read any register other than the power-down register..." to "to read any register..." in the DAC7678 I2C READ SEQUENCE section. ............................................................................................................................................... 30 44 Submit Documentation Feedback Copyright © 2010–2014, Texas Instruments Incorporated Product Folder Links: DAC7678 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DAC7678SPW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 DAC7678 DAC7678SPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 DAC7678 DAC7678SRGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 DAC7678 DAC7678SRGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 DAC7678 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of