DAC7714
DAC
®
771
4
Quad, Serial Input, 12-Bit, Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● LOW POWER: 250mW (max)
● UNIPOLAR OR BIPOLAR OPERATION
● SETTLING TIME: 10µs to 0.012%
The DAC7714 is a quad, serial input, 12-bit, voltage
output Digital-to-Analog Converter (DAC) with guaranteed 12-bit monotonic performance over the –40°C
to +85°C temperature range. An asynchronous reset
clears all registers to either mid-scale (800H) or zeroscale (000H), selectable via the RESETSEL pin. The
device can be powered from a single +15V supply or
from dual +15V and –15V supplies.
● 12-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
● USER SELECTABLE RESET TO MIDSCALE OR ZERO-SCALE
Low power and small size makes the DAC7714 ideal
for process control, data acquisition systems, and
closed-loop servo-control. The device is available in a
SO-16 package, and is guaranteed over the –40°C to
+85°C temperature range.
● SECOND-SOURCE for DAC8420
● SMALL SO-16 PACKAGE
APPLICATIONS
●
●
●
●
●
ATE PIN ELECTRONICS
PROCESS CONTROL
CLOSED-LOOP SERVO-CONTROL
MOTOR CONTROL
DATA ACQUISITION SYSTEMS
VCC
GND
VREFH
DAC
Register A
DAC A
DAC
Register B
DAC B
DAC
Register C
DAC C
DAC
Register D
DAC D
VOUTA
SDI
Serial-toParallel
Shift
Register
CLK
CS
VOUTB
12
DAC
Select
LOADDACS
RESET
RESETSEL
VOUTC
VOUTD
VREFL
VSS
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
http://www.burr-brown.com/
http://www.ti.com/
Copyright © 2000, Texas Instruments Incorporated
SBAS119
PDS-1533A
Printed in U.S.A. September, 2000
SPECIFICATIONS (Dual Supply)
At TA = –40°C to +85°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, unless otherwise noted.
DAC7714U
PARAMETER
CONDITIONS
ACCURACY
Linearity Error
Linearity Matching(2)
Differential Linearity Error
Monotonicity
Zero-Scale Error
Zero-Scale Drift
Zero-Scale Matching(2)
Full-Scale Error
Full-Scale Matching(2)
Power Supply Sensitivity
ANALOG OUTPUT
Voltage Output(3)
Output Current
Load Capacitance
Short-Circuit Current
Short-Circuit Duration
DIGITAL INPUT
Logic Levels
VIH
VIL
Data Format
TYP
MAX
MIN
TMIN to TMAX
Code = 000H
±2
At Full Scale
✻
VREFL
–5
VREFH
+5
No Oscillation
✻
✻
To VSS, VCC, or GND
VREFL +1.25
–10
–0.5
–3.5
+10
VREFH – 1.25
3.0
0
8
0.25
2
65
✻
✻
✻
✻
✻
✻
10
V
mA
pF
mA
✻
✻
✻
✻
V
V
mA
mA
✻
µs
LSB
nV-s
nV/√Hz
✻
✻
✻
3.325
✻
1.575
+14.25
–15.75
–40
✻
✻
✻
✻
✻
500
±20
Indefinite
6
–6
180
V
V
✻
Straight Binary
TEMPERATURE RANGE
Specified Performance
LSB(1)
LSB
LSB
Bits
LSB
ppm/°C
LSB
LSB
LSB
ppm/V
±1
✻
±1
10
–8
±1
±1
±1
✻
±2
±2
±2
f = 10kHz
UNITS
✻
Code = FFFH
To ±0.012%, 20V Output Step
Full-Scale Step
MAX
✻
12
1
IIH ≤ ±10µA
IIL ≤ ±10µA
POWER SUPPLY REQUIREMENTS
VCC
VSS
ICC
ISS
Power Dissipation
TYP
±2
±2
±1
REFERENCE INPUT
VREFH Input Range
VREFL Input Range
Ref High Input Current
Ref Low Input Current
DYNAMIC PERFORMANCE
Settling Time
Channel-to-Channel Crosstalk
Digital Feedthrough
Output Noise Voltage
MIN
DAC7714UB
+15.75
–14.25
8.5
✻
✻
✻
250
+85
✻
✻
✻
✻
✻
✻
✻
✻
V
V
mA
mA
mW
✻
°C
NOTES: (1) LSB means Least Significant Bit; if VREFH equals +10V and VREFL equals –10V, then one LSB equals 4.88mV. (2) All DAC outputs will match within
the specified error band. (3) Ideal output voltage does not take into account zero or full-scale error.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC7714
2
SPECIFICATIONS (Single Supply)
At TA = –40°C to +85°C, VCC = +15V, VSS = GND, VREFH = +10V, VREFL = 0V, unless otherwise noted.
DAC7714U
PARAMETER
ACCURACY
Linearity Error(1)
Linearity Matching(3)
Differential Linearity Error
Monotonicity
Zero-Scale Error
Zero-Scale Drift
Zero-Scale Matching(3)
Full-Scale Error
Full-Scale Matching(3)
Power Supply Sensitivity
ANALOG OUTPUT
Voltage Output(4)
Output Current
Load Capacitance
Short-Circuit Current
Short-Circuit Duration
CONDITIONS
DIGITAL INPUT/OUTPUT
Logic Levels
VIH
VIL
Data Format
POWER SUPPLY REQUIREMENTS
VCC
ICC
Power Dissipation
TEMPERATURE RANGE
Specified Performance
TYP
MAX
MIN
TYP
±2
±2
±1
TMIN to TMAX
Code = 004H
±4
At Full Scale
✻
VREFH
+5
No Oscillation
✻
✻
To VCC or GND
VREFL +1.25
0
–0.3
–2.0
✻
V
mA
pF
mA
✻
✻
✻
✻
V
V
mA
mA
✻
µs
LSB
nV-s
nV/√Hz
✻
✻
✻
500
±20
Indefinite
+10
VREFH – 1.25
1.5
0
8
0.25
2
65
✻
✻
✻
✻
✻
✻
10
✻
✻
✻
3.325
✻
1.575
14.25
V
V
✻
Straight Binary
15.75
✻
✻
✻
3.0
45
–40
LSB(2)
LSB
LSB
Bits
LSB
ppm/°C
LSB
LSB
LSB
ppm /V
±2
✻
±2
20
VREFL
–5
IIH ≤ ±10µA
IIL ≤ ±10µA
±1
±1
±1
✻
±4
±4
±4
f = 10kHz
UNITS
✻
Code = FFFH
To ±0.012%, 10V Output Step
MAX
✻
12
2
REFERENCE INPUT
VREFH Input Range
VREFL Input Range
Ref High Input Current
Ref Low Input Current
DYNAMIC PERFORMANCE
Settling Time(5)
Channel-to-Channel Crosstalk
Digital Feedthrough
Output Noise Voltage
MIN
DAC7714UB
+85
✻
✻
✻
V
mA
mW
✻
°C
NOTES: (1) If VSS = 0V, specification applies at code 004H and above. (2) LSB means Least Significant Bit; if VREFH equals +10V and VREFL equals 0V, then one
LSB equals 2.44mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage does not take into account zero or full-scale error.
(5) Full-scale positive 10V step and negative step from code FFFH to 020H.
®
3
DAC7714
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS(1)
VCC to VSS ........................................................................... –0.3V to +32V
VCC to GND ......................................................................... –0.3V to +16V
VSS to GND ......................................................................... +0.3V to –16V
VREFH to GND ....................................................................... –9V to +11V
VREFL to GND (VSS = –15V) ................................................. –11V to +9V
VREFL to GND (VSS = 0V) .................................................... –0.3V to +9V
VREFH to VREFL ....................................................................... –1V to +22V
Digital Input Voltage to GND .............................................. –0.3V to 5.8V
Digital Output Voltage to GND ............................................ –0.3V to 5.8V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................ –40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
PRODUCT
MAXIMUM
LINEARITY
ERROR
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
DAC7714U
PACKAGE
PACKAGE
DRAWING
NUMBER
SPECIFICATION
TEMPERATURE
RANGE
±2
±1
SO-16
211
–40°C to +85°C
"
"
"
"
"
"
DAC7714UB
±1
±1
SO-16
211
–40°C to +85°C
"
"
"
"
"
"
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
DAC7714U
DAC7714U/1K
DAC7714UB
DAC7714UB/1K
Rails
Tape and Reel
Rails
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC7714UB/1K” will get a single 1000-piece Tape and Reel.
ESD PROTECTION CIRCUITS
VCC
VCC
REFH
VOUT
REFL
VSS
VSS
Internal VDD
GND
Typical of Each
Logic Input Pin
®
DAC7714
4
PIN DESCRIPTIONS—U Package
PIN CONFIGURATION—U Package
Top View
PIN
SO
LABEL
DESCRIPTION
Positive Analog Supply Voltage, +15V nominal.
1
VCC
2
VOUTD
DAC D Voltage Output
3
VOUTC
DAC C Voltage Output
4
VREFL
Reference Input Voltage Low. Sets minimum
output voltage for all DACs.
5
VREFH
Reference Input Voltage High. Sets maximum
output voltage for all DACs.
VCC
1
16
RESETSEL
6
VOUTB
DAC B Voltage Output
VOUTD
2
15
RESET
7
VOUTA
DAC A Voltage Output
8
VSS
GND
VOUTC
3
VREFL
4
VREFH
5
Negative Analog Supply Voltage, 0V or –15V
nominal.
14
LOADDACS
13
NIC
9
12
CS
10
SDI
Serial Data Input
11
CLK
Serial Data Clock
12
CS
Chip Select Input
13
NIC
Not Internally Connected
14
LOADDACS
The selected DAC register becomes transparent
when LOADDACS is LOW. It is in the latched
state when LOADDACS is HIGH.
15
RESET
Asynchronous Reset Input. Sets all DAC
registers to either zero-scale (000H) or midscale (800H) when LOW. RESETSEL determines
which code is active.
16
RESETSEL
When LOW, a LOW on RESET will cause all
DAC registers to be set to code 000H. When
RESETSEL is HIGH, a LOW on RESET will set
the registers to code 800H.
DAC7714U
VOUTB
6
11
CLK
VOUTA
7
10
SDI
VSS
8
9
GND
Ground
®
5
DAC7714
TYPICAL PERFORMANCE CURVES: VSS = 0V
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 85°C
(Typical of Each Output Channel)
DLE (LSB)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
LE (LSB)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
200H
400H
600H
800H
A00H
C00H
E00H
FFFH
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
200H
400H
A00H
C00H
E00H
ZERO-SCALE ERROR vs TEMPERATURE
(Code 004H)
FFFH
2.0
1.5
DAC C
DAC A
1.0
0.5
0
–0.5
DAC B
DAC D
–1.0
–1.5
–2.0
200H
400H
600H
800H
A00H
C00H
E00H
–40 –30 –20 –10 0
FFFH
CURRENT vs CODE
All DACs Set to Indicated Code
VREFH
VREF Current (mA)
2.0
1.5
DAC C
1.0
DAC A
10 20 30 40 50 60 70 80 90
Temperature (°C)
FULL-SCALE ERROR vs TEMPERATURE
(Code FFFH)
DAC B
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
VREFL
0
VREF Current (mA)
Full-Scale Error (mV)
800H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel –40°C
(Typical of Each Output Channel)
Digital Input Code
0.5
600H
Digital Input Code
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
Digital Input Code
Zero-Scale Error (mV)
DLE (LSB)
LE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 25°C
(Typical of Each Output Channel)
–0.5
DAC D
–1.0
–1.5
–2.0
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90
Temperature (°C)
200H
400H
600H
800H
A00H
Digital Input Code
®
DAC7714
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
000H
6
C00H
E00H
FFFH
TYPICAL PERFORMANCE CURVES: VSS = 0V
(Cont.)
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER SUPPLY CURRENT vs TEMPERATURE
6.00
5.00
3.5
No Load, All 4 DACs Set to Indicated Code
ICC
4.00
ICC (mA)
2.5
1.5
ICC
3.00
2.00
0.5
1.00
–0.5
–40 –30 –20 –10 0
0
000H
10 20 30 40 50 60 70 80 90 100
400H
600H
800H
A00H C00H E00H FFFH
Digital Input Code
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +10V)
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to Code 020H)
Large Signal
Settling Time: 5V/div
Output Voltage
Output Voltage
200H
Temperature (°C)
Large Signal
Settling Time: 5V/div
Small Signal
Settling Time: 1LSB/div
Small Signal
Settling Time: 1LSB/div
+5V
LOADDACS
0
+5V
LOADDACS
0
Time (2µs/div)
Time (2µs/div)
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
7FFH to 800H
+5V
LOADDACS
0
Time (1µs/div)
Output Voltage (200mV/div)
Output Voltage (200mV/div)
Quiescent Current (mA)
4.5
800H to 7FFH
+5V
LOADDACS
0
Time (1µs/div)
®
7
DAC7714
TYPICAL PERFORMANCE CURVES: VSS = 0V
(Cont.)
At TA = +25°C, VCC = +15V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
OUTPUT NOISE vs FREQUENCY
OUTPUT VOLTAGE vs RLOAD
1000
15
12
Source
VOUT (V)
Noise (nV/√Hz)
Code 020H
100
Code FFFH
9
6
3
Sink
10
0
0.1
1
10
100
Frequency (kHz)
1000
0
0.01
10000
Short to Ground
PSRR (dB)
IOUT (mA)
5
0
–5
–10
Short to VCC
200H
400H
600H
800H
A00H C00H
–40
–50
–60
–70
–80
–90
–100
–110
–120
+15V
101
E00H FFFH
102
103
104
Frequency (Hz)
Digital Input Code
®
DAC7714
100
0
–10
–20
–30
10
–20
000H
10
POWER SUPPLY REJECTION RATIO vs FREQUENCY
SINGLE SUPPLY CURRENT LIMIT vs INPUT CODE
–15
1
RLOAD (kW)
20
15
0.1
8
105
106
TYPICAL PERFORMANCE CURVES: VSS = –15V
At TA = +25°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 85°C
(Typical of Each Output Channel)
DLE (LSB)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
LE (LSB)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
200H
400H
600H
800H
A00H
C00H
E00H
FFFH
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
400H
600H
800H
A00H
C00H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel –40°C
(Typical of Each Output Channel)
CURRENT vs CODE
All DACs Set to Indicated Code
VREF Current (mA)
VREF Current (mA)
200H
400H
600H
800H
A00H
C00H
E00H
E00H
FFFH
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
000H
VREFL
200H
400H
600H
800H
A00H
C00H
E000H FFFH
Digital Input Code
Digital Input Code
BIPOLAR ZERO-SCALE ERROR vs TEMPERATURE
(Code 800H)
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
(Code FFFH)
2.0
1.5
1.5
1.0
DAC C
0.5
0
–0.5
DAC D
DAC B
FFFH
VREFH
2.5
2.0
1.5
1.0
0.5
0
–0.5
2.0
–1.0
200H
Digital Input Code
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
Digital Input Code
Positive Full-Scale Error (mV)
Bipolar Zero-Scale Error (mV)
DLE (LSB)
LE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 25°C
(Typical of Each Output Channel)
DAC A
–1.5
–2.0
DAC C
1.0
0.5
DAC B
0
–0.5
DAC D
–1.0
DAC A
–1.5
–2.0
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90
–40 –30 –20 –10 0
Temperature (°C)
10 20 30 40 50 60 70 80 90
Temperature (°C)
®
9
DAC7714
TYPICAL PERFORMANCE CURVES: VSS = –15V
(Cont.)
At TA = +25°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, representative unit, unless otherwise specified.
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
(Code 000H)
POWER SUPPLY CURRENT vs TEMPERATURE
8
6
1.5
Quiescent Current (mA)
Negative Full-Scale Error (mV)
2.0
DAC C
1.0
DAC A
0.5
0
–0.5
DAC B
DAC D
–1.0
ICC
4
2
0
–2
ISS
–4
Data = FFFH (all DACs)
No Load
–6
–1.5
–8
–2.0
–40 –30 –20 –10 0
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
OUTPUT VOLTAGE vs RLOAD
SUPPLY CURRENT vs CODE
8
15
ICC
6
10
Supply Current (mA)
Source
0
–5
Sink
–10
4
No Load, All 4 DACs Set to Indicated Code
2
0
–2
–4
ISS
–6
–15
0.01
0.1
1
10
–8
000H
100
RLOAD (kΩ)
200H
400H
600H
800H
A00H
E00H FFFH
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to –10V)
Large Signal
Settling Time: 5V/div
Output Voltage
Large Signal
Settling Time: 5V/div
Small Signal
Settling Time: 0.5LSB/div
Small Signal
Settling Time: 0.5LSB/div
+5V
LOADDACS
0
+5V
LOADDACS
0
Time (2µs/div)
Time (2µs/div)
®
DAC7714
C00H
Digital Input Code
OUTPUT VOLTAGE vs SETTLING TIME
(–10V to +10V)
Output Voltage
VOUT (V)
5
10
TYPICAL PERFORMANCE CURVES: VSS = –15V
(Cont.)
At TA = +25°C, VCC = +15V, VSS = –15V, VREFH = +10V, VREFL = –10V, representative unit, unless otherwise specified.
DUAL SUPPLY CURRENT LIMIT vs INPUT CODE
SHORT TO GROUND
POWER SUPPLY REJECTION RATIO vs FREQUENCY
20
15
5
PSRR (dB)
IOUT (mA)
10
0
–5
–10
–15
400H
600H
800H
A00H C00H
–15V
+15V
–70
–80
–90
–100
–110
–120
101
E00H FFFH
102
103
104
Digital Input Code
Frequency (Hz)
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
BROADBAND NOISE
7FFH to 800H
105
106
Noise Voltage (500µV/div)
200H
800H to 7FFH
+5V
LOADDACS
0
Time (1ms/div)
Time (1µs/div)
OUTPUT NOISE vs FREQUENCY
1000
Noise (nV/√Hz)
Output Voltage (200mV/div)
–20
000H
0
–10
–20
–30
–40
–50
–60
100
Noise at any code
10
0
0.1
1
10
100
Frequency (kHz)
1000
10000
®
11
DAC7714
THEORY OF OPERATION
At the negative offset limit of –4LSB (–9.76mV), for the
single-supply case, the first specified output starts at code
004H.
The DAC7714 is a quad, serial input, 12-bit, voltage output
DAC. The architecture is a classic R-2R ladder configuration followed by an operational amplifier that serves as a
buffer. Each DAC has its own R-2R ladder network and
output op amp, but all share the reference voltage inputs, as
shown in Figure 1. The minimum voltage output (“zeroscale”) and maximum voltage output (“full-scale”) are set by
external voltage references (VREFL and VREFH, respectively).
The digital input is a 16-bit serial word that contains the
12-bit DAC code and a 2-bit address code that selects one of
the four DACs (the two remaining bits are unused). The
converter can be powered from a single +15V supply or a
dual ±15V supply. Each device offers a reset function which
immediately sets all DAC output voltages and internal
registers to either zero-scale (code 000H) or mid-scale (code
800H). The reset code is selected by the state of the
RESETSEL pin (LOW = 000H, HIGH = 800H). Figures 2
and 3 show the basic operation of the DAC7714.
REFERENCE INPUTS
The reference inputs, VREFL and VREFH, can be any voltage
between VSS + 4V and VCC – 4V provided that VREFH is at
least 1.25V greater than VREFL. The minimum output of
each D/A is equal to VREFL – 1LSB plus a small offset
voltage (essentially, the offset of the output op amp). The
maximum output is equal to VREFH plus a similar offset
voltage. Note that VSS (the negative power supply) must
either be connected to ground or must be in the range of
–14.75V to –15.75V. The voltage on VSS sets several bias
points within the converter. If VSS is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not guaranteed.
The current into the reference inputs depends on the DAC
output voltages and can vary from a few microamps to
approximately 3mA. The reference input appears as a varying load to the reference. If the reference can sink or source
the required current, a reference buffer is not required. See
“Reference Current vs Code” in the Typical Performance
Curves.
The analog supplies must come up before the reference
power supplies, if they are separate. If the power supplies for
the references come up first, then the VCC and VSS supplies
will be powered from the reference via the ESD protection
diodes (see page 4).
ANALOG OUTPUTS
When VSS = –15V (dual supply operation), the output
amplifier can swing to within 4V of the supply rails, over the
–40°C to +85°C temperature range. With VSS = 0V (singlesupply operation), the output can swing to ground. Note that
the settling time of the output op amp will be longer with
voltages very near ground. Care must also be taken when
measuring the zero-scale error when VSS = 0V. If the output
amplifier has a negative offset, the output voltage may not
change for the first few digital input codes (000H, 001H,
002H, etc.) since the output voltage cannot swing below
ground.
RF
R
R
2R
2R
2R
R
2R
R
R
2R
2R
R
2R
VOUT
R
2R
2R
VREFH
VREFL
FIGURE 1. DAC7714 Architecture.
®
DAC7714
12
+15V
+
1µF to 10µF
DAC7714
0.1µF
0V to +10.0V
0V to +10.0V
1
VCC
2
RESETSEL
16
VOUTD
RESET
15
Reset DACs(1)
3
VOUTC
LOADDACS
14
Update Selected Register
4
VREFL
NIC
13
5
VREFH
CS
12
Chip Select
6
VOUTB
CLK
11
Clock
7
VOUTA
SDI
10
Serial Data In
8
VSS
GND
9
+10.000V
0.1µF
0V to +10.0V
0V to +10.0V
NOTE: (1) As configured, RESET LOW sets all internal registers to code 000H (0V).
If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800H (5V).
FIGURE 2. Basic Single-Supply Operation of the DAC7714.
+15V
DAC7714
+
1µF to 10µF
0.1µF
1
VCC
–10V to +10V
2
–10V to +10V
–10.0V
16
VOUTD
RESET
15
Reset DACs(1)
3
VOUTC
LOADDACS
14
Update Selected Register
4
VREFL
NIC
13
5
VREFH
CS
12
Chip Select
6
VOUTB
CLK
11
Clock
7
VOUTA
SDI
10
Serial Data In
8
VSS
GND
9
0.1µF
+10.0V
0.1µF
–10V to +10V
–10V to +10V
+5V
RESETSEL
–15V
+
1µF to 10µF
0.1µF
NOTE: (1) As configured, RESET LOW sets all internal registers to code 800H (0V).
If RESETSEL is LOW, RESET LOW sets all internal registers to code 000H (–10V).
FIGURE 3. Basic Dual-Supply Operation of the DAC7714.
Note that CS and CLK are combined with an OR gate and
the output controls the serial-to-parallel shift register internal to the DAC7714 (see the block diagram on the front of
this data sheet). These two inputs are completely interchangeable. In addition, care must be taken with the state of
CLK when CS rises at the end of a serial transfer. If CLK is
LOW when CS rises, the OR gate will provide a rising edge
to the shift register, shifting the internal data one additional
bit. The result will be incorrect data and possible selection of
the wrong DAC.
DIGITAL INTERFACE
Figure 4 and Table I provide the basic timing for the
DAC7714. The interface consists of a serial clock (CLK),
serial data (SDI), and a load DAC signal (LOADDACS). In
addition, a chip select (CS) input is available to enable serial
communication when there are multiple serial devices. An
asynchronous reset input (RESET) is provided to simplify
start-up conditions, periodic resets, or emergency resets to a
known state.
The DAC code and address are provided via a 16-bit serial
interface (see Figure 4). The first two bits select the DAC
register that will be updated when LOADDACS goes LOW
(see Table II). The next two bits are not used. The last 12 bits
is the DAC code which is provided, most significant bit first.
If both CS and CLK are used, then CS should rise only when
CLK is HIGH. If not, then either CS or CLK can be used to
operate the shift register. See Table III for more information.
®
13
DAC7714
(MSB)
SDI
A1
A0
X
X
D11
(LSB)
D10
D9
D3
D2
D1
D0
CLK
tcss
tCSH
tLD1
tLD2
CS
LOADDACS
tLDDW
tDS
tDH
SDI
tCL
tCH
CLK
tLDDW
LOADDACS
tS
tS
1 LSB
ERROR BAND
VOUT
1 LSB
ERROR BAND
tRSTW
RESET
tRSSH
RESETSEL
FIGURE 4. DAC7714 Timing.
SYMBOL
tDS
tDH
tCH
tCL
tCSS
tCSH
tLD1
tLD2
tLDDW
tRSSH
tRSTW
tS
DESCRIPTION
Data Valid to CLK Rising
Data Held Valid after CLK Rises
CLK HIGH
CLK LOW
CS LOW to CLK Rising
CLK HIGH to CS Rising
LOADDACS HIGH to CLK Rising
CLK Rising to LOADDACS LOW
LOADDACS LOW Time
RESETSEL Valid to RESET LOW
RESET LOW Time
Settling Time
MIN
25
20
30
50
55
15
40
15
45
25
70
10
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
A0
LOADDACS
RESET
L(1)
L
H
L
H
X
X
L
L
L
L
H
X
H(2)
H
H
H
H
L
A
B
C
D
NONE
ALL
L
H
H
X(3)
X
STATE OF
SELECTED
DAC
REGISTER
Transparent
Transparent
Transparent
Transparent
(All Latched)
Reset(4)
NOTES: (1) L = Logic LOW. (2) H = Logic HIGH. (3) X = Don’t Care.
(4) Resets to either 000H or 800 H , per the RESETSEL state
(LOW = 000H, HIGH = 800H). When RESET rises, all registers that are in
their latched state retain the reset value.
TABLE I. Timing Specifications (TA = –40°C to +85°C).
TABLE II. Control Logic Truth Table.
®
DAC7714
A1
SELECTED
DAC
REGISTER
14
CS(1)
CLK(1) LOADDACS
RESET
SERIAL SHIFT REGISTER
H(2)
X(3)
H
H
No Change
L(4)
L
H
H
No Change
L
↑(5)
H
H
Advanced One Bit
↑
L
H
H
Advanced One Bit
H(6)
X
L(7)
H
No Change
H(6)
X
H
L(8)
No Change
LAYOUT
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies.
As the DAC7714 offers single-supply operation, it will often
be used in close proximity with digital logic, microcontrollers,
microprocessors, and digital signal processors. The more
digital logic present in the design and the higher the switching speed, the more difficult it will be to achieve good
performance from the converter.
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X =
Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH
value is suggested in order to avoid a “false clock” from advancing the shift
register and changing the shift register. (7) If data is clocked into the serial
register while LOADDACS is LOW, the selected DAC register will change as
the shift register bits “flow” through A1 and A0. This will corrupt the data in
each DAC register that has been erroneously selected. (8) RESET LOW
causes no change in the contents of the serial shift register.
Because the DAC7714 has a single ground pin, all return
currents, including digital and analog return currents, must
flow through the GND pin. Ideally, GND would be connected directly to an analog ground plane. This plane would
be separate from the ground connection for the digital
components until they were connected at the power entry
point of the system.
TABLE III. Serial Shift Register Truth Table.
The power applied to VCC (as well as VSS, if not grounded)
should be well regulated and low noise. Switching power
supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In
addition, digital components can create similar high-frequency spikes as their internal logic switches states. This
noise can easily couple into the DAC output voltage through
various paths between the power connections and analog
output.
Digital Input Coding
The DAC7714 input data is in Straight Binary format. The
output voltage is given by the following equation:
VOUT = VREFL +
(VREFH – VREFL ) • N
4096
where N is the digital input code (in decimal). This equation
does not include the effects of offset (zero-scale) or gain
(full-scale) errors.
®
15
DAC7714
PACKAGE OPTION ADDENDUM
www.ti.com
20-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC7714U
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7714U
DAC7714U/1K
ACTIVE
SOIC
DW
16
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7714U
DAC7714UB
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7714U
B
DAC7714UB/1K
ACTIVE
SOIC
DW
16
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7714U
B
DAC7714UBG4
ACTIVE
SOIC
DW
16
40
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7714U
B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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