DAC7724
DAC7725
®
DAC
772
4
DAC
772
5
For most current data sheet and other product
information, visit www.burr-brown.com
12-Bit Quad Voltage Output
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
● LOW POWER: 250mW max
● SINGLE SUPPLY OUTPUT RANGE: +10V
● DUAL SUPPLY OUTPUT RANGE: ±10V
● SETTLING TIME: 10µs to 0.012%
● 12-BIT LINEARITY AND MONOTONICITY:
–40°C to +85°C
● RESET TO MID-SCALE (DAC7724) OR
ZERO-SCALE (DAC7725)
● DATA READBACK
● DOUBLE-BUFFERED DATA INPUTS
The DAC7724 and DAC7725 are 12-bit quad voltage
output digital-to-analog converters with guaranteed
12-bit monotonic performance over the specified temperature range. They accept 12-bit parallel input data,
have double-buffered DAC input logic (allowing simultaneous update of all DACs), and provide a readback
mode of the internal input registers. An asynchronous
reset clears all registers to a mid-scale code of 800H
(DAC7724) or to a zero-scale of 000H (DAC7725). The
DAC7724 and DAC7725 can operate from a single
+15V supply, or from +15V and –15V supplies.
APPLICATIONS
● PROCESS CONTROL
● CLOSED-LOOP SERVO-CONTROL
● MOTOR CONTROL
● DATA ACQUISITION SYSTEMS
GND
12
DB0-DB11
A0
A1
R/W
CS
I/O
Buffer
Control
Logic
Low power and small size per DAC make the DAC7724
and DAC7725 ideal for automatic test equipment,
DAC-per-pin programmers, data acquisition systems,
and closed-loop servo-control. The DAC7724 and
DAC7725 are available in a PLCC-28 or a SO-28
package, and offer guaranteed specifications over the
–40°C to +85°C temperature range.
VDD
VCC
VREFH
Input
Register A
DAC
Register A
DAC A
VOUTA
Input
Register B
DAC
Register B
DAC B
VOUTB
Input
Register C
DAC
Register C
DAC C
VOUTC
Input
Register D
DAC
Register D
DAC D
VOUTD
RESET
LDAC
VREFL
VSS
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
SBAS112
PDS-1517B
Printed in U.S.A. April, 2000
SPECIFICATION (DUAL SUPPLY)
At TA = –40°C to +85°C, VCC = +15V, VDD = +5V, VSS = –15V, VREFH = +10V, VREFL = –10V, unless otherwise noted.
DAC7724N, U
DAC7725N, U
PARAMETER
CONDITIONS
ACCURACY
Linearity Error
Linearity Matching(2)
Differential Linearity Error
Monotonicity
Zero-Scale Error
Zero-Scale Drift
Zero-Scale Matching(2)
Full-Scale Error
Full-Scale Matching(2)
Power Supply Sensitivity
ANALOG OUTPUT
Voltage Output(3)
Output Current
Load Capacitance
Short-Circuit Current
Short-Circuit Duration
TYP
MAX
MIN
TYP
±2
±2
±1
TMIN to TMAX
Code = 000H
±2
At Full Scale
✻
VREFH
No Oscillation
VREFL +1.25
–10
–0.5
–3.5
POWER SUPPLY REQUIREMENTS
VDD
VCC
VSS
I DD
I CC
I SS
Power Dissipation
TEMPERATURE RANGE
Specified Performance
✻
✻
+10
VREFH – 1.25
3.0
0
8
0.25
2
65
2.4
–0.3
3.6
0.0
✻
✻
✻
✻
✻
✻
10
–40
V
V
mA
mA
✻
µs
LSB
nV-s
nV/√Hz
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
V
✻
✻
✻
✻
✻
✻
V
V
V
µA
mA
mA
mW
✻
°C
✻
Straight Binary
–8
✻
✻
✻
✻
✻
VDD +0.3
0.8
VDD
0.4
+5.25
+15.75
–15.75
50
6
–6
180
V
mA
pF
mA
✻
TTL-Compatible CMOS
+4.75
+14.25
–14.25
✻
✻
✻
✻
✻
500
±20
Indefinite
To VSS, V CC, or GND
IIH ≤ ±10µA
IIL ≤ ±10µA
IOH = –0.8mA
I OL = 1.6mA
LSB(1)
LSB
LSB
Bits
LSB
ppm/°C
LSB
LSB
LSB
ppm/V
±1
✻
±1
10
VREFL
±5
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
VOH
VOL
Data Format
±1
±1
±1
✻
±2
±2
±2
f = 10kHz
UNITS
✻
Code = FFFH
To ±0.012%, 20V Output Step
Full-Scale Step
MAX
✻
12
1
REFERENCE INPUT
VREFH Input Range
VREFL Input Range
Ref High Input Current
Ref Low Input Current
DYNAMIC PERFORMANCE
Settling Time
Channel-to-Channel Crosstalk
Digital Feedthrough
Output Noise Voltage
MIN
DAC7724NB, UB
DAC7725NB, UB
✻
✻
✻
8.5
✻
250
+85
✻
✻
✻
✻
✻
NOTES: (1) LSB means Least Significant Bit, when VREFH equals +10V and VREFL equals –10V, then one LSB equals 4.88mV. (2) All DAC outputs will match within
the specified error band. (3) Ideal output voltage, does not take into account zero or full-scale error.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC7724, 7725
2
SPECIFICATION (SINGLE SUPPLY)
At TA = –40°C to +85°C, VCC = +15V, VDD = +5V, VSS = GND, VREFH = +10V, VREFL = 0V, unless otherwise noted.
DAC7724N, U
DAC7725N, U
PARAMETER
ACCURACY
Linearity Error(1)
Linearity Matching(3)
Differential Linearity Error
Monotonicity
Zero-Scale Error
Zero-Scale Drift
Zero-Scale Matching(3)
Full-Scale Error
Full-Scale Matching(3)
Power Supply Sensitivity
ANALOG OUTPUT
Voltage Output(4)
Output Current
Load Capacitance
Short-Circuit Current
Short-Circuit Duration
CONDITIONS
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels
VIH
VIL
VOH
VOL
Data Format
POWER SUPPLY REQUIREMENTS
VDD
VCC
IDD
ICC
Power Dissipation
TEMPERATURE RANGE
Specified Performance
TYP
MAX
MIN
TYP
±2
±2
±1
TMIN to TMAX
Code = 004H
±4
At Full Scale
✻
VREFH
No Oscillation
✻
✻
To VCC or GND
VREFL +1.25
0
–0.3
–2.0
+10
VREFH – 1.25
1.5
0
8
0.25
2
65
2.4
–0.3
3.6
0.0
✻
✻
✻
✻
✻
✻
10
V
mA
pF
mA
✻
✻
✻
✻
V
V
mA
mA
✻
µs
LSB
nV-s
nV/√Hz
✻
✻
TTL-Compatible CMOS
VDD +0.3
0.8
VDD
0.4
✻
✻
✻
✻
✻
✻
✻
✻
✻
V
V
V
V
✻
✻
✻
✻
V
V
µA
mA
mW
✻
°C
✻
Straight Binary
+4.75
14.25
✻
✻
✻
✻
500
±20
Indefinite
+5.25
15.75
✻
✻
✻
✻
✻
50
3.0
45
–40
LSB(2)
LSB
LSB
Bits
LSB
ppm/°C
LSB
LSB
LSB
ppm /V
±2
✻
±2
20
VREFL
±5
IIH ≤ ±10µA
IIL ≤ ±10µA
IOH = –0.8mA
IOL = 1.6mA
±1
±1
±1
✻
±4
±4
±4
f = 10kHz
UNITS
✻
Code = FFFH
To ±0.012%, 10V Output Step
MAX
✻
12
2
REFERENCE INPUT
VREFH Input Range
VREFL Input Range
Ref High Input Current
Ref Low Input Current
DYNAMIC PERFORMANCE
Settling Time(5)
Channel-to-Channel Crosstalk
Digital Feedthrough
Output Noise Voltage
MIN
DAC7724NB, UB
DAC7725NB, UB
+85
✻
NOTES: (1) If VSS = 0V, specification applies at code 004H and above. (2) LSB means Least Significant Bit, when VREFH equals +10V and VREFL equals 0V, then
one LSB equals 2.44mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage, does not take into account zero or full-scale error.
(5) Full-scale positive 10V step and negative step from code FFFH to 004H.
®
3
DAC7724, 7725
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
VCC to VSS ........................................................................... –0.3V to +32V
VCC to GND ......................................................................... –0.3V to +16V
VSS to GND ......................................................................... +0.3V to –16V
VDD to GND ............................................................................. –0.3V to 6V
VREFH to GND ....................................................................... –9V to +11V
VREFL to GND (VSS = –15V) ................................................. –11V to +9V
VREFL to GND (VSS = 0V) .................................................... –0.3V to +9V
VREFH to VREFL ....................................................................... –1V to +22V
Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V
Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ........................................ –40°C to +85°C
Storage Temperature Range ......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE/ORDERING INFORMATION
PRODUCT
MAXIMUM
LINEARITY
ERROR
(LSB)
MAXIMUM
DIFFERENTIAL
NONLINEARITY ERROR
(LSB)
DAC7724N
PACKAGE
PACKAGE
DRAWING
NUMBER
SPECIFICATION
TEMPERATURE
RANGE
±2
±1
PLCC-28
251
–40°C to +85°C
"
"
"
"
"
"
DAC7724NB
±1
±1
PLCC-28
251
–40°C to +85°C
"
"
"
"
"
"
±2
±1
SO-28
217
–40°C to +85°C
DAC7724U
"
"
"
"
"
"
DAC7724UB
±1
±1
SO-28
217
–40°C to +85°C
"
DAC7725N
"
"
"
"
"
±2
±1
PLCC-28
251
–40°C to +85°C
"
"
"
"
"
"
DAC7725NB
±1
±1
PLCC-28
251
–40°C to +85°C
"
DAC7725U
"
"
"
"
"
±2
±1
SO-28
217
–40°C to +85°C
"
"
"
"
"
"
DAC7725UB
±1
±1
SO-28
217
–40°C to +85°C
"
"
"
"
"
"
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
DAC7724N
DAC7724N/750
DAC7724NB
DAC7724NB/750
DAC7724U
DAC7724U/1K
DAC7724UB
DAC7724UB/1K
DAC7725N
DAC7725N/750
DAC7725NB
DAC7725NB/750
DAC7725U
DAC7725U/1K
DAC7725UB
DAC7725UB/1K
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /750 indicates 750 devices per reel). Ordering 750 pieces
of “DAC7724/750” will get a single 750-piece Tape and Reel.
ESD PROTECTION CIRCUITS
VCC
VCC
RefH
VOUT
RefL
VSS
VSS
1 of 4
VDD
VDD
Typ of Each
Logic Input Pin
Typ of Each
I/O Pin
®
DAC7724, 7725
4
GND
PIN CONFIGURATIONS
Top View
VREFH
1
28
VREFL
VOUTA
VOUTB
VREFH
VREFL
VOUTC
VOUTD
PLCC
VSS
SO
VOUTB
2
27
VOUTC
4
3
2
1
28
27
26
VOUTA
3
26
VOUTD
7
DAC7724
DAC7725
8
9
22
21
20
7
(LSB) DB0
8
DB1
9
23 CS
CS
A0
20 R/W
DB2 10
R/W
19
DB11 (MSB)
DB3 11
18
DB10
DB4 12
17
DB9
DB5 13
16
DB8
DB6 14
15
DB7
22 A0
21 A1
A1
DB2 10
DAC7724
DAC7725
19 DB11 (MSB)
DB3 11
12
13
14
15
16
17
18
DB10
23
LDAC
DB9
DB1
6
VDD
24 VDD
DB8
(LSB) DB0
24
6
DB7
LDAC
5
RESET
VCC
DB6
RESET
25
25 VCC
DB5
GND
4
5
DB4
VSS
GND
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1
VREFH
Reference Input Voltage High. Sets maximum output voltage for all DACs.
2
VOUTB
DAC B Voltage Output.
3
VOUTA
DAC A Voltage Output.
4
VSS
5
GND
6
RESET
7
LDAC
8
DB0
Negative Analog Supply Voltage, 0V or –15V.
Ground.
Asynchronous Reset Input. Sets DAC and input registers to either mid-scale (800H, DAC7724) or zero-scale (000H, DAC7725)
when LOW.
Load DAC Input. All DAC Registers are transparent when LOW.
Data Bit 0. Least significant bit of 12-bit word.
9
DB1
Data Bit 1
10
DB2
Data Bit 2
11
DB3
Data Bit 3
12
DB4
Data Bit 4
13
DB5
Data Bit 5
14
DB6
Data Bit 6
15
DB7
Data Bit 7
16
DB8
Data Bit 8
17
DB9
Data Bit 9
18
DB10
Data Bit 10
19
DB11
Data Bit 11. Most significant bit of 12-bit word.
20
R/W
Read/Write Control Input (read = HIGH, write = LOW).
21
A1
Register/DAC Select (C or D = HIGH, A or B = LOW).
22
A0
Register/DAC Select (B or D = HIGH, A or C = LOW).
23
CS
Chip Select Input.
24
VDD
Positive Digital Supply, +5V.
25
VCC
Positive Analog Supply Voltage, +15V nominal.
26
VOUTD
DAC D Voltage Output.
27
VOUTC
DAC C Voltage Output.
28
VREFL
Reference Input Voltage Low. Sets minimum output voltage for all DACs.
®
5
DAC7724, 7725
TYPICAL PERFORMANCE CURVES: VSS = 0V
At TA = +25°C, VCC = +15V, VDD = +5V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 85°C
(Typical of Each Output Channel)
DLE (LSB)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
LE (LSB)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
200H
400H
600H
800H
A00H
C00H
E00H
FFFH
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
200H
400H
800H
A00H
C00H
E00H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel –40°C
(Typical of Each Output Channel)
ZERO-SCALE ERROR vs TEMPERATURE
(Code 004H)
FFFH
2.0
1.5
DAC B
1.0
DAC D
DAC A
0.5
0
–0.5
DAC C
–1.0
–1.5
–2.0
200H
400H
600H
800H
A00H
C00H
E00H
–40 –30 –20 –10 0
FFFH
CURRENT vs CODE
All DACs Sent to Indicated Code
FULL-SCALE ERROR vs TEMPERATURE
(Code FFFH)
VREFH
VREF Current (mA)
2.0
1.5
1.0
DAC B
DAC D
DAC A
0.5
VREF Current (mA)
0
–0.5
DAC C
–1.0
–1.5
–2.0
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90
Temperature (°C)
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
000H
VREFL
200H
400H
600H
800H
A00H
Digital Input Code
®
DAC7724, 7725
10 20 30 40 50 60 70 80 90
Temperature (°C)
Digital Input Code
Full-Scale Error (mV)
600H
Digital Input Code
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
Digital Input Code
Zero-Scale Error (mV)
DLE (LSB)
LE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 25°C
(Typical of Each Output Channel)
6
C00H
E00H
FFFH
TYPICAL PERFORMANCE CURVES: VSS = 0V
(Cont.)
At TA = +25°C, VCC = +15V, VDD = +5V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
POSITIVE SUPPLY CURRENT
vs DIGITAL INPUT CODE
POWER SUPPLY CURRENT vs TEMPERATURE
4.0
3.00
2.50
3.0
2.5
No Load
ICC (mA)
2.00
2.0
1.5
1.0
1.50
1.00
0.5
IDD
0.50
0
IDD
–0.5
–40 –30 –20 –10 0
0
000H
10 20 30 40 50 60 70 80 90 100
200H
400H
600H
800H
A00H C00H E00H FFFH
Temperature (°C)
Digital Input Code
OUTPUT VOLTAGE vs SETTLING TIME
(0V to +10V)
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to 0V)
Large Signal Settling Time: 5V/div
Output Voltage
Output Voltage
Large Signal Settling Time: 5V/div
Small Signal Settling Time: 1LSB/div
Small Signal
Settling Time: 1LSB/div
+5V
LDAC
0
+5V
LDAC
0
Time (2µs/div)
Time (2µs/div)
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
Output Voltage (200mV/div)
Output Voltage (200mV/div)
Quiescent Current (mA)
ICC
ICC
3.5
7FFH to 800H
+5V
LDAC
0
Time (1µs/div)
800H to 7FFH
+5V
LDAC
0
Time (1µs/div)
®
7
DAC7724, 7725
TYPICAL PERFORMANCE CURVES: VSS = 0V
(Cont.)
At TA = +25°C, VCC = +15V, VDD = +5V, VSS = 0V, VREFH = +10V, VREFL = 0V, representative unit, unless otherwise specified.
LOGIC SUPPLY CURRENT
vs LOGIC INPUT LEVEL FOR DATA BITS
OUTPUT NOISE vs FREQUENCY
1000
Logic Supply Current (mA)
5
Noise (nV/√Hz)
Code 004H
100
Code FFFH
10
4
3
2
1
0
0
0.1
1
10
100
Frequency (kHz)
1000
10000
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Logic Input Level for Data Bits (V)
OUTPUT VOLTAGE vs RLOAD
SINGLE SUPPLY CURRENT LIMIT vs INPUT CODE
16
20
14
15
12
Short to Ground
10
IOUT (mA)
10
8
6
4
5
0
–5
–10
2
Short to VCC
–15
Sink
0
0.01
0.1
1
10
–20
000H
100
200H
400H
RLOAD (kW)
600H
800H
A00H C00H
Digital Input Code
POWER SUPPLY REJECTION RATIO vs FREQUENCY
0
–10
PSRR (dB)
VOUT (V)
Source
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
+15V
+5V
101
102
103
104
Frequency (Hz)
®
DAC7724, 7725
8
105
106
E00H FFFH
TYPICAL PERFORMANCE CURVES: VSS = –15V
At TA = +25°C, VCC = +15V, VDD = +5V, VSS = –15V, VREFH = +10V, VREFL = –10V, representative unit, unless otherwise specified.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 85°C
(Typical of Each Output Channel)
DLE (LSB)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
LE (LSB)
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
200H
400H
600H
800H
A00H
C00H
E00H
FFFH
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
400H
600H
800H
A00H
C00H
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel –40°C
(Typical of Each Output Channel)
CURRENT vs CODE
All DACs Sent to Indicated Code
VREF Current (mA)
VREF Current (mA)
200H
400H
600H
800H
A00H
C00H
E00H
E00H
FFFH
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
000H
VREFL
200H
400H
600H
800H
A00H
C00H
E000H FFFH
Digital Input Code
Digital Input Code
BIPOLAR ZERO-SCALE ERROR vs TEMPERATURE
(Code 800H)
POSITIVE FULL-SCALE ERROR vs TEMPERATURE
(Code FFFH)
2.0
1.5
1.5
1.0
DAC A
DAC B
0.5
0
DAC D
–1.0
FFFH
VREFH
2.5
2.0
1.5
1.0
0.5
0
–0.5
2.0
–0.5
200H
Digital Input Code
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
000H
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
Digital Input Code
Positive Full-Scale Error (mV)
Bipolar Zero-Scale Error (mV)
DLE (LSB)
LE (LSB)
DLE (LSB)
LE (LSB)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
Single Channel 25°C
(Typical of Each Output Channel)
DAC C
–1.5
–2.0
1.0
DAC B
0.5
DAC D
0
–0.5
DAC A
–1.0
DAC C
–1.5
–2.0
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90
–40 –30 –20 –10 0
Temperature (°C)
10 20 30 40 50 60 70 80 90
Temperature (°C)
®
9
DAC7724, 7725
TYPICAL PERFORMANCE CURVES: VSS = –15V
(Cont.)
At TA = +25°C, VCC = +15V, VDD = +5V, VSS = –15V, VREFH = +10V, VREFL = –10V, representative unit, unless otherwise specified.
NEGATIVE FULL-SCALE ERROR vs TEMPERATURE
(Code 000H)
POWER SUPPLY CURRENT vs TEMPERATURE
1.5
1.0
Quiescent Current (mA)
Negative Full-Scale Error (mV)
2.0
DAC B
DAC D
DAC A
0.5
0
–0.5
DAC C
–1.0
–1.5
–2.0
–40 –30 –20 –10 0
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
ICC
Data = FFFH (all DACs)
No Load
IDD
ISS
–40 –30 –20 –10 0
10 20 30 40 50 60 70 80 90
OUTPUT VOLTAGE vs RLOAD
15
10
Supply Current (mA)
Source
0
–5
Sink
–10
0.1
1
10
100
SUPPLY CURRENT vs CODE
6
ICC
5
4
Data = FFFH (all DACs)
3
No Load
2
1
0
IDD
–1
–2
–3
–4
ISS
–5
–6
000H 200H 400H 600H 800H A00H C00H E00H FFFH
RLOAD (kΩ)
Digital Input Code
OUTPUT VOLTAGE vs SETTLING TIME
(–10V to +10V)
OUTPUT VOLTAGE vs SETTLING TIME
(+10V to –10V)
Output Voltage
Large Signal
Settling Time: 5V/div
Output Voltage
VOUT (V)
5
–15
0.01
10 20 30 40 50 60 70 80 90
Temperature (°C)
Temperature (°C)
Small Signal
Settling Time: 0.5LSB/div
Small Signal
Settling Time: 0.5LSB/div
Large Signal
Settling Time: 5V/div
+5V
LDAC
0
+5V
LDAC
0
Time (2µs/div)
Time (2µs/div)
®
DAC7724, 7725
10
TYPICAL PERFORMANCE CURVES: VSS = –15V
(Cont.)
At TA = +25°C, VCC = +15V, VDD = +5V, VSS = –15V, VREFH = +10V, VREFL = –10V, representative unit, unless otherwise specified.
DUAL SUPPLY CURRENT LIMIT vs INPUT CODE
SHORT TO GROUND
POWER SUPPLY REJECTION RATIO vs FREQUENCY
0
–10
–20
20
15
5
PSRR (dB)
IOUT (mA)
10
0
–5
–15V
+15V
–80
–90
–100
–110
–120
–10
–15
200H
400H
600H
800H
A00H C00H
+5V
101
E00H FFFH
102
103
104
OUTPUT VOLTAGE
MID-SCALE GLITCH PERFORMANCE
BROADBAND NOISE
7FFH to 800H
Noise Voltage (500µV/div)
Digital Input Code
Frequency (Hz)
Output Voltage (200mV/div)
–20
000H
–30
–40
–50
–60
–70
800H to 7FFH
106
BW = 1MHz
Code = 800H
+5V
LDAC
0
Time (1µs/div)
105
Time (1ms/div)
OUTPUT NOISE vs FREQUENCY
DATA BUS FEEDTHROUGH GLITCH
Output Voltage (20mV/div)
Noise (nV/√Hz)
1000
100
Noise at any code
+5V
DATA BUS
0
10
0
0.1
1
10
100
Frequency (kHz)
1000
10000
Time (0.5µs/div)
®
11
DAC7724, 7725
THEORY OF OPERATION
output (“full-scale”) are set by the external voltage references (VREFL and VREFH, respectively). The digital input is
a 12-bit parallel word and the DAC input registers offer a
readback capability. The converters can be powered from a
single +15V supply or a dual ±15V supply. Each device
offers a reset function which immediately sets all DAC
registers and DAC output voltages to mid-scale (DAC7724,
code 800H) or to zero-scale (DAC7725, code 000H). See
Figures 2 and 3 for the basic operation of the DAC7724/25.
The DAC7724 and DAC7725 are quad voltage output,
12-bit digital-to-analog converters (DACs). The architecture
is a classic R-2R ladder configuration followed by an operational amplifier that serves as a buffer, as shown in Figure 1.
Each DAC has its own R-2R ladder network and output opamp, but all share the reference voltage inputs. The minimum voltage output (“zero-scale”) and maximum voltage
RF
R
R
2R
2R
R
2R
2R
R
2R
R
R
2R
VOUT
R
2R
2R
2R
VREFH
VREFL
FIGURE 1. DAC7724/25 Architecture.
DAC7724
DAC7725
+10.00V
0.1µF
+15V
1
VREFH
VREFL
28
2
VOUTB
VOUTC
27
3
VOUTA
VOUTD
26
4
VSS
VCC
25
5
GND
VDD
24
Reset DACs(1)
6
RESET
CS
23
Chip Select
Load DAC Registers
7
LDAC
A0
22
8
DB0
A1
21
Address Bus
or Decoder
9
DB1
R/W
20
10
DB2
DB11
19
11
DB3
DB10
18
12
DB4
DB9
17
13
DB5
DB8
16
14
DB6
DB7
15
0V to +10V
0V to +10V
Data Bus
0V to +10V
0.1µF
+5V
Read/Write
Data Bus
NOTE: (1) Reset LOW sets all DACs to code 800H on the DAC7724 and to code 000H on the DAC7725.
®
DAC7724, 7725
12
1µF to 10µF
0V to +10V
0.1µF
FIGURE 2. Basic Single-Supply Operation of the DAC7724/25.
+
+
1µF to 10µF
DAC7724
DAC7725
+10.000V
–10.000V
0.1µF
–10V to +10V
–15V
+
–10V to +10V
1µF to 10µF
0.1µF
+15V
1
VREFH
VREFL
28
2
VOUTB
VOUTC
27
–10V to +10V
3
VOUTA
VOUTD
26
–10V to +10V
4
VSS
VCC
25
VDD
24
0.1µF
+
1µF to 10µF
+5V
0.1µF
5
GND
DACs(1)
6
RESET
CS
23
Chip Select
Load DAC Registers
7
LDAC
A0
22
8
DB0
A1
21
Address Bus
or Decoder
9
DB1
R/W
20
10
DB2
DB11
19
11
DB3
DB10
18
12
DB4
DB9
17
13
DB5
DB8
16
14
DB6
DB7
15
Reset
Data Bus
0.1µF
+
1µF to 10µF
Read/Write
Data Bus
NOTE: (1) Reset LOW sets all DACs to code 800H on the DAC7724 and to code 000H on the DAC7725.
FIGURE 3. Basic Dual-Supply Operation of the DAC7724/25.
ANALOG OUTPUTS
tially, the offset of the output op-amp). The maximum
output is equal to VREFH plus a similar offset voltage. Note
that VSS (the negative power supply) must either be connected to ground or must be in the range of –14.25V to
–15.75V. The voltage on VSS sets several bias points within
the converter, if VSS is not in one of these two configurations, the bias values may be in error and proper operation
of the device is not guaranteed.
When VSS = –15V (dual supply operation), the output
amplifier can swing to within 4V of the supply rails, guaranteed over the –40°C to +85°C temperature range. With
VSS = 0V (single-supply operation) and RLOAD connected to
ground, the output can swing to ground. Note that the
settling time of the output op-amp will be longer with
voltages very near ground. Additionally, care must be taken
when measuring the zero-scale error when VSS = 0V. Since
the output voltage cannot swing below ground, the output
voltage may not change for the first few digital input codes
(000H, 001H, 002H, etc.) if the output amplifier has a negative offset. At the negative offset limit of –4 LSB (-9.76mV),
for the single-supply case, the first specified output starts at
code 004H.
The current into the VREFH input and out of VREFL depends
on the DAC output voltages and can vary from a few
microamps to approximately 0.3mA. The reference input
appears as a varying load to the reference. If the reference
can sink or source the required current, a reference buffer is
not required. See “Reference Current vs Code” in the Typical Performance Curves.
The analog supplies (or the analog supplies and the reference power supplies) have to come up first. If the power
supplies for the references come up first, then the VCC and
VSS supplies will be “powered from the reference via the
ESD protection diodes” (see page 4).
REFERENCE INPUTS
For dual-supply operation, the reference inputs, VREFL and
VREFH, can be any voltage between VSS + 4V and VCC – 4V
provided that VREFH is at least 1.25V greater than VREFL.
For single-supply operation (VSS = 0V), VREFL value can be
above 0V, with the same provision that VREFH is at least
1.25V greater than VREFL. The minimum output of each
DAC is equal to VREFL plus a small offset voltage (essen-
Bypassing the reference voltage or voltages with at least a
0.1uF capacitor placed as close to the DAC7724/25 package
is strongly recommended.
®
13
DAC7724, 7725
DIGITAL INTERFACE
The double buffered architecture is mainly designed so that
each DAC Input Register can be written at any time and then
all DAC output voltages updated simultaneously by pulling
LDAC LOW. It also allows a DAC Input Register to be
written to at any point and the DAC voltage to be synchronously changed via a trigger signal connected to LDAC.
Table I shows the basic control logic for the DAC7724/25.
Note that each internal register is level triggered and not
edge triggered. When the appropriate signal is LOW, the
register becomes transparent. When this signal is returned
HIGH, the digital word currently in the register is latched.
The first set of registers (the Input Registers) are triggered
via the A0, A1, R/W, and CS inputs. Only one of these
registers is transparent at any given time. The second set of
registers (the DAC Registers) are all transparent when LDAC
input is pulled LOW.
DIGITAL TIMING
Figure 4 and Table II provide detailed timing for the digital
interface of the DAC7724 and DAC7725.
DIGITAL INPUT CODING
The DAC7724 and DAC7725 input data is in straight binary
format. The output voltage is given by the following equation:
– V REFL ) • N
(V
V OUT = V REFL + REFH
4096
Each DAC can be updated independently by writing to the
appropriate Input Register and then updating the DAC
Register. Alternatively, the entire DAC Register set can be
configured as always transparent by keeping LDAC LOW—
the DAC update will occur when the Input Register is
written.
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) errors.
A1
A0
L(1)
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
L
H
H
L
L
H
H
L
L
H
H
X(3)
X
X
R/W
L
L
L
L
L
L
L
L
H
H
H
H
X
X
X
CS
RESET
LDAC
SELECTED
INPUT
REGISTER
L
L
L
L
L
L
L
L
L
L
L
L
H
H
X
H(2)
L
L
L
L
H
H
H
H
H
H
H
H
L
H
X
A
B
C
D
A
B
C
D
A
B
C
D
NONE
NONE
ALL
H
H
H
H
H
H
H
H
H
H
H
H
H
L
STATE OF
SELECTED
INPUT
REGISTER
STATE OF
ALL DAC
REGISTERS
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Readback
Readback
Readback
Readback
(All Latched)
(All Latched)
Reset(4)
Transparent
Transparent
Transparent
Transparent
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Latched
Transparent
Latched
Reset(4)
NOTES: (1) L = Logic LOW. (2) H= Logic HIGH. (3) X = Don’t Care. (4) DAC7724 resets to 800H, DAC7725 resets to 000H. When RESET rises, all registers
that are in their latched state retain the reset value.
TABLE I. DAC7724 and DAC7725 Control Logic Truth Table.
®
DAC7724, 7725
14
tLD
tWCS
CS
tWS
tWH
tAS
tAH
R/W
tRCS
CS
A0/A1
tRDH
tRDS
tLWD
R/W
tAH
tAS
LDAC
±0.012% of FSR
Error Band
tDH
tDS
A0/A1
Data In
tDZ
tS
Data Valid
Data Out
tCSD
VOUT
Data Read Timing
Data Write Timing
±0.012% of FSR
Error Band
tRESET
RESET
tS
+FS
±0.012% of FSR
Error Band
VOUT, DAC7725
–FS
+FS
VOUT, DAC7724
Mid-Scale
–FS
±0.012% of FSR
Error Band
DAC7724/25 Reset Timing
FIGURE 4. Digital Input and Output Timing.
SYMBOL
DESCRIPTION
MIN
tRCS
tRDS
tRDH
tDZ
tCSD
tWCS
tWS
tWH
tAS
t AH
t LD
t DS
tDH
tLWD
CS LOW for Read
R/W HIGH to CS LOW
R/W HIGH after CS HIGH
CS HIGH to Data Bus in High Impedance
CS LOW to Data Bus Valid
CS LOW for Write
R/W LOW to CS LOW
R/W LOW after CS HIGH
Address Valid to CS LOW
Address Valid after CS HIGH
LDAC Delay from CS HIGH
Data Valid to CS LOW
Data Valid after CS HIGH
LDAC LOW
RESET LOW Time
Settling Time
200
10
10
tRESET
tS
TYP
100
100
MAX
160
50
0
0
0
0
10
0
0
50
50
10
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
TABLE II. Timing Specifications (TA = –40°C to +85°C).
®
15
DAC7724, 7725
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
DAC7724N
ACTIVE
PLCC
FN
28
37
RoHS & Green
Call TI
Level-3-245C-168 HR
-40 to 85
DAC7724N
Samples
DAC7724NB
ACTIVE
PLCC
FN
28
37
RoHS & Green
Call TI
Level-3-245C-168 HR
-40 to 85
DAC7724N
B
Samples
DAC7724NB/750
ACTIVE
PLCC
FN
28
750
RoHS & Green
Call TI
Level-3-245C-168 HR
-40 to 85
DAC7724N
B
Samples
DAC7724U
ACTIVE
SOIC
DW
28
20
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7724U
B
Samples
DAC7724U/1K
ACTIVE
SOIC
DW
28
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7724U
B
Samples
DAC7724UB
ACTIVE
SOIC
DW
28
20
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7724U
B
Samples
DAC7724UB/1K
ACTIVE
SOIC
DW
28
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7724U
B
Samples
DAC7725NB
ACTIVE
PLCC
FN
28
37
RoHS & Green
Call TI
Level-3-245C-168 HR
-40 to 85
DAC7725N
B
Samples
DAC7725NB/750
ACTIVE
PLCC
FN
28
750
RoHS & Green
Call TI
Level-3-245C-168 HR
-40 to 85
DAC7725N
B
Samples
DAC7725NB/750G4
ACTIVE
PLCC
FN
28
750
RoHS & Green
Call TI
Level-3-245C-168 HR
-40 to 85
DAC7725N
B
Samples
DAC7725U
ACTIVE
SOIC
DW
28
20
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7725U
B
Samples
DAC7725UB
ACTIVE
SOIC
DW
28
20
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7725U
B
Samples
DAC7725UB/1K
ACTIVE
SOIC
DW
28
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7725U
B
Samples
DAC7725UB/1KG4
ACTIVE
SOIC
DW
28
1000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DAC7725U
B
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
