DAC7734ECG4

DAC7734 DAC 773 4 www.ti.com SBAS138A – DECEMBER 1999 – REVISED OCTOBER 2008 16-Bit, Quad Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● LOW POWER: 200mW ● UNIPOLAR OR BIPOLAR OPERATION ● SINGLE SUPPLY OUTPUT RANGE: +10V ● DUAL SUPPLY OUTPUT RANGE: ±10V ● SETTLING TIME: 10µs to 0.003% ● 16-BIT MONOTONICITY: –40°C to +85°C ● PROGRAMMABLE RESET TO MID-SCALE OR ZERO-SCALE ● DOUBLE-BUFFERED DATA INPUTS ● ±1 LSB DNL: –40°C to +85°C The DAC7734 is a 16-bit, quad voltage output, digital-toanalog converter (DAC) with ensured 16-bit monotonic performance over the specified temperature range. It accepts 24-bit serial input data, has double-buffered DAC input logic (allowing simultaneous update of all DACs), and provides a serial data output for daisy-chaining multiple DACs. Programmable asynchronous reset clears all registers to a mid-scale code of 8000h or to a zero-scale of 0000h. The DAC7734 can operate from a single +15V supply or from +15V and –15V, and +5V supplies. Low power and small size per DAC make the DAC7734 ideal for automatic test equipment, DAC-per-pin programmers, data acquisition systems, and closed-loop servo-control. The DAC7734 is available in a 48-lead SSOP package and offers ensured specifications over the –40°C to +85°C temperature range. APPLICATIONS ● PROCESS CONTROL ● ATE PIN ELECTRONICS ● CLOSED-LOOP SERVO-CONTROL ● MOTOR CONTROL ● DATA ACQUISITION SYSTEMS ● DAC-PER-PIN PROGRAMMERS VDD VSS VREFL AB Sense VCC VREFL AB VREFH AB VREFH AB Sense DAC7734 SDI Shift Register Input Register A DAC Register A Input Register B DAC Register B DAC A VOUTA SDO VOUTA Sense DAC B VOUTB VOUTB Sense CS Input Register C DAC Register C Input Register D DAC Register D DAC C VOUTC CLOCK RST RESTSEL Control Logic LDAC VOUTC Sense DAC D VOUTD LOAD VOUTD Sense AGND VREFL CD Sense DGND VREFL CD VREFH CD VREFH CD Sense Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 1999-2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com SPECIFICATIONS (Dual Supply) At TA = TMIN to TMAX, VCC = +15V, VDD = +5V, VSS = –15V, VREFH = +10V, and VREFL = –10V, unless otherwise noted. DAC7734E PARAMETER ACCURACY Linearity Error (INL) TMIN to TMAX Linearity Match Differential Linearity Error (DNL) TMIN to TMAX Monotonicity, TMIN to TMAX Bipolar Zero Error Bipolar Zero Error, TMIN to TMAX Full-Scale Error Full-Scale Error, TMIN to TMAX Bipolar Zero Matching Full-Scale Matching Power Supply Rejection Ratio (PSRR) ANALOG OUTPUT Voltage Output Output Current Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration CONDITIONS Channel-to-Channel Crosstalk Digital Feedthrough Output Noise Voltage MAX MIN TYP ±3 ±4 DAC7734EC MAX MIN TYP ✻ ✻ MAX UNITS ±2 ±3 ±0.025 ±0.05 ±0.025 ±0.05 ±0.024 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ LSB LSB LSB LSB LSB Bits % of FSR % of FSR % of FSR % of FSR % of FSR Channel-to-Channel Matching ±0.024 ✻ ✻ % of FSR At Full Scale 25 ✻ ✻ ppm/V ✻ V mA pF mA ✻ ✻ V V mA mA ✻ µs ±4 14 T = 25°C Channel-to-Channel Matching VREFL ±5 VREFH VREFL + 1.25 –10 –0.3 –3.2 To ±0.003%, 20V Output Step See Figure 5 9 TEMPERATURE RANGE Specified Performance 3.6 +4.75 +14.25 –14.25 –40 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ 11 ✻ ✻ ✻ ✻ ✻ ✻ ✻ 0.7 • VDD 0 POWER SUPPLY VDD VCC VSS IDD ICC ISS Power ✻ ✻ 0.5 2 60 f = 10kHz ✻ ✻ ✻ ✻ +10 VREFH – 1.25 2.6 –0.3 VDD 0.3 • VDD ±10 ±10 +5.25 +15.75 –15.75 ✻ ✻ ✻ 200 +85 LSB nV-s nV/√Hz ✻ V V µA µA ✻ ✻ ✻ 0.4 +5.0 +15.0 –15.0 50 6 –5 170 ✻ ✻ ✻ ✻ ✻ 4.5 0.3 ±1 ±1 16 ✻ ✻ 500 ±20 Indefinite To VSS, VCC or GND IOH = –0.8mA IOL = 1.6mA ±2 ±2 15 ±0.01 T = 25°C ±2 ✻ ±3 ±3 T = 25°C DIGITAL INPUT VIH VIL IIH IIL DIGITAL OUTPUT VOH VOL TYP T = 25°C REFERENCE INPUT Ref High Input Voltage Range Ref Low Input Voltage Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time MIN DAC7734EB ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V ✻ ✻ ✻ V V V µA mA mA mW ✻ °C ✻ Specifications same as grade to the left. 2 DAC7734 www.ti.com SBAS138A SPECIFICATIONS (Single Supply) At TA = TMIN to TMAX, VCC = +15V, VDD = +5V, VSS = GND, VREFH = +10V, and VREFL = +50mV, unless otherwise noted. DAC7734E PARAMETER ACCURACY Linearity Error(1) (INL) TMIN to TMAX Linearity Match Differential Linearity Error (DNL) TMIN to TMAX Monotonicity, TMIN to TMAX Unipolar Zero Unipolar Zero Error, TMIN to TMAX Full-Scale Error Full-Scale Error, TMIN to TMAX Unipolar Zero Matching Full-Scale Matching Power Supply Rejection Ratio (PSRR) ANALOG OUTPUT Voltage Output Output Current Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration CONDITIONS Channel-to-Channel Crosstalk Digital Feedthrough Output Noise Voltage MAX MIN TYP ±3 ±4 DAC7734EC MAX MIN TYP ✻ ✻ MAX UNITS ±2 ±3 ±0.025 ±0.05 ±0.025 ±0.05 ±0.024 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ LSB LSB LSB LSB LSB Bits % of FSR % of FSR % of FSR % of FSR % of FSR Channel-to-Channel Matching ±0.024 ✻ ✻ % of FSR At Full Scale 25 ✻ ✻ ppm/V ✻ V ±4 14 T = 25°C Channel-to-Channel Matching VREFL = 0V, VSS = 0V R = 10kΩ 0 VREFH ±5 To ±0.003%, 10V Output Step See Figure 6 TEMPERATURE RANGE Specified Performance +4.75 +14.25 –40 ✻ ✻ ✻ ✻ ✻ ✻ ✻ +5.25 +15.75 ✻ ✻ 70 +85 ✻ µs LSB nV-s nV/√Hz ✻ V V µA µA ✻ ✻ ✻ 0.4 +5.0 +15.0 0 50 3.5 50 V V mA mA ✻ ✻ ✻ ✻ ✻ 4.5 0.3 ✻ ✻ ✻ ✻ ✻ ✻ ✻ VDD 0.3 • VDD ±10 ±10 mA pF mA ✻ ✻ ✻ ✻ ✻ 10 0.7 • VDD 0 POWER SUPPLY VDD VCC VSS IDD ICC Power ✻ ✻ ✻ 0.5 2 60 3.6 ✻ ✻ ✻ ✻ +10 VREFH – 1.25 1.0 –0.3 8 f = 10kHz ✻ ✻ VREFL + 1.25 0 –0.3 –1.5 ±1 ±1 16 ✻ 500 ±20 Indefinite To VCC or GND IOH = –0.8mA IOL = 1.6mA ±2 ±2 15 ±0.01 T = 25°C ±2 ✻ ±3 ±3 T = 25°C DIGITAL INPUT VIH VIL IIH IIL DIGITAL OUTPUT VOH VOL TYP T = 25°C REFERENCE INPUT Ref High Input Voltage Range Ref Low Input Voltage Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time MIN DAC7734EB ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V ✻ ✻ V V V µA mA mW ✻ °C ✻ Specifications same as grade to the left. NOTE: (1) If VSS = 0V, the specification applies at code 0021H and above, due to possible negative zero scale error. DAC7734 SBAS138A www.ti.com 3 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) VCC to VSS ........................................................................... –0.3V to +32V VCC to AGND ...................................................................... –0.3V to +16V VSS to AGND ...................................................................... +0.3V to –16V AGND to DGND ................................................................. –0.3V to +0.3V VREFH to AGND ..................................................................... –9V to +11V VREFL to AGND ...................................................................... –11V to +9V VDD to GND ........................................................................... –0.3V to +6V VREFH to VREFL ........................................................................ –1V to 22V Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION(1) PRODUCT LINEARITY ERROR (LSB) DIFFERENTIAL NONLINEARITY (LSB) DAC7734E PACKAGE PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE ±4 ±3 SSOP-48 333 –40°C to +85°C " " " " " " DAC7734EB ±4 ±2 SSOP-48 333 –40°C to +85°C " " " " " " DAC7734EC ±3 ±1 SSOP-48 333 –40°C to +85°C " " " " " " ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DAC7734E DAC7734E/1K Rails, 30 Tape and Reel, 1000 DAC7734EB DAC7734EB/1K Rails, 30 Tape and Reel, 1000 DAC7734EC DAC7734EC/1K Rails, 30 Tape and Reel, 1000 NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ESD PROTECTION CIRCUITS VCC VCC VOUT Sense RefH RefH Sense VOUT AGND RefL Sense RefL VSS VSS 1 of 2 1 of 4 VDD VDD Typ of Each Logic Input Pin DGND DGND SDO 4 DAC7734 www.ti.com SBAS138A PIN CONFIGURATION PIN DESCRIPTIONS Top View NC SSOP 1 48 VOUTA Sense PIN NAME DESCRIPTION 1 NC No Connection 2 NC No Connection 3 SDI DGND Serial Data Input NC 2 47 VOUTA 4 SDI 3 46 AGND 5 CLK 6 DGND Digital Ground 7 LDAC DAC Register Load Control, Rising Edge Triggered Digital Ground Data Clock Input DGND 4 45 VSS CLK 5 44 VREFL AB Sense 8 DGND Digital Ground DGND 6 43 VREFL AB 9 LOAD DAC Input Register Load Control, Active Low LDAC 7 42 VREFH AB 10 DGND Digital Ground 11 CS DGND DGND 8 41 VREFH AB Sense 12 LOAD 9 40 VOUTB Sense 13 SDO 14 DGND 15 RSTSEL 16 DGND 17 RST DGND 10 39 VOUTB CS 11 38 VOUTC Sense DGND 12 37 VOUTC DAC7734 Chip Select, Active Low Digital Ground Serial Data Output Digital Ground Reset Select. Determines the action of RST. If HIGH, a RST common will set the DAC registers to mid-scale (8000H). If LOW, a RST command will set the DAC registers to zero (0000H). Digital Ground SDO 13 36 VREFH CD Sense DGND 14 35 VREFH CD RSTSEL 15 34 VREFL CD 18 DGND Digital Ground DGND 16 33 VREFL CD Sense 19 NC No Connection 20 NC No Connection RST 17 32 VOUTD Sense 21 DGND Digital Ground DGND 18 31 VOUTD 22 DGND 23 VDD Digital +5V Power Supply 24 VDD Digital +5V Power Supply 25 VCC Analog +15V Power Supply 26 VCC Analog +15V Power Supply 27 AGND NC 19 30 VSS NC 20 29 VSS DGND 21 28 AGND DGND 22 27 AGND 28 AGND VDD 23 26 VCC 29 VSS VDD 24 25 VCC 30 VSS 31 VOUTD 32 VOUTD Sense 33 VREFL CD Sense 34 VREFL CD 35 VREFH CD 36 VREFH CD Sense 37 VOUTC 38 VOUTC Sense Digital Ground Analog Ground Analog Ground Analog –15V Power Supply or 0V Single Supply Analog –15V Power Supply or 0V Single Supply DAC D Output Voltage DAC D’s Output Amplifier Inverting Input. Used to close feedback loop at load. DAC C and D Reference Low Sense Input DAC C and D Reference Low Input DAC C and D Reference High Input DAC C and D Reference High Sense Input DAC C Output Voltage DAC C’s Output Amplifier Inverting Input. Used to close the feedback loop at the load. 39 VOUTB 40 VOUTB Sense 41 VREFH AB Sense 42 VREFH AB DAC A and B Reference High Input 43 VOUTL AB DAC A and B Reference Low Input 44 VREFL AB Sense 45 VSS 46 AGND Analog Ground 47 VOUTA DAC A Output Voltage 48 VOUTA Sense DAC7734 SBAS138A Reset, Rising Edge Triggered. Depending on the state of RSTSEL, the DAC registers are set to either mid-scale or zero. www.ti.com DAC B Output Voltage DAC B’s Output Amplifier Inverting Input. Used to close the feedback loop at the load. DAC A and B Reference High Sense Input DAC A and B Reference Low Sense Input Analog –15V Power Supply or 0V Single Supply DAC A’s Output Amplifier Inverting Input. Used to close the feedback loop at the load. 5 TYPICAL PERFORMANCE CURVES: VSS = 0V At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified. DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +85°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 6 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 Digital Input Code LE (LSB) LE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 +85°C DLE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) DLE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) +25°C 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code DAC7734 www.ti.com SBAS138A TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified. +85°C (cont.) DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, –40°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, –40°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code DAC7734 SBAS138A 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 Digital Input Code LE (LSB) LE (LSB) DLE (LSB) LE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –40°C DLE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +85°C) DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +85°C) www.ti.com 7 TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified. POSITIVE FULL-SCALE ERROR vs TEMPERATURE ZERO-SCALE ERROR vs TEMPERATURE 2 Code (FFFFH) Code (0000 (0040H) 1.5 Positive Full-Scale Error (mV) Negative Full-Scale Error (mV) 2 1 DAC A 0.5 0 DAC C –0.5 DAC B DAC D –1 –1.5 –2 0 10 20 30 40 50 60 70 80 DAC D 0.5 0 –0.5 DAC C DAC A –1 –1.5 90 –40 –30 –20 –10 0 10 20 30 40 50 60 70 REFERENCE CURRENT vs CODE All DACs Sent to Indicated Code (DAC A and B) VREFH REFERENCE CURRENT vs CODE All DACs Sent to Indicated Code (DAC C and D) VREFH VREFL 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH VREF (Current (mA) VREF (Current (mA) VREF (Current (mA) Temperature (°C) VREF (Current (mA) Temperature (°C) 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 80 90 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 VREFL 0 –0.2 –0.4 –0.6 –0.8 –1.0 –1.2 –1.4 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code POWER SUPPLY CURRENT vs TEMPERATURE POSITIVE SUPPLY CURRENT vs DIGITAL INPUT CODE 4.0 4.0 Data = FFFFH (all DACs) 3.5 No Load ICC No Load 3.5 3.0 3.0 2.5 2.5 ICC (mA) Quiescent Current (mA) DAC B 1 –2 –40 –30 –20 –10 2.0 1.5 1.0 ICC 2.0 1.5 1.0 0.5 0.5 IDD 0 IDD 0 –0.5 –0.5 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 0 Temperature (°C) 8 1.5 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code DAC7734 www.ti.com SBAS138A TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified. OUTPUT VOLTAGE vs SETTLING TIME (0V to +10V) OUTPUT VOLTAGE vs SETTLING TIME (+10V to 0V) Small-Signal Settling Time: 3LSB/div Output Voltage Output Voltage Large-Signal Settling Time: 5V/div Small-Signal Settling Time: 3LSB/div Large-Signal Settling Time: 5V/div +5V LDAC 0 +5V LDAC 0 Time (2µs/div) Time (2µs/div) OUTPUT VOLTAGE MIDSCALE GLITCH PERFORMANCE Output Voltage (200mV/div) Output Voltage (200mV/div) OUTPUT VOLTAGE MIDSCALE GLITCH PERFORMANCE 7FFFH to 8000H 8000H to 7FFFH +5V LDAC 0 +5V LDAC 0 Time (1µs/div) Time (1µs/div) BROADBAND NOISE OUTPUT NOISE VOLTAGE vs FREQUENCY 120 Noise (nV/√Hz) Noise Voltage (20µV/div) 100 BW = 10kHz Code = 8000H 80 60 40 20 0 100 Time (100µs/div) 1k 10k 100k 1M Frequency (Hz) DAC7734 SBAS138A www.ti.com 9 TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = 0, VREFH = +10V, and VREFL = 0V, representative unit, unless otherwise specified. OUTPUT VOLTAGE vs RLOAD POWER SUPPLY REJECTION RATIO vs FREQUENCY 0 16 –10 14 –20 12 +15V VOUT (V) PSRR (dB) –30 –40 –50 –60 +5V Source 10 8 6 4 –70 –80 2 –90 0 0.01 Sink 1k 100 10k 100k 1M 0.1 1 Frequency (Hz) RLOAD (kΩ) SINGLE-SUPPLY CURRENT LIMIT vs INPUT CODE CLOCK FEEDTHROUGH 10 100 20 15 10 5 Short to Ground Output Voltage (5mV/div) IOUT (mA) 30 25 0 –5 –10 –15 –20 –25 –30 0000H +5V CLK 0V Short to VCC 2000H 4000H 6000H 8000H A000H C000H E000H Time (50ns/div) FFFFH Input Code 10 DAC7734 www.ti.com SBAS138A TYPICAL PERFORMANCE CURVES: VSS = –15V At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) +25°C 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +85°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) +85°C Digital Input Code 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code DAC7734 SBAS138A 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 www.ti.com 11 TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified. +85°C (cont.) DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, –40°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, –40°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code 12 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 Digital Input Code LE (LSB) LE (LSB) DLE (LSB) LE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –40°C DLE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +85°C) DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +85°C) DAC7734 www.ti.com SBAS138A TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified. REFERENCE CURRENT vs CODE All DACs Sent to Indicated Code (DAC C and D) VREFH VREFL 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH VREF (Current (mA) VREF (Current (mA) 2.5 2.0 1.5 1.0 0.5 0 –0.5 2.5 2.0 1.5 1.0 0.5 0 –0.5 VREFL 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code BIPOLAR ZERO SCALE ERROR vs TEMPERATURE (Code 8000H) POSITIVE FULL-SCALE ERROR vs TEMPERATURE (Code FFFFH) 2 2 1.5 1.5 1 Positive Full-Scale Error (mV) Bipolar Zero Scale Error (mV) VREF (Current (mA) VREF (Current (mA) REFERENCE CURRENT vs CODE All DACs Sent to Indicated Code (DAC A and B) VREFH DAC A 0.5 0 –0.5 DAC D DAC B DAC C –1 –1.5 –2 –40 –30 –20 –10 0 1.0 DAC A 0.5 0 –0.5 DAC D DAC B –1.5 –2.0 –40 –30 –20 –10 10 20 30 40 50 60 70 80 90 0 NEGATIVE FULL-SCALE ERROR vs TEMPERATURE (Code 0000H) Quiescent Current (mA) Negative Full-Scale Error (mV) 1.5 1.0 DAC A 0.5 0 DAC B DAC C –1.0 –1.5 –2.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 7 6 5 4 3 2 1 0 –1 –2 –3 –4 –5 –6 –7 40 50 60 70 80 90 80 90 ICC IDD ISS Data = FFFFH (all DACs) No Load –40 –30 –20 –10 0 10 20 30 40 50 60 70 Temperature (°C) Temperature (°C) DAC7734 SBAS138A 20 30 POWER SUPPLY CURRENT vs TEMPERTURE 2 DAC D 10 Temperature (°C) Temperature (°C) –0.5 DAC C –1.0 www.ti.com 13 TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified. SUPPLY CURRENT vs CODE OUTPUT VOLTAGE vs RLOAD 7 6 5 4 3 2 1 0 –1 –2 –3 –4 –5 –6 –7 15 10 Source (mA) VOUT (V) 5 0 –5 Sink –10 –15 0.01 0.1 1 10 0000H 100 ICC IDD ISS 2000H 4000H 6000H 8000H A000H C000H E000H RLOAD (kΩ) Digital Input Code OUTPUT VOLTAGE vs SETTLING TIME (–10V to +10V) OUTPUT VOLTAGE vs SETTLING TIME (+10V to –10V) FFFFH Output Voltage Output Voltage Large-Signal Settling Time: 5V/div Small-Signal Settling Time: 3LSB/div Small-Signal Settling Time: 3LSB/div Large-Signal Settling Time: 5V/div +5V LDAC 0 +5V LDAC 0 Time (2µs/div) Time (2µs/div) DUAL-SUPPLY CURRENT LIMIT vs INPUT CODE (Short-to-Ground) POWER SUPPLY REJECTION RATIO vs FREQUENCY 20 0 15 –10 –20 –30 5 PSRR (dB) IOUT (mA) 10 0 –5 –40 –50 –15V –60 +15V –70 –10 –80 –15 –90 –20 –100 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH +5V 100 Digital Input Code 14 1k 10k 100k 1M Frequency (Hz) DAC7734 www.ti.com SBAS138A TYPICAL PERFORMANCE CURVES: VSS = –15V (Cont.) At TA = +25°C, VDD = +5V, VCC = +15V, VSS = –15V, VREFH = +10V, and VREFL = –10V, representative unit, unless otherwise specified. OUTPUT VOLTAGE MID-SCALE GLITCH PERFORMANCE Output Voltage (200mV/div) Output Voltage (200mV/div) OUTPUT VOLTAGE MID-SCALE GLITCH PERFORMANCE 7FFFH to 8000H +5V LDAC 0 +5V LDAC 0 Time (1µs/div) Time (1µs/div) DAC7734 SBAS138A 8000H to 7FFFH www.ti.com 15 THEORY OF OPERATION The digital input is a 24-bit serial word that contains a 2-bit address code for selecting one of four DACs, a quick load bit, five unused bits, and the 16-bit DAC code (MSB first). The converters can be powered from either a single +15V supply or a dual ±15V supply and a +5V logic supply. The device offers a reset function that immediately sets all DAC output voltages and DAC registers to mid-scale code 8000H or to zero-scale, code 0000H. See Figures 2 and 3 for the basic operation of the DAC7734. The DAC7734 is a quad voltage output, 16-bit Digital-toAnalog Converter (DAC). The architecture is an R-2R ladder configuration with the three MSBs segmented, followed by an operational amplifier that serves as a buffer. Each DAC has its own R-2R ladder network, segmented MSBs, and output op amp, as shown in Figure 1. The minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set by the external voltage references VREFL and VREFH. RF VOUT Sense VOUT R 2R 2R 2R 2R 2R 2R 2R 2R 2R VREFH VREFH Sense VREFL VREFL Sense FIGURE 1. DAC7734 Architecture. Serial Data In Clock Load DAC Registers Load Chips Select Serial Data Out Reset DAC Registers +5V + 1µF 1 NC VOUTA Sense 48 2 NC VOUTA 47 3 SDI AGND 46 4 DGND VSS 45 5 CLK VREFL AB Sense 44 6 DGND VREFL AB 43 7 LDAC VREFH AB 42 8 DGND VREFH AB Sense 41 9 LOAD VOUTB Sense 40 10 DGND VOUTB 39 11 CS VOUTC Sense 38 12 DGND VOUTC 37 13 SDO VREFH CD Sense 36 14 DGND VREFH CD 35 15 RSTSEL VREFL CD 34 16 DGND VREFL CD Sense 33 17 RST VOUTD Sense 32 18 DGND VOUTD 31 19 NC VSS 30 20 NC VSS 29 21 DGND AGND 28 22 DGND AGND 27 23 VDD VCC 26 24 VDD VCC 25 DAC7734 0.1µF 0V to +10V +10.000V 0V to +10V 0V to +10V +10.000V 0V to +10V 0.1µF + 1µF +15V NC = No Connection FIGURE 2. Basic Single-Supply Operation of the DAC7734. 16 DAC7734 www.ti.com SBAS138A Serial Data In Clock Load DAC Registers Load Chips Select Serial Data Out +5V Reset DAC Registers + +5V 1µF 1 NC VOUTA Sense 48 2 3 NC VOUTA 47 SDI AGND 46 4 DGND 5 CLK 6 –10V to +10V –15V VSS 45 VREFL AB Sense 44 DGND VREFL AB 43 –10.000V 7 LDAC VREFH AB 42 +10.000V 8 DGND VREFH AB Sense 41 9 LOAD VOUTB Sense 40 10 DGND 11 CS 12 DGND 13 SDO 14 DGND 15 RSTSEL 16 DGND 17 RST 18 DGND 19 VOUTB 39 VOUTC Sense 38 DAC7734 VOUTC 37 VREFH CD Sense 36 VREFH CD 35 VREFL CD 34 VREFL CD Sense 33 VOUTD Sense 32 VOUTD 31 NC VSS 30 20 NC VSS 29 21 DGND AGND 28 22 DGND AGND 27 23 VDD VCC 26 24 VDD VCC 25 –10V to +10V –10V to +10V +10.000V –10.000V –10V to +10V –15V 0.1µF 0.1µF 0.1µF + + 1µF 1µF +15V NC = No Connection FIGURE 3. Basic Dual-Supply Operation of the DAC7734. ANALOG OUTPUTS When VSS = –15V (dual-supply operation), the output amplifier can swing to within 4V of the supply rails, ensured over the –40°C to +85°C temperature range. When VSS = 0V (single-supply operation), and with RLOAD also connected to ground, the output can swing to ground. Care must also be taken when measuring the zero-scale error when VSS = 0V. Since the output voltage cannot swing below ground, the output voltage may not change for the first few digital input codes (0000H, 0001H, 0002H, etc.) if the output amplifier has a negative offset. At the negative limit of –5mV, the first specified output starts at code 0021H. Due to the high accuracy of these DACs, system design problems such as grounding and contact resistance become very important. A 16-bit converter with a 10V full-scale range has a 1LSB value of 152µV. With a load current of 1mA, series wiring and connector resistance of only 150mΩ (RW2) will cause a voltage drop of 150µV, as shown in Figure 4. To understand what this means in terms of a system layout, the resistivity of a typical 1-ounce copperclad printed circuit board is 1/2 mΩ per square. For a 1mA load, a 20 milli-inch wide printed circuit conductor 6 inches long will result in a voltage drop of 150µV. The DAC7734 offers a force and sense output configuration for the high open-loop gain output amplifier. This feature allows the loop around the output amplifier to be closed at the load (as shown in Figure 4), thus ensuring an accurate output voltage. RW1 DAC7734 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUTB Sense 40 VOUTB 39 RW2 VOUT +V +10V RW1 RW2 VOUT FIGURE 4. Analog Output Closed-Loop Configuration (1/2 DAC7734). RW represents wiring resistances. DAC7734 SBAS138A VOUTA Sense www.ti.com 17 The current into the VREFH input and out of VREFL depends on the DAC output voltages, and can vary from a few microamps to approximately 2.0mA. The reference input appears as a varying load to the reference. The DAC7734 features a reference drive and sense connection such that the internal errors caused by the changing reference current and the circuit impedances can be minimized. Figures 5 through 9 show different reference configurations, and the effect on the linearity and differential linearity. REFERENCE INPUTS The reference inputs, VREFL and VREFH, can be any voltage between VSS + 4V and VCC – 4V, provided that VREFH is at least 1.25V greater than VREFL. The minimum output of each DAC is equal to VREFL plus a small offset voltage (essentially, the offset of the output op amp). The maximum output is equal to VREFH plus a similar offset voltage. Note that VSS (the negative power supply) must either be connected to ground or must be in the range of –14.25V to –15.75V. The voltage on VSS sets several bias points within the converter. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not ensured. The analog supplies must come up first. If VCC and VSS do not come up together, then VSS should come up first. If the power supplies for the reference come up first, then the VCC and VSS supplies will be powered from the reference via the ESD protection diode; see the ESD protection circuits on page 4. +V VOUTA Sense 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUTB Sense 40 VOUTB 39 DAC7734 OPA2234 VOUT 100Ω 2200pF –10V –15V –V 1000pF +V 100Ω 1000pF +10V 2200pF VOUT –V FIGURE 5. Dual-Supply Configuration-Buffered References, used for Dual-Supply Performance (1/2 DAC7734). +V DAC7734 VOUTA Sense 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VOUT 100Ω 500Ω 2200pF OPA350 +0.050V 50Ω +V 99.5kΩ 1000pF VREFH AB Sense 41 VOUTB Sense 40 VOUTB 39 +10V 100Ω OPA227 1000pF 2200pF VOUT NOTE: VREFL has been chosen to be 50mV to allow for current sinking voltage drops across the 100Ω resistor and the output stage of the buffer op amp. FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV used for Single-Supply Performance Curves (1/2 DAC7734). 18 DAC7734 www.ti.com SBAS138A LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, 25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, 25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, 25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, 25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code FIGURE 7. Integral Linearity and Differential Linearity Error Curves for Figure 8. +V VOUTA Sense 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUTB Sense 40 VOUTB 39 DAC7734 OPA2234 VOUT 100Ω 2200pF –5V –V 1000pF +V 100Ω 1000pF +5V 2200pF VOUT –V FIGURE 8. Dual-Supply Buffered Reference with VREFL = –5V and VREFH = +5V (1/2 DAC7734). DAC7734 SBAS138A www.ti.com 19 DAC7734 VOUTA Sense 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUT +V 100Ω OPA350 1000pF VOUTB Sense 40 VOUTB 39 1kΩ 2200pF 0.05V 50Ω 100Ω 1000pF 99kΩ +V 2200pF OPA227 +5V VOUT NOTE: VREFL has been chosen to be 50mV to allow for current sinking voltage drops across the 100Ω resistor and the output stage of the buffer op amp. FIGURE 9. Single-Supply Buffered Reference with a Reference Low of 50mV and Reference High of +5V. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, 25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, 25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, 25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, 25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code FIGURE 10. Integral Linearity and Differential Linearity Error Curves for Figure 9. 20 DAC7734 www.ti.com SBAS138A DIGITAL INTERFACE Table I shows the basic control logic for the DAC7734. The interface consists of a Signal Data Clock (CLK) input, Serial Data (SDI), DAC Input Register Load Control Signal (LOAD), and DAC Register Load Control Signal (LDAC). In addition, a Chip Select (CS) input is available to enable serial communication when there are multiple serial devices. An asynchronous Reset (RST) input, by the rising edge, is provided to simplify start-up conditions, periodic resets, or emergency resets to a known state, depending on the status of the reset select (RSTSEL) signal. The DAC code, quick load control, and address are provided via a 24-bit serial interface (see Table I). The first two bits shifted into the shift register, B23 and B22, are the DAC register address. These bits select the input register that will be updated when LOAD goes LOW. The third bit, B21, is a “Quick Load” bit such that if HIGH, the code in the shift register is loaded into ALL DAC input registers when the LOAD signal goes LOW, independent of the state of the address bits, B23 and B22. If the “Quick Load” bit is LOW, the contents of the shift register is loaded only to the DAC register that is addressed. Bits B20 through B16 are not used and can assume any logical value. The last sixteen bits, B15 through B0, make up the DAC code to be loaded into the selected input register. The internal DAC register is edge-triggered and not leveltriggered. When the LDAC signal is transitioned from LOW to HIGH, the digital word currently in the DAC input register is latched. The first set of registers (the DAC input registers) are level triggered via the LOAD signal. This double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs. When the new data has been entered into the device, all of the DAC outputs can be updated simultaneously by the rising edge of LDAC. Additionally, it allows the DAC input registers to be written to at any point, then the DAC output voltages can be synchronously changed via a trigger signal (LDAC). Note that CS and CLK are combined with an OR gate, which controls the serial-to-parallel shift register. These two inputs are completely interchangeable. In addition, care must be taken with the state of CLK when CS rises at the end of a serial transfer. If CLK is LOW when CS rises, the OR gate will provide a rising edge to the shift register, shifting the internal data one additional bit. The result will be incorrect data and possible selection of the wrong input register(s). If both CS and CLK are used, CS should rise only when CLK is HIGH. If not, then either CS or CLK can be used to operate the shift register. See Table II for more information. CS(1) CLK(1) LOAD RST SERIAL SHIFT REGISTER H(2) X(3) H H No Change L(4) L H H No Change L ↑(5) H H Advanced One Bit Advanced One Bit ↑ L H H H(6) X L(7) H No Change H(6) X H ↑(8) No Change NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH value is suggested in order to avoid a “false clock” from advancing the shift register and changing the shift register. (7) If data is clocked into the serial register while LOAD is LOW, the selected DAC register will change as the shift register bits “flow” through A1 and A0. This will corrupt the data in each DAC register that has been erroneously selected. (8) Rising edge of RST causes no change in the contents of the serial shift register. TABLE II. Serial Shift Register Truth Table. SERIAL DATA INPUT B23 A1 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A0 QUICK LOAD X X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 CS RST RSTSEL LDAC LOAD INPUT REGISTER DAC REGISTER MODE DAC L L H H X X X X L H L H X X X X L L L L H H X X H H H H H H ↑ ↑ X X X X X X L H X X X X ↑ H X X L L L L H H X X Write Write Write Write Hold Hold Reset to Zero Reset to Midscale Hold Hold Hold Hold Write Hold Reset to Zero Reset to Midscale Write Input Write Input Write Input Write Input Update Hold Reset to Zero Reset to Midscale A B C D All All All All TABLE I. DAC7734 Logic Truth Table. DAC7734 SBAS138A www.ti.com 21 SERIAL-DATA OUTPUT The Serial-Data Output (SDO) is the internal shift register output. For DAC7734, the SDO is a driven output and does not require an external pull-up. Any number of DAC7734s can be daisy-chained by connecting the SDO pin of one device to the SDI pin of the following device in the chain, as shown in Figure 11. DIGITAL TIMING Figure 12 and Table III provide detailed timing for the digital interface of the DAC7734. DIGITALLY-PROGRAMMABLE CURRENT SOURCE The DAC7734 offers a unique set of features that allows a wide range of flexibility in designing applications circuits such as programmable current sources. The DAC7734 offers both a differential reference input, as well as an open-loop configuration around the output amplifier. The open-loop configuration around the output amplifier allows a transistor to be placed within the loop to implement a digitallyprogrammable, unidirectional current source. The availability of a differential reference allows programmability for both the full-scale and zero-scale currents. The output current is calculated as: DIGITAL INPUT CODING The DAC7734 input data is in Straight Binary format. The output voltage is given by Equation 1. VOUT = VREF L + (VREF H – VREF L) • N 65, 536   V H – VREF L   N   I OUT =   REF   •  R SENSE  65, 536    (2) + (VREF L / R SENSE ) (1) where N is the digital input code. This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. LDAC SCK DAC7734 LDAC DAC7734 LDAC DAC7734 LDAC CLK CLK CLK DIN SDI CS CS SDO LOAD SDI CS SDO LOAD SDI CS SDO LOAD To Other Serial Devices LOAD FIGURE 11. Daisy-Chaining DAC7734. 22 DAC7734 www.ti.com SBAS138A (LSB) (MSB) SDI A0 A1 QUICK LOAD XXXXX D15 D14 D3 D13 D1 D2 D0 CLK tcss tCSH tLD1 tLD2 CS tLDDD LOAD tLDRW LDAC tDS tDH SDI tSDO tCL tCH CLK SDO tLDDL tLDDH LDAC tS tS ±0.003% ERROR BAND VOUT tRSTL ±0.003% ERROR BAND tRSTH RESET tRSSH tRSSS RESETSEL FIGURE 12. Digital Input and Output Timing. SYMBOL DESCRIPTION MIN tDS tDH tCH tCL tCSS tCSH tLD1 tLD2 Data Valid to CLK Rising Data Held Valid after CLK Rises CLK HIGH CLK LOW CS LOW to CLK Rising CLK HIGH to CS Rising LOAD HIGH to CLK Rising CLK Rising to LOAD LOW LOAD LOW Time LDAC LOW Time LDAC HIGH Time SDO Propagation Delay RESETSEL Valid to RESET HIGH RESET HIGH to RESETSEL Not Valid RESET LOW Time RESET HIGH Time LOAD LOW to LDAC Rising Time Settling Time 10 20 25 25 15 0 10 30 30 40 40 10 0 100 10 10 40 tLDRW tLDDL tLDDH tSDO tRSSS tRSSH tRSTL tRSTH tLDDD tS MAX 45 11 (dual) /10(single) UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs TABLE III. Timing Specifications (TA = –40°C to +85°C). DAC7734 SBAS138A www.ti.com 23 Figure 13 shows a DAC7734 in a 4mA to 20mA current output configuration. The output current can be determined by Equation 3: (3)   5V – 1V   N    1V  • I OUT =   +   250Ω   65, 536    250Ω  At full-scale, the output current is 16mA, plus the 4mA, for the zero current. At zero scale, the output current is the offset current of 4mA (1V/250Ω). IOUT VPROGRAMMED RSENSE 250Ω VOUTA Sense 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUTB Sense 40 VOUTB 39 DAC7734 +V OPA2350 2200pF 100Ω 20kΩ 1.0V +V 80kΩ 1000pF 5V 100Ω 1000pF 2200pF IOUT VPROGRAMMED RSENSE 250Ω FIGURE 13. 4-to-20mA Digitally Controlled Current Source (1/2 DAC7734). 24 DAC7734 www.ti.com SBAS138A Revision History DATE REVISION 10/08 A PAGE SECTION 1 — 23 Table III DESCRIPTION Updated front page format to current standard; some page layout changed. Changed symbol from "tLDDWL" to "tLDDL" (typo). NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DAC7734 SBAS138A www.ti.com 25 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) DAC7734E ACTIVE SSOP DL 48 25 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 DAC7734E Samples DAC7734E/1K ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DAC7734E Samples DAC7734EB ACTIVE SSOP DL 48 25 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DAC7734E B Samples DAC7734EC ACTIVE SSOP DL 48 25 RoHS & Green Call TI Level-3-260C-168 HR -40 to 85 DAC7734E C Samples DAC7734EC/1K ACTIVE SSOP DL 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 DAC7734E C Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of