DA
DAC7822
C7
82
2
SBAS374A – JUNE 2006 – REVISED JULY 2007
Dual, 12-Bit, Parallel Input, Multiplying
Digital-to-Analog Converter
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
±1LSB INL
2.5V to 5.5V Supply Operation
Fast Parallel Interface:
17ns Write Cycle
Update Rate of 20.4MSPS
10MHz Multiplying Bandwidth
±15V Reference Input
Extended Temperature Range:
–40°C to +125°C
40-Lead QFN
12-Bit Monotonic
4-Quadrant Multiplication
Power-On Reset with Brownout Detection
Readback Function
Industry-Standard Pin Configuration
Pin-Compatible with the AD5405
APPLICATIONS
•
•
•
•
•
•
•
Portable Battery-Powered Instruments
Waveform Generators
Analog Processing
Programmable Amplifiers and Attenuators
Digitally-Controlled Calibration
Programmable Filters and Oscillators
Ultrasound
DESCRIPTION
The DAC7822 is a dual, CMOS, 12-bit, current
output digital-to-analog converter (DAC). This device
operates from a 2.5V to 5.5V power supply, making it
suitable for battery-powered and many other
applications.
The DAC7822 operates with a fast parallel interface.
Data readback allows the user to read the contents
of the DAC register via the DB pins. On power-up,
the internal register and latches are filled with zeroes
and the DAC outputs are at zero scale.
The
DAC7822
offers
excellent
4-quadrant
multiplication characteristics, with large signal
multiplying bandwidth of 10MHz. The applied
external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback
resistor (RFB) provides temperature tracking and
full-scale voltage output when combined with an
external current-to-voltage precision amplifier. The
DAC7822 also includes the resistors necessary for
4-quadrant multiplication and other configuration
modes.
The DAC7822 is available in a 40-lead QFN
package.
R2_3A
R3A
R3
2R
R2A VREFA
R1A
R2
2R
R1
2R
RFB
2R
RFBA
DATA
INPUTS
VDD
DB0
DB11
INPUT
BUFFER
IOUT1A
12-Bit
R-2R DAC A
LATCH
IOUT2A
DAC A/B
CS
CONTROL
LOGIC
R/W
IOUT1B
12-Bit
R-2R DAC B
LATCH
IOUT2B
LDAC
CLR
GND
R3
2R
POWER-ON
RESET
R1
2R
R2
2R
RFB
2R
RFBB
R3B
R2_3B
R2B VREFB
R1 B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2007, Texas Instruments Incorporated
DAC7822
www.ti.com
SBAS374A – JUNE 2006 – REVISED JULY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
DAC7822
UNIT
–0.3 to +7.0
V
Digital input voltage to GND
–0.3 to VDD + 0.3
V
VOUT to GND
VDD to GND
–0.3 to VDD + 0.3
V
Operating temperature range
–40 to +125
°C
Storage temperature range
–65 to +150
°C
Junction temperature (TJ max)
+150
°C
ESD Rating, HBM
2000
V
ESD Rating, CDM
1000
V
(1)
2
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
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SBAS374A – JUNE 2006 – REVISED JULY 2007
ELECTRICAL CHARACTERISTICS
VDD = +2.5V to +5.5V; IOUT1 = Virtual GND; IOUT2 = 0V; VREF = 10V; TA = full operating temperature. All specifications –40°C
to +125°C, unless otherwise noted.
DAC7822
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
12
Bits
Relative accuracy
±1
LSB
Differential nonlinearity
±1
LSB
±1
nA
Output leakage current
Data = 000h, TA = +25°C
Output leakage current
Data = 000h, TA = TMAX
Full-scale gain error
All ones loaded to DAC register
±10
±15
nA
±25
mV
±5
Full-scale tempco (1)
Bipolar zero-code error
Circuit configuration as shown in Figure 41
Output capacitance
DAC latches leaded with all 1s
25
ppm/°C
±25
mV
30
pF
15
V
REFERENCE INPUT
VREF range
–15
VREFA, VREFB, Input resistance
8
10
12
kΩ
R1, RFB resistance
17
20
25
kΩ
R2, R3 resistance
17
20
25
kΩ
VREFA to VREFB Input Mismatch
1.6
2.5
%
R2 to R3 Mismatch
0.06
0.18
%
VDD = +2.5V
0.6
V
VDD = +5V
0.8
V
LOGIC INPUTS AND OUTPUT (1)
Input low voltage
Input high voltage
Input leakage current
Input capacitance
VIL
VIH
VDD = +2.5V
2.1
V
VDD = +5V
2.4
V
IIL
1
µA
CIL
10
pF
POWER REQUIREMENTS
VDD
2.5
5.5
V
5
µA
0.8
5
µA
VIH = VDD and VIL = GND
0.4
2.5
µA
Reference multiplying BW
VREF = 7VPP, Data = FFFh
10
MHz
DAC glitch impulse
VREF = 0V to 10V,
Data = 7FFh to 800h to 7FFh
10
nV-s
Feedthrough error VOUT/VREF
Data = 000h, VREF = 100kHz
–70
dB
2
nV-s
IDD (normal operation)
Logic inputs = 0V
VDD = +4.5V to +5.5V
VIH = VDD and VIL = GND
VDD = +2.5V to +3.6V
AC CHARACTERISTICS (1)
Output voltage settling time
0.2
Digital feedthrough
µs
Total harmonic distortion
–105
dB
Output spot noise voltage
25
nV/√Hz
(1)
Specified by design and characterization; not production tested.
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SBAS374A – JUNE 2006 – REVISED JULY 2007
TIMING INFORMATION
t8
t2
t1
t2
R/W
t9
t3
CS
t4
t5
t10
t11
DACA/DACB
t6
t7
DATA
DATA VALID
t12
t13
DATA VALID
TIMING REQUIREMENTS: 2.5V to 5.5V
At tr = tf = 1ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD = 2.5V to 5.5V, VREF = 10V,
IOUT2 = 0V. All specifications –40°C to +125°C, unless otherwise noted.
DAC7822
PARAMETER (1)
(1)
4
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t1
R/W to CS setup time
0
ns
t2
R/W to CS hold time
t3
CS low time (write cycle)
0
ns
10
t4
Address setup time
10
ns
ns
t5
Address hold time
0
ns
t6
Data setup time
6
ns
t7
Data hold time
0
ns
t8
R/W high to CS low
5
ns
t9
CS minimum high time
7
ns
t10
Address setup time (Read Cycle)
0
ns
t11
Address hold time (Read Cycle)
0
ns
t12
Data access time
5
35
ns
t13
Bus relinquish time
5
10
ns
Ensured by design; not production tested.
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SBAS374A – JUNE 2006 – REVISED JULY 2007
DEVICE INFORMATION
RFBA
IOUT2A
IOUT1A
NC
NC
NC
NC
IOUT1B
IOUT2B
RFBB
40
39
38
37
36
35
34
33
32
31
RTA PACKAGE
QFN-40
(TOP VIEW)
R1A
1
30
R1B
R2A
2
29
R2B
R2_3A
3
28
R2_3B
R3A
4
27
R3B
VREFA
5
26
VREFB
DGND
6
25
VDD
LDAC
7
24
CLR
DAC A/B
8
23
R/W
NC
9
22
CS
DB11
10
21
DB0
16
17
18
DB5
DB4
DB3
20
15
DB6
DB1
14
DB7
19
13
DB8
DB2
12
DB9
DB10
11
DAC7822
TERMINAL FUNCTIONS
PIN NO.
PIN NAME
DESCRIPTION
DAC A 4-Quadrant Resistors. Allows a number of configuration modes, including bipolar operation with
minimum of external components.
1-4
R1A, R2A, R2_3A, R3A
5, 26
VREFA, VREFB
6
DGND
Digital Ground Pin.
7
LDAC
Load DAC Input. Allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously
updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or
synchronous update mode is selected whereby the DAC is updated on the rising edge of CS.
DAC Reference Voltage Input Terminals.
8
DAC A/B
9, 34-37
NC
Selects DAC A or B. Low selects DAC A, and high selects DAC B.
10-21
DB11 to DB0
22
CS
Chip Select Input; active low. Used in conjuction with R/W to load parallel data to the input latch or to read data
from the DAC register. Edge sensitive; when pulled high, the DAC data is latched.
23
R/W
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with
CS to read back contents of DAC register.
24
CLR
Active Low Control Input. Clears DAC output and input and DAC registers.
25
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.5V to 5.5V.
27-30
R3B, R2_3B, R2B, R1B
31, 40
RFBB, RFBA
32
IOUT2B
DAC A Analog Ground. This pin typically should be tied to the analog ground of the system, but can be biased
to achieve single-supply operation.
33
IOUT1B
DAC B Current Output.
38
IOUT1A
DAC A Current Output.
39
IOUT2A
DAC A Analog Ground. This pin typically should be tied to the analog ground of the system, but can be biased
to achieve single-supply operation.
Not internally connected.
Parallel Data Bits 11 through 0.
DAC B 4-Quadrant Resistors. Allow a number of configuration modes, including bipolar operation with a
minimum of external components.
External Amplifier Output.
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SBAS374A – JUNE 2006 – REVISED JULY 2007
TYPICAL CHARACTERISTICS: VDD = +5V
At TA = +25°C, +VDD = +5V, unless otherwise noted.
Channel A
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25°C
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0
-0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1536 2048 2560
Digital Input Code
3072
3584
Figure 2.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
4096
1.0
TA = -40°C
VREF = +10V
0.8
TA = -40°C
VREF = +10V
0.8
0.6
0.4
0.4
DNL (LSB)
0.6
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
Figure 3.
Figure 4.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4096
1.0
TA = +125°C
VREF = +10V
0.8
TA = +125°C
VREF = +10V
0.8
0.6
0.4
0.4
DNL (LSB)
0.6
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
Figure 5.
6
1024
Figure 1.
1.0
INL (LSB)
0.2
-0.4
-1.0
INL (LSB)
TA = +25°C
VREF = +10V
0.8
DNL (LSB)
INL (LSB)
0.8
512
1024
1536 2048 2560
Digital Input Code
Figure 6.
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3072
3584
4096
DAC7822
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SBAS374A – JUNE 2006 – REVISED JULY 2007
TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, +VDD = +5V, unless otherwise noted.
Channel B
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25°C
V
= +10V
0.8
0.6
0.6
0.4
DNL (LSB)
INL (LSB)
0.4
0.2
0
-0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
Figure 7.
Figure 8.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4096
1.0
TA = -40°C
VREF = +10V
0.8
TA = -40°C
VREF = +10V
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
0.2
-0.4
-1.0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
Figure 9.
Figure 10.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4096
1.0
TA = +125°C
VREF = +10V
0.8
TA = +125°C
VREF = +10V
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
TA = +25°C
VREF = +10V
0.8
REF
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
Figure 11.
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 12.
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DAC7822
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SBAS374A – JUNE 2006 – REVISED JULY 2007
TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, +VDD = +5V, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
REFERENCE MULTIPLYING BANDWIDTH
VDD = 5.0V
1.8
Supply Current (mA)
1.6
1.4
Applied to the CS pin.
R/W and LDAC held at 0V.
All other digital inputs
held at supply voltage.
1.2
1.0
0.8
0.6
VDD = 3.0V
0.4
VDD = 2.5V
0.2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0xFFF
0x800
0x400
0x200
0x100
0x080
0x040
0x020
0x010
0x008
0x004
0x002
0x001
Attenuation (dB)
2.0
6
0
-6
-12
-18
-24
-30
-36
-42
-48
-56
-60
-66
-72
-78
-84
-90
-96
-102
0x000
10
5.0
100
1k
10k
100k
10M
1M
Figure 14.
MIDSCALE DAC GLITCH
MIDSCALE DAC GLITCH
Code 2047 to 2048
DAC Update
Output Voltage (50mV/div)
Figure 13.
Output Voltage (50mV/div)
100M
Bandwidth (Hz)
Logic Input Voltage (V)
Code 2048 to 2047
DAC Update
Time (50ns/div)
Time (50ns/div)
Figure 15.
Figure 16.
DAC SETTLING TIME
GAIN ERROR
vs TEMPERATURE
10
8
Small Signal Settling
VREF = +10V
Gain Error (mV)
Output Voltage (%)
90
10
6
DAC Update
4
2
0
Channel B
-2
-4
-6
Channel A
-8
Time (20ns/div)
-10
-40
-20
0
20
40
60
Temperature (°C)
Figure 17.
8
Figure 18.
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100
120
DAC7822
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SBAS374A – JUNE 2006 – REVISED JULY 2007
TYPICAL CHARACTERISTICS: VDD = +5V (continued)
At TA = +25°C, +VDD = +5V, unless otherwise noted.
SUPPLY CURRENT
vs TEMPERATURE
2.0
2.0
VREF = +10V
1.8
VREF = +10V
1.6
1.6
Output Leakage (nA)
Quiescent Current (mA)
1.8
OUTPUT LEAKAGE
vs TEMPERATURE
1.4
1.2
1.0
VDD = +5.0V
0.8
0.6
0.4
1.4
1.2
1.0
0.8
0.6
0.4
VDD = +2.5V
0.2
0.2
0
0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
Temperature (°C)
Temperature (°C)
Figure 19.
Figure 20.
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100
120
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DAC7822
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SBAS374A – JUNE 2006 – REVISED JULY 2007
TYPICAL CHARACTERISTICS: VDD = +2.5V
At TA = +25°C, +VDD = +2.5V, unless otherwise noted.
Channel A
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25°C
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0
-0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1536 2048 2560
Digital Input Code
3072
3584
Figure 22.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
4096
1.0
TA = -40°C
VREF = +10V
0.8
TA = -40°C
VREF = +10V
0.8
0.6
0.4
0.4
DNL (LSB)
0.6
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
Figure 23.
Figure 24.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4096
1.0
TA = +125°C
VREF = +10V
0.8
TA = +125°C
VREF = +10V
0.8
0.6
0.4
0.4
DNL (LSB)
0.6
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
Figure 25.
10
1024
Figure 21.
1.0
INL (LSB)
0.2
-0.4
-1.0
INL (LSB)
TA = +25°C
VREF = +10V
0.8
DNL (LSB)
INL (LSB)
0.8
512
1024
1536 2048 2560
Digital Input Code
Figure 26.
Submit Documentation Feedback
3072
3584
4096
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SBAS374A – JUNE 2006 – REVISED JULY 2007
TYPICAL CHARACTERISTICS: VDD = +2.5V (continued)
At TA = +25°C, +VDD = +2.5V, unless otherwise noted.
Channel B
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
1.0
TA = +25°C
VREF = +10V
0.6
0.6
0.4
0.4
0.2
0
-0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
Figure 27.
Figure 28.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4096
1.0
TA = -40°C
VREF = +10V
0.8
TA = -40°C
VREF = +10V
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
0.2
-0.4
-1.0
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
Figure 29.
Figure 30.
LINEARITY ERROR
vs DIGITAL INPUT CODE
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
4096
1.0
TA = +125°C
VREF = +10V
0.8
TA = +125°C
VREF = +10V
0.8
0.6
0.6
0.4
0.4
DNL (LSB)
INL (LSB)
TA = +25°C
VREF = +10V
0.8
DNL (LSB)
INL (LSB)
0.8
0.2
0
-0.2
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
0
Figure 31.
512
1024
1536 2048 2560
Digital Input Code
3072
3584
4096
Figure 32.
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TYPICAL CHARACTERISTICS: VDD = +2.5V (continued)
At TA = +25°C, +VDD = +2.5V, unless otherwise noted.
MIDSCALE DAC GLITCH
Output Voltage (50mV/div)
Output Voltage (50mV/div)
MIDSCALE DAC GLITCH
Code 2048 to 2047
Code 2047 to 2048
DAC Update
DAC Update
10
8
Time (50ns/div)
Time (50ns/div)
Figure 33.
Figure 34.
GAIN ERROR
vs TEMPERATURE
OUTPUT LEAKAGE
vs TEMPERATURE
2.0
VREF = +10V
1.8
1.6
Output Leakage (nA)
Gain Error (mV)
6
4
2
0
Channel B
-2
-4
-6
-8
1.4
1.2
1.0
0.8
0.6
0.4
Channel A
0.2
0
-10
-40
12
VREF = +10V
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
Temperature (°C)
Temperature (°C)
Figure 35.
Figure 36.
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100
120
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SBAS374A – JUNE 2006 – REVISED JULY 2007
THEORY OF OPERATION
The DAC7822 is a dual channel, current output, 12-bit, digital-to-analog converter (DAC). The architecture,
illustrated in Figure 37, is an R-2R ladder configuration with the three MSBs segmented. Each 2R leg of the
ladder is either switched to IOUT1 or the IOUT2 terminal. The IOUT1 terminal of the DAC is held at a virtual GND
potential by the use of an external I/V converter op amp. The R-2R ladder is connected to an external reference
input VREF that determines the DAC full-scale current. The R-2R ladder presents a code-independent load
impedance to the external reference of 10kΩ ±20%. The external reference voltage can vary over a range of
–15V to +15V, thus providing bipolar IOUT current operation. By using an external I/V converter and the
DAC7822 RFB resistor, output voltage ranges of –VREF to VREF can be generated.
R
R
R
R
VREF
R1
2R
2R
2R
2R
2R
RFB
IOUT1
IOUT2
DB11
(MSB)
DB10
DB9
DB0
(LSB)
Figure 37. Equivalent R-2R DAC Circuit
When using an external I/V converter and the DAC7822 RFB and R1 resistors, the DAC output voltage is given
by Equation 1:
CODE
V OUT + * V REF
4096
(1)
Each DAC code determines the 2R leg switch position to either GND or IOUT. Because the DAC output
impedance as seen looking into the IOUT1 terminal changes versus code, the external I/V converter noise gain
also changes. Because of this, the external I/V converter op amp must have a sufficiently low offset voltage such
that the amplifier offset is not modulated by the DAC IOUT1 terminal impedance change. External op amps with
large offset voltages can produce INL errors in the transfer function of the DAC7822 as a result of offset
modulation versus DAC code.
For best linearity performance of the DAC7822, a low input offset voltage op amp (such as the OPA277) is
recommended (see Figure 38). This circuit allows VREF swinging from –10V to +10V.
VDD
15V
R2
R2/R3
R3
VDD
R1 RFB
IOUT1
DAC7822
GND
IOUT2
V+
OPA277
VOUT
VVREF
-15V
Figure 38. Voltage Output Configuration
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APPLICATION INFORMATION
Stability Circuit
For a current-to-voltage design (see Figure 39), the DAC7822 current output (IOUT) and the connection with the
inverting node of the op amp should be as short as possible and according to correct printed circuit board (PCB)
layout design practices. For each code change, there is a step function. If the gain bandwidth product (GBP) of
the op amp is limited and parasitic capacitance is excessive at the inverting node, then gain peaking is possible.
Therefore, for circuit stability, a compensation capacitor C1 (1pF to 5pF typ) can be added to the design, as
shown in Figure 39.
VDD
VDD
VREF
RFB
VREF DAC7822
C1
IOUT1
U1
IOUT2
GND
VOUT
Figure 39. Gain Peaking Prevention Circuit with Compensation Capacitor
Amplifier Selection
There are many choices and many differences in selecting the proper operational amplifier for a multiplying DAC
(MDAC). Making the analog signal out of the MDAC is one critical aspect. However, there are also other issues
to take into account such as amplifier noise, input bias current, and offset voltage, as well as MDAC resolution
and glitch energy. Table 1 and Table 2 suggest some suitable operational amplifiers for low power, fast settling,
and high-speed applications. A greater selection of operational amplifiers can be found at www.ti.com/amplifer.
Table 1. Suitable Precision Operational Amplifiers from Texas Instruments
IQ
PER
CHANNEL GBW
(max)
(typ)
(mA)
(MHz)
TOTAL
SUPPLY
VOLTAGE
(V) (min)
TOTAL
SUPPLY
VOLTAGE
(V) (max)
SLEW
RATE
(typ)
(V/μs)
OFFSET
DRIFT
(typ)
(μV/°C)
IIB
(max)
(pA)
CMRR
(min)
(dB)
OPA703
4
12
0.2
1
0.6
4
10
70
SOT5-23,
PDIP-8,
SOIC-8
12V, CMOS, Rail-to-Rail I/O,
Operational Amplifier
OPA735
2.7
12
0.75
1.6
1.5
0.01
200
115
SOT5-23,
SOIC-8
0.05μV/°C (max),
Single-Supply CMOS
Zero-Drift Series Operational
Amplifier
OPA344
2.7
5.5
0.25
1
1
2.5
10
80
SOT5-23,
PDIP-8,
SOIC-8
Low Power, Single-Supply,
Rail-To-Rail Operational
Amplifiers MicroAmplifier
Series
OPA348
2.1
5.5
0.065
1
0.5
2
10
70
SC5-70,
SOT5-23,
SOIC-8
1MHz, 45μA, Rail-to-Rail I/O,
Single Op Amp
OPA277
4
36
0.825
1
0.8
0.1
1000
130
PDIP-8,
SOIC-8,
SON-8
High Precision Operational
Amplifiers
OPA350
2.7
5.5
7.5
38
22
4
10
76
MSOP-8,
PDIP-8,
SOIC-8
High-Speed, Single-Supply,
Rail-to-Rail Operational
Amplifiers MicroAmplifier
Series
OPA727
4
12
6.5
20
30
0.6
500
86
MSOP-8,
SON-8
e-trim 20MHz, High
Precision CMOS Operational
Amplifier
OPA227
5
36
3.8
8
2.3
0.1
10000
120
PDIP-8,
SOIC-8
PRODUCT
PACKAGE/
LEAD
DESCRIPTION
Low Power
Fast Settling
14
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High Precision, Low Noise
Operational Amplifiers
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SBAS374A – JUNE 2006 – REVISED JULY 2007
Table 2. Suitable High Speed Operational Amplifiers from Texas Instruments (Multiple Channel Options)
SUPPLY
VOLTAGE
(V)
GBW
PRODUCT
(MHz)
VOLTAGE
NOISE
nV/√Hz
GBW
(typ)
(MHz)
SLEW
RATE
(V/μs)
VOS
(typ)
(μV)
VOS
(max)
(μV)
CMRR
(min)
(dB)
THS4281
±2.7 to ±15
38
12.5
35
500
3500
500
1000
SOT5-23,
MSOP-8,
SOIC-8
Very Low-Power High Speed
Rail-To-Rail Input/Output
Voltage Feedback
Operational Amplifier
THS4031
±4.5 to ±16.5
200
1.6
100
500
3000
3000
8000
CDIP-8,
MSOP-8,
SOIC-8
100-MHz Low Noise
Voltage-Feedback Amplifier
THS4631
±4.5 to ±16.5
210
7
900
260
2000
50pA
2
SOIC-8,
MSOP-8
High Speed FET-Input
Operational Amplifier
OPA656
±4 to ±6
230
7
290
250
2600
2pA
5pA
SOIC-8,
SOT5-23
Wideband, Unity Gain Stable
FET-Input Operational
Amplifier
OPA820
±2.5 to ±6
280
2.5
240
200
1200
900
23,000
SOIC-8,
SOT5-23
Unity Gain Stable, Low
Noise, Voltage Feedback
Operational Amplifier
THS4032
±4.5 to ±16.5
200
1.6
100
500
3000
3000
8000
SOIC-8,
MSOP-8
100-MHz Low Noise
Voltage-Feedback Amplifier,
Dual
OPA2822
±2 to ±6.3
220
2
170
200
1200
9600
12000
SOIC-8,
MSOP-8
SpeedPlus Dual Wideband,
Low-Noise Operational
Amplifier
PRODUCT
PACKAGE/
LEAD
DESCRIPTION
Single Channel
Dual Channel
Positive Voltage Output Circuit
As Figure 40 illustrates, in order to generate a positive voltage output, a negative reference is input to the
DAC7822. This design is suggested instead of using an inverting amp to invert the output as a result of resistor
tolerance errors. For a negative reference, VOUT and GND of the reference are level-shifted to a virtual ground
and a –2.5V input to the DAC7822 with an op amp.
+2.5V Reference
VOUT
VDD
VIN
GND
VDD
VREF
OPA277
RFB
DAC7822
-2.5V
GND
C1
IOUT1
IOUT2
OPA277
VOUT
0 < VOUT < +2.5V
Figure 40. Positive Voltage Output Circuit
Bipolar Output Section
The DAC7822, as a 2-quadrant multiplying DAC, can be used to generate a unipolar output. The polarity of the
full-scale output IOUT is the inverse of the input reference voltage at VREF.
Some applications require full 4-quadrant multiplying capabilities or bipolar output swing. As shown in Figure 41,
external op amp U2 is added as a summing amp and has a gain of 2X that widens the output span to 5V. A
4-quadrant multiplying circuit is implemented by using a 2.5V offset of the reference voltage to bias U2.
According to the circuit transfer equation given in Equation 2, input data (D) from code 0 to full-scale produce
output voltages of VOUT = –2.5V to VOUT = +2.5V.
V OUT +
ǒ0.5 D 2 *1Ǔ
N
VREF
(2)
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External resistance mismatching is the significant error in Figure 41.
VDD
R 1A
R1
2R
RFB
2R
RFBA
C1
R2A
VIN
R2_3A
R3A
U1
(2)
IOUT1A
R2
2R
DAC7822
(1)
VOUT = -VIN to +VIN
U2
IOUT2A
R3
2R
AGND
AGND
GND
VREFA
AGND
NOTES: (1) Similar configuration for DAC B.
(2) C1 phase compensation (1pF to 5pF) may be
required if U2 is a high-speed amplifier.
Figure 41. Bipolar Output Circuit
Parallel Interface
Data are loaded to the DAC7822 as a 12-bit parallel word. The bi-directional bus is controlled with CS and R/W,
allowing data to be written to or read from the DAC register. To write to the device, CS and R/W are brought
low, and data available on the data lines fills the input register. The rising edge of CS latches the data and
transfers the latched data-word to the DAC register. The DAC latches are not transparent; therefore, a write
sequence must consist of a falling and rising edge on CS in order to ensure that data are loaded to the DAC
register and its analog equivalent is reflected on the DAC output.
To read data stored in the device, R/W is held high and CS is brought low. Data are loaded from the DAC
register back to the input register and out onto the data line, where it can be read back to the controller.
Cross-Reference
The DAC7822 has an industry-standard pinout. Table 3 provides the cross-reference information.
Table 3. Cross-Reference
16
PRODUCT
INL (LSB)
DNL (LSB)
SPECIFIED
TEMPERATURE
RANGE
DAC7822
±1
±1
–40°C to +125°C
PACKAGE
DESCRIPTION
PACKAGE
OPTION
CROSSREFERENCE PART
40-Lead QFN
QFN-40
AD5405
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC7822IRTAR
ACTIVE
WQFN
RTA
40
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DAC7822
DAC7822IRTAT
ACTIVE
WQFN
RTA
40
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
DAC7822
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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