®
DAC811
For most current data sheet and other product
information, visit www.burr-brown.com
Microprocessor-Compatible
12-BIT DIGITAL-TO-ANALOG CONVERTER
FEATURES
● SINGLE INTEGRATED CIRCUIT CHIP
● MICROCOMPUTER INTERFACE:
Double-Buffered Latch
● VOLTAGE OUTPUT: ±10V, ±5V, +10V
● MONOTONICITY GUARANTEED OVER
TEMPERATURE
● ±1/2LSB MAXIMUM NONLINEARITY OVER
TEMPERATURE
● GUARANTEED SPECIFICATIONS AT ±12V
AND ±15V SUPPLIES
● TTL/5V CMOS-COMPATIBLE LOGIC
INPUTS
DESCRIPTION
The DAC811 is a complete, single-chip integratedcircuit, microprocessor-compatible, 12-bit digital-toanalog converter. The chip combines a precision voltage reference, microcomputer interface logic, and
double-buffered latch, in a 12-bit D/A converter with
a voltage output amplifier. Fast current switches and a
laser-trimmed thin-film resistor network provide a
highly accurate and fast D/A converter.
Input gating logic is designed so that loading the last
nibble or byte of data can be accomplished simultaneously with the transfer of data (previously stored in
adjacent latches) from adjacent input latches to the
D/A latch. This feature avoids spurious analog output
values while using an interface technique that saves
computer instructions.
The DAC811 is laser trimmed at the wafer level and
is specified to ±1/4LSB maximum linearity error (B
and K grades) at 25°C and ±1/2LSB maximum over
the temperature range. All grades are guaranteed monotonic over the specification temperature range.
The DAC811 is available in six performance grades
and three package types. DAC811J and K are specified over the temperature ranges of 0°C to +70°C;
DAC811A and B are specified over –25°C to +85°C;
DAC811J and K are packaged in a reliable 28-pin
plastic DIP or plastic SO package, while DAC811A
and B are available in a 28-pin 0.6" wide dual-inline
hermetically sealed ceramic side-brazed package (H
package).
Microcomputer interfacing is facilitated by a doublebuffered latch. The input latch is divided into three
4-bit nibbles to permit interfacing to 4-, 8-, 12-, or
16-bit buses and to handle right-or left-justified data.
The 12-bit data in the input latches is transferred to the
D/A latch to hold the output value.
4 MSBs
4 LSBs
SJ
Input Latch
Input Latch
Input Latch
RF
10V
D/A Latch
RF
12-Bit D/A Converter
RBPO
Voltage Reference
VOUT
BPO
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
®
© 1983 Burr-Brown Corporation
SBAS144
PDS-503L
1
Printed in U.S.A. April, 2000
DAC811
SPECIFICATIONS
At TA = +25°C. ±VCC = 12V or 15V, unless otherwise noted.
DAC811AH, JP, JU
PARAMETER
MIN
DIGITAL INPUT
Resolution
Codes(1)
Digital Inputs Over Temperature Range(2)
VIH
VIL
IIH, VI = +2.7V
IIL, VI = +0.4V
Digital Interface Timing Over Temperature Range
tWP, WR Pulse Width
tAW1, NX and LDAC Valid to End of WR
tDW, Data Valid to End of WR
tDH, Data Valid Hold Time
TYP
MAX
+15
+0.8
+10
±20
±10
±5
±5
±1/2
Guaranteed
✻
✻
±1/2
±3/4
±0.2
±0.15
Bits
✻
✻
✻
✻
VDC
VDC
µA
µA
ns
ns
ns
ns
±1/4
±1/2
✻
✻
LSB
LSB
%
% of FSR(5)
✻
✻
✻
% of FSR/%VCC
% of FSR/%VCC
% of FSR/%VDD
±30
±10
±10
±3/4
±10
±5
±5
±1/4
✻
±20
±7
±7
±1/2
ppm/°C
ppm of FSR/°C
ppm of FSR/°C
LSB
4
4
✻
✻
✻
✻
✻
✻
µs
µs
µs
V/µs
✻
✻
✻
0 to +10
±5, ±10
V
V
mA
Ω
✻
✻
✻
0.2
Indefinite
+11.4
–11.4
+4.5
✻
±1/8
±1/4
✻
✻
✻
✻
✻
✻
±0.003
±0.006
±0.0015
SETTLING TIME(6) (to within ±0.01% of FSR of Final Value; 2kΩ load)
For Full Scale Range Change, 20V Range
3
10V Range
3
For 1LSB Change at Major Carry(7)
1
Slew Rate(6)
8
12
+6.2
+2
UNITS
✻
✻
✻
✻
50
50
80
0
±5
MAX
✻
+2
0
DRIFT (Over Specification Temperature Range)
Gain
Unipolar Offset
Bipolar Zero
Linearity Error Over Temperature Range
Monotonicity Over Temperature Range
POWER SUPPLY REQUIREMENTS
Voltage: +VCC
–VCC
VDD
Current (no load): +VCC
–VCC
VDD
Potential at DCOM with Respect to ACOM(9)
Power Dissipation
TYP
12
±1/4
±1/2
±0.1
±0.05
Guaranteed
±0.001
±0.002
±0.0005
REFERENCE VOLTAGE
Voltage
Source Current Available for External Loads
Temperature Coefficient
Short Circuit to Common Duration
MIN
USB, BOB
ACCURACY
Linearity Error
Differential Linearity Error
Gain Error(3)
Offset Error(3, 4)
Monotonicity
Power Supply Sensitivity: +VCC
–VCC
VDD
ANALOG OUTPUT
Voltage Range (±VCC = 15V)(8): Unipolar
Bipolar
Output Current
Output Impedance (at DC)
Short Circuit to Common Duration
DAC811BH, KP, KU
+6.3
+6.4
±10
Indefinite
±30
+15
–15
+5
+16
–23
+8
±0.5
625
+16.5
–16.5
+5.5
+25
–35
+15
✻
✻
✻
✻
✻
800
✻
✻
±10
✻
±20
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
✻
TEMPERATURE RANGE
Specification: J, K
A, B
R, S
0
–25
–65
+70
+85
+150
✻
✻
✻
✻
✻
✻
Storage: J, K
A, B, R, S
–60
–65
+100
+150
✻
✻
✻
✻
V
mA
ppm/°C
VDC
VDC
VDC
mA
mA
mA
V
mW
°C
°C
°C
°C
°C
°C
✻ Specification same as DAC811AH, JP, JU.
NOTES: (1) USB = unipolar straight binary; BOB = bipolar offset binary. (2) TTL, LSTTL and 54/74 HC compatible. (3) Adjustable to zero with external trim
potentiometer. (4) Error at input code 00016 for both unipolar and bipolar ranges. (5) FSR means full scale range and is 20V for the ±10V range. (6) Maximum
represents the 3σ limit. Not 100% tested for this parameter. (7) At the major carry, 7FF16 to 80016 and 80016 to 7FF16. (8) Minimum supply voltage required for ±10V
output swing is ±13.5V. Output swing for ±11.4V supplies is at least –8V to +8V. (9) The maximum voltage at which ACOM and DCOM may be separated without
affecting accuracy specifications.
®
DAC811
2
PIN DESCRIPTIONS
PIN
ABSOLUTE MAXIMUM RATINGS
NAME
FUNCTION
1
+VDD
Logic supply, +5V.
2
WR
Write, command signal to load latches. Logic low
loads latches.
3
LDAC
Load D/A converter, enables WR to load the D/A
latch. Logic low enables.
4
NA
Nibble A, enables WR to load input latch A (the
most significant nibble). Logic low enables.
5
NB
Nibble B, enables WR to load input latch B. Logic
low enables.
6
NC
Nibble C, enables WR to load input latch C (the
least significant nibble). Logic low enables.
7
D11
Data bit 12, MSB, positive true.
8
D10
Data bit 11.
9
D9
Data bit 10.
10
D8
Data bit 9.
11
D7
Data bit 8.
12
D6
Data bit 7.
13
D5
Data bit 6.
+VCC ................................................................................................................................ 0 to +18V
–VCC to ACOM .......................................................................... 0 to –18V
VDD to DCOM .............................................................................. 0 to +7V
VDD to ACOM ...................................................................................... ±7V
ACOM to DCOM .................................................................................. ±7V
Digital Inputs (Pins 2–14, 16–19) to DCOM ...................... –0.4V to +18V
External Voltage Applied to 10V Range Resistor ............................ ±12V
Ref Out ............................................................. Indefinite Short to ACOM
External Voltage Applied to DAC Output ................................ –5V to +5V
Power Dissipation ........................................................................ 1000mW
Lead Temperature (soldering, 10s) ............................................... +300°C
Max Junction Temperature ............................................................ +165°C
Thermal Resistance, θJ-A: Plastic DIP and SOIC ....................... 100°C/W
Ceramic DIP .................................................................................. 65°C/W
NOTE: Stresses above those listed above may cause permanent damage to
the device. Exposure to absolute maximum conditions for extended periods
may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
14
D4
Data bit 5.
15
DCOM
Digital common, VDD supply return.
16
D0
Data bit 1, LSB.
17
18
19
20
21
22
23
24
25
26
27
D1
D2
D3
+VCC
–VCC
Gain Adj
ACOM
VOUT
10V Range
SJ
BPO
Data bit 2.
Data bit 3.
Data bit 4.
Analog supply input, +15V or +12V.
Analog supply input, –15V or –12V.
To externally adjust gain.
Analog common, ±VCC supply return.
D/A converter voltage output.
Connect to pin 24 for 10V range.
Summing junction of output amplifier.
Bipolar offset. Connect to pin 26 for bipolar
operation.
28
Ref Out
6.3V reference output.
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
MINIMUM
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
LINEARITY
(LSB)
DAC811AH
DAC811JP
DAC811JU
±1/2 LSB
±1/2 LSB
±1/2 LSB
3/4
3/4
3/4
"
DAC811KP
DAC811KU
PACKAGE
PACKAGE
DRAWING
NUMBER
SPECIFICATION
TEMPERATURE
RANGE
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
CERDIP-28
DIP-28
SO-28
149
215
217
–25°C to +85°C
0°C to +70°C
0°C to +70°C
DAC811AH
DAC811JP
DAC811JU
Rails
Rails
Rails
DAC811JU/1K
DAC811KP
DAC811KU
Tape and Reel
Rails
Rails
"
"
"
"
"
±1/4 LSB
±1/4 LSB
1/2
1/2
DIP-28
SO-28
215
217
0°C to +70°C
0°C to +70°C
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC811JU/1K” will get a single 1000-piece Tape and Reel.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
3
DAC811
TIMING DIAGRAMS
Write Cycle #2
Load second rank from first rank: NA , NB , N C = 1
Write Cycle #1
Load first rank from Data Bus: LDAC = 1
tAW
tAW
LDAC
N A , NB , N C
tWP
tDW
WR
DB11 –DB0
tSET
tWP
tDH
WR
±1/2LSB
DISCUSSION OF
SPECIFICATIONS
DRIFT
Gain drift is a measure of the change in the full scale range
(FSR) output over the specification temperature range. Drift is
expressed in parts per million per degree centigrade
(ppm/°C). Gain drift is established by testing the full scale
range value (e.g., +FS minus –FS) at high temperature, +25°C,
and low temperature, calculating the error with respect to the
+25°C value, and dividing by the temperature change.
INPUT CODES
The DAC811 accepts positive-true binary input codes.
DAC811 may be connected by the user for any one of the
following codes: USB (unipolar straight binary), BOB (bipolar offset binary) or, using an external inverter on the
MSB line, BTC (binary two’s complement). See Table I.
DIGITAL INPUT
Unipolar offset drift is a measure of the change in output
with all 0s on the input over the specification temperature
range. Offset is measured at high temperature, +25°C, and
low temperature. The offset drift is the maximum change in
offset referred to the +25°C value, divided by the temperature change. It is expressed in parts per million of full scale
range per degree centigrade (ppm of FSR/°C).
ANALOG OUTPUT
USB
Unipolar
Straight
Binary
BOB
Bipolar
Offset
Binary
BTC(1)
Binary
Two’s
Complement
+ Full Scale
+ 1/2 Full Scale
+ 1/2 Full Scale – 1LSB
Zero
+ Full Scale
Zero
–1LSB
– Full Scale
–1LSB
– Full Scale
+ Full Scale
Zero
Bipolar zero drift is measured at a digital input of 80016, the
code that gives zero volts output for bipolar operation.
NOTE: (1) Invert MSB of the BOB code with external inverter to obtain BTC code.
SETTLING TIME
Settling time is the total time (including slew time) for the
output to settle within an error band around its final value
after a change in input. Three settling times are specified to
±0.01% of full scale range (FSR): two for maximum full
scale range changes of 20V and 10V, and one for a 1LSB
change. The 1LSB change is measured at the major carry
(7FF16 to 80016 and 80016 to 7FF16), the input transition at
which worst-case settling time occurs.
MSB
LSB
↓
↓
111111111111
100000000000
011111111111
000000000000
TABLE I. Digital Input Codes.
LINEARITY ERROR
Linearity error as used in D/A converter specifications by
Burr-Brown is the deviation of the analog output from a
straight line drawn between the end points (inputs all 1s and
all 0s). The DAC811 linearity error is specified at ±1/4LSB
(max) at +25°C for B and K grades, and ±1/2LSB (max) for
A and J grades.
REFERENCE SUPPLY
DAC811 contains an on-chip 6.3V reference. This voltage
(pin 28) has a tolerance of ±0.1V. The reference output may
be used to drive external loads, sourcing at least 2mA. This
current should be constant for best performance of the D/A
converter.
DIFFERENTIAL LINEARITY ERROR
Differential linearity error (DLE) is the deviation from a
1LSB output change from one adjacent state to the next. A
DLE specification of 1/2LSB means that the output step size
can range from 1/2LSB to 3/2LSB when the input changes
from one state to the next. Monotonicity requires that DLE
be less than 1LSB over the temperature range of interest.
POWER SUPPLY SENSITIVITY
Power supply sensitivity is a measure of the effect of a
power supply change on the D/A converter output. It is
defined as a percent of FSR output change per percent of
change in either the positive, negative, or logic supply
voltages about the nominal voltages. Figure 1 shows typical
power supply rejection versus power supply ripple frequency.
MONOTONICITY
A D/A converter is monotonic if the output either increases
or remains the same for increasing digital inputs. All grades
of DAC811 are monotonic over their specification temperature range.
®
DAC811
4
The D/A latch is controlled by LDAC and WR. LDAC and
WR are internally NORed so that the latches transmit data to
the D/A switches when both LDAC and WR are at logic 0.
When either LDAC or WR are at logic 1, the data is latched
in the D/A latch and held until LDAC and WR go to logic 0.
Percent of FSR per Percent of
Change of Power Supply Voltage
1
–VCC
0.1
V DD
0.01
All latches are level-triggered. Data present when the control signals are logic 0 will enter the latch. When any one of
the control signals returns to logic 1, the data is latched.
Table II is a truth table for all latches.
+VCC
0.001
0.0001
10
100
1k
10k
1M
100k
Frequency (Hz)
FIGURE 1. Power Supply Rejection vs Power Supply Ripple
Frequency.
WR
NA
NB
NC
LDAC
1
0
0
0
0
0
X
0
1
1
1
0
X
1
0
1
1
0
X
1
1
0
1
0
X
1
1
1
0
0
OPERATION
No operation
Enables input latch 4MSBs
Enables input latch 4 middle bits
Enables input latch 4LSBs
Loads D/A latch from input latches
Makes all latches transparent
“X” = Don’t care.
OPERATION
TABLE II. DAC813 Interface Logic Truth Table.
DAC811 is a complete single IC chip 12-bit D/A converter.
The chip contains a 12-bit D/A converter, voltage reference,
output amplifier, and microcomputer-compatible input logic
as shown in Figure 2.
GAIN AND OFFSET ADJUSTMENTS
Figures 3 and 4 illustrate the relationship of offset and gain
adjustments to unipolar and bipolar D/A converter output.
INTERFACE LOGIC
Input latches A, B, and C hold data temporarily while a
complete 12-bit word is assembled before loading into the
D/A register. This double-buffered organization prevents the
generation of spurious analog output values. Each register is
independently addressable.
OFFSET ADJUSTMENT
For unipolar (USB) configurations, apply the digital input
code that should produce zero voltage output, and adjust the
offset potentiometer for zero output. For bipolar (BOB,
BTC) configurations, apply the digital input code that should
produce the maximum negative output voltage and adjust
the offset potentiometer for minus full scale voltage. Example: If the full scale range is connected for 20V, the
maximum negative output voltage is –10V. See Table III for
corresponding codes.
These input latches are controlled by NA, NB, NC, and WR.
NA, NB, and NC are internally NORed with WR so that the
input latches transmit data when both NA (or NB, NC ) and
WR are at logic 0. When either NA, (NB, NC ) or WR go to
logic 1, the input data is latched into the input registers and
held until both NA (or NB, NC ) and WR go to logic 0.
MSB D11
7
WR
8
9
D8
D7
10
11
12
13
D4
D3
14
19
D0
18
17
16
RBPO
2
4-Bit Latch, A
NA
4
NB
5
LSB
4-Bit Latch, B
4-Bit Latch, C
27
BPO
26
SJ
25
10V
Range
24
VOUT
23
ACOM
RF
NC
6
LDAC
3
12-Bit D/A Latch
RF
12-Bit D/A Converter
Reference
Ref Out
28
FIGURE 2. DAC811 Block Diagram.
®
5
DAC811
±12V OPERATION
+ Full Scale
The DAC811 is fully specified for operation on ±12V power
supplies. However, in order for the output to swing to ±10V,
the power supplies must be ±13.5V or greater. When operating with ±12VB supplies, the output swing should be
restricted to ±8V in order to meet specifications.
Range of
Gain Adjust
Full Scale Range
Analog Output
1LSB
Range of
Offset Adj.
LOGIC INPUT COMPATIBILITY
The DAC811 digital inputs are TTL, LSTTL, and 54/74HC
CMOS-compatible over the operating range of VDD. The
input switching threshold remains at the TLL threshold over
the supply range.
Gain Adjust
Rotates the Line
All Bits
Logic 0
All Bits
Logic 1
The logic input current over temperature is low enough to
permit driving the DAC811 directly from the outputs of
4000B and 54/74C CMOS devices.
Digital Input
Offset Adjust Translates the Line
Resistors of 47Ω should be placed in series with D0 through
D11, WR, NA, NB, NC and LDAC if edges are