DAC82001DRXR

DAC82001 SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 DAC82001 16-Bit, Low-Glitch, Single-Channel Voltage-Output, Unbuffered DAC 1 Features 3 Description • • • • • • • The 16-bit DAC82001 is a highly accurate, low-power, single-channel digital-to-analog converter (DAC) with an unbuffered voltage output. • • • • 16-bit performance: 1-LSB DNL and 2-LSB INL Low glitch energy: 0.5 nV-s Fast settling: 1 µs Wide power supply: 2.7 V to 5.5 V Wide reference range: 2.0 V to VDD Low power: 250 µA at 5.0 V 3-wire serial peripheral interface (SPI) up to 50‑MHz Reset to zero scale or midscale 1.62-V VIH with VDD = 5.5 V Temperature range: –40°C to +85°C Package: Tiny 10-pin WSON 2 Applications Oscilloscope (DSO) Battery test Semiconductor test Ultrasound scanner DC power supply, ac source, electronic load The DAC82001 uses a versatile, three-wire serial peripheral interface (SPI) that operates at clock rates of up to 50 MHz. Package Information PART NUMBER DAC82001 (1) VDD SDIN DAC82001 RESET RSTSEL REF DAC Buffer DAC Register BODY SIZE (NOM) DRX (WSON, 10) 2.50 mm × 2.50 mm For all available packages, see the package option addendum at the end of the data sheet. SYNC SCLK PACKAGE(1) VREF Input Interface Logic • • • • • The DAC82001 works with 3.3-V and 5-V supplies and offers linearity of 1‑LSB DNL and 2‑LSB INL. The high accuracy combined with a tiny package make the device an excellent choice for applications such as gain and offset calibration, voltage set point generation, and power-supply control. The DAC82001 incorporates a power-on-reset (POR) circuit. The POR circuit makes sure that the DAC output powers up at zero scale or midscale based on the status of RSTSEL pin, and remains at that scale until a valid code is written to the device. All internal registers are asynchronously reset after the RESET pin is pulled low. DAC Power On Reset AGND VOUT Op Amp 0 V to +VREF Single-Ended Output Buffer Op Amp Differential Output SingleEnded to Differential Conversion DAC82001 for Generating Time Gain Compensation (TGC) Control Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 4 6.1 Absolute Maximum Ratings........................................ 4 6.2 ESD Ratings............................................................... 4 6.3 Recommended Operating Conditions.........................4 6.4 Thermal Information....................................................4 6.5 Electrical Characteristics.............................................5 6.6 Timing Requirements.................................................. 6 6.7 Timing Diagram ..........................................................6 6.8 Typical Characteristics................................................ 7 7 Detailed Description...................................................... 11 7.1 Overview................................................................... 11 7.2 Functional Block Diagram......................................... 11 7.3 Feature Description...................................................12 7.4 Device Functional Modes..........................................13 7.5 Programming............................................................ 14 7.6 Register Maps...........................................................15 8 Application and Implementation.................................. 17 8.1 Application Information............................................. 17 8.2 Typical Applications.................................................. 17 8.3 Power Supply Recommendations.............................21 8.4 Layout....................................................................... 21 9 Device and Documentation Support............................22 9.1 Documentation Support............................................ 22 9.2 Receiving Notification of Documentation Updates....22 9.3 Support Resources................................................... 22 9.4 Trademarks............................................................... 22 9.5 Electrostatic Discharge Caution................................22 9.6 Glossary....................................................................22 10 Mechanical, Packaging, and Orderable Information.................................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (September 2022) to Revision A (November 2022) Page • Changed device status from advanced information (preview) to production data (active)................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 5 Pin Configuration and Functions VDD 1 10 VREF VOUT 2 9 NC RSTSEL 3 8 SDIN AGND 4 7 SYNC RESET 5 6 SCLK Not to scale Figure 5-1. DRX (10-Pin WSON) Package, Top View Table 5-1. Pin Functions PIN NAME NO. TYPE DESCRIPTION AGND 4 Ground NC 9 — Ground reference point for all circuitry on the device. RESET 5 Input Asynchronous reset. Active low. If RESET is low, all DAC channels reset either to zero-scale (RSTSEL = AGND) or to midscale (RSTSEL = VDD). RSTSEL 3 Input Reset select pin. DAC powers up to zero scale if RSTSEL = AGND. DAC powers up to midscale if RSTSEL = VDD. SCLK 6 Input Serial interface clock of SPI. SDIN 8 Input Serial interface data input of SPI. Data are clocked into the input shift register on each falling edge of the SCLK pin. SYNC 7 Input Serial data enable of SPI. Active low. This input is the frame-synchronization signal for the serial data. When the signal goes low, the serial interface input shift register is enabled. VDD 1 Power Analog supply voltage (2.7 V to 5.5 V) VOUT 2 Output Analog output voltage from DAC VREF 10 Input Do not connect This pin is the external reference input to the device. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 3 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN VS Input voltage MAX VDD to AGND –0.3 6 VREF to AGND –0.3 VDD + 0.3 Digital inputs to AGND –0.3 VDD + 0.3 Output voltage, VOUT to AGND –0.3 VDD + 0.3 UNIT V V Input current into any digital pin –10 10 mA TJ Junction temperature –40 150 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) UNIT ±1500 V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT POWER SUPPLY VS Positive supply voltage to ground, VDD to AGND 2.7 5.5 V DIGITAL INPUTS VIH Input high voltage VIL Input low voltage 1.62 V 0.45 V REFERENCE INPUT VREF Reference voltage to ground, VREF to AGND 2.0 VDD V Operating temperature –40 85 °C TEMPERATURE TA 6.4 Thermal Information DAC82001 THERMAL METRIC(1) DRX (WSON) UNIT 10 PINS RθJA Junction-to-ambient thermal resistance 99.7 °C/W RθJC(top) Junction-to-case (top) thermal resistance 49.9 °C/W RθJB Junction-to-board thermal resistance 35.9 °C/W ΨJT Junction-to-top characterization parameter 1.7 °C/W ΨJB Junction-to-board characterization parameter 35.7 °C/W (1) 4 For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 6.5 Electrical Characteristics all minimum and maximum values at TA = –40°C to +85°C and all typical values at TA = 25°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.0 V ≤ VREF ≤ 5.5 V , AGND = 0 V, and digital inputs at VDD or AGND (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±0.6 2 LSB STATIC PERFORMANCE Resolution 16 INL Integral nonlinearity –2 DNL Differential nonlinearity TUE Total unadjusted error Zero code error Bits –1 ±0.5 1 –0.06 0.04 0.06 %FSR –2.6 0.5 2.6 LSB Zero code error temperature coefficient ±0.02 Gain error –20 Gain error temperature coefficient 4 LSB ppm/°C 20 ±0.1 LSB ppm/°C OUTPUT CHARACTERISTICS VO Output voltage ZO Output impedance PSRR DC Power supply rejection ratio (dc) 0 VREF 6.25 DAC at midscale; VDD = 5 V ±10%, VREF = 2.5 V V kΩ 5 μV/V DYNAMIC PERFORMANCE ts Output voltage settling time To 1/2 LSB of FS, CL = 10 pF Output noise DAC at midcode, 0.1 Hz to 10 Hz 0.1 μVPP Output noise density DAC at midcode, measured at 10 kHz 10 nV/√Hz SFDR Spurious free dynamic range 1-kHz sinusoid at DAC output (unbuffered, full scale), DAC updated at 200 kSPS with 40-kHz low-pass filter, include up to 7th harmonics –96 dB THD Total harmonic distortion 1-kHz sinusoid at DAC output (unbuffered, full scale), DAC updated at 200 kSPS with 40-kHz low-pass filter, include up to 7th harmonics –91 dB DAC at midscale, VREF = 2.5 V, VDD = 5 V ±200 mV at 10 kHz –72 dB ±1 LSB around major carry 0.5 nV-s 0.5 nV-s 0.8 V PSRR AC Power supply rejection ratio (ac) Code change glitch impulse 1 Digital feedthrough Power on glitch magnitude CLOAD = 10 pF µs VOLTAGE REFERENCE INPUT Reference input voltage ZREF Reference input impedance CREF Reference input capacitance 2.0 VDD 5 V kΩ 75 pF 0.4 V DIGITAL INPUTS Hysteresis voltage Input current Pin capacitance –5 Per pin 5 10 µA pF POWER IDD Power-supply current Power VDD = 3 V 250 350 VDD = 5 V 250 350 VDD = 3 V 750 1050 VDD = 5 V 1250 1750 µA µW Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 5 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 6.6 Timing Requirements all input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VIL + VIH) / 2. 2.7 V ≤ VDD ≤ 5.5 V, VIH = 1.62 V, VIL = 0.15 V, 2.0 V ≤ VREF ≤ 5.5 V, and TA = –40°C to +85°C (unless otherwise noted) MIN NOM MAX UNIT 50 MHz fSCLK SCLK frequency tSCLKHIGH SCLK high time 9 ns tSCLKLOW SCLK low time 9 ns tSDIS SDIN setup 5 ns tSDIH SDIN hold 10 ns tSYNCS SYNC falling edge to SCLK falling edge setup 13 ns tSYNCH SCLK falling edge to SYNC rising edge 10 ns tSYNCHIGH SYNC high time 160 ns tSYNCIGNORE SCLK falling edge to SYNC ignore 15 ns tDACWAIT Sequential DAC update wait time 1 µs 6.7 Timing Diagram tSYNCHIGH tSYNCH tSYNCS SYNC tSYNCIGNORE tSCLKLOW SCLK tSCLKHIGH SDIN Bit 23 tSDIS Bit 1 Bit 0 tSDIH Figure 6-1. Timing Diagram 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 6.8 Typical Characteristics at TA = 25°C, channel output shown, and DAC outputs unloaded (unless otherwise noted) 1 0.6 85 C 25 C -40 C 0.8 Integral Nonlinearity Error (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -1 0 8192 16384 24576 32768 40960 49152 57344 65535 DAC Code 0 8192 16384 24576 32768 40960 49152 57344 65535 DAC Code VDD = 5.5 V, VREF = 5.0 V VDD = 2.7 V, VREF = 2.5 V Figure 6-2. Integral Linearity Error vs Digital Input Code 0.5 0.4 -40 C 25 C 85 C 0.4 -40 C 25 C 85 C 0.3 0.3 % of Units 0.2 0.2 0.1 0.1 Differential Nonlinearity Error (LSB) 85 C 25 C 1 1. 2 0. 8 0. 6 0. 4 Maximum/Minimum Integral Nonlinearity Error (LSB) VDD = 2.7 V, VREF = 2.5 V VDD = 5.5 V, VREF = 5.0 V Figure 6-4. Integral Linearity Error Histogram 0.4 0 1 0. 8 0. 6 0. 4 0. 2 0 -0 .2 -0 .4 -0 .6 -0 .8 -1 Maximum/Minimum Integral Nonlinearity Error (LSB) -1 -0 .8 -0 .6 -0 .4 -0 .2 0 0 -1 .2 % of Units Figure 6-3. Integrated Linearity Error vs Digital Input Code 0. 2 Integral Nonlinearity Error (LSB) 1 85 C 25 C -40 C 0.8 Figure 6-5. Integrated Linearity Error Histogram -40 C 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 8192 16384 24576 32768 40960 49152 57344 65535 DAC Code VDD = 2.7 V, VREF = 2.5 V VDD = 5.5 V, VREF = 5.0 V Figure 6-6. Differential Linearity Error vs Digital Input Code Figure 6-7. Differential Linearity Error vs Digital Input Code Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 7 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 6.8 Typical Characteristics (continued) at TA = 25°C, channel output shown, and DAC outputs unloaded (unless otherwise noted) Total Unadjusted Error (m%FSR) 5 -40 C 25 C 85 C 0 -5 -10 -15 -20 -25 -30 0 8192 16384 24576 32768 40960 49152 57344 65535 DAC Code VDD = 2.7 V, VREF = 2.5 V VDD = 5.5 V, VREF = 5.0 V Figure 6-9. Total Unadjusted Error vs Digital Input Code Figure 6-8. Total Unadjusted Error vs Digital Input Code -8 1.5 VREF = 2.5 V VREF = 5.0 V -9 Gain Error (LSB) Zero Scale Error (LSB) 1.4 1.3 1.2 -10 -11 1.1 VDD = 2.7 V VDD = 5.5 V 1 -40 -15 10 35 Temperature (C) 60 -12 -40 85 Figure 6-10. Zero-Code Error vs Temperature 60 85 Figure 6-11. Gain Error vs Temperature 260 250 240 230 VDD = 5.5 V VDD = 2.7 V 220 -40 -15 10 35 Temperature (C) 60 Figure 6-12. Supply Current vs Temperature 85 Power Down Current, IVDD (A) 270 Supply Current, IVDD (A) 10 35 Temperature (C) 10 280 8 -15 VDD = 5.5 V VDD = 2.7 V 8 6 4 2 0 -40 -15 10 35 Temperature (C) 60 85 Figure 6-13. Power-down Current vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 6.8 Typical Characteristics (continued) at TA = 25°C, channel output shown, and DAC outputs unloaded (unless otherwise noted) SYNC DAC (20 mV/div) Time (100 ns/div) VDD = 5.5 V, VREF = 5.0 V, DAC code transition from midscale – 1 to midscale LSB Figure 6-14. Glitch Impulse, Rising Edge, 1-LSB Step VDD = 5.5 V, VREF = 5.0 V, DAC code transition from midscale to midscale - 1 LSB Figure 6-15. Glitch Impulse, Falling Edge, 1-LSB Step SYNC DAC ( 0.5 V/div) Time (100 ns/div) VDD = 2.7 V, VREF = 2.5 V VDD = 2.7 V, VREF = 2.5 V Voltage (V) Figure 6-16. Full-Scale Settling Time, Rising Edge 6 5.5 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 Figure 6-17. Full-Scale Settling Time, Falling Edge VDD (1 V/div) VREF (1 V/div) DAC Output (50mV/div) VDD (V) VREF (V) DAC Output 0 1 2 3 4 5 6 Time (ms) 7 8 9 10 Time (1 ms/div) VDD = 5.5 V, VREF = 5.0 V VDD = 5.5 V, VREF = 5.0 V Figure 6-18. Power-On Glitch Figure 6-19. Power-Off Glitch Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 9 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 6.8 Typical Characteristics (continued) at TA = 25°C, channel output shown, and DAC outputs unloaded (unless otherwise noted) -40 -45 -50 AC PSRR (dB) -55 -60 -65 -70 -75 -80 -85 -90 1 10 100 1000 10000 Frequency (Hz) 100000 1000000 VDD = 5.5 V, VREF = 5.0 V VDD = 5.5 V, DAC code at midscale Figure 6-21. Output Noise Density vs Frequency Figure 6-20. Power-Supply Rejection Ratio (PSRR) 700 Reference Current (A) SCLK (2.7 V/div) VOUT (200 V/div) VREF = 2.5 V VREF = 5.0 V 600 500 400 300 200 100 0 0 8192 16384 24576 32768 40960 49152 57344 65535 DAC Code (LSB) Time (100 ns/div) VDD = 2.7 V, VREF = 2.5 V Figure 6-22. Reference Current vs Digital Input Code Figure 6-23. Clock Feedthrough 6 SYNC (2.7 V/div) VOUT (150 V/div) RESET DAC Output 5 Voltage (V) 4 3 2 1 0 -1 Time (200 ns/div) Time (50 ns/div) VDD = 5.5 V, VREF = 5.0 V VDD = 2.7 V, VREF = 2.5 V Figure 6-25. RESET Response Figure 6-24. Control Feedthrough 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 7 Detailed Description 7.1 Overview The DAC82001 device is a single-channel, unbuffered voltage output, 16‑bit digital-to-analog converter (DAC) operating from a single 3.3-V to 5-V power supply. This converter provides 1-LSB DNL and 2-LSB INL linearity. With a 10-pF load, the output of the DAC82001 settles to ½ LSB of full scale at 1 µs. The glitch impulse of 1-LSB code change around major carry is 0.5 nV-s. The device incorporates a power-on-reset circuit to make sure that the DAC output powers up at zero scale or midscale, depending on status of the RSTSEL pin, and remains at that scale until a valid code is written to the device. All internal registers are asynchronously reset after the RESET pin is pulled low. Similar to the power-on-reset, the RESET signal sets the DAC output to zero scale or midscale based on the status of the RSTSEL pin. The digital interface of the DAC82001 uses a 3-wire serial peripheral interface (SPI) that operates at clock rates of up to 50 MHz. 7.2 Functional Block Diagram VDD VREF SCLK SDIN RESET RSTSEL Interface Logic SYNC DAC Buffer DAC Register DAC VOUT Power On Reset AGND Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 11 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 7.3 Feature Description 7.3.1 Digital-to-Analog Converter (DAC) Architecture The output channel in the DAC82001 device consists of a segmented R-2R architecture. Figure 7-1 shows a block diagram of the DAC architecture. The four MSBs of the 16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects one of 15 matched resistors to either AGND or VREF. The remaining 12 bits of the data word drive switches S0 to S11 of a 12-bit voltage mode R-2R ladder network. R R VOUT 2R 2R 2R 2R 2R 2R 2R S0 S1 S11 E1 E2 E15 VREF GND 12-Bit R-2R Ladder 4 MSBs Decoded into 15 Equal Segments Figure 7-1. DAC82001 DAC Block Diagram 7.3.1.1 DAC Transfer Function The input data writes to the individual DAC data registers in straight binary format. After a power-on or a reset event, all DAC registers are set to zero code (RSTSEL = AGND) or midscale code (RSTSEL = VDD). The DAC transfer function is shown by Equation 1. where: • • • VOUT = DAC_DATA × VREF N (1) 2 N = 16 (resolution in bits) DAC_DATA = decimal equivalent of the binary code that is loaded to the DAC register (address 8h), DAC_DATA ranges from 0 to 2N – 1 VREF = DAC external reference voltage. VREF ranges from 2.0 V to VDD 7.3.1.2 DAC Register Structure Data written to the DAC data registers are initially stored in the DAC buffer registers. The update mode of the DAC output is determined by the status of the DAC_SYNC_EN bit (address 2h). In asynchronous mode (default, DAC_SYNC_EN = 0), a write to the DAC buffer register results in an immediate update of the DAC active register. The DAC output (VOUT pin) updates on the rising edge of SYNC. In synchronous mode (DAC_SYNC_EN = 1), writing to the DAC buffer register does not automatically update the DAC active register. Instead, the update occurs only after a software LDAC trigger event. A software LDAC trigger generates through the LDAC bit in the TRIGGER register (address 5h). 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 7.3.2 Power-On Reset (POR) The DAC82001 device includes a power-on reset function that controls the output voltage at power up. After the VDD supply has been established, a POR event is issued. The POR causes all registers to initialize to default values, and communication with the device is valid only after a 250-µs, power-on-reset delay. The default value for all DACs is zero code if RSTSEL = AGND, and midscale code if RSTSEL = VDD. The DAC channel remains at the power-up voltage until a valid command is written to the channel. When the device powers up, a POR circuit sets the device to the default mode. Figure 7-2 shows that the POR circuit requires specific VDD levels to make sure that the internal capacitors discharge and reset the device at power up. To make sure that a POR occurs, VDD must be less than 0.7 V for at least 1 ms. When VDD drops to less than 2.2 V but remains greater than 0.7 V (shown as the undefined region in Figure 7-2), the device may or may not reset under all specified temperature and power-supply conditions; in this case, initiate a POR. When VDD remains greater than 2.2 V, a POR does not occur. VDD (V) 5.50 No power-on reset Spe cified supply voltage range 2.70 2.20 Undefined 0.70 Power-on reset 0.00 Figure 7-2. Threshold Levels for the VDD POR Circuit 7.3.3 Hardware Reset The DAC output is asynchronously set to zero code if RSTSEL = AGND, and midscale code if RSTSEL = VDD, immediately after the RESET pin is brought low. The RESET signal resets all internal registers, meaning all registers initialize to default values. Bring the RESET pin back to high before a write sequence starts. Similar to the POR delay, communication with the device is valid only after a 250‑µs delay. The default value for the DAC channel remains at the reset voltage until a valid command is written to the channel. The RSTSEL pin can be reconfigured without a power cycle. The DAC output always reflects the current RSTSEL status when the RESET pin is pulled low. 7.3.4 Software Reset A device software reset event is initiated by writing the reserved code 0x1010 to the SOFT-RESET bits in the TRIGGER register (address 5h). A software reset initiates a POR event. 7.4 Device Functional Modes The DAC82001 has one mode of operation: normal. In normal mode, the DAC82001 is fully operational. The device translates digital input or reset input to corresponding analog output. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 13 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 7.5 Programming 7.5.1 Serial Peripheral Interface (SPI) The DAC82001 is controlled through a 3-wire serial peripheral interface (SPI) using SYNC, SCLK, and SDIN. The serial interface operates at up to 50 MHz. The input shift register is 24-bits wide. Table 7-1 shows the SPI frame format. Table 7-1. SPI Frame Format BIT 23 22 21 20 19 18 17 16 DESC W Register Address - Command Byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16-Bit MSB-Aligned DAC Data Serial clock SCLK is a continuous or a gated clock. The first falling edge of SYNC starts the operation cycle. When SYNC is high, the SCLK and SDIN signals are blocked. The device internal registers are updated from the shift register on the rising edge of SYNC. 7.5.1.1 SYNC Interrupt For SPI operation, the SYNC line stays low for at least 24 falling edges of SCLK, and the addressed DAC register updates on the SYNC rising edge. However, if the SYNC line is brought high before the 24th SCLK falling edge, this event acts as an interrupt to the write sequence. The shift register resets and the write sequence is discarded. As Figure 7-3 shows, the data buffer contents and the DAC register contents do not update, and the operating mode does not change. SCLK 1 2 24 SYNC SDIN DB23 DB0 Invalid or interrupted write sequence SCLK 1 2 24 SYNC SDIN DB23 DB0 Valid write sequence Figure 7-3. SYNC Interrupt 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 7.6 Register Maps 7.6.1 Registers Table 7-2. DAC82001 Registers Offset Register Description Section 0h No Operation NOOP Register 2h Synchronization SYNC Register 5h Trigger TRIGGER Register 8h DAC DAC Register 7.6.1.1 NOOP Register (offset = 0h) [reset = 0000h] Figure 7-4. NOOP Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 NOOP W-0h Table 7-3. NOOP Register Field Descriptions Bit 15-0 Field Type Reset Description NOOP W 0h No operation command Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 15 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 7.6.1.2 SYNC Register (offset = 2h) [reset = 0000h] Figure 7-5. SYNC Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED DAC-SYNCEN W-0h W-0h Table 7-4. SYNC Register Field Descriptions Bit 15-1 0 Field Type Reset Description RESERVED W 0h These bits are reserved. DAC-SYNC-EN W 0h When set to 1, the DAC output is set to update in response to an LDAC trigger (synchronous mode). When cleared to 0, the DAC output is set to update immediately (asynchronous mode), default. 7.6.1.3 TRIGGER Register (offset = 5h) [reset = 0000h] Figure 7-6. TRIGGER Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RESERVED LDAC SOFT-RESET [3:0] W-0h W-0h W-0h 0 Table 7-5. TRIGGER Register Field Descriptions Bit 15-5 4 3-0 Field Type Reset Description RESERVED W 0h These bits are reserved. LDAC W 0h Set this bit to 1 to synchronously load the DAC that is set to synchronous mode in the SYNC register. This bit self-resets. SOFT-RESET [3:0] W 0h When set to reserved code 1010, this bit resets the device to the default state. This bit self-resets. 7.6.1.4 DAC Register (offset = 8h) [reset = 0000h when RSTSEL is logic low, or reset = 8000h when RSTSEL is logic high] Figure 7-7. DAC Register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAC-DATA [15:0] W-0000h when RSTSEL is logic low or 8000h when RSTSEL is logic high Table 7-6. DAC Data Register Field Descriptions (8h) Bit 15-0 16 Field Type Reset Description DAC-DATA [15:0] W 0000h when RSTSEL is logic low or 8000h when RSTSEL is logic high Data are MSB aligned in straight binary format. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information Generating accurate, stable, programmable dc voltages is a key requirement in most precision end equipment. The DAC82001 serves a wide range of end equipment, such as battery testers, communications equipment, factory automation and control, test and measurement. The DAC82001 tiny package, high resolution, fast settling, and simple interface makes this device an excellent choice for applications such as offset and gain control, arbitrary waveform generation (AWG), closed-loop control, and bipolar analog outputs. A wide variety of operational amplifiers can be used as output buffers for the DAC82002, allowing the user to choose components that best fit their design. 8.2 Typical Applications 8.2.1 Arbitrary Waveform Generator Arbitrary waveform generation (AWG) circuits are common in test and measurement equipment. These circuits are used to generate ac waveforms for test applications. The key performance parameters in test and measurement circuits are total harmonic distortion and noise (THD+N), signal-to-noise ratio (SNR), and the update rate. Figure 8-1 shows a basic example of an AWG circuit using the DAC82001. VDD VREF 100 nF 47 pF 5V – DAC82001 VOUT + OPA328 Figure 8-1. Arbitrary Waveform Generator 8.2.1.1 Design Requirements • • • DAC output range: 0 V to 2.5 V THD+N at 1 kHz: < –91 dB Update rate: 200 kHz 8.2.1.2 Detailed Design Procedure Figure 8-1 shows a simplified circuit diagram of an arbitrary waveform generator. The DAC82001 specifies a THD+N of –91 dB at 1 kHz. The OPA328 provides a great balance between fast settling, bandwidth, and voltage and current noise. The buffer must have a negative voltage supply rail or an output offset to make sure the DAC output is not clipped. Attach two decoupling capacitors as close as possible to the VREF pin. Use 100 nF for the first capacitor to provide very good noise performance for the system. Use 47 pF for the second capacitor to allow for a good dynamic response performance that improves any code-to-code glitch. The REF5025 is a low-noise, very low-drift, precise voltage reference that generates a 2.5-V reference for this application. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 17 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 8.2.1.3 Application Curves Figure 8-2 shows the THD+N plot vs frequency of the buffer output using a 20-Hz to 20-kHz sine wave sweep with a DAC code range of 0x81FF ± 0x7E00 to prevent voltage clipping. A 40-kHz low-pass filter is also used in the measurement tool. -65 THD+Noise (dB) -70 -75 -80 -85 -90 -95 20 100 1k Frequency (Hz) 10k 20k 20-Hz to 20-kHz sine wave sweep with a code range of 0x81FF ± 0x7E00 40-kHz low-pass filter Figure 8-2. THD+N vs Frequency FFT Amplitude (dB) Figure 8-3 shows the FFT of the buffer output using a 1-kHz sine wave with a code range of 0x81FF ± 0x7E00 to prevent voltage clipping. 32768 bins, 8 averages, and a 40-kHz low-pass filter are also used in the measurement tool. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 10 100 1000 Frequency (Hz) 10000 40000 1-kHz sine wave with a code range of 0x81FF ± 0x7E00 32768 bins, 8 averages, 40-kHz low-pass filter Figure 8-3. FFT Amplitude vs Frequency 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 8.2.2 Bipolar Analog Output Configuration Programmable logic circuits (PLCs) have analog output modules that typically output ±10 V. This bipolar analog output circuit converts the unipolar DAC output to a bipolar ±10-V output. The key performance parameters of these circuits are noise and slew rate. The circuit can also be used to force voltage in semiconductor test applications. Figure 8-4 shows the example configuration using the DAC82001. VDD VREF 15 V DAC82001 VOUT OPA210 + VOP – VREF 8.25 k
–15 V 33.2 k 11 k 100 pF Figure 8-4. Bipolar Analog Output Circuit 8.2.2.1 Design Requirements • • • • DAC output range: 0 V to 2.5 V PLC analog output range: –10 V to +10 V Noise: < 3 µV/√Hz Slew rate: > 1 V/µs 8.2.2.2 Detailed Design Procedure The OPA210 output buffer provides a balance between fast settling, bandwidth, voltage and current noise, and wide voltage rails. The buffer uses ±15-V voltage rails to make sure there is no voltage clipping. The REF5025 is a low-noise, very low-drift, precise voltage reference and is used to generate a stable 2.5-V reference for this application. To further reduce noise, use a 100-pF capacitor between the non-inverting input pin and the output of the OPA210. 8.2.2.3 Application Curves Figure 8-5 shows the noise on the buffer output vs frequency using a 100-Hz to 1-MHz frequency sweep with a grounded reference to isolate the noise in the circuit. 2000 1800 1600 Noise (nV/vHz) 1400 1200 1000 800 600 400 200 0 100 1k 10k Frequency (Hz) 100k 1M Figure 8-5. Noise vs Frequency Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 19 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 Figure 8-6 shows the output of the circuit rising from –10 V to +10 V, with the DAC starting at code 0x0000 and ending at code 0xFFFF. The measured slew rate is 2.5 V/µs. The REF5025 is used as a 2.5-V reference. 12 10 8 DAC SYNC DAC OUT BUFFER OUT 6 Voltage (V) 4 2 0 -2 -4 -6 -8 -10 -12 -5 -3 -1 1 3 5 7 Time (µs) 9 11 13 15 DAC at code 0x0000 rising to code 0xFFFF Figure 8-6. Bipolar Output Rising Slew Rate Figure 8-7 shows the output of the circuit falling from +10 V to –10 V, with the DAC starting at code 0xFFFF and ending at code 0x0000. This measured slew rate is 2.5 V/µs. The REF5025 is used as a 2.5-V reference. 12 DAC SYNC DAC OUT BUFFER OUT 10 8 6 Voltage (V) 4 2 0 -2 -4 -6 -8 -10 -12 -5 -3 -1 1 3 5 7 Time (µs) 9 11 13 15 DAC at code 0xFFFF falling to code 0x0000 Figure 8-7. Bipolar Output Falling Slew Rate 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 8.3 Power Supply Recommendations The DAC82001 operates within the specified VDD supply range of 2.7 V to 5.5 V. The DAC82001 does not require specific supply sequencing, but VREF must be less than VDD, as noted in the Absolute Maximum Ratings. The VDD supply must be well-regulated and low-noise. Switching power supplies and DC/DC converters often have high-frequency glitches or spikes riding on the output voltage. Digital components also create similar high-frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. To further minimize noise from the power supply, include a 1-μF to 10-μF capacitor and 0.1-μF bypass capacitor. 8.4 Layout 8.4.1 Layout Guidelines A precision analog component requires careful layout. The following list provides some insight into good layout practices. • Bypass the VDD to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 0.1-µF to 0.22-µF ceramic capacitor, with a X7R or NP0 dielectric. • Bypass VREF to ground with low ESR ceramic bypass capacitors. • Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize performance. • The output pin, VOUT, has relatively high impedance and is susceptible to high parasitic capacitance. Use short and direct traces when routing VOUT. 8.4.2 Layout Example GND GND Reference Bypass Capacitor Decoupling Capacitor DAC82001 Pull-Down Resistor (for Zero Scale Reset) VDD 1 10 VOUT 2 9 3 8 4 7 GND 5 6 GND Pull-Down Resistor SDIN VDD Pull-up Resistor SYNC SCLK Ground and Power Planes Omitted for Clarity Figure 8-8. Layout Example Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 21 DAC82001 www.ti.com SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022 9 Device and Documentation Support 9.1 Documentation Support 9.1.1 Related Documentation For related documentation see the following: Texas Instruments, DAC82002EVM user's guide 9.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 9.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 9.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 9.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 9.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 10 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DAC82001 PACKAGE OPTION ADDENDUM www.ti.com 8-Aug-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) DAC82001DRXR ACTIVE WSON DRX 10 3000 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D821 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of