DA
C8
234
DAC8234
DA
C8
234
www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009
Quad, 14-Bit, High-Accuracy, ±16V Output, Serial Input
DIGITAL-TO-ANALOG CONVERTER
FEATURES
DESCRIPTION
1
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•
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2345
•
•
•
•
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Bipolar Output: Up to ±16V
Unipolar Output: 0V to +20V
14-Bit Monotonic
Relative Accuracy: 0.5 LSB Max
Low Zero and Gain Errors
– Before User Calibration: 1 LSB
– After User Calibration:
0.031 LSB Zero Error, 0.25 LSB Gain Error
Low Noise: 60nV/√Hz
Settling Time: 6µs
Configurable Gain: x2/x4
Analog Output Monitor
Power-Down Mode
SPI™: Up to 50MHz, 1.8V/3V/5V Logic
Daisy-Chain Mode
Operating Temperature: –40°C to +105°C
Packages: QFN-40 (6x6mm), TQFP-48 (7x7mm)
APPLICATIONS
•
•
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•
Automatic Test Equipment
Instrumentation
Industrial Process Control
Communications
IOVDD
DGND
DVDD
AGND
AVDD
AVSS
REF-A
REFGND-A
DAC8234
Command Register
Reference Buffer A
Analog
Monitor
CS
SCLK
SDI
SPI
Shift
Register
Input
Control
Logic
Zero Register 0
Gain Register 0
14-Bit DAC
Zero Register 1
Gain Register 1
RST
RFB1-2
RFB2-2
VOUT-2
SGND-2
UNI/BIP-A
14-Bit DAC
DAC Register 2
UNI/BIP-B
LDAC
GPIO-0
GPIO-1
Zero Register 2
Gain Register 2
Control
Logic
RFB1-3
RFB2-3
VOUT-3
SGND-3
14-Bit DAC
DAC Register 3
Zero Register 3
Gain Register 3
Reference Buffer B
The DAC8234 is pin-compatible with the DAC8734
(16-bit) and the DAC7716 (12-bit).
RFB1-1
RFB2-1
VOUT-1
SGND-1
SDO
DAC Register 1
The DAC8234 has integrated reference buffers and
output buffers. It features a standard high-speed
1.8V, 3V, or 5V serial peripheral interface (SPI) that
operates at clock rates of up to 50MHz to
communicate with a DSP or microprocessor. The four
DAC channels and the auxiliary registers are
addressed with four address bits. The device features
double-buffered interface logic for simultaneous
updates of all DACs. An asynchronous load input
(LDAC) transfers data from the input data register to
the DAC latch, and the contents of the DAC latch set
the output voltage. The asynchronous RST input sets
the output of all four DACs to 0V. The VMON pin is an
analog monitor output that multiplexes the individual
DAC outputs or the AIN pin.
VMON
RFB1-0
RFB2-0
VOUT-0
SGND-0
14-Bit DAC
DAC Register 0
The DAC8234 is a high-accuracy, quad-channel,
14-bit digital-to-analog converter (DAC) that operates
from supply voltages of ±5V to ±18V in bipolar output
mode, and from ±5V to +24V/–12V in unipolar mode.
With a 5V reference, the DAC8234 can be configured
to output ±10V, ±5V, 0V to 20V, or 0V to 10V. The
DAC8234 provides 14-bit monotonicity, excellent
integral nonlinearity (INL) error of ±0.5 LSB, low
glitch, and low noise over the operating temperature
range of –40°C to +105°C. This device is trimmed in
production for very low zero and gain errors. In
addition,
the
DAC8234
implements
a
user-programmable system-level calibration function
to achieve ±0.031 LSB zero error and ±0.25 LSB gain
error.
Power-Down
Control Logic
AIN
REF-B
REFGND-B
1
2
3
4
5
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DSP is a trademark of Texas Instruments.
SPI, QSPI are trademarks of Motorola Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
DAC8234
SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION (1)
PRODUCT
RELATIVE
ACCURACY
(LSB)
DIFFERENTIAL
LINEARITY
(LSB)
±0.5
±0.5
DAC8234
(1)
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
±0.5
QFN-40
RHA
–40°C to +105°C
DAC8234
±0.5
TQFP-48
PFB
–40°C to +105°C
DAC8234
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
AVDD to AVSS
(2)
DAC8234
UNIT
–0.3 to 38
V
AVDD to AGND (2)
–0.3 to 25
V
AVSS to AGND, DGND (2)
–19 to 0.3
V
DVDD to DGND
–0.3 to 6
V
IOVDD to DGND
–0.3 to DVDD + 0.3
V
Digital input voltage to DGND
–0.3 to IOVDD + 0.3
V
SDO to DGND
–0.3 to IOVDD + 0.3
V
SGND-x, REFGND-x, AGND to DGND
VOUT-x, RFB1-x, RFB2-x, VMON, AIN to AVSS
REF-x to REFGND-x, AGND
GPIO-x to DGND
–0.3 to +0.3
V
–0.3 to AVDD + 0.3
V
–0.3 to min(AVDD/2, –AVSS/2)
V
–0.3 to 6
V
5
mA
Operating temperature range
–40 to +105
°C
Storage temperature range
–65 to +150
°C
GPIO-x input current
Maximum junction temperature (TJ max)
ESD ratings
+150
°C
Human body model (HBM)
4
kV
Charged device model (CDM)
1
kV
TQFP
57
°C/W
QFN
32
°C/W
TQFP
35
°C/W
20
°C/W
(TJ max – TA) / θJA
W
Junction-to-ambient, θJA
Thermal impedance
Junction-to-case, θJC
QFN
Power dissipation (3)
(1)
(2)
(3)
2
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
AVSS must be < –3.5V if AVDD ≥ 1V.
TA is the ambient temperature.
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DAC8234
www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, AVDD = +11V to +18V, AVSS = –11V to –18V, VREF = REF-A = REF-B = +5V,
DVDD = +5V, IOVDD = +1.8V to DVDD, AGND = DGND = REFGND-A = REFGND-B = SGND-x = 0V, and DAC gain = 4, unless
otherwise noted.
DAC8234
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
±0.5
LSB
±0.5
LSB
±1
LSB
STATIC PERFORMANCE
Bipolar Output
Resolution
14
Bits
Linearity error, INL
Differential linearity error, DNL
TA = +25°C, before user calibration
Bipolar zero error (1)
Bipolar zero error TC
Gain error
TA = +25°C, after user calibration (2)
±0.031
(2)
±0.5
TA = +25°C, before user calibration
(1)
ppm FSR/°C
±1
TA = +25°C, after user calibration (2)
Gain error TC (2)
DC crosstalk (2) (3)
LSB
LSB
±0.25
LSB
±0.5
ppm FSR/°C
Output unloaded
±0.1
LSB
Unipolar Output
Resolution
14
Bits
Linearity error, INL
AVDD = +21V, AVSS = –11V
±0.5
LSB
Differential linearity error, DNL
AVDD = +21V, AVSS = –11V
±0.5
LSB
±1
LSB
AVDD = +21V, AVSS = –11V, TA = +25°C, before user
calibration
Zero error
Zero error TC
AVDD = +21V, AVSS = –11V, TA = +25°C, after user
calibration (2)
(2)
±0.031
AVDD = +21V, AVSS = –11V
±0.2
AVDD = +21V, AVSS = –11V, TA = +25°C, before user
calibration
Gain error
AVDD = +21V, AVSS = –11V
DC crosstalk (2) (3)
AVDD = +21V, AVSS = –11V, output unloaded
ppm FSR/°C
±1
AVDD = +21V, AVSS = –11V, TA = +25°C, after user
calibration (2)
Gain error TC (2)
LSB
LSB
±0.25
LSB
±0.5
ppm FSR/°C
±0.1
LSB
ANALOG OUTPUT (VOUT-0 to VOUT-3)
Bipolar voltage output (4)
Unipolar voltage output (4)
Output voltage drift vs time
Output impedance (2)
AVDD = +16.5V, AVSS = –16.5V, VREF = +7.5V, gain = 4
–15
+15
V
VREF = +5V, gain = 4
–10
+10
V
0
+20
V
AVDD = +21V, AVSS = –11V, VREF = +5V, gain = 4
Operating for 500 hours at +25°C
2
ppm of FSR
Operating for 1000 hours at +25°C
3
ppm of FSR
±3mA load current
Short-circuit current (2) (5)
Load current (4)
10
Output changes no more than ±1 LSB
Power-supply rejection
(1)
(2)
(3)
(4)
(5)
mA
±3
Capacitive load stability (2)
(2) (4)
Ω
0.005
mA
700
AVDD = +5V to +18V, AVSS = –5V to –18V,
DVDD = 5V ±10%, VREF = 2V
±0.1
pF
LSB
See the User Calibration for Zero-Code Error and Gain Error section for details.
Specified by design and characterization.
DC crosstalk is the dc change in the output of one channel as a result of a full-scale code change and subsequent output change on
another channel. The DAC outputs are buffered by op amps that share common AVDD and AVSS power supplies. Multiple VDD and VSS
terminals are provided to minimize dc crosstalk.
The analog output must not be greater than (AVDD – 1.0V) and must not be less than (AVSS + 1.0V).
When the output current is greater than the specification, the current is clamped at the specified maximum value.
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DAC8234
SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009 ........................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = TMIN to TMAX, AVDD = +11V to +18V, AVSS = –11V to –18V, VREF = REF-A = REF-B = +5V,
DVDD = +5V, IOVDD = +1.8V to DVDD, AGND = DGND = REFGND-A = REFGND-B = SGND-x = 0V, and DAC gain = 4, unless
otherwise noted.
DAC8234
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE (6)
To 0.03% of FS, CL = 200pF, RL= 10kΩ, output changes
from –10V to +10V or +10V to –10V
6
µs
To 1 LSB, CL = 200pF, RL = 10kΩ, output changes from
–10V to +10V or +10V to –10V
8
µs
To 1 LSB, CL = 200pF, RL = 10kΩ, code changes 512
LSBs
4
µs
Slew rate (7)
CL = 200pF, RL = 10kΩ
5
V/µs
Recovery time from
power-down mode
Delay from clearing bit PD-x to when DAC returns to
normal operation
50
µs
Digital-to-analog glitch (8)
1 LSB code change around midscale
8
nV-s
Glitch impulse peak amplitude
1 LSB code change around midscale
15
mV
Settling time
Channel-to-channel isolation (9)
–80
dB
DAC-to-DAC crosstalk (10)
2
nV-s
Digital crosstalk (11)
2
nV-s
Digital feedthrough (12)
2
nV-s
1
µVRMS
40
µVRMS
0.1Hz to 10Hz, ±10V output range, gain = 4, midscale code
Output noise
0.1Hz to 100kHz, ±10V output range, gain = 4, midscale
code
1/f corner frequency
Output noise spectral density
MONITOR PIN (VMON)
500
Hz
TA = +25°C, at 10kHz, ±10V output range, gain = 4,
midscale code
60
nV/√Hz
TA = +25°C, at 10kHz, 0V to +10V output range, gain = 2,
midscale code
45
nV/√Hz
(6)
Output impedance
Ω
2200
High-impedance leakage
current
100
nA
Continuous current limit
0.5
mA
REFERENCE INPUT
Reference input voltage range
1
Reference input dc impedance
10
Reference input capacitance (6)
8
V
100
MΩ
20
pF
(6)
(7)
(8)
Specified by design and characterization.
Slew rate is measured from 10% to 90% of the transition when the output changes from negative full-scale to positive full-scale.
Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as
the area of the glitch in nV-s. It is measured by toggling the DAC register data between 0000h and FFFCh in twos complement format.
(9) Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the
sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale.
(10) DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and
subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s.
(11) Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input
register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s.
(12) Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of
the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s.
4
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www.ti.com ........................................................................................................................................... SBAS464A – AUGUST 2009 – REVISED SEPTEMBER 2009
ELECTRICAL CHARACTERISTICS (continued)
All specifications at TA = TMIN to TMAX, AVDD = +11V to +18V, AVSS = –11V to –18V, VREF = REF-A = REF-B = +5V,
DVDD = +5V, IOVDD = +1.8V to DVDD, AGND = DGND = REFGND-A = REFGND-B = SGND-x = 0V, and DAC gain = 4, unless
otherwise noted.
DAC8234
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (13) (SDI, CS, SCLK, RST, UNI/BIP-A, UNI/BIP-B, LDAC, GPIO-x)
High-level input voltage, VIH
Low-level input voltage, VIL
IOVDD = 4.5V to 5.5V
2.5
IOVDD + 0.3
V
IOVDD = 2.7V to 3.3V
2.1
IOVDD + 0.3
V
IOVDD = +1.8V
1.6
IOVDD + 0.3
V
IOVDD = 4.5V to 5.5V
–0.3
0.8
V
IOVDD = 2.7V to 3.3V
–0.3
0.6
V
IOVDD = +1.8V
–0.3
0.2
V
1
µA
Input current
Input capacitance
5
pF
DIGITAL OUTPUTS (13) (SDO, GPIO-x)
SDO high-level output voltage,
VOH
IOVDD = 2.7V to 5.5V, sourcing 1mA
SDO low-level output voltage,
VOL
IOVDD = 2.7V to 5.5V, sinking 1mA
0.4
IOVDD = +1.8V, sinking 200µA
0.2
V
1
µA
IOVDD = +1.8V, sourcing 200µA
IOVDD – 0.4
V
1.6
V
SDO high-impedance leakage
SDO high-impedance output
capacitance
GPIO low-level output voltage,
VOL
GPIO open-drain high-level
output leakage current
V
10
pF
IOVDD = 2.7V to 5.5V, sinking 1mA
0
0.4
V
IOVDD = +1.8V, sinking 1mA
0
0.4
V
1
µA
GPIO in Hi-Z and configured as output
POWER SUPPLY
AVDD (14)
+4.75
+24
V
AVSS (15)
–18
–4.75
V
DVDD
+2.7
+5.5
V
IOVDD
+1.7
DVDD
AIDD (normal operation)
±10V output range, no loading current, VOUT = 0V
2.7
±10V output range, no loading current, VOUT = 0V
3.3
AIDD (power-down)
AISS (normal operation)
AISS (power-down)
3.4
V
mA/Channel
100
µA
4.0
mA/Channel
100
µA
DIDD
Static current through the DVDD pin with VIH = IOVDD and
VIL = DGND
25
50
µA
IOIDD
VIH = IOVDD, VIL = DGND
±1
±10
µA
Power dissipation (normal
operation)
±12V power, no loading current, VOUT = 0V
290
mW
TEMPERATURE RANGE
Specified performance
–40
+105
°C
(13) Specified by design and characterization.
(14) AVDD should not be greater than +24V or less than +4.75V. Also, AVDD should not be less than ( 2 × VREF + 1V) for bipolar output mode
and should not be less than (Gain × VREF + 1V) for unipolar output mode. In any case, (AVDD – AVSS) ≤ +36V.
(15) AVSS should not be greater than –4.75V or less than –18V. Also, AVSS should not be greater than (–2 × VREF – 1V). In any case, (AVDD
– AVSS) ≤ +36V.
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DAC8234
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FUNCTIONAL BLOCK DIAGRAM
IOVDD DGND
DVDD
AGND
AVDD
AVSS
REF-A
REFGND-A
AIN
RFB1-0
RFB1-1
RFB1-2
RFB1-3
Reference
Buffer A
SCLK
SDI
SDO
Command
Register
SPI Shift Register
CS
To DAC-0,
DAC-1
RFB1-0
RFB2
RFB2-0
User Calibration:
Zero Register 0
Gain Register 0
LDAC
GPIO-0
GPIO-1
Control Logic
RST
UNI/BIP-B
VMON
RFB1
DAC-0
Input Data
Register 0
UNI/BIP-A
Mux
Analog Monitor
DAC8234
VOUT-0
Latch-0
LDAC
Power-On/
Power-Down Control
SGND-0
RFB1-1
RFB2-1
DAC-1
VOUT-1
SGND-1
AIN
RFB1-2
RFB2-2
DAC-2
VOUT-2
SGND-2
RFB1-3
RFB2-3
DAC-3
VOUT-3
Internal Trimming
Zero, Gain, INL
SGND-3
To DAC-2, DAC-3
(Same Function Blocks for All Channels)
REF-B
6
Power-On/
Power-Down
Control
Reference
Buffer B
REFGND-B
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PIN CONFIGURATIONS
29
2
SCLK
AVDD
VMON
SDI
3
28
AVSS
SDO
4
27
REFGND-B
38 VOUT-3
37 NC
39 RFB2-3
41 SGND-3
40 RFB1-3
43 SGND-2
42 NC
45 RFB2-2
44 RFB1-2
47 AIN
46 VOUT-2
VOUT-3
31
30
1
CS
48 UNI/BIP-B
RFB2-3
32
SGND-2
SGND-3
RFB1-2
35
RFB1-3
RFB2-2
36
34
VOUT-2
38
37
PFB PACKAGE
TQFP-48
(TOP VIEW)
33
UNI/BIP-B
AIN
40
39
RHA PACKAGE(1)
QFN-40
(TOP VIEW)
NC
1
36
CS
2
35
AVDD
SCLK
3
34
VMON
NC
SDI
4
33
AVSS
SDO
5
32
REFGND-B
LDAC
6
31
REF-B
RST
7
30
REF-A
LDAC
5
26
REF-B
RST
6
25
REF-A
GPIO-0
7
24
REFGND-A
GPIO-0
8
29
REFGND-A
AVSS
GPIO-1
9
28
AVSS
UNI/BIP-A 10
27
AGND
DGND 11
26
AVDD
NC 12
25
NC
(1)
24
NC
NC
RFB2-1 22
18
19
SGND-0
VOUT-1 23
17
RFB1-0
RFB1-1 21
16
RFB2-0
SGND-1 20
15
20
VOUT-1
IOVDD
19
SGND-0
RFB2-1
16
RFB1-0
17
15
RFB2-0
18
14
VOUT-0
RFB1-1
13
DVDD
SGND-1
11
12
IOVDD
AVDD
13
21
10
DGND
AGND
VOUT-0
22
9
UNI/BIP-A
14
23
8
GPIO-1
DAC8234
DVDD
DAC8234
The thermal pad is internally connected to
the substrate. This pad can be connected
to AVSS or left floating.
PIN DESCRIPTIONS
PIN NO.
PIN
NAME
QFN-40
TQFP-48
I/O
CS
1
2
I
SPI bus chip select input (active low). Data are not clocked into the SPI shift register unless CS is
low. When CS is high, SDO is in a high-impedance state.
SCLK
2
3
I
SPI bus clock
SDI
3
4
I
SPI bus input data
SDO
4
5
O
SPI output data
LDAC
5
6
I
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the
contents of the Input Data Register are transferred to it. The DAC output changes to the
corresponding level simultaneously when the DAC latch is updated.
RST
6
7
I
Reset input (active low). Logic low on this pin resets the input registers and DACs to the values
defined by the UNI/BIP pins, and sets the Gain Register and Zero Register to default values.
GPIO-0
7
8
I/O
General-purpose digital input/output 0. This pin is a bidirectional, digital input/output, and has an
open-drain output. A 10kΩ pull-up resistor to IOVDD is needed when this pin is used as an output.
See the GPIO Pins section for details.
GPIO-1
8
9
I/O
General-purpose digital input/output 1. This pin is a bidirectional, digital input/output, and has an
open-drain output. A 10kΩ pull-up resistor to IOVDD is needed when this pin is used as an output.
See the GPIO Pins section for details.
UNI/BIP-A
9
10
I
Output mode selection of group A (DAC-0 and DAC-1). When UNI/BIP-A is tied to IOVDD, group A
is in unipolar output mode; when tied to DGND, group A is in bipolar output mode. The input data
written to the DAC are straight binary for unipolar output mode and twos complement for bipolar
output mode.
DGND
10
11
I
Digital ground
IOVDD
11
13
I
Interface power
DVDD
12
14
I
Digital power
VOUT-0
13
15
O
DAC-0 output
DESCRIPTION
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PIN DESCRIPTIONS (continued)
PIN
NAME
QFN-40
TQFP-48
I/O
RFB2-0 (1)
14
16
O
DAC-0 RFB2 feedback
RFB1-0 (1)
15
17
O
DAC-0 RFB1 feedback
SGND-0
16
18
I
DAC-0 signal ground. Connected to REFGND-A.
SGND-1
17
20
I
DAC-1 signal ground. Connected to REFGND-A.
(1)
18
21
O
DAC-1 RFB1 feedback
RFB2-1 (1)
19
22
O
DAC-1 RFB2 feedback
VOUT-1
20
23
O
DAC-1 output
AVDD
21, 30
26, 35
I
Positive analog power supply
AGND
22
27
I
Analog ground
AVSS
23, 28
28, 33
I
Negative analog power supply
REFGND-A
24
29
I
Reference REF-A ground. Connect to AGND.
REF-A
25
30
I
Group A (DAC-0, DAC-1) reference input
REF-B
26
31
I
Group B (DAC-2, DAC-3) reference input
REFGND-B
27
32
I
Reference REF-B ground. Connect to AGND.
VMON
29
34
O
Analog monitor output. This pin is either in Hi-Z status, or connected to one of the four DAC outputs
or AIN, depending on the content of the Monitor Register.
RFB1-1
(1)
8
PIN NO.
DESCRIPTION
VOUT-3
31
38
O
DAC-3 output
RFB2-3 (1)
32
39
O
DAC-3 RFB2 feedback
RFB1-3 (1)
33
40
O
DAC-3 RFB1 feedback
SGND-3
34
41
I
DAC-3 signal ground. Connected to REFGND-B.
SGND-2
35
43
I
DAC-2 signal ground. Connected to REFGND-B.
RFB1-2 (1)
36
44
O
DAC-2 RFB1 feedback
RFB2-2 (1)
37
45
O
DAC-2 RFB2 feedback
VOUT-2
38
46
O
DAC-2 output
AIN
39
47
I
Auxiliary analog input. Connected to the analog monitor mux.
UNI/BIP-B
40
48
I
Output mode selection of group B (DAC-2 and DAC-3). When UNI/BIP-A is tied to IOVDD, group B
is in unipolar output mode; when tied to DGND, group B is in bipolar output mode.
The input data written to the DAC are straight binary for unipolar output mode, and twos
complement for bipolar output mode.
NC
—
1, 12, 19,
24, 25, 36,
37, 42
Not connected
To set the DAC-x gain = 2, connect RFB1-x and RFB2-x to VOUT-x, and set the corresponding GAIN bit in the Command Register to '0'.
To set the DAC-x gain = 4, connect RFB1-x to VOUT-x, keep RFB2-x open, and set the corresponding GAIN bit in the Command Register
to '1'. After power-on reset or user reset, the GAIN bits are set to '1' by default; for gain = 2, the gain bits must be cleared to '0'.
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TIMING DIAGRAMS
Case 1: Stand-alone mode, LDAC tied low.
t8
t4
CS
t1
SCLK
Input Data Register and
DAC Latch Updated(1)
tF
t5
LDAC
tR
t3
t2
t6
BIT 23 (MSB)
SDI
t7
BIT 22
BIT 1
BIT 0
Low
Case 2: Stand-alone mode, LDAC active high.
t8
t4
CS
t1
SCLK
BIT 22
BIT 1
BIT 0
Input Word To Write the Data to the Selected DAC
High
Input Data Register Updated
but DAC Latch is Not Updated
tF
t6
BIT 23 (MSB)
SDI
LDAC
tR
t3
t2
t5
t7
t9
t10
DAC Latch Updated
= Don’t Care
Bit 23 = MSB
Bit 0 = LSB
Figure 1. SPI Timing for Stand-Alone Mode
TIMING CHARACTERISTICS For Figure 1 (1) (2) (3)
At TA = –40°C to +105°C, unless otherwise noted.
2.7V ≤ DVDD ≤ 5.5V,
IOVDD = 1.8V
PARAMETER
MIN
2.7V ≤ DVDD ≤ 3.6V,
2.7V ≤ IOVDD ≤ DVDD
MAX
MIN
MAX
MIN
40
MAX
UNIT
50
MHz
fSCLK
Clock frequency
t1
SCLK cycle time
33
25
20
ns
t2
SCLK high time
16
12
10
ns
t3
SCLK low time
16
12
10
ns
t4
CS falling edge to SCLK falling edge (4)
11
9
7
ns
t5
Input data setup time
5
5
5
ns
t6
Input data hold time
5
5
5
ns
t7
SCLK falling edge to CS rising edge
15
12
10
ns
t8
CS high time
60
50
30
ns
t9
CS rising edge to LDAC falling edge
30
25
20
ns
t10
LDAC pulse width
25
20
15
ns
RST pulse width
25
20
15
ns
(1)
(2)
(3)
(4)
30
3.6V < DVDD ≤ 5.5V,
2.7V ≤ IOVDD ≤ DVDD
Specified by design and characterization.
Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
The first SCLK edge after CS goes low must be a falling edge.
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Case 3: Daisy-Chain mode, LDAC tied low.
t8
t4
CS
t1
SCLK
tR
t3
t2
t6
BIT 23 (N)
BIT 22 (N)
BIT 0 (N)
BIT 23 (N+1)
t11
BIT 0 (N+1)
t12
BIT 23 (N)
SDO
LDAC
Input Data Register and
DAC Latch Updated(1)
tF
t5
SDI
t7
BIT 0 (N)
Low
Case 4: Daisy-Chain mode, LDAC active.
t8
t4
CS
t1
SCLK
t6
BIT 23 (N)
BIT 22 (N)
BIT 0 (N)
BIT 23 (N+1)
t11
BIT 0 (N+1)
t12
BIT 23 (N)
SDO
LDAC
Input Data Register Updated
but DAC Latch is Not Updated
tF
t5
SDI
tR
t3
t2
t7
BIT 0 (N)
t9
High
t10
DAC Latch Updated
= Don’t Care
Bit 23 = MSB
Bit 0 = LSB
Figure 2. SPI Timing for Daisy-Chain Mode
10
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Case 5: Readback for Stand-alone mode.
t4
t8
t7
CS
SCLK
Input Data Register Updated
tR
t1
t2
t3
t5
t6
tF
BIT 23
SDI
BIT 0
BIT 22
BIT 23
Input Word Specifies Register to be Read
t13
SDO
LDAC
BIT 22
t11
BIT 23
BIT 1
t12
BIT 22
BIT 0
Write NOP Command
BIT 1
BIT 0
Data from the Selected Register
Low
= Don’t Care
Bit 23 = MSB
Bit 0 = LSB
Figure 3. SPI Timing for Readback Operation in Stand-Alone Mode
TIMING CHARACTERISTICS For Figure 2 to Figure 3 (1) (2) (3)
At TA = –40°C to +105°C, unless otherwise noted.
2.7V ≤ DVDD ≤ 5.5V,
IOVDD = 1.8V
PARAMETER
MIN
2.7V ≤ DVDD ≤ 3.6V,
2.7V ≤ IOVDD ≤ DVDD
MAX
MIN
MIN
UNIT
25
MHz
Clock frequency
t1
SCLK cycle time
66
50
40
ns
t2
SCLK high time
33
25
20
ns
t3
SCLK low time
33
25
20
ns
t4
CS falling edge to SCLK falling edge (4)
25
22
17
ns
t5
Input data setup time
5
5
5
ns
t6
Input data hold time
5
5
5
ns
t7
SCLK falling edge to CS rising edge
15
12
10
ns
t8
CS high time
60
50
30
ns
t9
CS rising edge to LDAC falling edge
30
25
20
ns
t10
LDAC pulse width
25
t11
SDO data valid from SCLK rising edge
t12
SDO data hold time from SCLK falling
edge
t13
SDO data valid from CS falling edge
(1)
(2)
(3)
(4)
20
MAX
fSCLK
RST pulse width
15
MAX
3.6V < DVDD ≤ 5.5V,
2.7V ≤ IOVDD ≤ DVDD
20
25
30
15
20
25
20
25
20
17
20
ns
15
ns
ns
12
15
ns
ns
Specified by design and characterization.
Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
The first SCLK edge after CS goes low must be a falling edge.
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TYPICAL CHARACTERISTICS
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0
-0.1
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
-0.2
-0.4
-0.5
2048
4096
0.1
0
-0.1
-0.4
-0.5
6144 8192 10240 12288 14336 16383
Digital Input Code
0
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
(Bipolar Operation)
0.4
0.3
0.3
0.2
0.2
0.1
0
-0.1
TA = +105°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
-0.2
-0.3
-0.4
-0.5
4096
0.1
0
-0.1
TA = +105°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
-0.2
-0.3
-0.4
-0.5
6144 8192 10240 12288 14336 16383
Digital Input Code
0
4096
6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 7.
LINEARITY ERROR
vs DIGITAL INPUT CODE
(Bipolar Operation)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
(Bipolar Operation)
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0
-0.1
TA = -40°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
-0.2
-0.3
-0.4
-0.5
4096
6144 8192 10240 12288 14336 16383
Digital Input Code
0.1
0
-0.1
TA = -40°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
-0.2
-0.3
-0.4
-0.5
0
Figure 8.
12
2048
Figure 6.
0.5
2048
6144 8192 10240 12288 14336 16383
Digital Input Code
LINEARITY ERROR
vs DIGITAL INPUT CODE
(Bipolar Operation)
0.5
0
4096
Figure 5.
0.4
2048
2048
Figure 4.
0.5
0
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
-0.2
-0.3
DNL Error (LSB)
INL Error (LSB)
0
DNL Error (LSB)
0.5
-0.3
INL Error (LSB)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
(Bipolar Operation)
DNL Error (LSB)
INL Error (LSB)
LINEARITY ERROR
vs DIGITAL INPUT CODE
(Bipolar Operation)
2048
4096
6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
LINEARITY ERROR
vs DIGITAL INPUT CODE
(All Channels, Bipolar Operation)
0.5
Channel 0
Channel 1
Channel 2
Channel 3
0.4
INL Error (LSB)
0.3
0.2
0.1
0
-0.1
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
-0.2
-0.3
-0.4
-0.5
0
2048
4096
6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 10.
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0
-0.1
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +12V
AVSS = -12V
-0.2
-0.4
-0.5
0
2048
4096
DNL Error (LSB)
0.5
-0.3
INL Error (LSB)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
(Bipolar Operation)
0.1
0
-0.1
-0.4
-0.5
6144 8192 10240 12288 14336 16383
Digital Input Code
0
4096
6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 12.
LINEARITY ERROR
vs DIGITAL INPUT CODE
(Unipolar 0V to 20V Operation)
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
(Unipolar 0V to 20V Operation)
0.5
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0
-0.1
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +24V
AVSS = -12V
-0.2
-0.3
-0.4
-0.5
2048
2048
Figure 11.
0.5
0
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +12V
AVSS = -12V
-0.2
-0.3
4096
6144 8192 10240 12288 14336 16383
Digital Input Code
DNL Error (LSB)
INL Error (LSB)
LINEARITY ERROR
vs DIGITAL INPUT CODE
(Bipolar Operation)
0.1
0
-0.1
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +24V
AVSS = -12V
-0.2
-0.3
-0.4
-0.5
0
Figure 13.
2048
4096
6144 8192 10240 12288 14336 16383
Digital Input Code
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
LINEARITY ERROR
vs TEMPERATURE
(Bipolar Operation)
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
(Bipolar Operation)
0.3
0.3
0.2
0
INL Min
-0.1
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
-0.2
-0.3
5
-40 -25 -10
INL Error (LSB)
DNL Error (LSB)
INL Max
0.1
20 35 50 65
Temperature (°C)
80
95
DNL Max
0
DNL Min
-0.1
-0.3
110 125
-40 -25 -10
80
95
110 125
LINEARITY ERROR
vs REFERENCE VOLTAGE
(Bipolar Operation)
DIFFERENTIAL LINEARITY ERROR
vs REFERENCE VOLTAGE
(Bipolar Operation)
0.3
0.2
0.2
INL Max
0.1
0
INL Min
-0.1
TA = +25°C
Gain = 4
AVDD = +18V
AVSS = -18V
-0.3
2
3
4
5
6
Reference Voltage (V)
7
0.1
DNL Max
0
DNL Min
-0.1
TA = +25°C
Gain = 4
AVDD = +18V
AVSS = -18V
-0.2
-0.3
8
1
2
3
4
5
6
Reference Voltage (V)
7
Figure 17.
Figure 18.
LINEARITY ERROR
vs SUPPLY VOLTAGE
(Bipolar Operation)
DIFFERENTIAL LINEARITY ERROR
vs SUPPLY VOLTAGE
(Bipolar Operation)
0.3
8
0.3
TA = +25°C
Gain = 4
VREF = 2V
0.1
INL Max
0
INL Min
-0.1
-0.2
TA = +25°C
Gain = 4
VREF = 2V
0.2
DNL Error (LSB)
0.2
0.1
DNL Max
0
DNL Min
-0.1
-0.2
-0.3
-0.3
4.5
6.0
7.5
9.0 10.5 12.0 13.5
+AVDD, -AVSS (V)
15.0
16.5
18.0
4.5
Figure 19.
14
20 35 50 65
Temperature (°C)
Figure 16.
0.3
1
5
Figure 15.
-0.2
INL Error (LSB)
0.1
-0.2
DNL Error (LSB)
INL Error (LSB)
0.2
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
6.0
7.5
9.0 10.5 12.0 13.5
+AVDD, -AVSS (V)
15.0
16.5
18.0
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
0.5
1.5
0.4
Bipolar Zero Error (mV)
2.0
1.0
0.5
0
-0.5
TA = +25°C
Gain = 4
AVDD = +18V
AVSS = -18V
-1.0
-1.5
-2.0
1
Bipolar Gain Error (mV)
BIPOLAR ZERO ERROR
vs REFERENCE VOLTAGE
(10 Units, 40 Channels Total)
2
3
4
5
6
Reference Voltage (V)
7
0.2
0.1
0
-0.1
-0.2
TA = +25°C
Gain = 4
AVDD = +18V
AVSS = -18V
-0.3
-0.4
8
1
2
3
4
5
6
Reference Voltage (V)
7
Figure 21.
Figure 22.
BIPOLAR GAIN ERROR
vs TEMPERATURE
(10 Units, 40 Channels Total)
BIPOLAR ZERO ERROR
vs TEMPERATURE
(10 Units, 40 Channels Total)
2.0
1.0
1.5
0.8
1.0
0.5
0
-0.5
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
-1.0
-1.5
8
0.6
0.4
0.2
0
-0.2
-0.4
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
-0.6
-0.8
-1.0
-2.0
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
110 125
-40 -25 -10
5
20 35 50 65
Temperature (°C)
80
95
Figure 23.
Figure 24.
UNIPOLAR ZERO ERROR
vs REFERENCE VOLTAGE
(10 Units, 40 Channels Total)
UNIPOLAR ZERO ERROR
vs TEMPERATURE
(10 Units, 40 Channels Total)
TA = +25°C
Gain = 4
AVDD = +24V
AVSS = -12V
0.05
0
-0.05
-0.10
-0.15
0.3
0.2
0.1
0
-0.1
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
-0.2
-0.3
-0.20
110 125
0.4
Unipolar Zero Error (mV)
0.10
Unipolar Zero Error (mV)
0.3
-0.5
Bipolar Zero Error (mV)
Bipolar Gain Error (mV)
BIPOLAR GAIN ERROR
vs REFERENCE VOLTAGE
(10 Units, 40 Channels Total)
-0.4
1.0
1.5
2.0
2.5
3.0
3.5
Reference Voltage (V)
4.0
4.5
5.0
-40 -25 -10
Figure 25.
5
20 35 50 65
Temperature (°C)
80
95
110 125
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
DELTA OUTPUT VOLTAGE
vs SOURCE/SINK CURRENT
(Bipolar Operation)
TOTAL SUPPLY CURRENT
vs DIGITAL INPUT CODE
14
6
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
Code Change for One Channel
All Other Channel Outputs = 0V
12
11
10
9
BTC
7FFCh
4
DVOUT (mV)
AIDD, AISS (mA)
13
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +12V
AVSS = -12V
BTC 8000h
|AISS|
BTC C000h
2
BTC 4000h
+1 LSB
0
-1 LSB
-2
-4
|AIDD|
8
-6
0
2048
4096
6144 8192 10240 12288 14336 16383
Digital Input Code
-12 -10 -8
-4
-2 0
2
ILOAD (mA)
4
6
Figure 27.
Figure 28.
MAJOR CARRY GLITCH
MAJOR CARRY GLITCH
BTC Code Change: 0000h to FFFCh
2mV/div
-6
BTC Code Change: FFFCh to 0000h
VOUT
VOUT
5V/div
TA = +25°C
Gain = 4
VREF = 5V
DVDD = 5V
AVDD = +15V
AVSS = -15V
LDAC
5V/div
Figure 30.
SETTLING TIME
(+10V to –10V Transition)
SETTLING TIME
(–10V to +10V Transition)
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
10kW || 200pF
Large-Signal Output
1.2mV/div
Small-Signal Error
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
10kW || 200pF
5V/div
Large-Signal Output
LDAC
5V/div
LDAC
Time (5ms/div)
Time (5ms/div)
Figure 31.
16
TA = +25°C
Gain = 4
VREF = 5V
DVDD = 5V
AVDD = +15V
AVSS = -15V
Time (0.5ms/div)
1.2mV/div
5V/div
12
LDAC
Figure 29.
5V/div
10
2mV/div
Time (0.5ms/div)
Small-Signal Error
8
Figure 32.
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TYPICAL CHARACTERISTICS (continued)
0.1Hz TO 10Hz NOISE
(Bipolar Operation)
IOVDD SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
IOVDD Supply Current (mA)
Noise (2mV/div)
1.2
TA = +25°C
Gain = 4
VREF = 0V
AVDD = +15V
AVSS = -15V
Midscale Code
TA = +25°C
AVDD = +15V
AVSS = -15V
1.0
IOVDD = 5V
0.8
0.6
0.4
0.2
IOVDD = 2.7V
0
Time (1s/div)
0
0.5
1.0
1.5 2.0 2.5 3.0 3.5
Logic Input Voltage (V)
Figure 33.
AIDD PRODUCTION DISTRIBUTION
5.0
AISS PRODUCTION DISTRIBUTION
30
AIDD (mA/Channel)
AISS (mA/Channel)
Figure 35.
Figure 36.
BIPOLAR GAIN ERROR PRODUCTION DISTRIBUTION
15
10
4.00
3.80
3.90
70
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
60
50
Population (%)
20
3.60
BIPOLAR ZERO ERROR PRODUCTION DISTRIBUTION
25
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
3.70
3.40
3.50
3.20
3.30
3.00
3.10
3.40
3.30
3.10
3.20
2.90
3.00
2.70
2.80
2.60
2.50
2.40
0
2.30
0
2.10
5
2.20
5
2.80
10
2.90
10
15
2.60
15
20
2.70
20
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
VOUT = 0V
25
Population (%)
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +15V
AVSS = -15V
VOUT = 0V
25
Population (%)
4.5
Figure 34.
30
Population (%)
4.0
40
30
20
5
Bipolar Zero Error (LSB)
Figure 37.
Figure 38.
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1.00
0.20
0.25
0.10
Bipolar Gain Error (LSB)
0.15
0.05
0
-0.05
-0.10
-0.15
-0.20
-0.25
0
-1.00
1.00
0.25
0.15
0.20
0.05
0.10
0
-0.05
-0.10
-0.15
-0.20
-0.25
0
-1.00
10
17
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TYPICAL CHARACTERISTICS (continued)
UNIPOLAR GAIN ERROR PRODUCTION DISTRIBUTION
UNIPOLAR ZERO ERROR PRODUCTION DISTRIBUTION
25
90
Population (%)
20
15
10
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +24V
AVSS = -12V
80
70
Population (%)
TA = +25°C
Gain = 4
VREF = 5V
AVDD = +24V
AVSS = -12V
60
50
40
30
20
5
18
Unipolar Zero Error (LSB)
Figure 39.
Figure 40.
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1.00
0.20
0.25
0.10
Unipolar Gain Error (LSB)
0.15
0.05
0
-0.05
-0.10
-0.15
-0.20
-0.25
0
-1.00
1.00
0.25
0.15
0.20
0.05
0.10
0
-0.05
-0.10
-0.15
-0.20
-0.25
-1.00
10
0
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THEORY OF OPERATION
DAC ARCHITECTURE
The DAC8234 is a highly-integrated, quad-channel, 14-bit, voltage-output DAC with internal reference buffers
and output buffers. Each channel consists of an R-2R ladder configuration with the three MSBs segmented,
followed by an operational amplifier, as shown in Figure 41. The DAC8234 has a high-impedance, buffered
reference input; the output of the reference buffers drives the R-2R ladders. The output buffer is designed to
allow user-configurable adjustments, giving the DAC8234 four different output voltage range settings. With the
production trim process, this device has excellent dc accuracy and ac performance.
R
From Reference
Buffer Output
R
2R
2R
2R
2R
2R
S17
S16
S12
S11
S10
R
2R
S9
R
2R
S8
2R
S0
2R
RFB
VOUT
Three MSBs Decoded Into
Seven Equal Segments
11-Bit R-2R Ladder
SGND
Figure 41. DAC8234 Architecture
CHANNEL GROUPS
The four DAC channels are arranged into two groups (A and B) with two channels per group. Group A consists
of DAC-0 and DAC-1, and Group B consists of DAC-2 and DAC-3. The two DAC channels of Group A derive
their reference voltage from REF-A, and those of Group B from REF-B.
USER-CALIBRATION FOR ZERO ERROR AND GAIN ERROR
The DAC8234 implements a user-calibration function that allows for trimming the system gain and zero errors.
Each DAC channel has a Gain Register and Zero Register and the DAC output is calibrated according to the
value of the corresponding registers. The range of gain adjustment is typically ±0.195% of full-scale with 0.25
LSB per step. The zero code adjustment is typically ±0.0488% of full-scale with 0.03125 LSB per step. The input
data format of the Gain and Zero registers is twos complement. Refer to Table 9 and Table 10 for more details.
If the system-level calibration is not needed, these registers should be left at the respective default values
(0000h) at power-on.
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TRANSFER FUNCTION FOR THE ANALOG OUTPUTS (VOUT-0 to VOUT-3)
For bipolar output:
VOUT = Gain ´ VREF ´
INPUT_CODE ZERO_CODE
+
32 ´ 16384
16384
´
INPUT_CODE ZERO_CODE
+
32 ´ 16384
16384
´
1+
GAIN_CODE
8 ´ 16384
(1)
For unipolar output:
VOUT = Gain ´ VREF ´
1+
GAIN_CODE
4 ´ 16384
(2)
Where:
GAIN is the DAC gain, which can be set to x2 or x4 and is determined by the connection of pins RFB1-x and
RFB2-x to VOUT-x, and the GAIN bit in the Command Register.
INPUT_CODE is the decimal equivalent value of the code written into the DAC input register.
ZERO_CODE is the decimal equivalent value of the code written into the Zero Register.
GAIN_CODE is the decimal equivalent value of the code written into the Gain Register.
Note that the output voltage must not be greater than (AVDD – 1.0V) or less than (AVSS + 1.0V); otherwise, the
output may be saturated.
Input Data Format
For bipolar output operation, INPUT_CODE is always twos complement, and can accept values between –8192
to 8191.
For unipolar output operation, INPUT_CODE is always straight binary, and can accept values between 0 to
16383.
GAIN_CODE is always in twos complement format, and can accept values between –128 and +127.
ZERO_CODE is always in twos complement format and can accept values between –256 and +255.
The data written to the Command and Monitor registers are written as specified in the definitions. For read
operations, the read-back data format is the same as the format used to write to the device. Refer to the Internal
Registers section for more details.
OUTPUT RANGE
Each channel of the DAC8234 implements an output amplifier that provides a unipolar output or a bipolar output
with a gain of 2 or 4. The output span equals the gain times the reference voltage. For a 5V reference, the output
range can be configured as ±10V, ±5V, 0V to 20V, or 0V to 10V. The status of the UNI/BIP pin determines the
output mode (unipolar or bipolar) of each group. When the UNI/BIP-A pin is high, the outputs of Group A (DAC-0
and DAC-1) are unipolar; when the pin is low, the outputs of Group A are bipolar. Similarly, the UNI/BIP-B pin
defines the output mode of Group B (DAC-2 and DAC-3).
Each individual DAC can be configured with a gain of 4 or a gain of 2. To set the gain = 4, connect RFB1-x to
VOUT-x with RFB2-x left open, and set the gain bit for that channel to '1' in the Command Register. To set the gain
= 2, connect both RFB1-x and RFB2-x to VOUT-x, and set the gain bit for that channel to '0'. The gain bits in the
Command Register are set to '1' by default at power-on or reset, and must be cleared to '0' for gain = 2.
Note that the power supplies must meet the following requirements:
• AVDD must not be greater than 24V or less than 4.75V, and AVSS must not be greater than –4.75V or less
than –18V. In any case, (AVDD – AVSS) ≤ 36V.
• For bipolar mode: AVDD ≥ 2 × VREF + 1V, and AVSS ≤ –2 × VREF – 1V.
• For unipolar mode: AVDD ≥ Gain × VREF + 1V, and AVSS ≤ –2 × VREF – 1V.
For example, for a 5V reference in bipolar operation, the minimum supplies must be at least ±11V, regardless of
whether the output range is ±5V or ±10V. For unipolar operation with the same reference, the supplies must be
at least ±11V for a 0V to 10V operation, and +21V/–11V for a 0V to +20V operation.
20
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UPDATING THE DAC OUTPUTS
The DAC8234 has a double-buffered interface that consists of two register banks for every channel: the input
register and the DAC latch. The digital code is transferred from the SPI shift register to the addressed channel
input register upon completion of a valid write sequence. The DAC latch contains the digital code used by the
resistor R-2R ladder. The contents of the DAC latch define the output from the DAC. The DAC outputs can be
updated individually or simultaneously. The DAC8234 updates the DAC latch only if it has been accessed since
the last time the LDAC pin was brought low or the LD bit in the Command Register was set to '1', thereby
eliminating any unnecessary glitch. The DAC channels that were not accessed are not reloaded, and the output
values remain unchanged.
Individual DAC Channel Update
In this mode, the LDAC pin is held low while the CS pin is low and the data are clocked into the SPI shift register.
At the end of the data transfer into the shift register, the CS pin is brought high. This action updates both the
addressed input data register and the corresponding DAC latch register. The DAC latch register controls the
R-2R switches; thus, an update on the DAC latch register updates the corresponding DAC channel analog
output.
Simultaneous Update of Multiple DAC Channels
In this mode, the LDAC pin is held high while the CS pin is low and data are clocked into the SPI shift register. At
the end of the data transfer into the shift register, the CS pin is brought high. This action updates only the
addressed input data register; it does not update the DAC latch register or change the output. The DAC latch and
the analog output are updated only when the LDAC pin goes low, or when the LD bit in the Command Register is
set to '1' at anytime after the input data register is written.
HARDWARE RESET
When the RST pin is low, the device is in hardware reset. All the analog outputs (VOUT-0 to VOUT-3), the input
registers, and the DAC latches are set to the reset values shown in Table 1. All registers are loaded with default
values. Communication is disabled, and the signals on the SDI, CS, and SCLK pins are ignored. On the rising
edge of the RST pin, the analog outputs (VOUT-0 to VOUT-3) maintain the reset value (0V) until a new value is
programmed. After the RST pin goes high, the device returns to normal operation. Note that the default values of
the gain bits in the Command Register are '1' after a reset. For gain = 2, the gain bits must be cleared to '0'.
Table 1. Reset Values
UNI/BIP PIN
OUTPUT MODE
INPUT FORMAT
VALUE OF INPUT REGISTER
AND DAC LATCH
VOUT
DGND
Bipolar
Twos Complement
0000h
0V
IOVDD
Unipolar
Straight Binary
0000h
0V
Setting the RST bit in the Command Register to '1' performs a software reset, which is functionally the same as a
hardware reset. After reset completes, the RST bit returns to '0' automatically.
POWER-ON RESET
On power-on, the input data registers and DAC latches are loaded with the value defined by the UNI/BIP pins
(see Table 1). All other registers are loaded with default values. After power-on, the outputs of the VOUT pins are
set to 0V.
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ANALOG OUTPUT MONITOR PIN (VMON)
The VMON pin is the analog output monitor. The analog output monitor function consists of an analog multiplexer
addressed via the serial interface, allowing one of the four channel outputs or the AIN input to be routed to this
pin for monitoring. The monitor function is controlled by the Monitor Register, which allows the monitored output
to be enabled or disabled. When all multiplexer channels are disabled, the monitor output is high impedance;
therefore, several monitor outputs can be connected in parallel with only one enabled at a time. Table 5 shows
the settings relevant to the monitor function.
Note that the multiplexer is implemented as a series of analog switches. Care should be taken to ensure the
maximum current from the VMON pin must not be greater than the given specification because such a condition
could conceivably cause a large amount of current to flow from the input of the multiplexer (that is, from VOUT-x
or AIN) to the output of the multiplexer (VMON). Also, the VMON pin output impedance is approximately 2.2kΩ;
therefore, VMON should be measured with a high-impedance input.
POWER-DOWN MODE
The DAC8234 implements a group power-down feature to reduce power consumption in case some channels
are idle. When the power-down bit (PD-A and/or PD-B) in the Command Register is set to '1', the corresponding
group goes into a power-down state. During power-down, the reference buffer and output buffers of that group
are powered down and the corresponding analog outputs are set to 0V through an internal 10kΩ resistor to
AGND. The contents of the internal registers do not change, and the bus interface remains active in order to
continue communication and receive commands from the host controller. Any internal register can be read from
or written to. The host controller can wake the device from power-down mode and return to normal operating
mode by clearing the power-down bit (PD-A and/or PD-B) in the Command Register. Recovery completes in
approximately 50µs.
POWER-SUPPLY SEQUENCING
In order to ensure proper initialization of the DAC8234, the digital supplies (DVDD and IOVDD) and logic inputs
(UNI/BIP-x) must be applied before AVSS and AVDD. Additionally, AVSS must be applied before AVDD unless both
can ramp up at the same time. REF-x should be applied after AVDD comes up in order to make sure the ESD
protection circuitry does not turn on.
GENERAL-PURPOSE INPUT/OUTPUT PINS (GPIO-0, -1)
The GPIO-0 and GPIO-1 pins are general-purpose, bidirectional, digital input/output (I/O) signals, as Figure 42
shows. These pins can receive an input or produce an output. When the GPIO-n pin acts as an output, it has an
open-drain, and the status is determined by the corresponding GPIO-n bit of the Command Register. The output
status is high impedance when the GPIO-n bit is set to '1', and is logic low when the GPIO-n bit is cleared ('0').
Note that a 10kΩ pullup resistor is required when using the GPIO-n pin as an output.
To use the GPIO-n pin as an input, the GPIO-n bits in the Command Register must be set to '1'. When the
GPIO-n pin acts as input, the digital value on the pin is acquired by reading the GPIO-n bit.
After a power-on reset or any forced hardware or software reset, all GPIO-n bits are set to '1', and the GPIO-n
pin goes to a high-impedance state.
+V
GPIO-x
Enable
Bit GPIO-x (when writing)
Bit GPIO-x (when reading)
Figure 42. GPIO Pins
22
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SERIAL INTERFACE
The DAC8234 is controlled over a versatile, three-wire serial interface that operates at clock rates of up to
50MHz and is compatible with SPI, QSPI™, Microwire™, and DSP™ standards.
SPI Shift Register
The SPI Shift Register is 24 bits wide. Data are loaded into the device MSB first as a 24-bit word under the
control of the serial clock input, SCLK. The falling edge of CS starts the communication cycle. Data are latched
into the SPI Shift Register on the falling edge of SCLK while CS is low. When CS is high, SCLK is blocked, SDI
is ignored, and the SDO line is in a high-impedance state. The contents of the SPI Shift Register are loaded into
the addressed internal register on the rising edge of CS. The SPI Shift Register consists of a read/write bit, four
register address bits, 14 data bits, and five reserved bits, as shown in Table 2. The timing for this operation is
shown in the Timing Diagrams section. When the device is loaded, the command is decoded, and the new data
are transferred into the proper data registers.
The serial interface works with both continuous and non-continuous serial clocks. A continuous SCLK source can
only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used and CS must be taken high after the final clock in
order to latch the data.
Stand-Alone Operation
The first falling edge of CS starts the operation cycle. Exactly 24 falling clock edges must be applied before CS is
brought back high again. If CS is brought high before the 24th falling SCLK edge, then the data are ignored. If
more than 24 falling SCLK edges are applied before CS is brought high, then the last 24 bits are considered. The
addressed internal register is updated from the Shift Register on the rising edge of CS. In order for another serial
transfer to take place, CS must be brought low again.
When the data have been transferred into the chosen register of the addressed DAC, all DAC latches and analog
outputs can be updated by taking the LDAC pin low or setting the LD bit in the Command Register.
Daisy-Chain Operation
For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices
together. Daisy-chain operation can be useful in system diagnostics and in reducing the number of serial
interface lines. Note that before daisy-chain operation can begin, the SDO pin must be enabled by clearing the
SDO disable bit in the Command Register (DSDO = '0'). By default, this bit is cleared after power-on or reset.
The first falling edge of CS starts the operation cycle. SCLK is continuously applied to the input shift register
when CS is low. If more than 24 clock pulses are applied, the data ripple out of the shift register and appear on
the SDO line. These data are clocked out on the rising edge of SCLK and are valid on the falling edge. By
connecting the SDO output of the first device to the SDI input of the next device in the chain, a multiple-device
interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock
cycles must equal 24 × N, where N is the total number of DAC8234s in the chain. When the serial transfer to all
devices is complete, CS is taken high. This action latches data from the SPI shift register into the device input
register of each device in the daisy-chain, and prevents any further data from being clocked in.
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Read-Back Operation
The READ command is used to start read-back operation. However, before read-back operation can be initiated,
the SDO pin must be enabled by clearing the DSDO bit in the Command Register (DSDO = '0'); this bit is cleared
by default. Read-back operation is then started by executing a READ command (R/W bit = '1'; see Table 2). Bits
A3 to A0 in the READ command select the register to be read. The remaining data in the command are don’t
care bits. During the next SPI operation, the data that appear on the SDO output are from the previously
addressed register. For a read of a single register, a NOP command can be used to clock out the data from the
selected register on SDO. Multiple registers can be read if multiple READ commands are issued. The readback
diagram in Figure 43 shows the read-back sequence. The read-back data format is the same format as what was
used to write to the device.
Single Reading
CS
SCLK
DB23
SDI
DB23
DB0
READ Command Specifies
Register to be Read
DB23
SDO
DB0
NOP Command
or Write Command
DB23
DB0
Undefined
DB0
Data from
Selected Register
Multiple Readings
CS
SCLK
SDI
DB23
DB0
DB23
Command to Read
Register A
SDO
DB23
DB0
Undefined
DB0
Command to Read
Register B
DB23
DB23
DB0
DB23
Command to Read
Register C
DB0
Data from
Register A
= Don’t Care
DB23
DB0
Data from
Register B
DB0
NOP Command
or Write Command
DB23
DB0
Data from
Register C
DB23 = MSB
DB0 = LSB
Figure 43. Read-Back Operation
24
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SPI SHIFT REGISTER
The SPI Shift Register is 24 bits wide, as shown in Table 2. By default, the SPI shift register resets to 000000h at
power-on or after a reset.
Table 2. SPI Shift Register Format
MSB
(1)
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15:DB2
DB1:DB0
R/W
0
0
0
A3
A2
A1
A0
DATA
Rsvd (1)
Writing to a reserved bit has no effect; reading the bit returns '0'.
R/W—Indicates a read from or a write to the addressed register.
R/W = '0' sets a write operation and the data are written to the specified register.
R/W = '1' sets a read-back operation. For read operation, bits A3 to A0 select the register to be read. The
remaining are don’t care bits. During the next SPI operation, the data appearing on SDO pin are from the
previously addressed register.
[A3:A0]—Address bits that specify which register is accessed.
DATA—14 data bits
All DAC8234 registers (command registers and data registers) are 16-bit. Table 3 shows the register map.
Table 3. Register Map
ADDRESS BITS
A3 A2 A1 A0
DATA BITS
DB15
DB14
DB13
DB12
DB11
DB10
DB8
DSDO
DB6
DB5:
DB2
NOP
GAIN
Bits
DB1:
DB0
Rsvd
(1)
REGISTER
Command
Register
0
0
0
A/B
LD
RST
PD-A
PD-B
0
0
0
1
MDAC-3
MDAC-2
MDAC-1
MDAC-0
AIN
0
1
0
0
D13:D0
Rsvd (1)
DAC-0
0
1
0
1
D13:D0
Rsvd (1)
DAC-1
0
1
1
0
D13:D0
Rsvd (1)
DAC-2
0
1
1
1
D13:D0
Rsvd (1)
1
0
0
0
Reserved (1)
Z8:Z0
Zero Register-0
1
0
0
1
Reserved (1)
Z8:Z0
Zero Register-1
1
0
1
0
Reserved (1)
Z8:Z0
Zero Register-2
1
0
1
1
Reserved (1)
Z8:Z0
1
1
0
0
Reserved (1)
G7:G0
Gain Register-0
1
1
0
1
Reserved (1)
G7:G0
Gain Register-1
1
1
1
0
Reserved (1)
G7:G0
Gain Register-2
1
1
1
1
Reserved (1)
G7:G0
Gain Register-3
(1)
GPIO-1 GPIO-0
DB7
0
Others
Rsvd
(1)
DB9
Reserved (1)
Monitor Register
DAC-3
Zero Register-3
Reserved (1)
—
Writing to a reserved bit has no effect; reading the bit returns '0'.
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INTERNAL REGISTERS
The DAC8234 internal registers consist of the Command Register, the Monitor Register, the DAC Input Data
Registers, the Zero Registers, and the Gain Registers.
Command Register. Default = 033Ch.
The Command Register determines the actions performed by the DAC8234.
Table 4. Command Register
BIT
DB15
NAME
A/B
DEFAULT
VALUE
DESCRIPTION
0
A/B bit.
When A/B = '0', reading DAC-x returns the value in the Input Data Register.
When A/B = '1', reading DAC-x returns the value in the DAC latch.
DB14
LD
0
Synchronously update DACs bit. Functions in the same manner as the LDAC pin.
When LDAC is tied high, set LD = '1' at any time after the write operation and the correction process proceeds to
synchronously update all DAC latches with the content of the corresponding Input Data Register, and sets VOUT to a new
level. The DAC8234 updates the DAC latch only if it has been accessed since the last time LDAC was brought low or the
LD bit was set to '1', thereby eliminating unnecessary glitch. Any DACs that were not accessed are not reloaded. After
updating, the bit returns to '0'. Refer to the Updating Via LDAC section for details.
When the LDAC pin is tied low, the LD bit is ignored.
DB13
RST
0
Software reset bit.
Set the RST bit to '1' to reset the device; functions the same as a hardware reset. After reset completes, the RST bit
returns to '0'.
DB12
PD-A
0
Power-down bit for Group A.
Setting the PD-A bit to '1' places Group A (DAC-0 and DAC-1) into power-down operation. All output buffers are in Hi-Z
and all analog outputs (VOUT-x) connect to AGND through an internal 10kΩ resistor. The interface remains active.
Setting the PD-A bit to '0' returns Group A to normal operation.
DB11
PD-B
0
Power-down bit for Group B.
Setting the PD-B bit to '1' places Group B (DAC-2 and DAC-3) into power-down operation. All output buffers are in Hi-Z
and all analog outputs (VOUT-x) connect to AGND through an internal 10kΩ resistor. The interface remains active.
Setting the PD-B bit to '0' returns Group B to normal operation.
DB10
Rsvd
0
Reserved. Writing to this bit has no effect; reading this bit returns '0'.
DB9
GPIO-1
1
GPIO-1 status bit.
Writing a '1' to the GPIO-1 bit puts the GPIO-1 pin into a Hi-Z state (default).
Writing a '0' to the GPIO-1 bit forces the GPIO-1 pin low.
When reading this bit, the digital value on the GPIO-1 pin is acquired.
DB8
GPIO-0
1
GPIO-0 status bit.
Writing a '1' to the GPIO-0 bit puts the GPIO-1 pin into a Hi-Z state (default).
Writing a '0' to the GPIO-0 bit forces the GPIO-1 pin low.
When reading this bit, the digital value on the GPIO-0 pin is acquired.
DB7
DSDO
0
Disable SDO bit.
Set the DSDO bit to '0' to enable the SDO pin (default). The SDO pin works as a normal SPI output.
Set the DSDO bit to '1' to disable the SDO pin. The SDO pin is always in a Hi-Z state regardless of the status of the CS
pin is.
DB6
NOP
0
No operation bit.
Writing '0' or '1' to this bit has no effect and the bit returns to '0' at the end of the write operation.
Reading the bit always returns '0'.
DB5
GAIN-3
1
DAC-3 gain bit.
Set the GAIN-3 bit to '1' for a gain = 4.
Set the GAIN-3 bit to '0' for a gain = 2.
DB4
GAIN-2
1
DAC-2 gain bit.
Set the GAIN-2 bit to '1' for a gain = 4.
Set the GAIN-2 bit to '0' for a gain = 2.
DB3
GAIN-1
1
DAC-1 gain bit.
Set the GAIN-1 bit to '1' for a gain = 4.
Set the GAIN-1 bit to '0' for a gain = 2.
DB2
GAIN-0
1
DAC-0 gain bit.
Set the GAIN-0 bit to '1' for a gain = 4.
Set the GAIN-0 bit to '0' for a gain = 2.
DB1:DB0
—
0
Reserved. Writing to these bits has no effect; reading these bits returns '0'.
26
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Monitor Register. Default = 0000h.
The Monitor Register selects one of the four DAC outputs or the external signal AIN that is to be monitored
through the VMON pin. Only one bit can be set to '1' at a time. When all bits = '0', the monitor is disabled and
VMON is placed in a high-impedance state. The default value after power-on or reset is 0000h.
Table 5. Monitor Register
DB15
DB14
DB13
DB12
DB11
DB10:DB0
0
0
0
0
1
Reserved (1)
AIN
0
0
0
1
0
Reserved (1)
DAC-0
0
0
1
0
0
Reserved (1)
DAC-1
0
1
0
0
0
Reserved (1)
DAC-2
1
0
0
0
0
Reserved (1)
DAC-3
0
(1)
0
(1)
0
0
0
Reserved
VMON CONNECTS TO
Monitor disabled, Hi-Z (default)
Writing to a reserved bit has no effect; reading the bit returns '0'.
Input Data Register for DAC-n (where n = 0, 1, 2, or 3). Default = 0000h.
This register stores the DAC data written to the device. When the data are loaded into the corresponding DAC
latch, the DAC output changes to the new level defined by the DAC data. The default value after power-on or
reset is 0000h.
For bipolar operation, the input data format is always twos complement. For unipolar operation, the input data
format is always straight binary.
Table 6. DAC-n (n = 0, 1, 2, or 3) Input Data Register
MSB
DB15
D13
(1)
(2)
(1)
LSB
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB1
DB0
Reserved (2)
D13:D0 are the DAC data bits.
Writing to a reserved bit has no effect; reading the bit returns '0'.
Table 7. DAC Output vs Twos Complement Code for Bipolar Output Operation
TWOS COMPLEMENT CODE (D13:D0)
OUTPUT
DESCRIPTION
0111 1111 1111 11
+0.5 × Gain × VREF × (8191/8192)
+Full-Scale – 1 LSB
••• •••
••• •••
••• •••
0000 0000 0000 01
+0.5 × Gain × VREF × (1/8192)
+1 LSB
0000 0000 0000 00
0
Zero
1111 1111 1111 11
–0.5 × Gain × VREF × (1/8192)
–1 LSB
••• •••
••• •••
••• •••
1000 0000 0000 00
–0.5 × Gain × VREF × (8192/8192)
–Full-Scale
Table 8. DAC Output vs Straight Binary Code for Unipolar Output Operation
STRAIGHT BINARY CODE (D13:D0)
OUTPUT
DESCRIPTION
1111 1111 1111 11
Gain × VREF × (16383/16384)
+Full-Scale – 1 LSB
••• •••
••• •••
••• •••
1000 0000 0000 00
Gain × VREF × (8192/16384)
1/2 Full-Scale
0111 1111 1111 11
Gain × VREF × (8191/16384)
1/2 Full-Scale – 1 LSB
••• •••
••• •••
••• •••
0000 0000 0000 00
0
Zero
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Zero Register n (where n = 0, 1, 2, or 3). Default = 0000h.
The Zero Register stores the user-calibration data that are used to eliminate the offset error. The data are nine
bits wide, 0.03125 LSB/step, and the total adjustment is typically –8 LSB to +7.96875 LSB, or ±0.0488% of
full-scale range. The Zero Register uses a twos complement data format in both bipolar and unipolar modes of
operation.
Table 9. Zero Register
(1)
DB15:DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Reserved (1)
Z8
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
Writing to a reserved bit has no effect; reading the bit returns '0'.
Z8:Z0—OFFSET BITS
ZERO ADJUSTMENT
011111111
+7.96875 LSB
011111110
+7.9375 LSB
••• ••• •••
••• ••• •••
000000001
+0.03125 LSB
000000000
0 LSB (default)
111111111
–0.03125 LSB
••• ••• •••
••• ••• •••
100000001
–7.96875 LSB
100000000
–8 LSB
Gain Register n (where n = 0, 1, 2, or 3). Default = 0000h.
The Gain Register stores the user-calibration data that are used to eliminate the gain error. The data are eight
bits wide, 0.25 LSB/step, and the total adjustment is typically –32 LSB to +31.75 LSB, or ±0.195% of full-scale
range. The Gain Register uses a twos complement data format in both bipolar and unipolar modes of operation.
Table 10. Gain Register
DB15:DB8
Reserved
(1)
28
(1)
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
G7
G6
G5
G4
G3
G2
G1
G0
Writing to a reserved bit has no effect; reading the bit returns '0'.
G7:G0—GAIN-CODE BITS
GAIN ADJUSTMENT
01111111
+31.75 LSB
01111110
+31.50 LSB
••• ••• •••
••• ••• •••
00000001
+0.25 LSB
00000000
0 LSB (default)
11111111
–0.25 LSB
••• ••• •••
••• ••• •••
10000001
–31.75 LSB
10000000
–32 LSB
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APPLICATION INFORMATION
BASIC OPERATION
46
45
44
43
42
41
40
39
38
37
VOUT-2
RFB2-2
RFB1-2
SGND-2
NC
SGND-3
RFB1-3
RFB2-3
VOUT-3
NC
VOUT-3
47
AIN
VOUT-2
48
UNI/BIP-B
AIN
The DAC8234 is a highly-integrated device with high-performance reference buffers and output buffers, greatly
reducing the printed circuit board (PCB) area and cost. On-chip reference buffers eliminate the need for a
negative external reference. Configurable on-chip output buffers support four different output modes. Figure 44
shows a basic application for the DAC8234.
NC
36
AVDD
35
SCLK
VMON
34
4
SDI
AVSS
33
SDO
5
SDO
REFGND-B
32
LDAC
6
LDAC
REF-B
31
REF-B
RST
7
RST
REF-A
30
REF-A
8
GPIO-0
REFGND-A
29
9
GPIO-1
AVSS
28
1
NC
CS
2
CS
SCLK
3
SDI
0.1mF
10
UNI/BIP-A
11
DGND
12
NC
27
AVDD
26
NC
25
10mF
VOUT-0
RFB2-0
RFB1-0
SGND-0
NC
SGND-1
RFB1-1
RFB2-1
VOUT-1
NC
15
16
17
18
19
20
21
22
23
24
DVDD
14
0.1mF
13
10kW
IOVDD
0.1mF
10kW
+
10mF
AVSS
0.1mF
AGND
10mF
VMON
0.1mF
DAC8234
+
+
+
10mF
10mF
AVDD
0.1mF
+
10mF
VOUT-1
DVDD
VOUT-0
IOVDD
+
NOTES: AVDD = +15V, AVSS = -15V, DVDD = +5V, IOVDD = +1.8 to +5V, REF-A = +5V, and REF-B = +2.5V.
The gain bits in the Command Register are: GAIN-0 = ‘0’, GAIN-1 = ‘1’, GAIN-2 = ‘0’, and GAIN-3 = ‘1’.
The DACs are set to the following gains: DAC-0 = x2, DAC-1 = x4, DAC-2 = x2, and DAC-3 = x4.
The output ranges are: VOUT-0 = -5V to +5V
VOUT-1 = -10V to +10V,
VOUT-2 = 0V to +5V,
VOUT-3 = 0V to +10V.
Figure 44. Basic Application Example
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USER ZERO- AND GAIN-CALIBRATION
The DAC8234 is trimmed during production for nominal operating conditions to have very low gain error and
offset error. However, to trim the offset and gain errors introduced at other conditions of operation or by other
components in the signal chain, the DAC8234 has a user zero and gain digital calibration feature for each DAC
channel. Figure 45 and Figure 46 illustrate the relationship of zero and gain calibration for the DAC8234 in
unipolar output and bipolar output configurations, respectively.
Gain ´ VREF
+ Full Scale
Full-Scale Range
Analog Output
1LSB
Gain Adjust
Rotates the
Transfer
Function
Input =
0000h
Input =
FFFCh
Zero Scale
Digital Input
Zero Adjust Translates the Transfer Function
Figure 45. Relationship of Zero and Gain Calibration for a Unipolar Output Configuration
0.5 ´ Gain ´ VREF
+ FullScale
Analog Output
Input = 8000h
Full-Scale
Range
1LSB
Gain Adjust
Rotates the
Transfer
Function
Zero Adjust
Translates the
Transfer Function
Input = 7FFCh
Input = 0000h
- Full-Scale
-0.5 ´ Gain ´ VREF
Digital Input
Figure 46. Relationship of Zero and Gain Calibration for a Bipolar Output Configuration
30
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System Zero Adjust Example
The DAC8234 zero calibration feature can minimize system offset errors to 0.00019% FSR or 38µV over a 20V
output range. The total adjustment range is approximately ±0.0488% of FSR, or ±9.7mV over a 20V output span.
Assuming that the DAC has been set up with a full-scale range of 20V, and the offset error to be eliminated from
the signal chain is –1mV, then the step size = 0.0000019 × 20V = 38µV.
-1 ´ Offset_Error
Number of Steps of Zero Calibration =
Step Size
(3)
Where Offset_Error is the value of the offset error to be corrected.
For this example, the number of steps of zero calibration = 1mV / 38µV ≈ 26. Therefore, the Zero Register should
be coded with the twos complement of 26 = 0 0001 1010.
Suppose the offset error to be eliminated is +1mV instead; then the number of steps of zero calibration is the
twos complement equivalent of –26, which is 1 1110 0110.
System Gain Adjust Example
The DAC8234 gain calibration feature can minimize system gain errors to 0.001525% FSR or 305µV over a 20V
output range. The total adjustment range is approximately ±0.195% FSR, or –39mV to +38.7mV over a 20V
output span.
Assuming that the DAC has been set up with a full-scale range of 20V, and the gain error to be eliminated from
the signal chain is –10mV, then the step size = 0.00001525 × 20V = 305µV.
-1 ´ Gain_Error
Number of Steps of Gain Calibration =
Step Size
(4)
Where Gain_Error is the value of the gain error to be corrected.
For this example, the number of steps of the gain calibration = 10mV/305µV ≈ 33. Therefore, the Gain Register
should be coded with the twos complement of 33 = 0010 0001.
Suppose the gain error to be eliminated is +10mV instead; then the number of steps of Gain calibration is the
twos complement equivalent of –33, which is 1101 1111.
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LAYOUT AND GROUNDING
Precision analog circuits require careful layout, adequate bypass capacitors, and a clean, well-regulated power
supply to obtain the best possible dc and ac performance. A careful consideration of the power-supply and
ground-return layout helps to ensure the rated performance.
The PCB must be designed so that the analog and digital sections are separated and confined to certain areas of
the board. Fast switching signals, such as clocks, must be shielded with the digital ground to avoid radiating
noise to other sections of the board, and must never be run near the reference inputs. It is essential to minimize
noise on the reference inputs because it couples through to the DAC output. Avoid crossover of digital and
analog signals. Traces on opposite sides of the board must run at right angles to each other. This configuration
reduces the effects of feedthrough on the board. A microstrip technique may be considered, but may not always
be possible with a double-sided board. In this technique, the component side of the board is dedicated to the
ground plane, and signal traces are placed on the solder side.
DGND is the return path for digital currents and AGND is the analog power ground for the DAC. For the best ac
performance, care should be taken to connect DGND and AGND with very low resistance back to the supply
ground. If multiple devices require an AGND-to-DGND connection, the connection must be made at one point
only. The star ground point must be established as close as possible to the device. Each DAC has a ground pin
(SGND-x) that must be connected directly to the corresponding reference ground in low-impedance paths to
achieve the best performance. SGND-0 and SGND-1 must be connected with REFGND-A, and SGND-2 and
SGND-3 must be connected with REFGND-B. It is critical that this trace resistance be extremely small in order to
prevent the voltage drops across the path from affecting device linearity and gain performance. The reference
ground pins, REFGND-A and REFGND-B, must be connected to analog ground AGND.
POWER-SUPPLY NOISE
The DAC8234 should have ample supply bypassing of 1µF to 10µF in parallel with 0.1µF on each supply,
located as close to the package as possible; ideally, placed next to the device. The 1µF to 10µF capacitors must
be a tantalum-bead type. The 0.1µF capacitor must have low effective series resistance (ESR) and low effective
series inductance (ESI), such as common ceramic types that provide a low-impedance path to ground at high
frequencies to handle transient currents because of internal logic switching. The power-supply lines must use
traces as wide as possible to provide low-impedance paths and reduce the effects of glitches on the
power-supply line. Apart from these considerations, the wideband noise on the AVDD, AVSS, DVDD, and IOVDD
supplies should be filtered before being fed to the DAC in order to obtain the best noise performance possible.
PRECISION VOLTAGE REFERENCE SELECTION
To achieve the optimum performance from the DAC8234 over its full operating temperature range, a precision
voltage reference must be used. Consideration should be given to the selection of a precision voltage reference.
The DAC8234 has two reference inputs, REF-A and REF-B. The voltages applied to the reference inputs are
used to provide a buffered positive and negative reference for the DAC cores. Therefore, any error in the voltage
reference is reflected in the outputs of the device. There are four possible sources of error to consider when
choosing a voltage reference for high-accuracy applications: initial accuracy, temperature coefficient of the output
voltage, long-term drift, and output voltage noise. Initial accuracy error on the output voltage of an external
reference can lead to a full-scale error in the DAC. Therefore, to minimize these errors, a reference with a low
initial accuracy error specification is preferred. Long-term drift is a measurement of how much the reference
output voltage drifts over time. A reference with a tight, long-term drift specification ensures that the overall
solution remains relatively stable over its entire lifetime. The temperature coefficient of a reference output voltage
affects INL, DNL, gain error, and zero error. Choose a reference with a tight temperature coefficient specification
to reduce the dependence of the DAC output voltage on ambient conditions. In high-accuracy applications that
have a relatively low noise budget, reference output voltage noise must be considered. Choosing a reference
with as low an output noise voltage as practical for the system resolution required is important. Precision voltage
references such as the TI REF50xx (2V to 5V) and REF32xx (1.25V to 4V), provide low-drift and high-accuracy
reference voltage.
32
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC8234SPFB
ACTIVE
TQFP
PFB
48
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
DAC8234
DAC8234SPFBR
ACTIVE
TQFP
PFB
48
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
DAC8234
DAC8234SRHAR
ACTIVE
VQFN
RHA
40
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
DAC8234
DAC8234SRHAT
ACTIVE
VQFN
RHA
40
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
DAC8234
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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