DAC8532IDGKR

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents DAC8532 SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 DAC8532 Dual Channel, 16-Bit, Low Power, Serial Input Digital-To-Analog Converter 1 Features 3 Description • • • • • • • The DAC8532 is a dual channel, 16-bit digital-toanalog converter (DAC) offering low power operation and a flexible serial host interface. Each on-chip precision output amplifier allows rail-to-rail output swing to be achieved over the supply range of 2.7 V to 5.5 V. The device supports a standard 3-wire serial interface capable of operating with input data clock frequencies up to 30 MHz for VDD = 5 V. 1 • • • • 16-Bit Monotonic Over Temperature MicroPower Operation: 500 µA at 5 V Power-On Reset to Zero-Scale Power Supply: 2.7 V to 5.5 V Settling Time: 10 µs to ±0.003% FSR Ultra-Low AC Crosstalk: –100 dB Typ Low-Power Serial Interface With Schmitt-Triggered Inputs On-Chip Output Buffer Amplifier With Rail-to-Rail Operation Double-Buffered Input Architecture Simultaneous or Sequential Output Update and Powerdown Available in a Tiny VSSOP-8 Package 2 Applications • • • • • • Portable Instrumentation Closed-Loop Servo Control Process Control Data Acquisition Systems Programmable Attenuation PC Peripherals The DAC8532 requires an external reference voltage to set the output range of each DAC channel. The device incorporates a power-on reset circuit which ensures that the DAC outputs power up at zero-scale and remain there until a valid write takes place. The DAC8532 provides a flexible power-down feature, accessible over the serial interface, that reduces the current consumption of the device to 200 nA at 5 V. The low-power consumption of the device in normal operation makes it ideally suited to portable batteryoperated equipment and other low-power applications. The power consumption is 2.5 mW at 5 V, reducing to 1 µW in power-down mode. The DAC8532 is available in a VSSOP-8 package with a specified operating temperature range of –40°C to 105°C. Device Information(1) PART NUMBER DAC8532 PACKAGE VSSOP (8) BODY SIZE (NOM) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Simplified Diagram VREF VDD Data Buffer A DAC Register A DAC A VOUTA Data Buffer B DAC Register B DAC B VOUTB Channel Select Load Control 16 SYNC SCLK DIN 24−Bit Serial−to− Parallel Shift Register 8 Control Logic Power−Down Control Logic 2 Resistor Network GND 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DAC8532 SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Diagram ................................................ Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 3 7.1 7.2 7.3 7.4 7.5 7.6 7.7 3 3 4 4 4 6 7 Absolute Maximum Ratings ...................................... Handling Ratings ...................................................... Recommended Operating Conditions ...................... Thermal Information ................................................. Electrical Characteristics........................................... Timing Requirements ............................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 8.1 Overview ................................................................. 12 8.2 8.3 8.4 8.5 9 Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Register Maps ......................................................... 12 12 14 16 Application and Implementation ........................ 18 9.1 Application Information............................................ 18 9.2 Typical Application .................................................. 21 10 Power Supply Recommendations ..................... 23 11 Layout................................................................... 23 11.1 Layout Guidelines ................................................. 23 11.2 Layout Example .................................................... 24 12 Device and Documentation Support ................. 24 12.1 Trademarks ........................................................... 24 12.2 Electrostatic Discharge Caution ............................ 24 12.3 Glossary ................................................................ 24 13 Mechanical, Packaging, and Orderable Information ........................................................... 24 5 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (May 2003) to Revision B • Added Device Information and Handling Rating tables, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1 Changes from Original (December 2001) to Revision A • 2 Page Page Added text string "No device pin should be brought high before power is applied to the device." to the Power-On Reset Description. ............................................................................................................................................................... 14 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 DAC8532 www.ti.com SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 6 Pin Configuration and Functions VSSOP (DGK) Package 8 Pins Top View VDD 1 VREF 2 8 GND 7 DIN DAC8532 VOUTB 3 6 SCLK VOUTA 4 5 SYNC Pin Functions PIN NAME FUNCTION 1 VDD Power supply input, 2.7 V to 5.5 V 2 VREF Reference voltage input 3 VOUTB Analog output voltage from DAC B 4 VOUTA Analog output voltage from DAC A 5 SYNC Level triggered SYNC input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred on the falling edges of SCLK. The action specified by the 8-bit control byte and 16-bit data word is executed following the 24th falling SCLK clock edge (unless SYNC is taken HIGH before this edge in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8532). 6 SCLK Serial Clock Input. Data can be transferred at rates up to 30 MHz at 5 V. 7 DIN Serial Data Input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input. 8 GND Ground reference point for all circuitry on the part. 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX VDD to GND –0.3 6 Digital input voltage to GND –0.3 VDD+0.3 VOUTA or VOUTB to GND –0.3 VDD+0.3 Operating temperature range –40 105 TJ (1) 150 UNIT V °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 Handling Ratings Tstg Storage temperature range V(ESD) (1) (2) Electrostatic discharge MIN MAX UNIT –65 150 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 1000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 3 DAC8532 SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 www.ti.com 7.3 Recommended Operating Conditions all specifications –40°C to 105°C (unless otherwise noted) MIN NOM MAX VDD to GND 0 5.5 Digital input voltage to GND 0 VDD VOUTA or VOUTB to GND 0 VDD –40 105 Operating temperature range UNIT V °C 7.4 Thermal Information DAC8532 THERMAL METRIC (1) DGK UNIT 8 PINS RθJA Junction-to-ambient thermal resistance 164.0 RθJC(top) Junction-to-case (top) thermal resistance 59.4 RθJB Junction-to-board thermal resistance 84.8 ψJT Junction-to-top characterization parameter 6.5 ψJB Junction-to-board characterization parameter 83.3 RθJC(bot) Junction-to-case (bottom) thermal resistance n/a (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 7.5 Electrical Characteristics VDD = 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC PERFORMANCE (1) Resolution 16 Bits Relative accuracy Differential nonlinearity ±0.0987 16-bit monotonic ±1 % of FSR LSB Zero code error 5 25 mV Full-scale error –0.15 –1 % of FSR ±1 % of FSR Gain error Zero code error drift Gain temperature coefficient Channel-to-channel matching PSRR ±20 µV/°C ±5 ppm of FSR/°C 15 RL = 2 kΩ, CL = 200 pF mV 0.75 mV/V OUTPUT CHARACTERISTICS (2) Output voltage range Output voltage settling time 0 To ±0.003% FSR 0200H to FD00H, RL = 2 kΩ; 0 pF < CL < 200 pF, RL = 2 kΩ; CL = 500 pF Slew rate Capacitive load stability RL = ∞ 1 LSB change around major carry 4 µs pF 20 nV-s 0.5 nV-s 0.25 –100 DC output impedance V V/µs 1000 AC crosstalk (1) (2) 10 470 RL = 2 kΩ Digital feedthrough Short circuit current 8 12 1 Code change glitch impulse DC crosstalk VREF 1 VDD = 5 V 50 VDD = 3 V 20 LSB –96 dB Ω mA Linearity calculated using a reduced code range of 485 to 64714; output unloaded. Ensured by design and characterization, not production tested. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 DAC8532 www.ti.com SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 Electrical Characteristics (continued) VDD = 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted) PARAMETER Power-up time TEST CONDITIONS MIN TYP MAX UNIT Coming out of power-down mode VDD = 5 V 2.5 µs Coming out of power-down mode VDD = 3 V 5 µs AC PERFORMANCE SNR 94 THD 67 BW = 20 kHz, VDD = 5 V, FOUT = 1 kHz, 1st 19 harmonics removed SFDR dB 69 SINAD 65 REFERENCE INPUT Reference current VREF = VDD = 5 V 67 90 VREF = VDD = 3 V 40 54 Reference input range 0 Reference input impedance LOGIC INPUTS VDD 75 µA V kΩ (2) Input current VINL, Input LOW voltage VINH, Input HIGH voltage ±1 VDD = 5 V 0.8 VDD = 3 V 0.6 VDD = 5 V 2.4 VDD = 3 V 2.1 µA V V Pin capacitance 3 pF 5.5 V POWER REQUIREMENTS VDD IDD (normal mode) VDD = 3.6 V to 5.5 V VDD = 2.7 V to 3.6 V 2.7 DAC active and excluding load current VIH = VDD and VIL = GND 500 800 450 750 0.2 1 0.05 1 µA IDD (all power-down modes) VDD = 3.6 V to 5.5 V VDD = 2.7 V to 3.6 V VIH = VDD and VIL = GND µA POWER EFFICIENCY IOUT/IDD ILOAD = 2 mA, VDD = 5 V 89% TEMPERATURE RANGE Specified performance –40 105 °C Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 5 DAC8532 SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 7.6 Timing Requirements www.ti.com (1) (2) VDD = 2.7 V to 5.5 V, all specifications –40°C to 105°C (unless otherwise noted) PARAMETER (3) t1 TEST CONDITIONS SCLK cycle time t2 SCLK HIGH time t3 SCLK LOW time t4 SYNC to SCLK rising edge setup time t5 Data setup time t6 Data hold time t7 24th SCLK falling edge to SYNC rising edge t8 Minimum SYNC HIGH time t9 24th SCLK falling edge to SYNC falling edge (1) (2) (3) MIN VDD = 2.7 V to 3.6 V 50 VDD = 3.6 V to 5.5 V 33 VDD = 2.7 V to 3.6 V 13 VDD = 3.6 V to 5.5 V 13 VDD = 2.7 V to 3.6 V 22.5 VDD = 3.6 V to 5.5 V 13 VDD = 2.7 V to 3.6 V 0 VDD = 3.6 V to 5.5 V 0 VDD = 2.7 V to 3.6 V 5 VDD = 3.6 V to 5.5 V 5 VDD = 2.7 V to 3.6 V 4.5 VDD = 3.6 V to 5.5 V 4.5 VDD = 2.7 V to 3.6 V 0 VDD = 3.6 V to 5.5 V 0 VDD = 2.7 V to 3.6 V 50 VDD = 3.6 V to 5.5 V 33 VDD = 2.7 V to 5.5 V 100 TYP MAX UNIT ns ns ns ns ns ns ns ns ns All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Serial Write Operation timing diagram Figure 1. Maximum SCLK frequency is 30 MHz at VDD = 3.6 V to 5.5 V and 20 MHz at VDD = 2.7 V to 3.6 V. spacer spacer t1 SCLK t9 1 24 t8 t4 t3 t2 t7 SYNC t6 t5 DIN DB23 DB0 DB23 Figure 1. Serial Write Operation 6 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 DAC8532 www.ti.com SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 DLE (LSB) LE (LSB) 0000H 2000H 64 48 32 16 0 −16 −32 −48 −64 LE (LSB) DLE (LSB) Channel A Output 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 4000H 6000H 8000H A000H C000H A000H C000H E000H FFFFH Digital Input Code Figure 2. Linearity Error and Differential Linearity Error vs Code Figure 3. Linearity Error and Differential Linearity Error vs Code VDD = VREF = 2.7V, T A = 25°C, Channel A Output 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 64 48 32 16 0 −16 −32 VDD = V REF = 2.7V, T A = 25° −48 Channel B Output −64 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code Figure 4. Linearity Error and Differential Linearity Error vs Code Figure 5. Linearity Error and Differential Linearity Error vs Code 15 VDD = VREF VDD = 5V, CH B 10 20 Output Error (mV) VDD = 5V, CH A 15 10 VDD = 2.7V, CH B 5 (To avoid clipping of the output signal during the test, V REF = VDD – 10mV) 5 VDD = 2.7V, CH B VDD = 5V, CH B 0 –5 VDD = 2.7V, CH A –10 VDD = 2.7V, CH A 0 –40 4000H 6000H 8000H Digital Input Code 25 Output Error (mV) VDD = VREF = 5V, T A = 25°C, Channel B Output 0000H 2000H E000H FFFFH LE (LSB) 2.0 1.5 1.0 0.5 0.0 −0.5 −1.0 −1.5 −2.0 64 48 32 16 0 −16 −32 −48 −64 VDD = VREF = 5V, T A = 25°C, DLE (LSB) LE (LSB) 64 48 32 16 0 −16 −32 −48 −64 DLE (LSB) 7.7 Typical Characteristics –10 20 50 80 105 –15 –40 VDD = 5V, CH A –10 20 50 80 105 Temperature (° C) Temperature (° C) Figure 6. Zero-Scale Error vs Temperature Figure 7. Full-Scale Error vs Temperature Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 7 DAC8532 SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 www.ti.com Typical Characteristics (continued) 30 25 30 VDD = V REF = 5V, T A = 25°C 25 20 15 Output Error (mV) Output Error (mV) 15 Channel B Output 10 5 0 −5 −10 VDD = V REF = 2.7V, T A = 25°C 20 Channel A Output 10 0 −5 −10 −15 −15 −20 −20 −25 −25 −30 0000H 2000H 4000H 6000H 8000H A000H C000H Channel B Output 5 Channel A Output −30 0000H 2000H E000H FFFFH 4000H 6000H 8000H Digital Input Code A000H C000H E000H FFFFH Digital Input Code Figure 8. Absolute Error Figure 9. Absolute Error 2500 VDD = VREF = 5V, T A = 25°C (±1°C), Digital Code = 7FFFH VDD = VREF = 5V, Reference Current Included Frequency VOUT (25µV/div) 2000 1500 1000 500 0 Time (1min/div) 400 440 480 520 560 600 640 680 720 760 800 IDD (µA) Figure 10. Output Voltage Drift Figure 11. Histogram of Current Consumption 2500 0.15 VDD = VREF = 2.7V , Reference Current Included VREF = VDD −10mV DAC Loaded with 0000H 0.125 2000 VOUT (V) Frequency 0.1 1500 1000 0.075 VDD = 2.7V 0.05 VDD = 5V 500 0.025 0 0 280 320 360 400 440 480 520 560 600 640 680 0 Figure 12. Histogram of Current Consumption 8 1 2 3 4 5 ISINK (mA) IDD (µA) Submit Documentation Feedback Figure 13. Sink Current Capability Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 DAC8532 www.ti.com SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 5 2.7 4.95 2.65 VOUT (V) VOUT (V) Typical Characteristics (continued) 4.9 2.6 2.55 4.85 VREF = VDD −10mV DAC Loaded with FFFFH VDD = 5V 4.8 0 1 VREF = VDD −10mV DAC Loaded with FFFFH VDD = 2.7V 2.5 2 3 4 0 5 2 3 4 ISOURCE (mA) Figure 14. Source Current Capability Figure 15. Source Current Capability 700 700 600 500 500 IDD (µA) 600 400 VDD = VREF = 2.7V 300 400 VDD = VREF = 2.7V 300 200 200 100 100 0 0000H 2000H 4000H 6000H 8000H A000H C000H Reference Current Included, CH A and CH B Active, No Load 0 –40 E000H FFFF H 5 VDD = VREF = 5V VDD = VREF = 5V IDD (µA) 1 ISOURCE (mA) –10 20 50 80 105 Temperature (° C) Digital Input Code Figure 17. Supply Current vs Temperature Figure 16. Supply Current vs Digital Input Code 800 50 VREF = VDD Both DACs Active, Reference Current Included, No Load 750 Reference Current Excluded 45 40 35 650 I DD (nA) IDD (µA) 700 600 550 30 TA = +105°C TA = –40°C 25 20 TA = +25°C 15 500 10 450 400 5 0 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 2.7 VDD (V) 3.4 4.1 4.8 5.5 VDD (V) Figure 18. Supply Current vs Supply Voltage Figure 19. Power-Down Current vs Supply Voltage Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 9 DAC8532 SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 www.ti.com Typical Characteristics (continued) 1150 TA = 25°C, SYNC Input (All Other Inputs = GND) Reference Current Included, CHA and CHB Active, No Load 1050 950 4 VOUT (V) VDD = VREF = 5V I DD (µA) VDD = VREF = 5V, Output Loaded with 2kΩ and 200pF to GND 5 850 750 3 2 650 1 550 VDD = VREF = 2.7V 0 450 0 1 2 3 4 Time (2µs/div) 5 VLOGIC (V) Figure 21. Full-Scale Settling Time (Large Signal) Figure 20. Supply Current vs Logic Input Voltage 3 2.5 3.5 VDD = VREF = 5V, Output Loaded with 2kΩ and 200pF to GND 3 2.5 VDD = VREF = 2.7V, Output Loaded with 2kΩ and 200pF to GND VOUT (V) VOUT (V) 2 1.5 2 1.5 1 1 0.5 0.5 0 0 Time (2µs/div) Time (2µs/div) Figure 22. Half-Scale Settling Time (Large Signal) VOUT (V) 1.5 VDD = VREF = 2.7V, Output Loaded with 2kΩ and 200pF to GND Figure 23. Full-Scale Settling Time (Large Signal) Loaded with 2kΩ to GND VDD (2V/div) VOUT (1V/div) 1 0.5 0 Time (100µs/div) Time (2µs/div) Figure 24. Half-Scale Settling Time (Large Signal) 10 Submit Documentation Feedback Figure 25. Power-On Reset to Zero-Scale Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 DAC8532 www.ti.com SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 Typical Characteristics (continued) 5.5 5 4.72 VDD = VREF = 5V, Power Up to Code FFFFH 4.7 4.5 4.68 VOUT (V, 20mV/div) 4 VOUT (V) 3.5 3 2.5 2 1.5 4.66 4.64 4.62 4.6 4.58 1 4.56 0.5 VDD = VREF = 5V, Code F000H to EFFFH to F000H (Glitch Occurs Every N S 4096 Code Boundary) 4.54 0 −0.5 4.52 Time (1µs/div) Time (1µs/div) Figure 26. Exiting Power-Down Mode Figure 27. Output Glitch (Worst Case) 2.54 96 2.52 94 2.5 92 SNR (dB) VOUT (V, 20mV/div) VDD = 5V 2.48 88 2.46 2.44 VDD = 2.7V 90 VDD = VREF = 5V, Code 8000H to 7FFFH to 8000H (Glitch Occurs Every N S 4096 Code Boundary) VDD = VREF −1dB FSR Digital Input, FS = 52ksps Measurement Bandwidth = 20kHz 86 84 2.42 0 Time (1µs/div) 500 1000 1500 2000 2500 3000 3500 4000 Output Frequency (Hz) Figure 29. Signal-to-Noise Ratio vs Output Frequency Figure 28. Output Glitch (Mid-Scale) 0 VDD = VREF = 5V, −1dB FSR Digital Input, FS = 52ksps Measurement Bandwidth = 20kHz –20 THD (dB) –40 THD –60 –80 2nd Harmonic 3rd Harmonic –100 –120 0 500 1000 1500 2000 2500 3000 3500 4000 Output Frequency (Hz) Figure 30. Total Harmonic Distortion vs Output Frequency Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 11 DAC8532 SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 www.ti.com 8 Detailed Description 8.1 Overview The DAC8532 is a dual channel, 16-bit digital-to-analog converter (DAC) offering low power operation and a flexible serial host interface. Each on-chip precision output amplifier allows rail-to-rail output swing to be achieved over the supply range of 2.7 V to 5.5 V. The device supports a standard 3-wire serial interface capable of operating with input data clock frequencies up to 30 MHz for VDD = 5 V. 8.2 Functional Block Diagram VREF VDD Data Buffer A DAC Register A DAC A VOUTA Data Buffer B DAC Register B DAC B VOUTB Channel Select Load Control 16 SYNC SCLK DIN 24−Bit Serial−to− Parallel Shift Register 8 Control Logic Power−Down Control Logic 2 Resistor Network GND 8.3 Feature Description 8.3.1 DAC Section The architecture of each channel of the DAC8532 consists of a resistor string DAC followed by an output buffer amplifier. Figure 31 shows a simplified block diagram of the DAC architecture. VREF DAC Register REF (+) Resistor String REF (–) VOUTX Output Amplifier GND Figure 31. DAC8532 Architecture The input coding for each device is unipolar straight binary, so the ideal output voltage is given by: D VOUT X = VREF ´ 65536 (1) where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535. VOUTX refers to channel A or B. 12 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 DAC8532 www.ti.com SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 Feature Description (continued) 8.3.2 Resistor String The resistor string section is shown in Figure 32. It is simply a divide-by-2 resistor followed by a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off. This voltage is then applied to the output amplifier by closing one of the switches connecting the string to the amplifier. VREF RDIVIDER VREF 2 R R To Output Amplifier (2´ Gain) R R Figure 32. Resistor String 8.3.3 Output Amplifier Each output buffer amplifier is capable of generating rail-to-rail voltages on its output which approaches an output range of 0 V to VDD (gain and offset errors must be taken into account). Each buffer is capable of driving a load of 2 kΩ in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical characteristics. 8.3.4 Serial Interface The DAC8532 uses a 3-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPI™ and QSP™, and Microwire™ interface standards, as well as most DSPs. See the Serial Write Operation timing diagram for an example of a typical write sequence. The write sequence begins by bringing the SYNC line LOW. Data from the DIN line is clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the DAC8532 compatible with high speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked into the shift register and the programmed function is executed (i.e., a change in Data Buffer contents, DAC register contents, and/or a change in the power-down mode of a specified channel or channels). Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 13 DAC8532 SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 www.ti.com Feature Description (continued) At this point, the SYNC line may be kept LOW or brought HIGH. In either case, the minimum delay time from the 24th falling SCLK edge to the next falling SYNC edge must be met in order to properly begin the next cycle. To assure the lowest power consumption of the device, care should be taken that the digital input levels are as close to each rail as possible. (See the Typical Characteristics section for the Supply Current vs Logic Input Voltage transfer characteristic curve). 8.3.5 Power-On Reset The DAC8532 contains a power-on reset circuit that controls the output voltage during power-up. On power-up, the DAC registers are filled with zeros and the output voltages are set to zero-scale; they remain there until a valid write sequence and load command is made to the respective DAC channel. This is useful in applications where it is important to know the state of the output of each DAC output while the device is in the process of powering up. No device pin should be brought high before power is applied to the device. 8.4 Device Functional Modes 8.4.1 Input Shift Register The input shift register of the DAC8532 is 24 bits wide (see Figure 33) and is made up of 8 control bits (DB16–DB23) and 16 data bits (DB0–DB15). The first two control bits (DB22 and DB23) are reserved and must be 0 for proper operation. LD A (DB20) and LD B (DB21) control the updating of each analog output with the specified 16-bit data value or power- down command. Bit DB19 is a Don't Care bit which does not affect the operation of the DAC8532 and can be 1 or 0. The following control bit, Buffer Select (DB18), controls the destination of the data (or power-down command) between DAC A and DAC B. The final two control bits, PD0 (DB16) and PD1 (DB17), select the power-down mode of one or both of the DAC channels. The four modes are normal mode or any one of three power-down modes. A more complete description of the operational modes of the DAC8532 can be found in the Power-Down Modes section. The remaining sixteen bits of the 24-bit input word make up the data bits. These are transferred to the specified Data Buffer or DAC Register, depending on the command issued by the control byte, on the 24th falling edge of SCLK. See Table 2 and Table 3 for more information. DB23 0 DB12 0 LDB LDA X Buffer Select PD1 PD0 D15 D14 D13 D12 D9 D8 D7 D6 D5 D5 D3 D2 D1 D0 DB11 D11 DB0 D10 Figure 33. DAC8532 Data Input Register Format 8.4.2 SYNC Interrupt In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the addressed DAC register is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, it acts as an interrupt to the write sequence; the shift register is reset and the write sequence is discarded. Neither an update of the data buffer contents, DAC register contents or a change in the operating mode occurs (see Figure 34). 14 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 DAC8532 www.ti.com SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 SCLK 1 24th Falling 24th Falling Edge Edge 2 1 2 SYNC Invalid Write-Sync Interrupt: SYNC HIGH before 24th Falling Edge DIN DB0 DB23 DB22 Valid Write-Buffer/DAC Update: SYNC HIGH after 24th Falling Edge DB23 DB22 DB1 DB0 Figure 34. Interrupt and Valid SYNC Timing 8.4.3 Power-Down Modes The DAC8532 utilizes four modes of operation. These modes are accessed by setting two bits (PD1 and PD0) in the control Load action to one or both DACs. Table 1 shows how the state of the bits correspond to the register and performing a mode of operation of each channel of the device. (Each DAC channel can be powered down simultaneously or independently of each other. Power-down occurs after proper data is written into PD0 and PD1 and a Load command occurs.) See the Operation Examples section for additional information. Table 1. Modes of Operation for the DAC8532 PD1 (DB17) PD0 (DB16) OPERATING MODE 0 0 Normal Operation — — Power-down modes 0 1 Output typically 1 kΩ to GND 1 0 Output typically 100 kΩ to GND 1 1 High impedance When both bits are set to 0, the device works normally with a typical power consumption of 500 µA at 5 V. For the three power-down modes, however, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output impedance of the device is known while it is in power-down mode. There are three different options for power-down: The output is connected internally to GND through a 1 kΩ resistor, a 100 kΩ resistor, or it is left open-circuited (High-Impedance). The output stage is illustrated in Figure 35. Resistor String DAC VOUTX Amplifier Power–Down Circuitry Resistor Network Figure 35. Output Stage During Power-Down (High Impedance) Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 15 DAC8532 SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 www.ti.com All analog circuitry is shut down when the power-down mode is activated. Each DAC will exit power-down when PD0 and PD1 are set to 0, new data is written to the Data Buffer, and the DAC channel receives a Load command. The time to exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs for VDD = 3 V (see the Typical Characteristics section. 8.5 Register Maps Table 2. Control Matrix D23 D22 Reserved D21 Reserved Load B D20 D19 D18 Load A Don't Care Buffer Select D17 D16 PD1 PD0 0 0 D15 MSB D14 D13–D0 MSB-1 MSB-2... LSB DESCRIPTION 0 = A, 1=B (Always Write 0) 0 0 0 0 X # 0 0 0 0 X # 0 0 0 1 X # 0 0 0 1 X 0 See Table 3 0 0 0 1 X 1 See Table 3 0 0 1 0 X # 0 0 1 0 X 0 See Table 3 X WR Buffer A w/Power-Down Command and LOAD DAC B 0 0 1 0 X 1 See Table 3 X WR Buffer B w/Power-Down Command and LOAD DAC B (DAC B Powered Down) 0 0 1 1 X # 0 0 1 1 X 0 See Table 3 X WR Buffer A w/Power-Down Command and Load DACs A and B (DAC A Powered Down) 0 0 1 1 X 1 See Table 3 X WR Buffer B w/Power-Down Command and Load DACs A and B (DAC B Powered Down) See Table 3 0 0 0 0 0 0 Data WR Buffer # w/Data X WR Buffer # w/Power-down Command Data WR Buffer # w/Data and Load DAC A X WR Buffer A w/Power-Down Command and LOAD DAC A (DAC A Powered Down) X WR Buffer B w/Power-Down Command and LOAD DAC A Data WR Buffer # w/Data and Load DAC B Data WR Buffer # w/Data and Load DACs A and B Table 3. Power-Down Commands D17 D16 PD1 PD0 0 1 1 kΩ 1 0 100 kΩ 1 1 High Impedance OUTPUT IMPEDANCE POWER DOWN COMMANDS 8.5.1 Operation Examples Example 1: Write to Data Buffer A; Through Buffer B; Load DACA Through DACB Simultaneously • 1st — Write to DataBuffer A: Reserved 0 • Reserved 0 LDB 0 LDA 0 DC X Buffer Select 0 PD1 0 PD0 0 DB15 D15 — — DB1 D1 DB0 D0 DB15 D15 — — DB1 D1 DB0 D0 2nd — Write to Data Buffer B and Load DAC A and DAC B simultaneously: Reserved 0 Reserved 0 LDB 1 LDA 1 DC X Buffer Select 1 PD1 0 PD0 0 The DACA and DACB analog outputs simultaneously settle to the specified values upon completion of the 2nd write sequence. (The Load command moves the digital data from the data buffer to the DAC register at which time the conversion takes place and the analog output is updated. Completion occurs on the 24th falling SCLK edge after SYNC LOW.) Example 2: Load New Data to DACA and DACB Sequentially • 1st — Write to Data Buffer A and Load DAC A: DACA output settles to specified value upon completion: Reserved 0 16 Reserved 0 LDB 0 LDA 1 DC X Buffer Select 0 PD1 0 Submit Documentation Feedback PD0 0 DB15 D15 — — DB1 D1 DB0 D0 Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 DAC8532 www.ti.com • SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 2nd — Write to Data Buffer B and Load DAC B: DACB output settles to specified value upon completion: Reserved 0 Reserved 0 LDB 1 LDA 0 DC X Buffer Select 1 PD1 0 PD0 0 DB15 D15 — — DB1 D1 DB0 D0 After completion of the 1st write cycle, the DACA analog output settles to the voltage specified; upon completion of write cycle 2, the DACB analog output settles. Example 3: Power-Down DACA to 1 kΩ and Power-Down DACB to 100 kΩ Simultaneously • 1st — Write power-down command to Data Buffer A: Reserved 0 • Reserved 0 LDB 0 LDA 0 DC X Buffer Select 0 PD1 0 PD0 1 DB15 — DB1 Don't Care DB0 2nd — Write power-down command to Data Buffer B and Load DACA and DACB simultaneously: Reserved 0 Reserved 0 LDB 1 LDA 1 DC X Buffer Select 1 PD1 1 PD0 0 DB15 — DB1 Don't Care DB0 The DACA and DACB analog outputs simultaneously power-down to each respective specified mode upon completion of the 2nd write sequence. Example 4: Power-Down DACA and DACB to High-Impedance Sequentially: • 1st — Write power-down command to Data Buffer A and Load DAC A: DAC A output = Hi-Z: Reserved 0 • Reserved 0 LDB 0 LDA 1 DC X Buffer Select 0 PD1 1 PD0 1 DB15 — DB1 Don't Care DB0 2nd — Write power-down command to Data Buffer B and Load DAC B: DAC B output = Hi-Z: Reserved 0 Reserved 0 LDB 1 LDA 0 DC X Buffer Select 1 PD1 1 PD0 1 DB15 — DB1 Don't Care DB0 The DACA and DACB analog outputs sequentially power-down to high-impedance upon completion of the 1st and 2nd write sequences, respectively. Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated Product Folder Links: DAC8532 17 DAC8532 SBAS246B – DECEMBER 2001 – REVISED NOVEMBER 2014 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Current Consumption The DAC8532 typically consumes 250 µA at VDD = 5 V and 225 µA at VDD = 3 V for each active channel, including reference current consumption. Additional current consumption can occur at the digital inputs if VIH