DAC8552
DA
C8
552
SLAS430A – JULY 2006 – REVISED OCTOBER 2006
16-BIT, DUAL CHANNEL, ULTRA-LOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
•
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•
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•
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DESCRIPTION
Relative Accuracy: 4LSB
Glitch Energy: 0.15nV-s
MicroPower Operation:
155µA per Channel at 2.7V
Power-On Reset to Zero-Scale
Power Supply: 2.7V to 5.5V
16-Bit Monotonic Over Temperature
Settling Time: 10µs to ±0.003% FSR
Ultra-Low AC Crosstalk: –100dB Typ
Low-Power Serial Interface with
Schmitt-Triggered Inputs
On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
Double-Buffered Input Architecture
Simultaneous or Sequential Output Update
and Power-down
Available in a Tiny MSOP-8 Package
The DAC8552 is a 16-bit, dual channel, voltage
output digital-to-analog converter (DAC) offering low
power operation and a flexible serial host interface.
Each on-chip precision output amplifier allows
rail-to-rail output swing to be achieved over the
supply range of 2.7V to 5.5V. The device supports a
standard 3-wire serial interface capable of operating
with input data clock frequencies up to 30MHz for
VDD = 5V.
The DAC8552 requires an external reference voltage
to set the output range of each DAC channel. Also
incorporated into the device is a power-on reset
circuit which ensures that the DAC outputs power up
at zero-scale and remain there until a valid write
takes place. The DAC8552 provides a flexible
power-down feature, accessed over the serial
interface, that reduces the current consumption of
the device to 700nA at 5V.
The low-power consumption of this device in normal
operation makes it ideally suited for portable,
battery-operated equipment and other low-power
applications. The power consumption is 0.5mW per
channel at 2.7V, reducing to 1µW in power-down
mode.
APPLICATIONS
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•
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Portable Instrumentation
Closed-Loop Servo Control
Process Control
Data Acquisition Systems
Programmable Attenuation
PC Peripherals
The DAC8552 is available in a MSOP-8 package
with a specified operating temperature range of
–40°C to +105°C.
VDD
VREF
Data
Buffer A
DAC
Register A
DAC A
VOUTA
Data
Buffer B
DAC
Register B
DAC B
VOUTB
Channel
Select
Load
Control
16
SYNC
SCLK
DIN
24-Bit,
Serial-toParallel
8
Shift
Register
Control Logic
Power-Down
Control Logic
2
Resistor
Network
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSP are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
DAC8552
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SLAS430A – JULY 2006 – REVISED OCTOBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGING/ORDERING INFORMATION (1)
PRODUCT
MAXIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
DIFFERENTIAL
NONLINEARITY
(LSB)
PACKAGE
LEAD
PACKAGE
DESIGNATOR
SPECIFICATION
TEMPERATURE
RANGE
PACKAGE
MARKING
DAC8552
±12
±1
MSOP-8
DGK
–40°C to +105°C
D82
(1)
TRANSPORT
MEDIA,
QUANTITY
ORDERING
NUMBER
DAC8552IDGKT
Tape and Reel, 250
DAC8552IDGKR
Tape and Reel, 2500
For the most current package and ordering information, see the Package Option Addendum at the of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted). (1)
UNIT
VDD to GND
–0.3V to 6V
Digital input voltage to GND
–0.3V to VDD + 0.3V
VOUTA or VOUTB to GND
–0.3V to VDD + 0.3V
Operating temperature range
–40°C to +105°C
Storage temperature range
–65°C to +150°C
Junction temperature (TJ max)
+150°C
Power dissipation
Thermal impedance
(1)
(TJ max – TA)/θJA
θJA
206°C/W
θJC
44°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±4
±12
LSB
STATIC PERFORMANCE (1)
Resolution
16
Measured by line passing through codes 513 and
64741
Differential nonlinearity
16-bit monotonic
±0.35
±1
LSB
Zero code error
Measured by line passing through codes 485 and
64741
±2.5
±12
mV
Full-scale error
Measured by line passing through codes 485 and
64741
±0.1
±0.5
% of FSR
Gain error
Measured by line passing through codes 485 and
64741
±0.08
±0.2
% of FSR
±5
Zero code error drift
±1
Gain temperature coefficient
PSRR
(1)
2
Bits
Relative accuracy
Output unloaded
Linearity calculated using a reduced code range of 513 to 64741. Output unloaded.
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0.75
µV/°C
ppm of FSR/°C
mV/V
DAC8552
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SLAS430A – JULY 2006 – REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VREF
V
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time
0
To ±0.003% FSR 0200h to FD00h, RL = 2kΩ;
0pF < CL < 200pF
8
RL = 2kΩ; CL = 500pF
µs
12
Slew rate
Capacitive load stability
10
1.8
RL = ∞
V/µs
470
pF
RL = 2kΩ
1000
Code change glitch impulse
1LSB change around major carry
0.15
nV-s
Digital feedthrough
50kΩ series resistance on digital lines
0.15
nV-s
DC crosstalk
Full-scale swing on adjacent channel.
VDD = 5V, VREF = 4.096V
0.25
LSB
AC crosstalk
1kHz sine wave
–100
dB
DC output impedance
At mid-point input
1
Ω
Short circuit current
Power-up time
VDD = 5V
50
VDD = 3V
20
Coming out of power-down mode, VDD = 5V
2.5
µs
Coming out of power-down mode, VDD = 3V
5
µs
mA
AC PERFORMANCE
SNR
95
THD
–85
SFDR
BW = 20kHz, VDD = 5V, fOUT = 1kHz,
1st 19 harmonics removed for SNR calculation
dB
87
SINAD
84
REFERENCE INPUT
Reference current
VREF = VDD = 5.5V
90
120
VREF = VDD = 3.6V
60
100
Reference input range
0
Reference input impedance
VDD
62
µA
V
kΩ
LOGIC INPUTS (2)
±1
Input current
VINL, Input LOW voltage
VINH, Input HIGH voltage
VDD = 5V
0.8
VDD = 3V
0.6
VDD = 5V
2.4
VDD = 3V
2.1
µA
V
V
Pin capacitance
3
pF
5.5
V
POWER REQUIREMENTS
VDD
2.7
IDD (normal mode)
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
Input code = 32768, no load, does not include
reference current
VIH = VDD and VIL = GND
340
500
310
480
0.7
2
0.4
2
µA
IDD (all power-down modes)
VDD = 3.6V to 5.5V
VDD = 2.7V to 3.6V
VIH = VDD and VIL = GND
µA
POWER EFFICIENCY
IOUT/IDD
ILOAD = 2mA, VDD = 5V
89
%
TEMPERATURE RANGE
Specified performance
(2)
–40
+105
°C
Specified by design and characterization; not production tested.
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SLAS430A – JULY 2006 – REVISED OCTOBER 2006
PIN CONFIGURATION
DGK PACKAGE
MSOP-8
(Top View)
VDD
1
VREF
2
8
GND
7
DIN
DAC8552
VOUTB
3
6
SCLK
VOUTA
4
5
SYNC
PIN DESCRIPTIONS
PIN
4
NAME
FUNCTION
1
VDD
Power supply input, 2.7V to 5.5V
2
VREF
Reference voltage input
3
VOUTB
Analog output voltage from DAC B
4
VOUTA
Analog output voltage from DAC A
5
SYNC
Level triggered SYNC input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes
LOW, it enables the input shift register and data is transferred on the falling edges of SCLK. The action specified by the
8-bit control byte and 16-bit data word is executed following the 24th falling SCLK clock edge (unless SYNC is taken
HIGH before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored
by the DAC8552). Schmitt-Trigger logic input.
6
SCLK
Serial Clock Input. Data can be transferred at rates up to 30MHz at 5V. Schmitt-Trigger logic input.
7
DIN
Serial Data Input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input.
Schmitt-Trigger logic input.
8
GND
Ground reference point for all circuitry on the part.
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SLAS430A – JULY 2006 – REVISED OCTOBER 2006
SERIAL WRITE OPERATION
t9
t1
SCLK
1
24
t8
t3
t4
t2
t7
SYNC
t6
t5
DIN
DB23
DB0
DB23
TIMING CHARACTERISTICS (1) (2)
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
t1 (3)
SCLK cycle time
t2
SCLK HIGH time
t3
SCLK LOW time
t4
SYNC to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
24th SCLK falling edge to SYNC rising edge
t8
Minimum SYNC HIGH time
t9
24th SCLK falling edge to SYNC falling edge
(1)
(2)
(3)
TEST CONDITIONS
MIN
VDD = 2.7V to 3.6V
50
VDD = 3.6V to 5.5V
33
VDD = 2.7V to 3.6V
13
VDD = 3.6V to 5.5V
13
VDD = 2.7V to 3.6V
22.5
VDD = 3.6V to 5.5V
13
VDD = 2.7V to 3.6V
0
VDD = 3.6V to 5.5V
0
VDD = 2.7V to 3.6V
5
VDD = 3.6V to 5.5V
5
VDD = 2.7V to 3.6V
4.5
VDD = 3.6V to 5.5V
4.5
VDD = 2.7V to 3.6V
0
VDD = 3.6V to 5.5V
0
VDD = 2.7V to 3.6V
50
VDD = 3.6V to 5.5V
33
VDD = 2.7V to 5.5V
100
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
See Serial Write Operation Timing Diagram.
Maximum SCLK frequency is 30MHz at VDD = 3.6V to 5.5V and 20MHz at VDD = 2.7V to 3.6V.
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SLAS430A – JULY 2006 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
1.0
1.0
0.5
0.5
0
-0.5
-1.0
VDD = 5V, VREF = 4.9V, TA = +25°C
Channel B Output
0
-0.5
-1.0
0
7.5
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Figure 1.
Figure 2.
ZERO-SCALE ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
57344 65536
5
VDD = 5V
VREF = 4.99V
VDD = 5V
VREF = 4.99V
Full-Scale Error (mV)
5.0
Zero-Scale Error (mV)
8
6
4
2
0
-2
-4
-6
-8
LE (LSB)
VDD = 5V, VREF = 4.9V, TA = +25°C
Channel A Output
DLE (LSB)
DLE (LSB)
LE (LSB)
8
6
4
2
0
-2
-4
-6
-8
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
2.5
CH B
0
-2.5
CH A
CH B
0
CH A
-5
-5.0
-7.5
-10
0
-40
40
80
120
0
-40
Temperature (°C)
40
80
120
Temperature (°C)
Figure 3.
Figure 4.
SOURCE CURRENT CAPABILITY
AT POSITIVE RAIL
SINK CURRENT CAPABILTY
AT NEGATIVE RAIL
6.0
0.150
VREF = VDD - 10mV
DAC Loaded with 0000h
0.125
5.6
VOUT (V)
VOUT (V)
0.100
5.2
4.8
VDD = 2.7V
0.075
VDD = 5.5V
0.050
4.4
VDD = 5.5V
VREF = VDD - 10mV
DAC Loaded with FFFFh
0.025
4.0
0
0
2
4
6
8
10
0
ISOURCE (mA)
4
6
ISINK (mA)
Figure 5.
6
2
Figure 6.
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SLAS430A – JULY 2006 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs DIGITAL INPUT CODE
SUPPLY CURRENT
vs SUPPLY VOLTAGE
600
600
Reference Current Included
500
VDD = VREF = 5.5V
500
400
VDD = VREF = 3.6V
300
450
IDD (mA)
IDD (mA)
VREF = VDD, All DACs Powered
Reference Current Included, No Load
550
400
350
200
300
100
250
0
200
0
2.7
8192 16384 24576 32768 40960 49152 57344 65536
3.1
3.5
4.3
4.7
5.1
5.5
VDD (V)
Digital Input Code
Figure 7.
Figure 8.
SUPPLY CURRENT
vs TEMPERATURE
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
2400
600
TA = 25°C, SYNC Input (all other inputs = GND)
CH A Powered Up; All Other Channels in Power-Down
Reference Current Included
2000
500
VDD = VREF = 5.5V
1600
VDD = VREF = 3.6V
IDD (mA)
IDD (mV)
400
300
VDD = VREF = 5.5V
1200
200
800
100
400
0
0
-40
0
40
80
0
120
2
3
5
Figure 9.
Figure 10.
POWER SPECTRAL DENSITY
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
-40
VDD = 5V
VREF = 4.096V
fOUT = 1kHz
f
= 1MSPS
-30
CLK
-60
THD (dB)
-70
-70
THD
-90
-80
-110
-90
-130
-100
2nd Harmonic
5
10
15
20
5.5
VDD = 5V
VREF = 4.9V
-1dB FSR Digital Input
fS = 1MSPS
Measurement Bandwidth = 20kHz
-50
-50
0
4
VLOGIC (V)
-10
Gain (dB)
1
Temperature (°C)
0
1
3rd Harmonic
2
3
Frequency (kHz)
fOUT (kHz)
Figure 11.
Figure 12.
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5
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SLAS430A – JULY 2006 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
98
VREF = VDD = 5V
-1dB FSR Digital Input
fS = 1MSPS
Measurement Bandwidth = 20kHz
94
VDD = 5V
VREF = 4.99V
Code = 7FFFh
No Load
300
Voltage Noise (nV/ÖHz)
96
SNR (dB)
OUTPUT NOISE DENSITY
350
92
90
88
250
200
150
86
100
84
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.5
100
1k
10k
Frequency (Hz)
Figure 13.
Figure 14.
FULL-SCALE SETTLING TIME: 5V RISING EDGE
FULL-SCALE SETTLING TIME: 5V FALLING EDGE
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: D000
To Code: FFFF
Rising Edge
1V/div
Zoomed Rising Edge
1mV/div
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: FFFF
To Code: 0000
Falling
Edge
1V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 15.
Figure 16.
HALF-SCALE SETTLING TIME: 5V RISING EDGE
HALF-SCALE SETTLING TIME: 5V FALLING EDGE
Trigger Pulse 5V/div
Trigger Pulse 5V/div
VDD = 5V
VREF = 4.096V
From Code: CFFF
To Code: 4000
Rising
Edge
1V/div
VDD = 5V
VREF = 4.096V
From Code: 4000
To Code: CFFF
Zoomed Rising Edge
1mV/div
Falling
Edge
1V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 17.
8
100k
fOUT (kHz)
Figure 18.
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TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
VDD = 5V
VREF = 4.096V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 19.
Figure 20.
GLITCH ENERGY: 5V, 16LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 16LSB STEP, FALLING EDGE
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
VDD = 5V
VREF = 4.096V
From Code: 8010
To Code: 8000
Glitch: 0.08nV-s
VOUT (500mV/div)
VOUT (500mV/div)
Time (400ns/div)
Time (400ns/div)
Figure 21.
Figure 22.
GLITCH ENERGY: 5V, 256LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 256LSB STEP, FALLING EDGE
VDD = 5V
VREF = 4.096V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
VOUT (5mV/div)
VOUT (5mV/div)
GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE
VOUT (500mV/div)
VOUT (500mV/div)
GLITCH ENERGY: 5V, 1LSB STEP, RISING EDGE
VDD = 5V
VREF = 4.096V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 23.
Figure 24.
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TYPICAL CHARACTERISTICS: VDD = 2.7V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
8
6
4
2
0
-2
-4
-6
-8
LE (LSB)
VDD = 2.7V, VREF = 2.5V, TA = +25°C
Channel A Output
1.0
1.0
0.5
0.5
DLE (LSB)
DLE (LSB)
LE (LSB)
8
6
4
2
0
-2
-4
-6
-8
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
0
-0.5
-1.0
VDD = 2.7V, VREF = 2.5V, TA = +25°C
Channel B Output
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Figure 25.
Figure 26.
ZERO-SCALE ERROR vs TEMPERATURE
7.5
VDD = 2.7V
VREF = 2.69V
Full-Scale Error (mV)
Zero-Scale Error (mV)
FULL-SCALE ERROR vs TEMPERATURE
5
VDD = 2.7V
VREF = 2.69V
5.0
57344 65536
2.5
CH B
0
-2.5
CH A
CH B
0
CH A
-5
-5.0
-7.5
-10
0
-40
40
80
120
0
-40
Temperature (°C)
40
Figure 27.
SOURCE CURRENT CAPABILITY AT POSITIVE RAIL
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE
800
700
2.7
TA = 25°C, SYNC Input (all other inputs = GND)
CH A Powered Up; All Other Channels in Power-Down
600
2.4
IDD (mA)
VOUT (V)
120
Figure 28.
3.0
2.1
500
VDD = VREF = 2.7V
400
300
200
VDD = 2.7 V
VREF = VDD − 10mV
DAC loaded with FFFFh
1.8
100
1.5
0
0
2
4
6
ISOURCE (mA)
8
10
0
0.5
1.0
1.5
VLOGIC (V)
Figure 29.
10
80
Temperature (°C)
Figure 30.
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2.5 2.7
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TYPICAL CHARACTERISTICS: VDD = 2.7V (continued)
At TA = +25°C, unless otherwise noted.
FULL-SCALE SETTLING TIME: 2.7V RISING EDGE
FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
VREF = 2.5V
From Code: FFFF
To Code: 0000
Rising
Edge
0.5V/div
VDD = 2.7V
VREF = 2.5V
From Code: 0000
To Code: FFFF
Falling
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 31.
Figure 32.
HALF-SCALE SETTLING TIME: 2.7V RISING EDGE
HALF-SCALE SETTLING TIME: 2.7V FALLING EDGE
Trigger Pulse 2.7V/div
Trigger Pulse 2.7V/div
VDD = 2.7V
VREF = 2.5V
From Code: CFFF
To Code: 4000
VDD = 2.7V
VREF = 2.5V
From Code: 4000
To Code: CFFF
Rising
Edge
0.5V/div
Falling
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Time (2ms/div)
Time (2ms/div)
Figure 33.
Figure 34.
GLITCH ENERGY: 2.7V, 1LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 1LSB STEP, FALLING EDGE
VDD = 2.7V
VREF = 2.5V
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
VOUT (200mV/div)
VOUT (200mV/div)
Zoomed Falling Edge
1mV/div
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS: VDD = 2.7V (continued)
At TA = +25°C, unless otherwise noted.
12
VDD = 2.7V
VREF = 2.5V
From Code: 8010
To Code: 8000
Glitch: 0.12nV-s
VOUT (200mV/div)
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE
Time (400ns/div)
Time (400ns/div)
Figure 37.
Figure 38.
GLITCH ENERGY: 2.7V, 256LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 256LSB STEP, FALLING EDGE
VDD = 2.7V
VREF = 2.5V
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
VOUT (5mV/div)
VOUT (5mV/div)
VOUT (200mV/div)
GLITCH ENERGY: 2.7V, 16LSB STEP, RISING EDGE
VDD = 2.7V
VREF = 2.5V
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 39.
Figure 40.
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THEORY OF OPERATION
DAC SECTION
VREF
The architecture of each channel of the DAC8552
consists of a resistor-string DAC followed by an
output buffer amplifier. Figure 41 shows a simplified
block diagram of the DAC architecture.
VREF
50kW
RDIVIDER
VREF
2
50kW
R
62kW
DAC
Register
VOUT
REF(+)
Resistor String
REF(-)
R
To Output Amplifier
(2x Gain)
GND
Figure 41. DAC8552 Architecture
The input coding for each device is unipolar straight
binary, so the ideal output voltage is given by:
D
V OUT A, B + VREF
65536
(1)
R
Where:
D = decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0
to 65535.
VOUTA,B refers to channel A or B.
R
RESISTOR STRING
Figure 42. Resistor String
The resistor string section is shown in Figure 42. It is
simply a divide-by-2 resistor followed by a string of
resistors, each of value R. The code loaded into the
DAC register determines at which node on the string
the voltage is tapped off. This voltage is then applied
to the output amplifier by closing one of the switches
connecting the string to the amplifier.
OUTPUT AMPLIFIER
Each output buffer amplifier is capable of generating
rail-to-rail voltages on its output which approaches
an output range of 0V to VDD (gain and offset errors
must be taken into account). Each buffer is capable
of driving a load of 2kΩ in parallel with 1000pF to
GND. The source and sink capabilities of the output
amplifier can be seen in the Typical Characteristics.
SERIAL INTERFACE
The DAC8552 uses a 3-wire serial interface (SYNC,
SCLK, and DIN) that is compatible with SPI™,
QSP™, and Microwire™ interface standards, as well
as most DSPs. See the Serial Write Operation
Timing Diagram for an example of a typical write
sequence.
The write sequence begins by bringing the SYNC
line LOW. Data from the DIN line are clocked into the
24-bit shift register on each falling edge of SCLK.
The serial clock frequency can be as high as 30MHz,
making the DAC8552 compatible with high speed
DSPs. On the 24th falling edge of the serial clock,
the last data bit is clocked into the shift register and
the shift register is locked. Further clocking does not
change the shift register data. Once 24 bits are
locked into the shift register, the eight MSBs are
used as control bits and the 16 LSBs are used as
data. After receiving the 24th falling clock edge, the
DAC8552 decodes the eight control bits and 16 data
bits to perform the required function, without waiting
for a SYNC rising edge. A new SPI sequence starts
at the next falling edge of SYNC. A rising edge of
SYNC before the 24-bit sequence is complete resets
the SPI interface; no data transfer occurs.
After the 24th falling edge of SCLK is received, the
SYNC line may be kept LOW or brought HIGH. In
either case, the minimum delay time from the 24th
falling SCLK edge to the next falling SYNC edge
must be met in order to properly begin the next
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cycle. To assure the lowest power consumption of
the device, care should be taken that the levels are
as close to each rail as possible. (See the Typical
Characteristics section for the Supply Current vs
Logic Input Voltage transfer characteristic curve).
the destination of the data (or power-down
command) between DAC A and DAC B. The final
two control bits, PD0 (DB16) and PD1 (DB17), select
the power-down mode of one or both of the DAC
channels. The four modes are normal mode or any
one of three power-down modes. A more complete
description of the operational modes of the DAC8552
can be found in the Power-Down Modes section. The
remaining 16 bits of the 24-bit input word make up
the data bits. These bits are transferred to the
specified Data Buffer or DAC Register, depending on
the command issued by the control byte, on the 24th
falling edge of SCLK. See Table 1 and Table 2 for
more information.
INPUT SHIFT REGISTER
The input shift register of the DAC8552 is 24 bits
wide (shown in Figure 43) and is made up of eight
control bits (DB16–DB23) and 16 data bits
(DB0–DB15). The first two control bits (DB22 and
DB23) are reserved and must be '0' for proper
operation. LDA (DB20) and LD B (DB21) control the
updating of each analog output with the specified
16-bit data value or power- down command. Bit
DB19 is a don't care bit that does not affect the
operation of the DAC8552, and can be '1' or '0'. The
following control bit, Buffer Select (DB18), controls
DB23
DB12
0
0
LDB
LDA
X
Buffer Select
PD1
PD0
D15
D14
D13
D12
DB11
DB0
D11
D10
D9
D8
D7
D6
D5
D5
D3
D2
D1
D0
Figure 43. DAC8552 Data Input Register Format
Table 1. Control Matrix
D23
Reserved
D22
Reserved
D21
Load B
D20
D19
D18
Load A
Don't
Care
Buffer
Select
D17
D16
PD1
PD0
0
0
D15
MSB
D14
D13–D0
MSB-1
MSB-2...
LSB
0 = A,
1=B
(Always Write 0)
DESCRIPTION
0
0
0
0
X
#
0
0
0
0
X
#
0
0
0
1
X
#
0
0
0
1
X
0
See Table 2
0
0
0
1
X
1
See Table 2
0
0
1
0
X
#
0
0
1
0
X
0
See Table 2
X
WR Buffer A w/Power-Down Command and LOAD DAC B
0
0
1
0
X
1
See Table 2
X
WR Buffer B w/Power-Down Command and LOAD DAC B
(DAC B Powered Down)
0
0
1
1
X
#
0
0
1
1
X
0
See Table 2
X
WR Buffer A w/Power-Down Command and Load DACs A and
B (DAC A Powered Down)
0
0
1
1
X
1
See Table 2
X
WR Buffer B w/Power-Down Command and Load DACs A and
B (DAC B Powered Down)
See Table 2
0
0
0
0
0
0
Data
WR Buffer # w/Data
X
WR Buffer # w/Power-down Command
Data
WR Buffer # w/Data and Load DAC A
X
WR Buffer A w/Power-Down Command and LOAD DAC A
(DAC A Powered Down)
X
WR Buffer B w/Power-Down Command and LOAD DAC A
Data
WR Buffer # w/Data and Load DAC B
Data
WR Buffer # w/Data and Load DACs A and B
Table 2. Power-Down Commands
14
D17
D16
PD1
PD0
0
1
1kΩ
1
0
100kΩ
1
1
High Impedance
OUTPUT IMPEDANCE POWER DOWN COMMANDS
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SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the
addressed DAC register is updated on the 24th
falling edge. However, if SYNC is brought HIGH
before the 24th falling edge, it acts as an interrupt to
the write sequence; the shift register is reset and the
write sequence is discarded. Neither an update of
the data buffer contents, DAC register contents nor a
change in the operating mode occurs, as shown in
Figure 45.
POWER-ON RESET
3V). Not only does the supply current fall, but the
output stage is also internally switched from the
output of the amplifier to a resistor network of known
values. This configuration has the advantage that the
output impedance of the device is known while it is in
power-down mode. There are three different options
for power-down: The output is connected internally to
GND through a 1kΩ resistor, a 100kΩ resistor, or it is
left open-circuited (High-Impedance). The output
stage is illustrated in Figure 44.
Table 3. Operating Modes
PD1 (DB17)
PD0 (DB16)
0
0
Normal Operation
—
—
Power-down modes
0
1
Output typically 1kΩ to GND
1
0
Output typically 100kΩ to GND
1
1
High impedance
The DAC8552 contains a power-on reset circuit that
controls the output voltage during power-up. Upon
power-up, the DAC registers are filled with zeros and
the output voltages are set to zero-scale; they
remain that way until a valid write sequence and load
command are made to the respective DAC channel.
The power-on reset is useful in applications where it
is important to know the state of the output of each
DAC output while the device is in the process of
powering up.
Resistor
String
DAC
OPERATING MODE
Amplifier
VOUTA,B
No device pin should be brought high before power
is applied to the device.
Power-Down
Circuitry
POWER-DOWN MODES
The DAC8552 usees four modes of operation. These
modes are accessed by setting two bits (PD1 and
PD0) in the control register to one or both DACs.
Table 3 shows how the state of the bits correspond
to the register and perform a mode of operation on
each channel of the device. (Each DAC channel can
be powered down simultaneously or independently of
each other. Power-down occurs after proper data is
written into PD0 and PD1 and a Load command
occurs.) See the Operation Examples section for
additional information.
When both bits are set to '0', the device works
normally with a typical power consumption of 450µA
at 5V. For the three power-down modes, however,
the supply current falls to 700nA at 5V (400nA at
Figure 44. Output Stage During Power-Down
(High Impedance)
All analog circuitry is shut down when the
power-down mode is activated. Each DAC will exit
power-down when PD0 and PD1 are set to '0', new
data is written to the Data Buffer, and the DAC
channel receives a Load command. The time to exit
power-down is typically 2.5µs for VDD = 5V and 5µs
for VDD = 3V (see the Typical Characteristics).
24th Falling Edge
SCLK
1
2
Resistor
Network
1
24th Falling Edge
2
SYNC
Invalid Write - Sync Interrupt:
SYNC HIGH Before 24th Falling Edge
DIN
DB23 DB22
DB0
Valid Write - Buffer/DAC Update:
SYNC HIGH After 24th Falling Edge
DB23 DB22
DB1 DB0
Figure 45. Interrupt and Valid SYNC Timing
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OPERATION EXAMPLES
Example 1: Write to Data Buffer A Through Buffer B; Load DAC A Through DAC B Simultaneously
• 1st — Write to Data Buffer A:
•
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
DB15
—
DB1
DB0
0
0
0
0
X
0
0
0
D15
—
D1
D0
2nd — Write to Data Buffer B and Load DAC A and DAC B simultaneously:
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
DB15
—
DB1
DB0
0
0
1
1
X
1
0
0
D15
—
D1
D0
The DAC A and DAC B analog outputs simultaneously settle to the specified values upon completion of the 2nd
write sequence. (The Load command moves the digital data from the data buffer to the DAC register at which
time the conversion takes place and the analog output is updated. Completion occurs on the 24th falling SCLK
edge after SYNC LOW.)
Example 2: Load New Data to DAC A and DAC B Sequentially
• 1st — Write to Data Buffer A and Load DAC A: DAC A output settles to specified value upon completion:
•
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
DB15
—
DB1
DB0
0
0
0
1
X
0
0
0
D15
—
D1
D0
2nd — Write to Data Buffer B and Load DAC B: DAC B output settles to specified value upon completion:
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
DB15
—
DB1
DB0
0
0
1
0
X
1
0
0
D15
—
D1
D0
After completion of the 1st write cycle, the DAC A analog output settles to the voltage specified; upon
completion of write cycle 2, the DAC B analog output settles.
Example 3: Power-Down DAC A to 1kΩ and Power-Down DAC B to 100kΩ Simultaneously
• 1st — Write power-down command to Data Buffer A:
•
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
0
0
0
0
X
0
0
1
DB15
—
DB1
DB0
Don't Care
2nd — Write power-down command to Data Buffer B and Load DAC A and DAC B simultaneously:
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
0
0
1
1
X
1
1
0
DB15
—
DB1
DB0
Don't Care
The DAC A and DAC B analog outputs simultaneously power-down to each respective specified mode upon
completion of the 2nd write sequence.
Example 4: Power-Down DAC A and DAC B to High-Impedance Sequentially:
• 1st — Write power-down command to Data Buffer A and Load DAC A: DAC A output = Hi-Z:
•
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
0
0
0
1
X
0
1
1
DB15
—
DB1
DB0
Don't Care
2nd — Write power-down command to Data Buffer B and Load DAC B: DAC B output = Hi-Z:
Reserved
Reserved
LDB
LDA
DC
Buffer Select
PD1
PD0
0
0
1
0
X
1
1
1
DB15
—
DB1
DB0
Don't Care
The DAC A and DAC B analog outputs sequentially power-down to high-impedance upon completion of the 1st
and 2nd write sequences, respectively.
16
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MICROPROCESSOR INTERFACING
DAC8552 to 8051 INTERFACE
DAC8552 to 68HC11 INTERFACE
Figure 46 shows a serial interface between the
DAC8552 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8552, while RXD
drives the serial data line of the device. The SYNC
signal is derived from a bit-programmable pin on the
port of the 8051. In this case, port line P3.3 is used.
When data are to be transmitted to the DAC8552,
P3.3 is taken LOW. The 8051 transmits data in 8-bit
bytes; thus, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is
left LOW after the first eight bits are transmitted, then
a second and third write cycle are initiated to
transmit the remaining data. P3.3 is taken HIGH
following the completion of the third write cycle. The
8051 outputs the serial data in a format that presents
the LSB first, while the DAC8552 requires its data
with the MSB as the first bit received. The 8051
transmit routine must therefore take this into account,
and mirror the data as needed
Figure 48 shows a serial interface between the
DAC8552 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8552, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
80C51/80L51(1)
DAC8552(1)
P3.3
SYNC
TXD
SCLK
RXD
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 46. DAC8552 to 80C51/80L51 Interface
68HC11(1)
DAC8552(1)
PC7
SYNC
SCK
SCLK
MOSI
DIN
NOTE: (1) Additional pins omitted for clarity.
Figure 48. DAC8552 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCK. When data are
being transmitted to the DAC, the SYNC line is held
LOW (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8552, PC7 is left LOW after the first eight bits
are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
DAC8552 to Microwire INTERFACE
DAC8552 to TMS320 DSP INTERFACE
Figure 47 shows an interface between the DAC8552
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
clocked into the DAC8552 on the rising edge of the
SK signal.
Figure 49 shows the connections between the
DAC8552 and a TMS320 digital signal processor. By
decoding the FSX signal, multiple DAC8552s can be
connected to a single serial port of the DSP.
DAC8552
MicrowireTM
VDD
DAC8552(1)
CS
SYNC
SK
SCLK
SO
DIN
NOTE: (1) Additional pins omitted for clarity.
Positive Supply
0.1mF
TMS320 DSP
FSX
DX
CLKX
10mF
SYNC
VOUTA
Output A
VOUTB
Output B
DIN
SCLK
VREF
Figure 47. DAC8552 to Microwire Interface
0.1mF
Reference
Input
1mF to 10mF
GND
Figure 49. DAC8552 to TMS320 DSP
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APPLICATION INFORMATION
CURRENT CONSUMPTION
The DAC8552 typically consumes 170µA at VDD =
5 V and 155µA at VDD = 2.7V for each active
channel, excluding reference current consumption.
Additional current consumption can occur at the
digital inputs if VIH
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