DA
C8
55
DAC8555
5
SLAS475B – NOVEMBER 2005 – REVISED OCTOBER 2006
16-BIT, QUAD CHANNEL, ULTRA-LOW GLITCH, VOLTAGE OUTPUT
DIGITAL-TO-ANALOG CONVERTER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Relative Accuracy: 4LSB
Glitch Energy: 0.15nV-s
MicroPower Operation:
150µA per Channel at 2.7V
Power-On Reset to Zero-Scale or Midscale
Power Supply: +2.7V to +5.5V
16-Bit Monotonic Over Temperature
Settling Time: 10µs to ±0.003% FSR
Ultra-Low AC Crosstalk: –100dB Typ
Low-Power SPI™-Compatible Serial Interface
with Schmitt-Triggered Inputs: Up to 50MHz
On-Chip Output Buffer Amplifier with
Rail-to-Rail Operation
Double Buffered Input Architecture
Simultaneous or Sequential Output Update
and Power-Down
Binary and 2's Complement Capability
Asynchronous Clear to Zero-Scale and
Midscale
1.8V to 5.5V Logic Compatibility
Available in a TSSOP-16 Package
APPLICATIONS
•
•
•
•
•
•
Portable Instrumentation
Closed-Loop Servo-Control
Process Control
Data Acquisition Systems
Programmable Attenuation
PC Peripherals
DESCRIPTION
The DAC8555 is a 16-bit, quad channel, voltage
output digital-to-analog converter (DAC) offering
low-power operation and a flexible serial host
interface. It offers monotonicity, good linearity, and
exceptionally low glitch. Each on-chip precision
output amplifier allows rail-to-rail output swing to be
achieved over the supply range of 2.7V to 5.5V. The
device supports a standard 3-wire serial interface
capable of operating with input data clock
frequencies up to 50MHz for IOVDD = 5V.
The DAC8555 requires an external reference voltage
to set the output range of each DAC channel. Also
incorporated into the device is a power-on reset
circuit, which can be programmed to ensure that the
DAC outputs power up at zero-scale or midscale and
remain there until a valid write takes place. The
device also has the capability to function in both
binary and 2's complement mode. The DAC8555
provides a per channel power-down feature,
accessed over the serial interface, that reduces the
current consumption to 175nA per channel at 5V.
The low-power consumption of this device in normal
operation makes it ideally suited to portable batteryoperated
equipment
and
other
low-power
applications. The power consumption is 5mW at 5V,
reducing to 4µW in power-down mode.
The DAC8555 is available in a TSSOP-16 package
with a specified operating temperature range of
–40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
AVDD
IOVDD
VREFH
Data
Buffer A
DAC
Register A
VOUTA
DAC A
VOUTB
VOUTC
Data
Buffer D
18
SYNC
SCLK
24-Bit
Serial-to-Parallel
Shift Register
8
Buffer
Control
DAC
Register D
Register
Control
Power-Down
Control Logic
Resistor
Network
DIN
RST RSTSEL
LDAC
ENABLE
VOUTD
DAC D
VREFL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI, QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
DAC8555
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SLAS475B – NOVEMBER 2005 – REVISED OCTOBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
PACKAGING/ORDERING INFORMATION (1)
PRODUCT
MAXIMUM
RELATIVE
ACCURACY
(LSB)
MAXIMUM
DIFFERENTIAL
NONLINEARITY
(LSB)
PACKAGELEAD
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
DAC8555
±12
±1
TSSOP-16
PW
–40°C to +105°C
D8555
(1)
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
DAC8555IPW
Tube, 90
DAC8555IPWR
Tape and Reel, 2000
For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
UNIT
AVDD, IOVDD to GND
–0.3V to 6V
Digital input voltage to GND
–0.3V to +AVDD + 0.3V
VO(A) to VO(D) to GND
–0.3V to +AVDD + 0.3V
Operating temperature range
–40°C to +105°C
Storage temperature range
–65°C to +150°C
Junction temperature range (TJ max)
+150°C
Power dissipation
(1)
(TJ max – TA)/θJA
θJA Thermal impedance
118°C/W
θJC Thermal impedance
29°C/W
Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±4
±12
LSB
±0.25
±1
LSB
±2
±12
STATIC PERFORMANCE (1)
Resolution
16
Relative accuracy
Measured by line passing through codes 485 and 64741
Differential nonlinearity
16-bit Monotonic
Zero-scale error
Measured by line passing through codes 485 and 64741
±5
Zero-scale error drift
Full-scale error
Gain error
Measured by line passing through codes 485 and 64741,
(AVDD = 5V, VREF = 4.99V) and (AVDD = 2.7V, VREF = 2.69V)
Power-Supply Rejection Ratio RL = 2kΩ, CL = 200pF
mV
µV/°C
±0.3
±0.5
% of FSR
±0.05
±0.15
% of FSR
ppm of
FSR/°C
±1
Gain temperature coefficient
PSRR
Bits
0.75
mV/V
OUTPUT CHARACTERISTICS (2)
Output voltage range
Output voltage settling time
0
To ±0.003% FSR, 0200h to FD00h, RL = 2kΩ,
0pF < CL < 200pF
RL = 2kΩ, CL = 500pF
Slew rate
Capacitive load stability
(1)
(2)
2
RL = ∞
RL = 2kΩ
Linearity calculated using a reduced code range of 485 to 64741; output unloaded.
Ensured by design and characterization; not production tested.
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8
VREFH
V
10
µs
12
µs
1.8
V/µs
470
pF
1000
pF
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SLAS475B – NOVEMBER 2005 – REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
Code change glitch impulse
TEST CONDITIONS
MIN
1LSB change around major carry
TYP
MAX
0.15
Digital feedthrough
UNIT
nV-s
0.15
DC crosstalk
Full-scale swing on adjacent channel. AVDD = 5V,
VREF = 4.096V
0.25
LSB
AC crosstalk
1kHz sine wave
–100
dB
DC output impedance
At mid-point input
1
Ω
Short-circuit current
Power-up time
AVDD = 5V
50
AVDD = 3V
20
Coming out of power-down mode, AVDD = 5V
2.5
Coming out of power-down mode, AVDD = 3V
5
mA
µs
AC PERFORMANCE
SNR
95
THD
–85
BW = 20kHz, AVDD = 5V, fOUT = 1kHz,
1st 19 harmonics removed for SNR calculation
SFDR
dB
87
SINAD
84
REFERENCE INPUT
VREFH Voltage
VREFL < VREFH, AVDD– (VREFH + VREFL) /2 > 1.2V
0
AVDD
VREFL Voltage
VREFL < VREFH, AVDD– (VREFH + VREFL) /2 > 1.2V
0
AVDD/2
V
Reference input current
Reference input impedance
V
VREFL = GND, VREFH = AVDD = 5V
180
250
µA
VREFL = GND, VREFH = AVDD = 3V
120
200
µA
VREFL < VREFH
31
kΩ
LOGIC INPUTS (3)
VIL
Logic input LOW voltage
VIH
Logic input HIGH voltage
2.7V ≤ IOVDD ≤ 5.5V
0.3 × IOVDD
1.8V ≤ IOVDD ≤ 2.7V
0.1 × IOVDD
2.7 ≤ IOVDD ≤ 5.5V
0.7 × IOVDD
1.8 ≤ IOVDD < 2.7V
0.95 × IOVDD
V
V
Pin capacitance
3
pF
POWER REQUIREMENTS
AVDD
2.7
5.5
IOVDD
1.8
5.5
IDD (normal mode)
Input code = 32768, no load, reference current not included
IOIDD
AVDD = 3.6V to 5.5V
V
VIH = IOVDD and VIL = GND
AVDD = 2.7V to 3.6V
10
20
0.65
0.95
0.6
0.9
0.7
2
0.4
2
µA
mA
IDD (all power-down modes)
AVDD = 3.6V to 5.5V
VIH = IOVDD and VIL = GND
AVDD = 2.7V to 3.6V
µA
POWER EFFICIENCY
IOUT/IDD
IL = 2mA, AVDD = 5V
89
%
TEMPERATURE RANGE
Specified performance
(3)
–40
+105
°C
Ensured by design and characterization; not production tested.
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SLAS475B – NOVEMBER 2005 – REVISED OCTOBER 2006
PIN CONFIGURATION
VOUTA
1
16 LDAC
VOUTB
2
15 ENABLE
VREFH
3
14 RSTSEL
AVDD
4
13 RST
DAC8555
VREFL
5
12
IOVDD
GND
6
11
DIN
VOUTC
7
10 SCLK
VOUTD
8
9
SYNC
PIN DESCRIPTIONS
4
PIN
NAME
DESCRIPTION
1
VOUTA
Analog output voltage from DAC A.
2
VOUTB
Analog output voltage from DAC B.
3
VREFH
Positive reference voltage input.
4
AVDD
Power supply input, 2.7V to 5.5V.
5
VREFL
Negative reference voltage input.
6
GND
Ground reference point for all circuitry on the device.
7
VOUTC
Analog output voltage DAC C.
8
VOUTD
Analog output voltage DAC D.
9
SYNC
Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When
SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th clock (unless SYNC is taken HIGH before this edge,
in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the
DAC8555). Schmitt-Trigger logic input.
10
SCLK
Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input.
11
DIN
12
IOVDD
13
RST
Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock
input. Schmitt-Trigger logic input.
Digital input-output power supply
Asynchronous reset. Active low. If RST is low, all DAC channels reset either to zero-scale (RSTSEL = 0) or
to midscale (RSTSEL = 1).
14
RSTSEL
Reset select. If RSTSEL is low, input coding is binary; if high = 2's complement.
15
ENABLE
Active LOW, ENABLE LOW connects the SPI interface to the serial port.
16
LDAC
Load DACs, rising edge triggered loads all DAC registers.
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SLAS475B – NOVEMBER 2005 – REVISED OCTOBER 2006
SERIAL WRITE OPERATION
t9
t1
SCLK
1
24
t8
t2
t3
t4
t7
SYNC
t6
t5
DIN
DB23
DB0
DB23
t10
RST
TIMING REQUIREMENTS (1) (2)
AVDD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
t1 (3)
SCLK cycle time
t2
SCLK HIGH time
t3
SCLK LOW time
t4
SYNC falling edge to SCLK rising edge setup time
t5
Data setup time
t6
Data hold time
t7
24th SCLK falling edge to SYNC rising edge
t8
Minimum SYNC HIGH time
t9
24th SCLK falling edge to SYNC falling edge
t10
Miniumum RST low time
(1)
(2)
(3)
MIN
IOVDD = AVDD = 2.7V to 3.6V
40
IOVDD = AVDD = 3.6V to 5.5V
20
IOVDD = AVDD = 2.7V to 3.6V
20
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
20
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
0
IOVDD = AVDD = 3.6V to 5.5V
0
IOVDD = AVDD = 2.7V to 3.6V
5
IOVDD = AVDD = 3.6V to 5.5V
5
IOVDD = AVDD = 2.7V to 3.6V
4.5
IOVDD = AVDD = 3.6V to 5.5V
4.5
IOVDD = AVDD = 2.7V to 3.6V
0
IOVDD = AVDD = 3.6V to 5.5V
0
IOVDD = AVDD = 2.7V to 3.6V
40
IOVDD = AVDD = 3.6V to 5.5V
20
IOVDD = AVDD = 2.7V to 5.5V
130
IOVDD = AVDD = 2.7V to 3.5V
40
IOVDD = AVDD = 3.6V to 5.5V
20
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
All input signals are specified with tR = tF = 3ns (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2.
See Serial Write Operation timing diagram.
Maximum SCLK frequency is 50MHz at IOVDD = AVDD = 3.6V to 5.5V and 25 MHz at IOVDD = AVDD = 2.7V to 3.6V.
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TYPICAL CHARACTERISTICS: VDD = 5V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
LE (LSB)
1.0
1.0
0.5
0.5
0
-0.5
-1.0
8
6
4
2
0
-2
-4
-6
-8
0
-0.5
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
16384 24576 32768 40960 49152
Digital Input Code
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
8
6
4
2
0
-2
-4
-6
-8
VDD = 5V, VREF = 4.99V
LE (LSB)
Channel C
VDD = 5V, VREF = 4.99V
Channel D
1.0
0.5
0
-0.5
-1.0
0.5
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Figure 3.
Figure 4.
ZERO-SCALE ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
57344 65536
0
5.0
VDD = 5V
VREF = 4.99V
AVDD = 5V, VREF = 4.99V
CH C
-5
Error (mV)
2.5
CH A
0
CH D
-10
CH C
-15
CH A
CH B
-2.5
CH D
-20
CH B
-25
-5.0
-40
6
57344 65536
Figure 2.
DLE (LSB)
DLE (LSB)
8192
Figure 1.
1.0
Error (mV)
VDD = 5V, VREF = 4.99V
Channel B
-1.0
0
LE (LSB)
8
6
4
2
0
-2
-4
-6
-8
VDD = 5V, VREF = 4.99V
Channel A
DLE (LSB)
DLE (LSB)
LE (LSB)
8
6
4
2
0
-2
-4
-6
-8
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
0
40
80
120
-40
0
40
Temperature (°C)
Temperature (°C)
Figure 5.
Figure 6.
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80
120
DAC8555
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SLAS475B – NOVEMBER 2005 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
SOURCE CURRENT CAPABILITY (ALL CHANNELS)
6.0
2000
5.6
1600
TA = +25°C, SYNC Input (All other inputs = GND)
CH A Powered Up (All other channels in powerdown)
Reference Current Included
5.2
IDD (mA)
VOUT (V)
IOVDD = AVDD = VREF = 5V
4.8
4.4
AVDD = 5.5V
VREF = AVDD - 10mV
DAC Loaded with FFFFh
1200
800
400
4.0
0
0
2
4
6
8
10
0
1
2
ISOURCE (mA)
Figure 8.
POWER SPECTRAL DENSITY
TOTAL HARMONIC DISTORTION
vs OUTPUT FREQUENCY
-50
-70
-40
-60
-70
THD
-90
-80
-110
-90
-130
-100
2nd Harmonic
5k
10k
5
AVDD = VREF = 5V
-1dB FSR Digital Input
fS = 1MSPS
Measurement Bandwidth = 20kHz
-50
THD (dB)
AVDD = 5V
VREF = 4.096V
fCLK = 1MSPS
fOUT = 1kHz
THD = 79dB
SNR = 96dB
-30
Gain (dB)
4
Figure 7.
-10
0
3
VLOGIC (V)
15k
20k
0
1
3rd Harmonic
2
3
4
5
Frequency (Hz)
fOUT (kHz)
Figure 9.
Figure 10.
FULL-SCALE SETTLING TIME: 5V RISING EDGE
FULL-SCALE SETTLING TIME: 5V FALLING EDGE
Trigger Pulse: 5V/div
Trigger Pulse: 5V/div
AVDD = 5V,
VREF = 4.096V,
From Code: FFFF
To Code: 0000
AVDD = 5V,
VREF = 4.096V,
From Code: 0000
To Code: FFFF
Rising
Edge
1V/div
Zoomed Rising Edge
1mV/div
Falling
Edge
1V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
HALF-SCALE SETTLING TIME: 5V RISING EDGE
HALF-SCALE SETTLING TIME: 5V FALLING EDGE
Trigger Pulse: 5V/div
Rising
Edge
1V/div
Trigger Pulse: 5V/div
AVDD = 5V,
VREF = 4.096V,
From Code: CFFF
To Code: 4000
AVDD = 5V,
VREF = 4.096V,
From Code: 4000
To Code: CFFF
Falling
Edge
1V/div
Zoomed Rising Edge
1mV/div
8
Time (2ms/div)
Figure 14.
GLITCH ENERGY: 5V, 1LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 1LSB STEP, FALLING EDGE
VOUT (500mV/div)
Figure 13.
AVDD = 5V,
VREF = 4.096V,
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
AVDD = 5V,
VREF = 4.096V,
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 15.
Figure 16.
GLITCH ENERGY: 5V, 16LSB STEP, RISING EDGE
GLITCH ENERGY: 5V, 16LSB STEP, FALLING EDGE
AVDD = 5V,
VREF = 4.096V,
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
VOUT (500mV/div)
VOUT (500mV/div)
VOUT (500mV/div)
Time (2ms/div)
Zoomed Falling Edge
1mV/div
AVDD = 5V,
VREF = 4.096V,
From Code: 8010
To Code: 8000
Glitch: 0.08nV-s
Time (400ns/div)
Time (400ns/div)
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS: VDD = 5V (continued)
At TA = +25°C, unless otherwise noted.
GLITCH ENERGY: 5V, 256LSB STEP, FALLING EDGE
AVDD = 5V,
VREF = 4.096V,
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 19.
Figure 20.
OUTPUT NOISE DENSITY
SIGNAL-TO-NOISE RATIO
vs OUTPUT FREQUENCY
350
98
AVDD = 5V
VREF = 4.096V
Code = 7FFF
No Load
300
AVDD = VREF = 5V
-1dB FSR Digital Inputs
fS = 1MSPS
Measurement Bandwidth = 20kHz
96
94
250
SNR (dB)
Noise (nV/ÖHz)
AVDD = 5V,
VREF = 4.096V,
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
VOUT (5mV/div)
VOUT (5mV/div)
GLITCH ENERGY: 5V, 256LSB STEP, RISING EDGE
200
92
90
88
150
86
100
100
84
1k
10k
100k
0
Frequency (Hz)
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
fOUT (kHz)
Figure 21.
Figure 22.
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TYPICAL CHARACTERISTICS: VDD = 2.7V
At TA = +25°C, unless otherwise noted.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
8
6
4
2
0
-2
-4
-6
-8
VDD = 2.7V, VREF = 2.69V
Channel A
LE (LSB)
LE (LSB)
8
6
4
2
0
-2
-4
-6
-8
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
1.0
DLE (LSB)
DLE (LSB)
1.0
0.5
0
-0.5
-1.0
8
6
4
2
0
-2
-4
-6
-8
8192
16384 24576 32768 40960 49152
Digital Input Code
0
-0.5
57344 65536
0
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
Figure 24.
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR
vs DIGITAL INPUT CODE
8
6
4
2
0
-2
-4
-6
-8
VDD = 2.7V, VREF = 2.69V
LE (LSB)
Channel C
1.0
1.0
0.5
0.5
0
-0.5
-1.0
VDD = 2.7V, VREF = 2.69V
Channel D
0
-0.5
-1.0
0
8192
16384 24576 32768 40960 49152
Digital Input Code
57344 65536
0
8192
16384 24576 32768 40960 49152
Digital Input Code
Figure 25.
Figure 26.
ZERO-SCALE ERROR
vs TEMPERATURE
FULL-SCALE ERROR
vs TEMPERATURE
57344 65536
0
5.0
VDD = 2.7V
VREF = 2.69V
AVDD = 2.7V, VREF = 2.69V
-5
Error (mV)
CH C
2.5
Error (mV)
8192
Figure 23.
DLE (LSB)
LE (LSB)
DLE (LSB)
0.5
-1.0
0
CH A
0
CH D
CH B
-2.5
CH C
CH A
-10
CH D
CH B
-15
-20
-25
-5.0
-40
10
VDD = 2.7V, VREF = 2.69V
Channel B
0
40
80
120
-40
0
40
Temperature (°C)
Temperature (°C)
Figure 27.
Figure 28.
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TYPICAL CHARACTERISTICS: VDD = 2.7V (continued)
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs LOGIC INPUT VOLTAGE
SOURCE CURRENT CAPABILITY (ALL CHANNELS)
3.0
800
TA = +25°C, SYNC Input (All other inputs = GND)
CH A Powered Up (All other channels in powerdown)
Reference Current Included
2.7
600
IDD (mA)
VOUT (V)
IOVDD = AVDD = VREF = 2.7V
2.4
2.1
1.8
400
200
AVDD = 2.7V
VREF = AVDD - 10mV
DAC Loaded with FFFFh
1.5
0
0
2
4
6
8
10
0
0.5
1.0
1.5
2.0
2.5 2.7
ISOURCE (mA)
VLOGIC (V)
Figure 29.
Figure 30.
FULL-SCALE SETTLING TIME: 2.7V RISING EDGE
FULL-SCALE SETTLING TIME: 2.7V FALLING EDGE
Trigger Pulse: 2.7V/div
Rising
Edge
0.5V/div
Trigger Pulse: 2.7V/div
AVDD = 2.7V,
VREF = 2.5V,
From Code: 0000
To Code: FFFF
Zoomed Rising Edge
1mV/div
AVDD = 2.7V,
VREF = 2.5V,
From Code: FFFF
To Code: 0000
Falling
Edge
0.5V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 31.
Figure 32.
HALF-SCALE SETTLING TIME: 2.7V RISING EDGE
HALF-SCALE SETTLING TIME: 2.7V FALLING EDGE
Trigger Pulse: 2.7V/div
Trigger Pulse: 2.7V/div
AVDD = 2.7V,
VREF = 2.5V,
From Code: CFFF
To Code: 4000
AVDD = 2.7V,
VREF = 2.5V,
From Code: 4000
To Code: CFFF
Rising
Edge
0.5V/div
Zoomed Rising Edge
1mV/div
Falling
Edge
0.5V/div
Time (2ms/div)
Zoomed Falling Edge
1mV/div
Time (2ms/div)
Figure 33.
Figure 34.
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TYPICAL CHARACTERISTICS: VDD = 2.7V (continued)
At TA = +25°C, unless otherwise noted.
VOUT (200mV/div)
AVDD = 2.7V,
VREF = 2.5V,
From Code: 7FFF
To Code: 8000
Glitch: 0.08nV-s
AVDD = 2.7V,
VREF = 2.5V,
From Code: 8000
To Code: 7FFF
Glitch: 0.16nV-s
Measured Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 35.
Figure 36.
GLITCH ENERGY: 2.7V, 16LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 16LSB STEP, FALLING EDGE
AVDD = 2.7V,
VREF = 2.5V,
From Code: 8000
To Code: 8010
Glitch: 0.04nV-s
AVDD = 2.7V,
VREF = 2.5V,
From Code: 8010
To Code: 8000
Glitch: 0.12nV-s
Time (400ns/div)
Figure 37.
Figure 38.
GLITCH ENERGY: 2.7V, 256LSB STEP, RISING EDGE
GLITCH ENERGY: 2.7V, 256LSB STEP, FALLING EDGE
AVDD = 2.7V,
VREF = 2.5V,
From Code: 8000
To Code: 80FF
Glitch: Not Detected
Theoretical Worst Case
VOUT (5mV/div)
Time (400ns/div)
VOUT (5mV/div)
12
GLITCH ENERGY: 2.7V, 1LSB STEP, FALLING EDGE
VOUT (200mV/div)
VOUT (200mV/div)
VOUT (200mV/div)
GLITCH ENERGY: 2.7V, 1LSB STEP, RISING EDGE
AVDD = 2.7V,
VREF = 2.5V,
From Code: 80FF
To Code: 8000
Glitch: Not Detected
Theoretical Worst Case
Time (400ns/div)
Time (400ns/div)
Figure 39.
Figure 40.
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TYPICAL CHARACTERISTICS: VDD = 5V and 2.7V
At TA = +25°C, unless otherwise noted.
SUPPLY CURRENT
vs DIGITAL INPUT CODE
SINK CURRENT CAPABILITY (ALL CHANNELS)
0.150
1200
VREF = AVDD - 10mV
DAC Loaded with 0000h
Reference Current Included
1000
0.125
800
IDD (mA)
VOUT (V)
AVDD = VREF = 5V
VDD = 2.7V
0.100
VDD = 5.5V
0.075
600
AVDD = VREF = 2.7V
0.050
400
0.025
200
0
0
0
2
4
6
8
0
10
8192 16384 24576 32768 40960 49152 57344 65535
Digital Input Code
ISINK (mA)
Figure 41.
Figure 42.
SUPPLY CURRENT
vs FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs SUPPLY VOLTAGE
1200
900
VREF = AVDD, All DACs Powered,
Reference Current Included, No Load
Reference Current Included
1000
850
AVDD = VREF = 5V
800
IDD (mA)
IDD (mA)
800
AVDD = VREF = 2.7V
600
750
400
700
200
650
0
-40
600
0
40
80
120
2.7
3.05
3.4
3.75
4.1
4.45
Temperature (°C)
AVDD (V)
Figure 43.
Figure 44.
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5.15
5.5
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THEORY OF OPERATION
DAC SECTION
VREFH
The architecture of each channel of the DAC8555
consists of a resistor-string DAC followed by an
output buffer amplifier. Figure 45 shows a simplified
block diagram of the DAC architecture.
VREFH
50kW
RDIVIDER
VREF
2
50kW
R
62kW
VOUT
REF(+)
Resistor String
REF(-)
DAC
Register
R
To Output Amplifier
(2x Gain)
VREFL
Figure 45. DAC8555 Architecture
The input coding for each device can be 2's
complement or unipolar straight binary, so the ideal
output voltage is given by:
V
OUT
X+2
V
REF
ǒ
L) V
REF
H*V
REF
Ǔ
L
R
D
IN
65536
where DIN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from
0 to 65535.
RESISTOR STRING
VREFL
The resistor string section is shown in Figure 46. It is
simply a divide-by-2 resistor followed by a string of
resistors. The code loaded into the DAC register
determines at which node on the string the voltage is
tapped off. This voltage is then applied to the output
amplifier by closing one of the switches connecting
the string to the amplifier.
OUTPUT AMPLIFIER
Each output buffer amplifier is capable of generating
rail-to-rail voltages on its output that approaches an
output range of 0V to AVDD (gain and offset errors
must be taken into account). Each buffer is capable
of driving a load of 2kΩ in parallel with 1000pF to
GND. The source and sink capabilities of the output
amplifier can be seen in the Typical Characteristics.
SERIAL INTERFACE
The DAC8555 uses a 3-wire serial interface (SYNC,
SCLK, and DIN), which is compatible with SPI,
QSPI™, and Microwire™ interface standards, as well
as most DSPs. See the Serial Write Operation timing
diagram for an example of a typical write sequence.
14
R
Figure 46. Resistor String
The write sequence begins by bringing the SYNC
line LOW. Data from the DIN line are clocked into the
24-bit shift register on each falling edge of SCLK.
The serial clock frequency can be as high as 50MHz,
making the DAC8555 compatible with high-speed
DSPs. On the 24th falling edge of the serial clock,
the last data bit is clocked into the shift register and
the shift register gets locked. Further clocking does
not change the shift register data. Once 24 bits are
locked into the shift register, the eight MSBs are
used as control bits and the 16 LSBs are used as
data. After receiving the 24th falling clock edge, the
DAC8555 decodes the eight control bits and 16 data
bits to perform the required function, without waiting
for a SYNC rising edge. A new SPI sequence starts
at the next falling edge of SYNC. A rising edge of
SYNC before the 24-bit sequence is complete resets
the SPI interface; no data transfer occurs.
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After the 24th falling edge of SCLK is received, the
SYNC line may be kept LOW or brought HIGH. In
either case, the minimum delay time from the 24th
falling SCLK edge to the next falling SYNC edge
must be met in order to properly begin the next
cycle.
To assure the lowest power consumption of the
device, care should be taken that the levels are as
close to each rail as possible. (Refer to the Typical
Characteristics section for Figure 41, the Supply
Current vs Logic Input Voltage transfer characteristic
curve.)
IOVDD AND VOLTAGE TRANSLATORS
The IOVDD pin powers the the digital input structures
of the DAC8555. For single-supply operation, it can
be tied to AVDD. For dual-supply operation, the
IOVDD pin provides interface flexibility with various
CMOS logic families and should be connected to the
logic supply of the system. Analog circuits and
internal logic of the DAC8555 use AVDD as the
supply voltage. The external logic high inputs get
translated to AVDD by level shifters. These level
shifters use the IOVDD voltage as a reference to shift
the incoming logic HIGH levels to AVDD. IOVDD is
ensured to operate from 2.7V to 5.5V regardless of
the AVDD voltage, which ensures compatibility with
various logic families. Although specified down to
2.7V, IOVDD will operate at as low as 1.8V with
degraded timing and temperature performance. For
lowest power consumption, logic VIH levels should be
as close as possible to IOVDD, and logic VIL levels
should be as close as possible to GND voltages.
ASYNCHRONOUS CLEAR
The DAC8555 output is asynchronously set to
zero-scale voltage or midscale voltage (depending
on RSTSEL) immediately after the RST pin is
brought low. The RST signal resets all internal
registers, and therefore, behaves like the Power-On
Reset. The RST pin must be brought back to high
before a write sequence is started.
If the RSTSEL pin is high, RST signal going low
resets all outputs to midscale. If the RSTSEL pin is
low, RST signal going low resets all outputs to
zero-scale. RSTSEL should be set at power up.
INPUT SHIFT REGISTER
The input shift register (SR) of the DAC8555 is 24
bits wide, as shown in Figure 47, and is made up of
eight control bits (DB23–DB16) and 16 data bits
(DB15–DB0). DB23 and DB22 should always be '0'.
LD1 (DB21) and LD0 (DB20) control the updating of
each analog output with the specified 16-bit data
value or power-down command. Bit DB19 is a don't
care bit that does not affect the operation of the
DAC8555, and can be '1' or '0'. The DAC channel
select bits (DB18, DB17) control the destination of
the data (or power-down command) from DAC A
through DAC D. The final control bit, PD0 (DB16),
selects the power-down mode of the DAC8555
channels.
DB23
0
DB12
0
LD1
LD0
X
DAC Select 1
DAC Select 0
PD0
D15
D14
D13
DB11
D11
D12
DB0
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 47. DAC8555 Data Input Register Format
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The DAC8555 also supports a number of different
load commands. The load commands can be
summarized as follows:
DB16 is a power-down flag. If this flag is set, then
DB15 and DB14 select one of the four power-down
modes of the device as described in Table 1. If DB16
= 1, DB15 and DB14 no longer represent the two
MSBs of data, but represent a power-down condition
described in Table 1. Similar to data, power-down
conditions can be stored at the temporary registers
of each DAC. It is possible to update DACs
simultaneously either with data, power-down, or a
combination of both.
DB21 = 0 and DB20 = 0: Single-channel store.
The temporary register (data buffer) corresponding to
a DAC selected by DB18 and DB17 is updated with
the contents of SR data (or power-down).
DB21 = 0 and DB20 = 1: Single-channel update.
The temporary register and DAC register
corresponding to a DAC selected by DB18 and DB17
are updated with the contents of SR data (or
power-down).
Refer to Table 2 for more information.
Table 1. DAC8555 Power-Down Modes
DB21 = 1 and DB20 = 0: Simultaneous update. A
channel selected by DB18 and DB17 gets updated
with the SR data, and simultaneously, all the other
channels get updated with previous stored data (or
power-down) from temporary registers.
PD0
PD1
PD2
(DB16) (DB15) (DB14)
DB21 = 1 and DB20 = 1: Broadcast update. If
DB18 = 0, then SR data gets ignored, all channels
get updated with previously stored data (or
power-down). If DB18 = 1, then SR data (or
power-down) updates all channels.
OPERATING MODE
1
0
0
Output high impedance
1
0
1
Output typically 1kΩ to GND
1
1
0
Output typically 100kΩ to GND
1
1
1
Output high impedance
Power-down/data selection is as follows:
Table 2. Control Matrix
DB23
0
DB22
0
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13-DB0
LD 1
LD 0
Don't
Care
DAC Sel 1
DAC Sel 0
PD0
MSB
MSB-1
MSB-2...LSB
0
0
X
0
0
0
Data
Write to buffer A with data
0
0
X
0
1
0
Data
Write to buffer B with data
0
0
X
1
0
0
Data
Write to buffer C with data
0
0
X
1
1
0
Data
Write to buffer D with data
0
0
X
(00, 01, 10, or 11)
1
0
1
X
(00, 01, 10, or 11)
0
0
1
X
(00, 01, 10, or 11)
1
1
0
X
(00, 01, 10, or 11)
0
1
0
X
(00, 01, 10, or 11)
1
See Table 1
0
0
Write to buffer with power-down command and load
DAC (selected by DB17 and DB18)
Write to buffer with data (selected by DB17 and DB18)
and then load all DACs simultaneously from their
corresponding buffers.
Data
See Table 1
Write to buffer (selected by DB17 and DB18) with
power-down command
Write to buffer with data and load DAC (selected by
DB17 and DB18)
Data
See Table 1
DESCRIPTION
0
Write to buffer with power-down command (selected by
DB17 and DB18) and then load all DACs
simultaneously from their corresponding buffers.
Broadcast Modes
16
X
X
1
1
X
X
X
1
1
X
X
X
1
1
X
0
X
X
1
X
0
1
X
1
Simultaneously update all channels of DAC8555 with
data stored in each channels temporary register.
X
Data
See Table 1
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Write to all channels and load all DACs with SR data
0
Write to all channels and load all DACs with
power-down command in SR.
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SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept
LOW for at least 24 falling edges of SCLK and the
addressed DAC register is updated on the 24th
falling edge. However, if SYNC is brought HIGH
before the 24th falling edge, it acts as an interrupt to
the write sequence; the shift register is reset and the
write sequence is discarded. Neither an update of
the data buffer contents, DAC register contents, nor
a change in the operating mode occurs (see
Figure 48).
POWER-ON RESET TO
ZERO-SCALE/MIDSCALE
The DAC8555 contains a power-on reset circuit that
controls the output voltage during power-up.
Depending on RSTSEL signal, on power-up, the
DAC registers are reset and the output voltages are
set to zero-scale (RSTSEL = 0) or midscale
(RSTSEL = 1); they remain that way until a valid
write sequence and load command are made to the
respective DAC channel. The power-on reset is
useful in applications where it is important to know
the state of the output of each DAC while the device
is in the process of powering up.
24th Falling Edge
SCLK
1
2
1
24th Falling Edge
2
SYNC
Invalid Write-Sync Interrupt:
SYNC HIGH Before 24th Falling Edge
DIN
DB23 DB22
DB0
Valid Write-Buffer/DAC Update:
SYNC HIGH After 24th Falling Edge
DB23 DB22
DB1 DB0
Figure 48. Interrupt and Valid SYNC Timing
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POWER-DOWN MODES
The DAC8555 uses four modes of operation. These
modes are accessed by setting three bits (PD2, PD1,
and PD0) in the shift register and performing a Load
action to the DACs. The DAC8555 offers a very
flexible power-down interface based on channel
register operation. A channel consists of a single
16-bit DAC with power-down circuitry, a temporary
storage register (TR), and a DAC register (DR). TR
and DR are both 18 bits wide. Two MSBs represent
a power-down condition and 16 LSBs represent data
for TR and DR. By adding bits 17 and 18 to TR and
DR, a power-down condition can be temporarily
stored and used as data. Internal circuits ensure that
DB15 and DB14 are transferred to TR17 and TR16
(DR17 and DR16), when DB16 = '1'.
The DAC8555 treats the power-down condition as
data; all the operational modes are still valid for
power-down. It is possible to broadcast a
power-down condition to all the DAC8555s in a
system, or it is possible to simultaneously
power-down a channel while updating data on other
channels.
Individual channels can be separately powered
down, reducing the total power consumption. When
all channels are powered down, the DAC8555 power
consumption drops below 2µA. There is no power-up
command. When a channel is updated with data, it
automatically exits power-down. All channels exit
power-down simultaneously after a broadcast data
update. The time to exit power-down is
approximately 5µs. See Table 1 and Table 2 for
power-down operation details.
Resistor
String
DAC
Power-Down
Circuitry
VOUTX
Resistor
Network
Figure 49. Output Stage During Power-Down
(High-Impedance)
DB16, DB15, and DB14 = '100' (or '111') represent a
power-down condition with Hi-Z output impedance
for a selected channel. '101' represents a
power-down condition with 1kΩ output impedance
and '110' represents a power-down condition with
100kΩ output impedance.
18
Amplifier
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OPERATION EXAMPLES
Example 1: Write to Data Buffer A Through Buffer D; Load DAC A Through DAC D Simultaneously
• 1st — Write to data buffer A:
•
•
•
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
—
DB1
DB0
0
0
0
0
X
0
0
0
D15
—
D1
D0
2nd — Write to data buffer B:
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
—
DB1
DB0
0
0
0
0
X
0
1
0
D15
—
D1
D0
3rd — Write to data buffer C:
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
—
DB1
DB0
0
0
0
0
X
1
0
0
D15
—
D1
D0
4th — Write to data buffer D and simultaneously update all DACs:
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
—
DB1
DB0
0
0
1
0
X
1
1
0
D15
—
D1
D0
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the 4th write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling
edge of the 4th write cycle).
Example 2: Load New Data to DAC A Through DAC D Sequentially
• 1st — Write to data buffer A and load DAC A: DAC A output settles to specified value upon completion:
•
•
•
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
—
DB1
DB0
0
0
0
1
X
0
0
0
D15
—
D1
D0
2nd — Write to data buffer B and load DAC B: DAC B output settles to specified value upon completion:
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
—
DB1
DB0
0
0
0
1
X
0
1
0
D15
—
D1
D0
3rd — Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion:
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
—
DB1
DB0
0
0
0
1
X
1
0
0
D15
—
D1
D0
4th — Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion:
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
—
DB1
DB0
0
0
0
1
X
1
1
0
D15
—
D1
D0
After completion of each write cycle, DAC analog output settles to the voltage specified.
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Example 3: Power Down DAC A and DAC B to 1kΩ and Power Down DAC C and DAC D to 100kΩ
Simultaneously
• Write power-down command to data buffer A: DAC A to 1kΩ.
•
•
•
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
DB14
DB13
—
0
0
0
0
X
0
0
1
0
1
X
—
Write power-down command to data buffer B: DAC B to 1kΩ.
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
DB14
DB13
—
0
0
0
0
X
0
1
1
0
1
X
—
Write power-down command to data buffer C: DAC C to 1kΩ.
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
DB14
DB13
—
0
0
0
0
X
1
0
1
1
0
X
—
Write power-down command to data buffer D: DAC D to 100kΩ and simultaneously update all DACs.
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
DB14
DB13
—
0
0
1
0
X
1
1
1
1
0
X
—
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power down to each respective
specified mode upon completion of the 4th write sequence.
Example 4: Power Down DAC A Through DAC D to High-Impedance Sequentially:
• Write power-down command to data buffer A and load DAC A: DAC A output = Hi-Z:
•
•
•
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
DB14
DB13
—
0
0
0
1
X
0
0
1
1
1
X
—
Write power-down command to data buffer B and load DAC B: DAC B output = Hi-Z:
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
DB14
DB13
—
0
0
0
1
X
0
1
1
1
1
x
—
Write power-down command to data buffer C and load DAC C: DAC C output = Hi-Z:
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
DB14
DB13
—
0
0
0
1
X
1
0
1
1
1
X
—
Write power-down command to data buffer D and load DAC D: DAC D output = Hi-Z:
DB23
DB22
LD1
LD0
DC
DAC Sel 1
DAC Sel 0
PD0
DB15
DB14
DB13
—
0
0
0
1
X
1
1
1
1
1
X
—
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power down to high-impedance upon
completion of the 1st, 2nd, 3rd, and 4th write sequences, respectively.
20
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LDAC FUNCTIONALITY
The DAC8555 offers both a software and hardware
simultaneous update function. The DAC8555
double-buffered architecture has been designed so
that new data can be entered for each DAC without
disturbing the analog outputs. The software
simultaneous update capability is controlled by the
load 1 (LD1) and load 0 (LD0) control bits. By setting
load 1 = 1 all of the DAC registers will be updated on
the falling edge of the 24th clock signal. When the
new data has been entered into the device, all of the
DAC outputs can be updated simultaneously and
synchronously with the clock.
DAC8555 data updates are synchronized with the
falling edge of the 24th SCLK cycle, which follows a
falling edge of SYNC. For such synchronous
updates, the LDAC pin is not required and it must be
connected to GND permanently. The LDAC pin is
used as a positive edge triggered timing signal for
asynchronous DAC updates. Data buffers of all
channels must be loaded with desired data before
LDAC is triggered. After a low-to-high LDAC
transition, all DACs are simultaneously updated with
the contents of the corresponding data buffers. If the
contents of a data buffer are not changed by the
serial interface, the corresponding DAC output will
remain unchanged after the LDAC trigger.
ENABLE PIN
For normal operation, the enable pin must be tied to
a logic low. If the enable pin is tied high, the
DAC8555 stops listening to the serial port. This
feature can be useful for applications that share the
same serial port.
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DAC8555
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DAC8555 to 68HC11 Interface
MICROPROCESSOR INTERFACING
DAC8555 to 8051 Interface
See Figure 50 for a serial interface between the
DAC8555 and a typical 8051-type microcontroller.
The setup for the interface is as follows: TXD of the
8051 drives SCLK of the DAC8555, while RXD
drives the serial data line of the device. The SYNC
signal is derived from a bit-programmable pin on the
port of the 8051. In this case, port line P3.3 is used.
When data are to be transmitted to the DAC8555,
P3.3 is taken LOW. The 8051 transmits data in 8-bit
bytes; thus, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is
left LOW after the first eight bits are transmitted, then
a second and third write cycle are initiated to
transmit the remaining data. P3.3 is taken HIGH
following the completion of the third write cycle. The
8051 outputs the serial data in a format that presents
the LSB first, while the DAC8555 requires data with
the MSB as the first bit received. The 8051 transmit
routine must therefore take this into account, and
mirror the data as needed.
80C51/80L51(1)
DAC8555
P3.3
SYNC
TXD
SCLK
RXD
DIN
(1) Additional pins omitted for clarity.
Figure 50. DAC8555 to 80C51/80L51 Interface
DAC8555 to Microwire Interface
Figure 51 shows an interface between the DAC8555
and any Microwire-compatible device. Serial data are
shifted out on the falling edge of the serial clock and
is clocked into the DAC8555 on the rising edge of
the SK signal.
Figure 52 shows a serial interface between the
DAC8555 and the 68HC11 microcontroller. SCK of
the 68HC11 drives the SCLK of the DAC8555, while
the MOSI output drives the serial data line of the
DAC. The SYNC signal is derived from a port line
(PC7), similar to the 8051 diagram.
68HC11(1)
DAC8555
PC7
SYNC
SCK
SCLK
MOSI
DIN
(1) Additional pins omitted for clarity.
Figure 52. DAC8555 to 68HC11 Interface
The 68HC11 should be configured so that its CPOL
bit is '0' and its CPHA bit is '1'. This configuration
causes data appearing on the MOSI output to be
valid on the falling edge of SCLK. When data are
being transmitted to the DAC, the SYNC line is held
LOW (PC7). Serial data from the 68HC11 are
transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. (Data are
transmitted MSB first.) In order to load data to the
DAC8555, PC7 is left LOW after the first eight bits
are transferred, then a second and third serial write
operation are performed to the DAC. PC7 is taken
HIGH at the end of this procedure.
DAC8555 to TMS320 DSP Interface
Figure 53 shows the connections between the
DAC8555 and a TMS320 Digital Signal Processor
(DSP). A single DSP can control up to four
DAC8555s without any interface logic.
DAC8555
Positive Supply
AVDD
0.1mF
MicrowireTM
DAC8555
10mF
TMS320 DSP
CS
SYNC
FSX
SK
SCLK
DX
SO
DIN
CLKX
(1) Additional pins omitted for clarity.
SYNC
DIN
SCLK
VOUTA
Output A
VOUTD
Output D
VREFL
Microwire is a registered trademark of National Semiconductor.
Reference
Input
VREFH
0.1mF
1mF to 10mF
GND
Figure 51. DAC8555 to Microwire Interface
Figure 53. DAC8555 to TMS320 DSP
22
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APPLICATION INFORMATION
CURRENT CONSUMPTION
The DAC8555 typically consumes 208µA at AVDD =
5V and 180µA at AVDD = 3V for each active channel,
including reference current consumption. Additional
current consumption can occur at the digital inputs if
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