DAC8581IPW

Not Recommended For New Designs DA C 858 1 DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 16-BIT, HIGH-SPEED, LOW-NOISE, VOLTAGE OUTPUT DIGITAL-TO-ANALOG CONVERTER Check for Samples: DAC8581 FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • • • • • 1 23 16-Bit Monotonic ±5-V Bipolar Output Very Low Glitch: 0.5 nV-s Fast Settling: 0.65 μs Fast Slew Rate: 35 V/μs Low Noise: 20 nV/√Hz ±25-mA Load Drive ±5-V Dual Power Supply Single External Reference Power-On Reset to Midscale 3-MSPS Update Rate SPI™ Interface, Up to 50 MHz 1.8-V–5-V Logic Compatible Twos Complement Data Format Hardware Reset to Midscale TSSOP-16 Package Industrial Process Control CRT Projection TV Digital Convergence Waveform Generation Automated Test Equipment Ultrasound DESCRIPTION The DAC8581 is a 16-bit, high-speed, low-noise DAC operating from dual ±5-V power supplies. The DAC8581 is monotonic, and has exceptionally low noise and exceptionally low glitch. The DAC8581 high-performance, bipolar output buffer is capable of settling within 0.65 μs for a 10-V step. Small-signal settling time is well under 0.3 μs, supporting data update rates up to 3 MSPS. A power-on-reset circuit sets the output at midscale voltage on power up. The DAC8581 is simple to use, with a single external reference and a standard 3-wire SPI interface that allows clock rates up to 50 MHz. Also see the DAC8580, a member of the same family. The DAC8580 combines DAC8581 performance with an on-chip, 16x over-sampling digital filter. The DAC8581 is specified over the –40°C to +85°C temperature range. space FUNCTIONAL BLOCK DIAGRAM OF DAC8581 AVDD AVSS DVDD GND VREF SDIN SCLK Serial Interface DAC CS Shift Register Latch CLR VOUT DAC Control Logic DAC8581 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2012, Texas Instruments Incorporated Not Recommended For New Designs DAC8581 SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE PACKAGE DRAWING NUMBER DAC8581 TSSOP-16 PW (1) SPECIFICATION TEMPERATURE RANGE PACKAGE ORDERING MARKING –40°C to +85°C D8581I ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DAC8581IPW Tube, 90-Piece DAC8581IPWR Tape and Reel, 2000-Piece For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) UNIT AVDD or DVDD to AVSS –0.3 V to 12 V Digital input voltage to AVSS –0.3 V to 12 V VOUT or VREF to AVSS –0.3 V to 12 V DGND and AGND to AVSS –0.3 V to 6 V Operating temperature range –40°C to +85°C Storage temperature range –65°C to +150°C Junction temperature range (TJ max) Power dissipation (1) 2 +150°C Thermal impedance (θJA) 118°C/W Thermal impedance (θJC) 29°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: DAC8581 Not Recommended For New Designs DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 ELECTRICAL CHARACTERISTICS All specifications at TA = TMIN to TMAX, +AVDD = +5 V, –AVDD = –5 V, DVDD = +5 V (unless otherwise noted). DAC8581 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ±0.03 ±0.1 %FS ±0.25 ±0.5 LSB 2 3 %FS STATIC PERFORMANCE Resolution Linearity error 16 VREF = 4.096 V Differential linearity error Gain error 1 Gain drift Bits ±5 ppm/°C Bipolar zero error –5 Bipolar zero drift ±20 ±25 μV/°C mV Total drift ±10 ppm/°C OUTPUT CHARACTERISTICS Voltage output VREF up to 5.5 V, when AVDD = 6 V, AVSS = –6 V –VREF Output impedance V Ω 1 Maximum output current Settling time VREF ±25 CL < 200 pF, RL = 2 kΩ, to 0.1% FS, 8-V step mA 0.65 To 0.003% FS μs 1 Slew rate (1) Code change glitch 1 LSB change around major carry Overshoot Full-scale change Digital feedthrough (2) 35 V/μs 0.5 nV-S 50 mV 0.5 nV-S SNR Digital sine wave input, fOUT = 1 kHz, BW = 10 kHz, 2-MSPS update rate 108 dB THD Digital sine wave input, fOUT = 20 kHz, 8-VPP output, 2-MSPS update rate –72 dB 0.1 Hz to 10 Hz 25 μVPP Output voltage noise At 10-kHz offset frequency 25 nV/√Hz At 100-kHz offset frequency 20 nV/√Hz Power supply rejection VDD varies ±10% 0.75 mV/V 3 MHz REFERENCE Reference input bandwidth Large signal: 2-VPP sine wave on 4 V DC Small signal: 100-mVPP sine wave on 4 V DC Reference input voltage range 10 3 MHz AVDD V Reference input impedance 5 kΩ Reference input capacitance 5 pF DIGITAL INPUTS VIH 0.7 x DVDD VIL GND 0.3 x DVDD V Input current ±1 μA Input capacitance 10 pF Power-on delay (1) (2) From VDD high to CS low 20 μs Slew rate is measured from 10% to 90% of transition when the output changes from 0 to full-scale. Digital feedthrough is defined as the impulse injected into the analog output from the digital input. It is measured when the DAC output does not change, CS is held high, and while SCLK and SDIN signals are toggled. Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: DAC8581 3 Not Recommended For New Designs DAC8581 SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = TMIN to TMAX, +AVDD = +5 V, –AVDD = –5 V, DVDD = +5 V (unless otherwise noted). DAC8581 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY +AVDD 4.0 5 6.0 V –AVDD –4.0 –5 –6.0 V DVDD 1.8 IDVDD IDD IREF and IDVDD included ISS AVDD V 10 20 μA 17 24 mA –23 –32 mA +85 °C TEMPERATURE RANGE Specified performance –40 PIN CONFIGURATION PW PACKAGE TSSOP-16 (TOP VIEW) VREF VOUT AVSS AVDD AGND DGND DGND DGND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DVDD DGND CLR DVDD DGND CS SCLK SDIN TERMINAL FUNCTIONS TERMINAL NAME NO. VREF 1 Reference input voltage. VOUT 2 DAC output voltage. Output swing is ±VREF AVSS 3 Negative analog supply voltage, tie to –5 V AVDD 4 Positive analog supply voltage, tie to +5 V AGND 5 The ground reference point of all analog circuitry of the device. Tie to 0 V. DGND 6, 7, 8, 15 SDIN 9 Digital input, serial data. Ignored when CS is high. SCLK 10 Digital input, serial bit clock. Ignored when CS is high. CS 11 Digital input. Chip Select (CS) signal. Active low. When CS is high, SCLK and SDI are ignored. When CS is low, data can be transferred into the device. DGND 12 Ground reference for digital circuitry. Tie to 0 V. DVDD 13 Positive digital supply, 1.8 V–5.5 V compatible CLR 14 Digital input for forcing the output to midscale. Active low. When pin CLR is low during 16th SCLK following the falling edge of CS, the falling edge of 16th SCLK sets DAC Latch to midcode, and the DAC output to 0 V. When pin CLR is High, the falling edge of 16th SCLK updates DAC latch with the value of input shift register, and changes DAC output to corresponding level. DVDD 16 Tie to DVDD to ensure correct operation. 4 Tie to DGND to ensure correct operation. Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: DAC8581 Not Recommended For New Designs DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 TIMING REQUIREMENTS (1) PARAMETER MIN MAX UNIT tSCK SCLK period 20 ns tWSCK SCLK high or low time 10 ns tLead Delay from falling CS to first rising SCLK 20 ns tTD CS High between two active Periods 20 ns tSU Data setup time (Input) 5 ns tHI Data hold time (input) 5 tR Rise time tF Fall time tWAIT Delay from 16th falling edge of SCLK to CS low tUPDAC Delay from 16th falling edge of SCLK to DAC output VDD High to CS Low (power-up delay) (1) ns 30 ns 30 ns 100 ns 1 μs 100 μs Assured by design. Not production tested. t td CS t sck t Lead t wsck 1st SCLK tsu SDIN t wsck t WAIT tf 2nd 15th tr t hi BIT-15 (MSB) BIT-14 16th tUPDAC BIT-13, …, 1 DAC Updated BIT-0 -- Don’t Care Figure 1. DAC8581 Timing Diagram Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: DAC8581 5 Not Recommended For New Designs DAC8581 SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 www.ti.com TYPICAL CHARACTERISTICS LINEARITY ERROR vs INPUT CODE DIFFERENTIAL LINEARITY ERROR vs INPUT CODE 20 0.5 15 10 DLE − LSBs 0.25 LE − LSBs 5 0 −5 −10 0 −0.25 −15 −20 −0.5 8192 0 16384 24576 32768 40960 49152 57344 8192 0 65536 16384 24576 Input Code 30 INTEGRAL NONLINEARITY ERROR vs SUPPLY VOLTAGE 65536 30 AVDD = 6 V, AVSS = −6 V 20 10 AVSS = −AVDD, VREF = AVDD −0.3 V INL max 10 INL − LSBs INL − LSBs INTEGRAL NONLINEARITY ERROR vs VREF 0 0 −10 INL min INL min −20 −20 −30 −30 3 3.5 4 4.5 5 5.5 3 4 4.5 5 AVDD − Supply Voltage − V Figure 4. Figure 5. OFFSET ERROR vs TEMPERATURE GAIN ERROR vs TEMPERATURE 193 AVDD = 5 V, AVSS = –5 V, VREF = 4.096 V 5.5 6 AVDD = 5 V, AVSS = –5 V, VREF = 4.096 V 191 Gain Error − mV 2 0 189 187 −2 −4 −40 3.5 VREF − Reference Voltage − V 4 Offset Error − mV 49152 57344 Figure 3. −10 −20 0 20 40 60 80 185 −40 −20 0 20 40 60 80 TA − Free-Air Temperature − 5C TA − Free-Air Temperature − 5C Figure 6. 6 40960 Figure 2. INL max 20 32768 Input Code Figure 7. Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: DAC8581 Not Recommended For New Designs DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 TYPICAL CHARACTERISTICS (continued) POSITIVE SUPPLY CURRENT—IDD vs TEMPERATURE NEGATIVE SUPPLY CURRENT—ISS vs TEMPERATURE 25 I SS − Supply Current − mA IDD − Supply Current − mA −11 20 15 −13 −15 −17 −19 −21 −23 10 −40 −20 0 20 40 60 −25 −40 80 TA − Free-Air Temperature − °C 20 40 60 80 Figure 8. Figure 9. POSITIVE SUPPLY CURRENT—IDD vs CODE NEGATIVE SUPPLY CURRENT—ISS vs CODE −19.5 I SS − Supply Current − mA 14.5 14 13.5 −16384 0 16384 −20 −20.5 −21 −32768 32768 −16384 0 16384 Code Code Figure 10. Figure 11. LARGE-SIGNAL SETTLING SMALL-SIGNAL SETTLING 32768 V − 2 V/div mV − 50 mV/div I DD − Supply Current − mA 0 TA − Free-Air Temperature − °C 15 13 −32768 −20 t − Time − 50 ns t − Time − 1µs Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: DAC8581 7 Not Recommended For New Designs DAC8581 SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) DIGITAL FEEDTHROUGH AND MIDCODE GLITCH OUTPUT VOLTAGE NOISE 100 k Hz V n − Output Noise Voltage − nV/ mV − 10 mV/div Glitch Feedthrough FSYNC 10 k 1k 100 10 1 t − Time − 1µs 10 100 1k 10 k 100 k f − Frequency − Hz Figure 14. Figure 15. POWER SPECTRAL DENSITY FROM DC TO 6 kHz SOFTWARE-TRIMMED UNIT POWER SPECTRAL DENSITY 0 −10 0 Fo = 1 kHz, Fclk = 192 KSPS, OSR = 1, THD = −71 dB, SNR = 113 dBFS, Digitizer = Delta−Sigma −20 −30 −40 Code − dB Gain − dB −40 −50 −60 −70 −80 −90 −60 −80 −100 −100 −110 −120 −120 −130 −140 Fo = 1 kHz, Fs = 192 KSPS −20 −140 0 2000 4000 f − Frequency − Hz 6000 0 1000 2000 3000 4000 f − Frequency − Hz Figure 16. 5000 6000 Figure 17. SOFTWARE-TRIMMED UNIT LINEARITY ERROR vs INPUT CODE 4 3 LE − LSBs 2 1 0 −1 −2 −3 −4 0 16384 32768 49152 65536 Input Code Figure 18. 8 Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: DAC8581 Not Recommended For New Designs DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 THEORY OF OPERATION The DAC8581 uses a proprietary, monotonic, high-speed resistor string architecture. The 16-bit input data are coded in twos complement, MSB-first format and transmitted using a 3-wire serial interface. The serial interface sends the input data to the DAC latch. The digital data are then decoded to select a tap voltage of the resistor string. The resistor string output is sent to a high-performance output amplifier. The output buffer has bipolar (±5 V) swing capability on a 600-Ω, 200-pF load. The resistor string DAC architecture provides exceptional differential linearity and temperature stability whereas the output buffer provides fast-settling, low-glitch, and exceptionally low idle-channel noise. The DAC8581 settles within 1 μs for large input signals. Exceptionally low glitch (0.5 nV-s) is attainable for small-signal, code-to-code output changes. The resistor string architecture also provides code-independent power consumption and code-independent settling time. The DAC8581 resistor string needs an external reference voltage to set the output voltage range of the DAC. To aid fast settling, VREF input is internally buffered. Supply Pins The DAC8581 uses ±5-V analog power supplies (AVDD, AVSS) and a 1.8-V to 5.5-V digital supply (DVDD). Analog and digital ground pins (AGND and DGND) are also provided. For low-noise operation, analog and digital power and ground pins should be separated. Sufficient bypass capacitors, at least 1 μF, should be placed between AVDD and AVSS, AVSS and DGND, and DVDD and DGND pins. Series inductors are not recommended on the supply paths. The digital input pins should not exceed the ground potential during power up. During power up, AGND and DGND are first applied with all digital inputs and the reference input kept at 0 V. Then, AVDD, DVDD, AVSS, and VREF should be applied together. Care should be taken to avoid applying VREF before AVDD and AVSS. All digital pins must be kept at ground potential before power up. Reference Input Voltage The reference input pin VREF is typically tied to a +3.3-V, +4.096-V, or +5.0-V external reference. A bypass capacitor (0.1 μF or less) is recommended, depending on the load-driving capability of the voltage reference. To reduce crosstalk and improve settling time, the VREF pin is internally buffered by a high-performance amplifier. The VREF pin has constant 5-kΩ impedance to AGND. The output range of the DAC8581 is equal to ±VREF voltage. The VREF pin should be powered at the same time, or after the supply pins. REF3133 and REF3140 are recommended to set the DAC8581 output range to ±3.3 V and ±4.096 V, respectively. Output Voltage The input data format is in twos-complement format as shown in Table 1. The DAC8581 uses a highperformance, bipolar output buffer capable of driving a 600-Ω, 200-pF load with fast 0.65-μs settling. The buffer has exceptional noise performance (20 nV/√Hz) and fast slew rate (35 V/μs). The small-signal settling time is under 300 ns, allowing update rates up to 3 MSPS. Loads of 50 Ω or 75 Ω could be driven as long as output current does not exceed ±25 mA continuously. Long cables, up to 1 nF in capacitance, can be driven without the use of external buffers. To aid stability under large capacitive loads (>1 nF), a small series resistor can be used at the output. Table 1. Data Format DIGITAL CODE DAC OUTPUT BINARY HEX +VREF 0111111111111111 7FFF +VREF/2 0100000000000000 4000 0 0000000000000000 0000 –VREF/2 1011111111111111 BFFF –VREF 1000000000000000 8000 Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: DAC8581 9 Not Recommended For New Designs DAC8581 SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 www.ti.com Glitch area is low at 0.5 nV-s, with peak glitch amplitude under 10 mV, and the glitch duration under 100 ns. Low glitch is obtained for code-to-code (small signal) changes across the entire transfer function of the device. For large signals, settling characteristics of the reference and output amplifiers are observed in terms of overshoot and undershoot. Combined with ±5-V output range, and extremely good noise performance, the outstanding differential linearity performance of this device becomes significant. That is, each DAC step can be clearly observed at the DAC output, without being corrupted by wideband noise. SERIAL INTERFACE The DAC8581 serial interface consists of the serial data input pin SDIN, bit clock pin SCLK, and chip-select pin, CS. The serial interface is designed to support the industry standard SPI interface up to 50 MHz. The serial inputs are 1.8-V to 5.5-V logic compatible. CS operates as an active-low, chip-select signal. The falling edge of CS initiates the data transfer. Each rising edge of SCLK following the falling edge of CS shifts the SDIN data into a 16-bit shift register, MSB-first. At the 16th rising edge of SCLK, the shift register becomes full and the DAC data updates on the falling edge that follows the 16th rising edge. After the data update, further clocking gets ignored. The sequence restarts at the next falling edge of CS. If the CS is brought high before the DAC data are updated, the data are ignored. See the timing diagram (Figure 1) for details. Pin CLR Pin CLR is implemented to set the DAC output to 0 V. When the CS pin is low during the 16th SCLK cycle following the falling edge of CS, the falling edge of the 16th SCLK sets the DAC latch to midcode, and the DAC output to 0 V. If the CLR pin is high during the 16th clock, the falling edge of the 16th clock updates the DAC latch with the input data. Therefore, if the CLR pin is brought back to High from Low during serial communication, the DAC output stays at 0 V until the falling edge of the next 16th clock is received. The CLR pin is active low. CLR low does not affect the serial data transfer. The serial data input doe not get interrupted or lost while the output is set at midscale. SCLK This digital input pin is the serial bit-clock. Data are clocked into the device at the rising edge of SCLK. CS This digital input pin is the chip-select signal. When CS is low, the serial port is enabled and data can be transferred into the device. When CS is high, all SCLK and SDIN signals are ignored. SDIN This digital input is the serial data input. Serial data are shifted on the rising edge of the SCLK when CS is low. 10 Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: DAC8581 Not Recommended For New Designs DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 APPLICATION INFORMATION IMPROVING DAC8581 LINEARITY USING EXTERNAL CALIBRATION At output frequencies up to 50 kHz, DAC8581 linearity error and total harmonic distortion are dominated by resistor mismatches in the string. These resistor mismatches are fairly insensitive to temperature and aging effects and also to reference voltage changes. Therefore, it is possible to use a piece-wise linear (PWL) approximation to cancel linearity errors, and the calibration remains effective for different supply and VREF voltages, etc. The cancellation of linearity errors also improves the total harmonic distortion (THD) performance. It is possible to improve the integral linearity errors from ±25 LSB to ±1 LSB and the THD from –70 dB to almost –98 dB (see Figure 17 and Figure 18). The improvements are at the expense of ~2x DNL deterioration, which is not critical for the generation of large-signal waveforms. Lookup Table (FLASH) MCU DAC8581 Figure 19. A Simple Printed-Circuit Board Scheme for Calibrated Use of DAC8581 Board Tester (ATE) Lookup Table (FLASH) MCU DAC8581 DVM Board Tester Computer Figure 20. Production Test Setup for a DAC8581 Board With Calibration The PWL calibration scheme uses a DAC8581 and a microcontroller unit (MCU) with flash memory, on a printedcircuit board as seen in Figure 19. Calibration is done during board test, and the calibration coefficients are stored permanently in flash memory as seen in Figure 20. An automated board tester is assumed to have a precision digital voltmeter (DVM) and a tester computer. The test flow for a 1024-segment, piece-wise linear calibration is as follows: 1. Use the tester computer to load software into the MCU to ramp the DAC8581 and: – Take a reading at each step after a short wait time – Store 65,536 readings in the tester computer volatile memory 2. Use the tester computer to: – Search the 65,536-point capture data and find the actual DAC8581 codes which would generate ideal DAC outputs for DAC input codes 0, 64, 128, 192, … . – Store these actual codes in the onboard microcontroller’s flash memory in a 1025-point array called COEFF[]. 3. Use the tester computer to program the MCU such that, when the end-user provides new 16-bit input data D0 to the MCU: – The 10 MSBs of D0 directly index the array COEFF[]. – The content of indexed memory of COEFF[] and the content of the next higher memory location are placed in variables I1 and I2. – The six LSBs of the user data D0 with two variables I1 and I2 are used for computing Equation 1 (see Figure 21). – Instead of D0, I0 is loaded to DAC8581 Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: DAC8581 11 Not Recommended For New Designs DAC8581 SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 www.ti.com Ideal−DAC Transfer Curve Main −DAC Transfer Curve VI2 PWL Segment VI0 VI0B VI1 I0 I0B I1 I2 Figure 21. The Geometry Behind the PWL Calibration I0 + I1 ) (I2 * I1)(D0 * VI1) VI2 * VI1 (1) Where both x-axis and y-axis are normalized from 0 to 65535, and: VI0: Desired ideal DAC voltage corresponding to input code D0. VI0B: DAC8581 output voltage, which approximates VI0 after PWL calibration. This is the actual DAC8581 output for input code D0 after PWL calibration. I0: DAC8581 code generating VI0B, an approximation to the desired voltage VI0. This is actual code loaded into DAC latch for input code D0, after PWL calibration. I0B: DAC8581 code, which generates output VI0. This code is approximated by the N-segment PWL calibration. I1: Contents of memory COEFF[], addressed by the 10 MSBs of user input code D0. I2: Contents of the next memory location in COEFF[]. VI1: DAC8581 output voltage corresponding to code I1. Notice that (D0–VI1) is nothing but the six LSBs of the input code D0, given that the y-axis is normalized from 0 to 65,536. VI2: DAC8581 output voltage corresponding to code I2. Notice that (VI2–VI1) is always equal to number 64, given that the y-axis is normalized from 0 to 65,536. Division becomes a 6-bit arithmetic right shift. Other similar PWL calibration implementations exist. This particular algorithm does not need digital division, and it does not accumulate measurement errors at each segment. 12 Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: DAC8581 Not Recommended For New Designs DAC8581 www.ti.com SLAS481C – AUGUST 2005 – REVISED OCTOBER 2012 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (August, 2005) to Revision B Page • Updated document format to current stylistic standards ...................................................................................................... 1 • Deleted lead temperature specifications from Absolute Maximum Ratings table ................................................................ 2 • Deleted footnote 1 from Electrical Characteristics table ....................................................................................................... 3 • Revised test conditions for voltage output specification ....................................................................................................... 3 Changes from Revision B (December 2009) to Revision C Page • Changed "rail-to-rail" to "bipolar" .......................................................................................................................................... 1 • Changed "rail-to-rail" to "bipolar" .......................................................................................................................................... 9 Submit Documentation Feedback Copyright © 2005–2012, Texas Instruments Incorporated Product Folder Links: DAC8581 13 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) DAC8581IPW NRND TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 D8581I DAC8581IPWR NRND TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 D8581I (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of