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DAC8771
SLASEE2 – FEBRUARY 2018
DAC8771 Single-Channel,16-Bit Voltage and Current Output
Digital-to-Analog Converter with Adaptive Power Management
1 Features
3 Description
•
The DAC8771 is a single channel, precision, fully
integrated 16-bit digital to analog converter (DAC)
with adaptive power management, and is designed to
meet the requirements of industrial control
applications. The adaptive power management
circuit, when enabled, minimizes the power
dissipation of the chip. When programmed as a
current output, the supply voltage on the current
output driver is regulated between 4 V and 32 V
based on continuous feedback of voltage on the
current output pin via a buck/boost converter. When
programmed as a voltage output, this circuit
generates a programmable supply voltage for the
voltage output stage (±15 V). DAC8771 contains an
LDO to generate the digital supply (5 V) from a single
power supply pin, particularly helpful in isolated
applications.
1
•
•
•
•
•
•
•
•
•
•
•
•
Output Current:
– 0 mA - 24 mA; 3.5 mA - 23.5 mA;
0 mA - 20 mA; 4 mA - 20 mA; ±24 mA
Output Voltage (with/without 20% over-range):
– 0 V - 5 V; 0 V - 10 V; ±5 V; ±10 V
– 0 V - 6 V; 0 V - 12 V; ±6 V; ±12 V
Adaptive Power Management
Single Wide Power Supply Pin
– 12 V - 36 V with Buck-Boost
– 12 V - 33 V without Buck-Boost
±0.1% FSR Total Unadjusted Error (TUE)
DNL: ±1 LSB Max
Internal 5-V Reference (10 ppm/°C max)
Internal 5-V Digital Power Supply Output
CRC/Frame Error Check, Watchdog Timer
Thermal Alarm, Open/Short circuit
Safe actions on alarm condition
Auto Learn Feature
Wide Temperature Range: –40°C to +125°C
DAC8771 is also implemented with a HART Signal
Interface to superimpose an external HART signal on
the current output. The slew rate of the current output
DAC is register programmable. The devices can
operate with a single external power supply of +12 V
to +36 V using the integrated buck/boost converter or
with external power supplies when the buck/boost
converter is disabled.
2 Applications
•
•
•
•
Device Information(1)
4 mA to 20 mA Current Loops
Analog Output Modules
Programmable Logic Controllers (PLCs)
Building Automation
PART NUMBER
DAC8771
PACKAGE
VQFN (48)
BODY SIZE (NOM)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
DAC8771 Block Diagram
REFOUT DVDD_EN DVDD
Internal
Reference
ALARM
RESET
CLR
SYNC
SDO
SPI Shift Register Input
Control Logic
SDIN
PVDD
VNEG_IN
Amp
LP
LN
VPOS_IN
Buck/Boost Converters
PVSS
AGND
DVDD
LDO
LDAC
SCLK
REFIN AVDD
User
Calibration
Register
IRANGE
X
DAC
IENABLE
Alarm
Current
Source
IOUT
HART_IN
DAC Input
Register
Watchdog
Timer
IAmp
CCOMP
VENABLE
VAmp
Slew Rate
Control
VOUT
VSENSEN
Feedback
Power On
Reset
GND
VSENSEP
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC8771
SLASEE2 – FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
8.4 Device Functional Modes........................................ 40
8.5 Register Maps ........................................................ 45
1
1
1
2
3
3
5
9
Application and Implementation ........................ 60
9.1 Application Information............................................ 60
9.2 Typical Application ................................................. 63
10 Power Supply Recommendations ..................... 66
11 Layout................................................................... 68
11.1 Layout Guidelines ................................................. 68
11.2 Layout Example .................................................... 69
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
Timing Requirements: Write and Readback Mode . 13
Typical Characteristics ............................................ 15
12 Device and Documentation Support ................. 72
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Detailed Description ............................................ 31
8.1 Overview ................................................................. 31
8.2 Functional Block Diagram ....................................... 31
8.3 Feature Description................................................. 31
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
72
72
72
72
72
72
72
13 Mechanical, Packaging, and Orderable
Information ........................................................... 72
4 Revision History
2
DATE
REVISION
NOTES
February 2018
*
Initial release.
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5 Device Comparison Table
PRODUCT
RESOLUTION
DIFFERENTIAL
NONLINEARITY (LSB)
SPECIFIED
TEMPERATURE
RANGE
DAC8771
16
±1
–40°C to +125°C
6 Pin Configuration and Functions
NC
NC
NC
ALARM
RESET
CLR
LDAC
SYNC
SCLK
SDIN
SDO
NC
47
46
45
44
43
42
41
40
39
38
37
PIN 1
INDICATOR
36
NC
35
DNC
GND 3
34
DNC
REFOUT 4
33
DNC
REFIN 5
32
HART_IN
DVDD_EN 6
31
CCOMP
DVDD 7
30
VSENSEN
NC 8
29
VSENSEP
GND 9
28
GND
NC 10
27
VNEG_IN
VNEG_IN 11
26
IOUT
NC 12
25
VOUT
AVDD 2
NC
24
VPOS_IN 23
DNC 22
NC 21
GND 20
NC 19
LN 17
PVSS 16
LP 15
PVDD 14
NC 13
EXPOSED THERMAL PAD
GND 18
NC 1
48
RGZ Package
48 Pin VQFN
Top View
Thermal pad connected to ground.
Pin Functions
NAME
NUMBER
TYPE
DESCRIPTION
AVDD
2
Supply
Power supply for all analog circuitry of the device except buck-boost converter and output
amplifiers.
GND
3, 9, 18, 20,
28
Supply
Ground.
REFOUT
4
Analog
Output
Internal reference output. Connects to REFIN when using internal reference.
REFIN
5
Analog Input
Reference input. Connects to REFOUT when using internal reference.
DVDD_EN
6
Digital Input
Internal power-supply enable pin. Connect this pin to GND to disable the internal DVDD, or
leave this pin unconnected to enable the internal DVDD. When this pin is connected to GND an
external supply must be connected to the DVDD pin.
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Pin Functions (continued)
NAME
NUMBER
TYPE
DESCRIPTION
7
Supply
Digital supply pin (Input/Output). Internal DVDD enabled when DVDD_EN is floating, External
DVDD must be supplied when DVDD_EN is connected to GND.
11, 27
Supply
Negative power supply for output stage. Connected internally, however both external
connections are required.
14
Supply
Buck-Boost converter power supply.
LP
15
Analog
Output
External inductor positive terminal.
PVSS
16
Supply
Switch ground for Buck-Boost converter.
LN
17
Analog
Output
External inductor negative terminal.
VPOS_IN
23
Supply
Positive power supply for output stage.
VOUT
25
Analog
Output
Voltage output pin.
IOUT
26
Analog
Output
Current output pin.
VSENSEP
29
Analog Input
Positive sense pin for voltage output.
VSENSEN
30
Analog Input
Negative sense pin for voltage output.
CCOMP
31
Analog
Output
HART_IN
32
Analog Input
SDO
38
Digital Output Serial data output. Data is valid on the falling edge of SCLK.
SDIN
39
Digital Input
Serial data input. Data is clocked into the 24-bit input shift register on the falling edge of the
serial clock input. Schmitt-Trigger logic input.
SCLK
40
Digital Input
Serial clock input of serial peripheral interface (SPI™). Data can be transferred at rates up to
25 MHz. Schmitt-Trigger logic input.
SYNC
41
Digital Input
SPI™ bus chip select input (active low). Data bits are not clocked into the serial shift register
unless SYNC is low. When SYNC is high SDO is in a high-impedance state.
LDAC
42
Digital Input
Load DAC latch control input. A logic low on this pin loads the input shift register data into the
DAC register and updates the DAC output.
CLR
43
Digital Input
Level triggered clear pin (active high). Clears DAC output to zero code or mid code (see DAC
Clear section).
RESET
44
Digital Input
Reset input (active low). Logic low on this pin causes the device to perform a reset.
ALARM
45
DVDD
VNEG_IN
PVDD
NC
DNC
4
External compensation capacitor connection pin for voltage output. Addition of the external
capacitor improves stability for high capacitive loads at the VOUT pin by reducing the
bandwidth of the output amplifier at the expense of settling time.
Input pin for HART modulation. If this pin is used it must be AC coupled to the HART input
sinusoidal waveforms via a capacitor. If this feature is not used TI recommends to AC couple
this pin to ground via a capacitor, though it may also be left floating.
ALARM pin. Open drain output. External pull-up resistor required (10 kΩ). The pin goes low
Digital Output (active) when any ALARM condition is detected (open-circuit, over-temperature, watchdog
timeout, and others).
1, 8, 10, 12,
13, 19, 21,
24, 36, 37,
46, 47, 48
N/A
No connection is required on these pins.
22,33, 34,
35
N/A
Do not connect these pins.
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7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
Input voltage
Output voltage
Input Current
MIN
MAX
PVDD/AVDD to PBKG
-0.3
40
PVSS to GND
-0.3
0.3
VPOS_IN to VNEG_IN
-0.3
40
VPOS_IN to GND
-0.3
33
VNEG_IN to GND
-20
0.3
VSENSEN to GND
VNEG_IN
VPOS_IN
VSENSEP to GND
VNEG_IN
VPOS_IN
CCOMP to VNEG_IN
-0.3
6
DVDD to GND
-0.3
6
REFOUT/REFIN to GND
-0.3
6
Digital input voltage to GND
-0.3
DVDD+0.3
VOUT to GND
VNEG_IN
VPOS_IN
IOUT to GND
VNEG_IN
VPOS_IN
SDO, ALARM to GND
-0.3
DVDD+0.3
Current into any pin
-10
Power dissipation
Operating junction temperature, TJ
Storage temperature, Tstg
V
V
10
mA
(TJmax –
TA)/ThetaJA
W
-40
150
Junction temperature range (TJ max)
(1)
UNIT
150
-65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1)
±2000
Charged device model (CDM), per
JEDEC specification JESD22-C101, all
pins (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
NOM
MAX
UNIT
POWER SUPPLY
PVDD/AVDD/ to
Positive supply voltage to ground
GND
VPOS_IN to
GND
VNEG_IN to
GND
12
36
-0.3
33
Negative supply voltage to substrate for
current output mode
-18
0
V
Negative supply voltage to substrate for
voltage output mode
-18
-5
V
12
36
V
-7
7
V
2.7
5.5
V
Positive supply voltage to ground for all
modes
VPOS_IN to
VNEG_IN
VSENSEN to
GND
The minimum headroom spec for voltage
output stage must be met
DVDD to GND
Digital supply voltage to substrate
V
DIGITAL INPUTS
VIH, input high
voltage
VIL, input low
voltage
2
V
3.6 V < DVDD < 5.5 V
0.8
V
2.7 V < DVDD < 3.6 V
0.6
V
4.95
5.05
V
-40
125
°C
REFERENCE INPUT
REFIN to GND
Reference input to substrate
TEMPERATURE RANGE
TA
(1)
Operating temperature
The minimum headroom spec for voltage output stage and the compliance voltage for current output stage should be met. When BuckBoost converter is enabled VPOS_IN_x/VNEG_IN_x are generated internally to meet headroom and compliance specs. When BuckBoost converter is disabled VPOS_IN_x, AVDD, and PVDD must be tied together.
7.4 Thermal Information
DAC8771
THERMAL METRIC
(1)
RGZ
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
21.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
9.2
°C/W
RθJB
Junction-to-board thermal resistance
5.6
°C/W
ΨJT
Junction-to-top characterization parameter
0.1
°C/W
ΨJB
Junction-to-board characterization parameter
5.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.3
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953
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7.5 Electrical Characteristics
AVDD/PVDD/VPOS_IN = +15V, VNEG_IN = -15V, VSENSEN = GND = PVSS = 0 V, External DVDD = 2.7 V. VOUT : RL = 1
kΩ, CL = 200 pF, IOUT : RL = 250Ω; all specifications -40C to +125C, unless otherwise noted. REFIN= +5 V external,
REFOUT = +5V internal, Buck-Boost Converter disabled unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT OUTPUT
0
IOUT
Output Current Ranges
24
mA
0
20
mA
3.5
23.5
mA
-24
24
mA
4
20
mA
ACCURACY
Resolution
INL
Relative accuracy (1)
DNL
Differential Nonlinearity (1)
16
-10
10
LSB
Bipolar range only
-12
12
LSB
Ensured monotonic
-1
1
LSB
-0.1
0.1
-40°C to 125°C
TUE
Total Unadjusted Error (1)
Offset Error (1)
OE
TA = +25°C
-0.08
0.08
-0.130
0.130
TA = +25°C (4-20mA)
-0.08
0.08
-40°C to 125°C
-0.06
0.06
TA = +25°C
-0.05
0.05
-0.085
0.085
-0.04
0.04
-40°C to 125°C (4-20mA)
-40°C to -125°C (4-20mA)
TA = +25°C (4-20mA)
OE-TC
Offset Error Temperature Coefficient
ZCE
Zero Code Error
ZCE-TC
Zero Code Error Temperature
Coefficient
-40°C to -125°C
Gain Error (1)
FSE
Gain Error Temperature Coefficient
Full Scale Error
NFSE
Negative Full Scale Error
FSE-TC
Full Scale Error Temperature
Coefficient
BPZE
BPZE-TC
(1)
Bipolar Zero Error
Bipolar Zero Error Temperature
Coefficient
%FSR
ppm FSR /
ºC
1.5
-13
13
uA
DAC data set to 0x0000 (4-20mA)
-13
13
uA
DAC data set to 0x0000, -40°C to
-125°C
1.5
ppm/ ºC
-0.1
0.1
TA = +25°C
-0.075
0.075
-40°C to -125°C (4-20mA)
-0.110
0.110
-0.08
0.08
TA = +25°C (4-20mA)
GE-TC
%FSR
DAC data set to 0x0000
-40°C to -125°C
GE
Bits
All ranges except bipolar range
-40C to -125C
%FSR
ppm FSR /
ºC
3
DAC data set to 0xFFFF, -40°C to
-125°C
-0.1
0.1
%FSR
DAC data set to 0xFFFF, -40°C to
-125°C (4-20mA)
-0.130
0.130
%FSR
-0.05
0.05
%FSR
DAC data set to 0x0000, bipolar range
only, -40°C to -125°C
ppm FSR /
ºC
3
bipolar range only, DAC data set to
0x8000, -40°C to -125°C
-0.05
0.05
bipolar range only, DAC data set to
0x8000, TA = +25°C
-0.02
0.02
0x8000h into DAC,-40°C to -125°C
%FSR
4
ppm/ ºC
For current output all ranges except ±24 mA, low code of 256d and a high code of 65280d are used, for ±24 mA range low code of 0d
and a high code of 65280d. For voltage output, low code of 256d and a high code of 65280d are used
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Electrical Characteristics (continued)
AVDD/PVDD/VPOS_IN = +15V, VNEG_IN = -15V, VSENSEN = GND = PVSS = 0 V, External DVDD = 2.7 V. VOUT : RL = 1
kΩ, CL = 200 pF, IOUT : RL = 250Ω; all specifications -40C to +125C, unless otherwise noted. REFIN= +5 V external,
REFOUT = +5V internal, Buck-Boost Converter disabled unless otherwise stated
PARAMETER
TEST CONDITIONS
MIN
TYP
Output=24mA
VCL
Loop Compliance Voltage
Output=±24mA
MAX
VPOS_I
N-3
|VNEG
_IN|-3
VPOS_I
N-3
All except ±24 mA range
1.2K
UNIT
V
RL
Resistive Load
DC-PSRR
DC Power Supply Rejection Ratio
DAC data set to 0x8000, 20mA range
0.1
µA/V
Zo
Output Impedance
DAC data set to 0x8000
10
MΩ
IOLEAK
Output Current Leakage
Iout is disabled or in power-down
1
nA
±24 mA range
0.625K
Ω
HART INTERFACE
VHART-IN
HART Input
400
Corresponding Output
HART In = 500mVpp 1.2KHz
500
600
1
mVpp
mApp
VOLTAGE OUTPUT
Voltage Output Ranges (normal mode)
VOUT
Voltage Output Ranges (Overrange
mode)
0
5
0
10
-5
5
-10
10
0
6
0
12
-6
6
-12
12
ACCURACY
Resolution
INL
Relative Accuracy, INL (1)
DNL
Differential Nonlinearity, DNL (1)
TUE
Total Unadjusted Error, TUE (1)
BPZE
Bipolar Zero Error
16
Ensured monotonic
-40°C to 125°C, VOUT unloaded
-1
1
LSB
-0.1
±0.05
0.1
0.75
bipolar range only, DAC data set to
0x8000, -40°C to 125°C, VOUT
unloaded
-0.05
0.05
bipolar range only, DAC data set to
0x8000, TA = +25°C, VOUT unloaded
-0.03
bipolar range only, DAC data set to
0x8000, -40°C to 125°C, (VOUT
unloaded)
OE
Offset Error
Unipolar ranges only, (Vout unloaded),
-40°C to 125°C
OE
Offset Error
Unipolar ranges only, (Vout unloaded),
TA = 25°C
OE-TC
Offset Error Temperature Coefficient
Unipolar ranges only, -40°C to 125°C
GE
Gain Error (1)
GE-TC
Gain Error Temperature Coefficient
8
LSB
-0.75
Bipolar Zero Error Temperature
Coefficient
Full Scale Error
12
TA = +25°C, VOUT unloaded
BPZE-TC
FSE
Bits
-12
-40°C to 125°C, VOUT unloaded
TA = +25°C, VOUT unloaded
%FSR
0.03
ppm FSR /
ºC
1
-5
5
DAC data set to 0xFFFF, 25°C, (Vout
unloaded)
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mV
0.65
mV
1.5
ppm FSR/ ºC
-0.1
0.1
-0.07
0.07
-0.1
0.1
0.03
%FSR
ppm FSR /
ºC
3
DAC data set to 0xFFFF, -40° to
125°C, (Vout unloaded)
%FSR
%FSR
%FSR
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Electrical Characteristics (continued)
AVDD/PVDD/VPOS_IN = +15V, VNEG_IN = -15V, VSENSEN = GND = PVSS = 0 V, External DVDD = 2.7 V. VOUT : RL = 1
kΩ, CL = 200 pF, IOUT : RL = 250Ω; all specifications -40C to +125C, unless otherwise noted. REFIN= +5 V external,
REFOUT = +5V internal, Buck-Boost Converter disabled unless otherwise stated
PARAMETER
NFSE
FSE-TC
Negative Full Scale Error
Full Scale Error Temperature
Coefficient
Headroom
Footroom
Short-Circuit Current
RL
CL
TEST CONDITIONS
Bipolar ranges only, DAC data set to
0x0000, -40°C to 125°C, (Vout
unloaded)
TYP
-0.07
Bipolar ranges only, DAC data set to
0x0000, -40°C to 125°C, (Vout
unloaded)
DC-PSRR
0.07
%FSR
%FSR
ppm FSR /
ºC
Output unloaded, VPOS_IN with
respect to VOUT, DAC data set to
0xFFFF, specified by design
0.5
V
1kΩ output load, VPOS_IN with
respect to VOUT, DAC data set to
0xFFFF, specified by design
3
V
Bipolar, ranges only, VNEG_IN with
respect to VOUT, DAC data set to
0x0000, specified by design
-3
V
Unipolar ranges only, VNEG_IN with
respect to VOUT, DAC data set to
0x0000, specified by design
-5
V
SCLIM[1:0] = "00" (see register map)
17
27
mA
SCLIM[1:0] = "01" (see register map)
8
12
mA
SCLIM[1:0] = "10" (see register map)
22
30
mA
SCLIM[1:0] = "11" (see register map)
26
36
mA
1
kΩ
RL = Open
20
nF
RL = 1 kΩ
20
nF
1
µF
Voltage output enabled, Vout = MidScale, 0-10V range
DC Output Impedance
UNIT
2
RL = 1 kΩ with External compensation
capacitor (150pF) connected.
ZO
MAX
0.002
(Vout unloaded)
Load
Capacitive Load Stability
MIN
0.01
Ω
Voltage output disabled
50
Voltage output disabled (POC = '0')
30
MΩ
kΩ
DC Power Supply Rejection Ratio
No Output Load
10
µV/V
VSENSEP Impedance
VOUT Enabled, Vout = Mid-Scale, 010V Range, specified by design
120
kΩ
VSENSEN Impedance
VOUT Enabled, Vout = Mid-Scale, 010V Range, specified by design
240
kΩ
Vout = Negative Full-Scale, ±12V
range
350
µA
100
pF
EXTERNAL REFERENCE INPUT
IREF
External reference current
Reference Input Capacitance
INTERNAL REFERENCE OUTPUT
VREF
Reference Output
TA = 25°C
VREF-TC
Reference TC
TA = -40°C to 125°C
DAC Voltage Output Total unadjusted
error (1)
-40°C to 125°C, VOUT unloaded,
Internal reference enabled
0.2
%FSR
DAC Current Output Total unadjusted
error (1)
-40°C to +125°C, Internal reference
enabled
0.2
%FSR
Output Noise (0.1 Hz to 10 Hz)
TA = 25°C
Noise Spectral Density
At 10 kHz, 25°C
TUE
4.99
5.01
-10
10
V
ppm/°C
13
µV p-p
200
nV/sqrtHz
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Electrical Characteristics (continued)
AVDD/PVDD/VPOS_IN = +15V, VNEG_IN = -15V, VSENSEN = GND = PVSS = 0 V, External DVDD = 2.7 V. VOUT : RL = 1
kΩ, CL = 200 pF, IOUT : RL = 250Ω; all specifications -40C to +125C, unless otherwise noted. REFIN= +5 V external,
REFOUT = +5V internal, Buck-Boost Converter disabled unless otherwise stated
PARAMETER
CL
Capacitive Load
IL
Load Current
TEST CONDITIONS
MIN
TYP
MAX
600
±5
UNIT
nF
mA
Short Circuit Current
Reference output shorted to GND
20
mA
Load Regulation
Sourcing and Sinking, TA = +25°C
5
µV/mA
Line regulation
TA = +25°C
1
uV/V
BUCK BOOST CONVERTER
RON
Switch On Resistanvce
TA = +25°C
3
Ω
ILEAK
Switch Leakage Current
TA = +25°C
20
nA
L
Inductor
between LP and LN
100
µH
ILMAX
Peak Inductor Current
TA = +25°C, maximum specified by
design
0.35
VO
Output Voltage
CL
Load Capacitor
VPOS_IN and VNEG_IN
Start up time
After enabling VPOS_IN and
VNEG_IN with 10µF load capacitor on
these pins
0.5
A
V
VPOS_IN
4
32
VNEG_IN
-18
-5
10
V
µF
3
ms
5
V
DVDD LDO
VO
Output Voltage
ILOAD
Load Current
10
mA
CL
Load Capacitor
0.2
µF
THERMAL ALARM
Trip point
150
°C
Hysteresis
15
°C
0.4
V
DIGITAL INPUTS
Hysteresis voltage
Input Current
Pin Capacitance
-5
Per pin
5
10
µA
pF
DIGITAL OUTPUTS
SDO
VOL
Output Low Voltage
VOH
Output High Voltage
ILEAK
High Impedance Leakage
Sinking 200 µA
Sourcing 200 µA
0.4
DVDD0.5
V
-5
High Impedance Output Capacitance
V
5
10
µA
pF
ALARM
VOL
Output Low Voltage
0.4
V
ILEAK
High Impedance Leakage
At 10 mA
50
µA
High Impedance Output Capacitance
10
pF
3
mA
1.3
mA
POWER REQUIREMENTS
IAVDD
IPVDD
Current Flowing into AVDD
Current Flowing into PVDD
Buck-Boost converter enabled, All
IOUT Active, 0mA, 0-20mA range
IOUT Active, 0 mA, 0-20mA range,
VNEG_IN = 0V
Buck-Boost converter enabled, Peak
Current, specified by design
Buck-Boost converter disabled
10
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0.5
0.1
A
mA
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Electrical Characteristics (continued)
AVDD/PVDD/VPOS_IN = +15V, VNEG_IN = -15V, VSENSEN = GND = PVSS = 0 V, External DVDD = 2.7 V. VOUT : RL = 1
kΩ, CL = 200 pF, IOUT : RL = 250Ω; all specifications -40C to +125C, unless otherwise noted. REFIN= +5 V external,
REFOUT = +5V internal, Buck-Boost Converter disabled unless otherwise stated
PARAMETER
IDVDD
Current Flowing into DVDD
IVPOS_IN
Current Flowing into VPOS_IN
IVNEG_IN
Current Flowing into VNEG_IN
TEST CONDITIONS
All digital pins at DVDD, DVDD 2.7V to
5.5V
MIN
TYP
MAX
UNIT
1.8
IOUT Active, 0mA, 0-20mA range
VOUT Active, no load, 0-10V range,
mid scale code
IOUT Active, 0mA, ±24mA range
VOUT Active, no load, 0-10V range,
mid scale code
mA
1.2
mA
3
mA
1.2
mA
3
mA
0.275
W
PDISS
Power dissipation (PVDD+AVDD)
Buck-Boost converter positive output
enabled, IOUT mode operation, All
IOUT channels enabled, Rload = 1Ω,
24mA, PVDD = AVDD = 12V
IVSENSEP
Current Flowing into VSENSEP
VOUT Disabled, specified by design
40
nA
IVSENSEN
Current Flowing into VSENSEN
VOUT Disabled, specified by design
20
nA
0.226
DYNAMIC PERFORMANCE
VOLTAGE OUTPUT
Tsett
Output Voltage Settling Time
SR
0 to 10V, to ±0.03% FSR RL = 1kΩ ||
CL = 200pF
15
µs
0 to 5V, to ±0.03% FSR RL = 1kΩ ||
CL = 200pF
10
µs
-5 to 5V, to ±0.03% FSR RL = 1kΩ ||
CL = 200pF
20
µs
-10 to 10V, to ±0.03% FSR RL = 1kΩ
|| CL = 200pF
30
µs
mVpp
Output voltage ripple
Buck-Boost converter enabled, 50 KHz
20dB/decade low-pass filter on
VPOS_IN
2
Slew Rate
RL = 1kΩ || CL = 200pF
1
Power-On Glitch Energy (2)
Specified by design
0.1
V
Power-off Glitch Energy (3)
Specified by design
0.8
V
Code-Code Glitch
Digital Feedthrough
AC-PSRR
V/µs
0.15
µV-sec
1
nV-sec
LSB p-p
Output Noise (0.1 Hz to 10 Hz
Bandwidth)
0-10V range, Mid-Scale
0.1
Output Noise (100 kHz Bandwidth)
0-10V range, Mid-Scale
200
µVrms
Output Noise Spectral Density
±10V Measured at 10 kHz, Mid-Scale
200
nV/sqrtHz
AC Power Supply Rejection Ratio
200mV 50/60Hz sinusoid
superimposed on power supply
voltage (AC analysis).
-75
dB
24 mA Step, to 0.1% FSR, no L
10
µs
24 mA Step, to 0.1% FSR , L = 1mH,
CL = 22nF
50
µs
2
µApp
CURRENT OUTPUT
Tsett
Output Current Settling Time
Output current ripple
L
(2)
(3)
(4)
Buck-boost converter enabled, 50 KHz
20dB/decade low-pass filter on
VPOS_IN
Inductive Load (4)
50
mH
No load, DVDD supply ramps up before VPOS_IN, and VNEG_IN, ramp rate of VPOS_IN,and VNEG_IN limited to 18V/msec
Vout disabled, no load, ramp rate of VPOS_IN, and VNEG_IN limited to 18V/msec
680nF is required at IOUT pin for 50mH pure inductor load
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Electrical Characteristics (continued)
AVDD/PVDD/VPOS_IN = +15V, VNEG_IN = -15V, VSENSEN = GND = PVSS = 0 V, External DVDD = 2.7 V. VOUT : RL = 1
kΩ, CL = 200 pF, IOUT : RL = 250Ω; all specifications -40C to +125C, unless otherwise noted. REFIN= +5 V external,
REFOUT = +5V internal, Buck-Boost Converter disabled unless otherwise stated
PARAMETER
AC-PSRR
12
AC Power Supply Rejection Ratio
TEST CONDITIONS
200mV 50/60Hz Sine wave
superimposed on power supply
voltage
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MIN
TYP
-75
MAX
UNIT
dB
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SLASEE2 – FEBRUARY 2018
7.6 Timing Requirements: Write and Readback Mode
At TA = –40°C to +125°C and DVDD = +2.7 V to +5.5 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
25
MHz
fSCLK
Max clock frequency
t1
SCLK cycle time
40
ns
t2
SCLK high time
18
ns
t3
SCLK low time
18
ns
t4
SYNC falling edge to SCLK falling edge setup time
15
ns
t5
24th/32nd SCLK falling edge to SYNC rising edge
13
ns
t6
SYNC high time
40
ns
t7
Data setup time
8
ns
t8
Data hold time
5
ns
t9
SYNC rising edge to LDAC falling edge
33
ns
t10
LDAC pulse width low
10
t11
LDAC falling edge to DAC output response time
t12
DAC output settling time
t13
CLR high time
t14
CLR activation time
50
ns
t15
SCLK rising edge to SDO valid
14
ns
t16
SYNC rising edge to DAC output response time
50
ns
t17
LDAC falling edge to SYNC rising edge
100
ns
t18
RESET pulse width
10
ns
t19
SYNC rising edge to CLR falling/rising edge
60
ns
Digital slew rate control disabled
ns
50
See section 5.3
10
ns
µs
ns
t1
SCLK
1
t6
2
24
t3
t4
t5
t2
SYNC
t7
SDIN
t8
t19
MSB
LSB
LDAC = 0
t12
t16
VOUT_x
t10
t9
LDAC
t17
t11
VOUT_x
t13
t19
t19
CLR
t14
VOUT_x
t18
RESET
VOUT_x
Figure 1. Write Mode Timing
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SCLK
1
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2
24
1
2
24
SYNC
Read Command
SDIN
MSB
NOP Command
LSB
MSB
LSB
Readback Data
SDO
MSB
GARBAGE
LSB
t15
Figure 2. Readback Mode Timing
14
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7.7 Typical Characteristics
1.0
8
±10 V
±5 V
0.8
0 V to 10 V
0 V to 5 V
±10 V
±5 V
6
0 V to 10 V
0 V to 5 V
0.6
INL Error (LSB)
DNL Error (LSB)
4
0.4
0.2
0.0
-0.2
2
0
-2
-0.4
-4
-0.6
-6
-0.8
-1.0
-8
0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
D001
0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
D001
Figure 3. VOUT DNL vs Code (DC/DC Enabled)
Figure 4. VOUT INL vs Code (DC/DC Enabled)
1.0
8
±10 V
±5 V
0.8
0 V to 10 V
0 V to 5 V
±10 V
±5 V
6
0 V to 10 V
0 V to 5 V
0.6
INL Error (LSB)
DNL Error (LSB)
4
0.4
0.2
0.0
-0.2
2
0
-2
-0.4
-4
-0.6
-6
-0.8
-1.0
-8
0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
D002
0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
D002
Figure 5. VOUT DNL vs Code (DC/DC Disabled)
Figure 6. VOUT INL vs Code (DC/DC Disabled)
26.0
20.0
±10 V
±5 V
0 V to 10 V
0 V to 5 V
18.0
12.0
14.0
8.0
10.0
6.0
2.0
0.0
-4.0
-8.0
-6.0
-12.0
-10.0
-16.0
-14.0
-20.0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
SLAS
D003
Figure 7. VOUT TUE vs Code (DC/DC Enabled)
0 V to 10 V
0 V to 5 V
4.0
-2.0
0
±10 V
±5 V
16.0
TUE (m%FSR)
TUE (m%FSR)
22.0
0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
SLAS
D004
Figure 8. VOUT TUE vs Code (DC/DC Disabled)
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Typical Characteristics (continued)
8
1.0
6
0.8
0.6
DNL Error (LSB)
INL Error (LSB)
4
2
0
-2
0.4
0.2
0.0
-0.2
-0.4
-4
-0.6
±10 V
±5 V
-6
-8
-40
-25
-10
5
20 35 50 65
Temperature (oC)
0 V to 10 V
0 V to 5 V
80
95
±10 V
±5 V
-0.8
-1.0
-40
110 125
-25
Figure 9. VOUT INL vs Temperature
24.0
Bipolar Zero Error (m%FSR)
30.0
40.0
TUE (m%FSR)
30.0
20.0
10.0
0.0
-10.0
-20.0
-30.0
±10 V
±5 V
-50.0
-40
-25
-10
5
20 35 50 65
Temperature (oC)
0 V to 10 V
0 V to 5 V
80
95
80
95
110 125
D006
18.0
12.0
6.0
0.0
-6.0
-12.0
-18.0
-30.0
-40
110 125
±10 V
±5 V
-25
-10
5
D007
20 35 50 65
Temperature (oC)
80
95
110 125
D008
Figure 12. VOUT Bipolar Zero Error vs Temperature
50.0
50.0
40.0
40.0
30.0
30.0
Gain Error (m%FSR)
Full Scale Error (m%FSR)
20 35 50 65
Temperature (oC)
-24.0
Figure 11. VOUT TUE vs Temperature
20.0
10.0
0.0
-10.0
-20.0
-30.0
±10 V
±5 V
0 V to 10 V
0 V to 5 V
20.0
10.0
0.0
-10.0
-20.0
-30.0
±10 V
±5 V
-40.0
-50.0
-40
-25
-10
5
20 35 50 65
Temperature (oC)
0 V to 10 V
0 V to 5 V
80
95
-40.0
110 125
-50.0
-40
-25
D009
Figure 13. VOUT Full-Scale Error vs Temperature
16
5
Figure 10. VOUT DNL vs Temperature
50.0
-40.0
-10
D005
0 V to 10 V
0 V to 5 V
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
D010
Figure 14. VOUT Gain Error vs Temperature
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Typical Characteristics (continued)
2.0
50.0
Negative Full Scale Error (m%FSR)
0 V to 10 V
0 V to 5 V
1.6
Zero Code Error (mV)
1.2
0.8
0.4
0.0
-0.4
-0.8
-1.2
-1.6
-2.0
-40
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
40.0
30.0
20.0
10.0
0.0
-10.0
-20.0
-30.0
-50.0
-40
110 125
±10 V
±5 V
-40.0
-25
-10
5
20 35 50 65
Temperature (oC)
D011
Figure 15. VOUT Zero-Code Error vs Temperature
80
95
110 125
D012
Figure 16. VOUT Negative Full-Scale Error vs Temperature
8
1.0
6
0.8
0.6
DNL Error (LSB)
INL Error (LSB)
4
2
0
-2
0.4
0.2
0.0
-0.2
-0.4
-4
-0.6
±10 V
±5 V
-6
-8
12
13
14
15
VPOS (V)
16
0 V to 10 V
0 V to 5 V
17
±10 V
±5 V
-0.8
-1.0
12
18
13
50
25
40
20
30
15
20
10
0
-10
-20
-30
±10 V
±5 V
-50
12
13
14
15
VPOS (V)
16
0 V to 10 V
0 V to 5 V
17
Figure 19. VOUT TUE vs VPOS
15
VPOS (V)
16
17
18
D014
Figure 18. VOUT DNL vs VPOS
VOUT Delta (ppm FSR)
TUE Error (m%FSR)
Figure 17. VOUT INL vs VPOS
-40
14
D013
0 V to 10 V
0 V to 5 V
10
5
0
-5
-10
-15
-20
18
-25
-24 -20 -16 -12
D015
-8 -4
0
4
8 12
VOUT Load Current (mA)
16
20
24
D016
Figure 20. VOUT Load Regulation (SCLM = 11)
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Typical Characteristics (continued)
VOUT (2 V/div)
SYNC (5 V/div)
small signal settling (0.1 %FSR/ div)
VOUT (2 V/div)
SYNC (5 V/div)
small signal settling (0.1 %FSR/ div)
Time (4 Ps/div)
Time (4 Ps/div)
D017
Figure 21. VOUT Settling Time, Rising Signal
D018
Figure 22. VOUT Settling Time, Falling Signal
SYNC (5 V/div)
VOUT (50 mV/div)
SYNC (5 V/div)
VOUT (50 mV/div)
Time (0.8 Ps/div)
Time (0.8 Ps/div)
D020
Figure 23. VOUT Major-Carry Glitch, Positive
D021
Figure 24. VOUT Major-Carry Glitch, Negative
VOUT (50 mV/div)
VPOS (5 V/div)
VNEG (5 V/div)
Time (1 ms/div)
D022
Figure 25. VOUT Power-On Glitch
18
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Typical Characteristics (continued)
VOUT (0.2 V/div)
SYNC (5 V/div)
VOUT (10 PV/div)
Time (1 s/div)
Time (0.8 Ps/div)
D023
D024
Figure 26. VOUT Output-Enable Glitch
Figure 27. VOUT Noise (DC/DC Disabled)
1000
VNEG (50 mV/div)
Noise Spectral Density (nV/sqrt-Hz)
VOUT (2 mV/div)
VPOS (0.2 V/divv)
VOUT = 0 V
VOUT = 5 V
VOUT = 10 V
900
800
700
600
500
400
300
200
100
0
10
Time (0.2 ms/div)
100
D025
Figure 28. VOUT DC/DC Ripple (50kHz First-Order Low-Pass
Filter)
100k
1M
D026
Figure 29. VOUT Noise Spectral Density (DC/DC Disabled)
8000
4
VOUT = 0 V
VOUT = 5 V
VOUT = 10 V
7200
6400
3
VPOS/ VNEG IDD (mA)
Noise Spectral Density (nV/sqrt-Hz)
1k
10k
Frequency (Hz)
5600
4800
4000
3200
2400
2
1
IDD-VNEG
IDD-VPOS
0
-1
-2
1600
-3
800
0
10
-4
100
1k
10k
Frequency (Hz)
100k
1M
D027
Figure 30. VOUT Noise Spectral Density (DC/DC Enabled)
0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
D028
Figure 31. VOUT Quiescent Current vs Code (No Load)
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4
4
3
3
VPOS/ VNEG IDD (mA)
VPOS/ VNEG IDD (mA)
Typical Characteristics (continued)
2
1
IDD-VNEG
IDD-VPOS
0
-1
-2
2
1
IDD-VNEG
IDD-VPOS
0
-1
-2
-3
-3
-4
-40
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
-4
12
110 125
13
14
D029
Figure 32. VOUT Quiescent Current vs Temperature (No
Load)
15
VPOS (V)
16
17
18
D030
Figure 33. VOUT Quiescent Current vs VPOS (No Load)
1.0
VOUT (0.5 mV/div)
SCLK (5 V/div)
0.8
DNL Error (LSB)
0.6
0.4
0.2
0.0
-0.2
-0.4
±24 mA
0 mA to 20 mA
0 mA to 24 mA
-0.6
-0.8
3.5 mA to 23.5 mA
4 mA to 20 mA
-1.0
Time (4 Ps/div)
0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
D033
D032
Figure 34. VOUT Digital Feedthrough
Figure 35. IOUT DNL vs Code (DC/DC Enabled)
1.0
8
±24 mA
0 mA to 20 mA
0 mA to 24 mA
6
3.5 mA to 23.5 mA
4 mA to 20 mA
0.8
0.6
DNL Error (LSB)
INL Error (LSB)
4
2
0
-2
0.4
0.2
0.0
-0.2
-0.4
-4
±24 mA
0 mA to 20 mA
0 mA to 24 mA
-0.6
-6
-0.8
-1.0
-8
0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
D033
Figure 36. IOUT INL vs Code (DC/DC Enabled)
20
3.5 mA to 23.5 mA
4 mA to 20 mA
0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
D034
Figure 37. IOUT DNL vs Code (DC/DC Disabled)
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Typical Characteristics (continued)
40
8
±24 mA
0 mA to 20 mA
0 mA to 24 mA
6
3.5 mA to 23.5 mA
4 mA to 20 mA
TUE (m%FSR)
2
0
-2
10
0
-10
-4
-20
-6
-30
-40
-8
0
0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
D034
8
30
6
20
4
10
2
0
-10
-20
±24 mA
0 mA to 20 mA
0 mA to 24 mA
-30
0
-2
-4
3.5 mA to 23.5 mA
4 mA to 20 mA
±24 mA
0 mA to 20 mA
0 mA to 24 mA
-6
-40
0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
D035
Figure 39. IOUT TUE vs Code (DC/DC Enabled)
40
INL (LSB)
TUE (m%FSR)
Figure 38. IOUT INL vs Code (DC/DC Disabled)
-8
-40
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
D036
-25
Figure 40. IOUT TUE vs Code (DC/DC Enabled)
1.0
50
0.8
40
0.6
30
0.4
20
0.2
0.0
-0.2
5
20 35 50 65
Temperature (oC)
80
95
110 125
D037
10
0
-10
-20
-0.4
±24 mA
0 mA to 20 mA
0 mA to 24 mA
-0.6
-0.8
-1.0
-40
-10
3.5 mA to 23.5 mA
4 mA to 20 mA
Figure 41. IOUT INL vs Temperature
TUE (m%FSR)
DNL (LSB)
3.5 mA to 23.5 mA
4 mA to 20 mA
20
4
INL Error (LSB)
±24 mA
0 mA to 20 mA
0 mA to 24 mA
30
-25
-10
5
20 35 50 65
Temperature (oC)
3.5 mA to 23.5 mA
4 mA to 20 mA
80
95
±24 mA
0 mA to 20 mA
0 mA to 24 mA
-30
-40
110 125
-50
-40
-25
D038
Figure 42. IOUT DNL vs Temperature
-10
5
3.5 mA to 23.5 mA
4 mA to 20 mA
20 35 50 65
Temperature (oC)
80
95
110 125
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D039
Figure 43. IOUT TUE vs Temperature
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Typical Characteristics (continued)
50
30.0
18.0
Full Scale Error (m%FSR)
Bipolar Zero Error (m%FSR)
40
±24 mA
24.0
12.0
6.0
0.0
-6.0
-12.0
-18.0
20
10
0
-10
-20
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
-50
-40
110 125
40
40
30
30
Offset Error (m%FSR)
Gain Error (m%FSR)
50
20
10
0
-10
-20
±24 mA
0 mA to 20 mA
0 mA to 24 mA
-40
-25
-10
5
3.5 mA to 23.5 mA
4 mA to 20 mA
20 35 50 65
Temperature (oC)
20 35 50 65
Temperature (oC)
95
95
110 125
D041
0
-10
-20
±24 mA
0 mA to 20 mA
0 mA to 24 mA
-40
80
80
10
-30
-50
-40
110 125
-25
-10
5
3.5 mA to 23.5 mA
4 mA to 20 mA
20 35 50 65
Temperature (oC)
D042
80
95
110 125
D043
Figure 47. IOUT Offset Error vs Temperature
50
8
40
6
±24 mA
30
4
20
INL Error (LSB)
Negative Full Scale Error (m%FSR)
5
20
Figure 46. IOUT Gain Error vs Temperature
10
0
-10
2
0
-2
-20
-4
±24 mA
-30
-6
-40
-50
-40
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
-8
12
13
D044
Figure 48. IOUT Negative Full-Scale Error vs Temperature
22
-10
3.5 mA to 23.5 mA
4 mA to 20 mA
Figure 45. IOUT Full-Scale Error vs Temperature
50
-30
-25
D040
Figure 44. IOUT Bipolar Zero Error vs Temperature
-50
-40
±24 mA
0 mA to 20 mA
0 mA to 24 mA
-30
-40
-24.0
-30.0
-40
30
14
15
VPOS (V)
16
17
18
D045
Figure 49. IOUT Bipolar Range INL vs VPOS
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Typical Characteristics (continued)
1.0
8
0 mA to 20 mA
0 mA to 24 mA
6
3.5 mA to 23.5 mA
4 mA to 20 mA
0.8
±24 mA
0.6
DNL Error (LSB)
INL Error (LSB)
4
2
0
-2
0.4
0.2
0.0
-0.2
-0.4
-4
-0.6
-6
-0.8
-8
12
-1.0
12
14
16
18
20
22
24
VPOS (V)
26
28
30
32
Figure 50. IOUT Unipolar Ranges INL vs VPOS
15
VPOS (V)
16
17
18
D046
50
0 mA to 20 mA
0 mA to 24 mA
0.8
3.5 mA to 23.5 mA
4 mA to 20 mA
40
30
TUE Error (m%FSR)
0.6
DNL Error (LSB)
14
Figure 51. IOUT Bipolar Range DNL vs VPOS
1.0
0.4
0.2
0.0
-0.2
-0.4
10
0
-10
-20
-30
-0.8
-40
14
16
18
20
22
24
VPOS (V)
26
28
30
32
±24 mA
20
-0.6
-1.0
12
13
D045
-50
12
13
D046
Figure 52. IOUT Unipolar Ranges DNL vs VPOS
14
15
VPOS (V)
16
17
18
D047
Figure 53. IOUT Bipolar Range TUE vs VPOS
50
40
TUE (m%FSR)
30
IOUT (8 mA/div)
SYNC (5 V/div)
small signal (0.1 %FSR/ div)
20
10
0
-10
-20
-30
0 mA to 20 mA
0 mA to 24 mA
-40
-50
12
14
16
18
20
22
24
VPOS (V)
3.5 mA to 23.5 mA
4 mA to 20 mA
26
28
30
Time (2 Ps/div)
32
D048
D047
Figure 54. IOUT Unipolar Ranges TUE vs VPOS
Figure 55. IOUT Settling Time, Rising Signal
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Typical Characteristics (continued)
IOUT (8 mA/div)
SYNC (5 V/div)
small signal (0.1 %FSR/ div)
IOUT (8 mA/div)
SYNC (5 V/div)
Time (2 Ps/div)
Time (2 Ps/div)
D049
Figure 56. IOUT Settling Time, Falling Signal
D050
Figure 57. IOUT Settling Time, Bipolar Range, Rising Signal
IOUT (160 PA/div)
SYNC (5 V/div)
IOUT (8 mA/div)
SYNC (5 V/div)
Time (800 ns/div)
Time (2 Ps/div)
D053
D051
Figure 58. IOUT Settling Time, Bipolar Range, Falling Signal
Figure 59. IOUT Major Carry Glitch, Positive
IOUT (4 PA/div)
VPOS (5 V/div)
IOUT (400 PA/div)
SYNC (5 V/div)
Time (800 ns/div)
Time (1 ms/div)
D054
Figure 60. IOUT Major Carry Glitch, Negative
24
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D055
Figure 61. IOUT Power On Glitch
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Typical Characteristics (continued)
IOUT (40 nA/div)
IOUT (8 PA/div)
SYNC (5 V/div)
Time (1 s/div)
Time (0.8 Ps/div)
D056
D057
Figure 62. IOUT Output Enable Glitch
Figure 63. IOUT Noise (DC/DC Disabled)
1000
Noise Spectral Density (nV/sqrt-Hz)
IOUT (4 PA/div)
VPOS (5 mV/div)
IOUT = 0 mA
IOUT = 12 mA
IOUT = 24 mA
900
800
700
600
500
400
300
200
100
0
10
Time (20 ms/div)
100
1k
10k
Frequency (Hz)
100k
1M
D059
Figure 64. IOUT DC/DC Ripple (50kHz First-Order Low-Pass
Filter)
Figure 65. IOUT Noise Spectral Density (DC/DC Disabled)
1000
30
IOUT = 0 mA
IOUT = 12 mA
IOUT = 24 mA
900
800
700
600
500
400
300
18
12
6
0
-6
-12
200
-18
100
-24
0
10
IDD-VNEG
IDD-VPOS
24
VPOS/ VNEG IDD (mA)
Noise Spectral Density (nV/sqrt-Hz)
D058
-30
100
1k
10k
Frequency (Hz)
100k
1M
D060
Figure 66. IOUT Noise Spectral Density (DC/DC Enabled)
0
8192 16384 24576 32768 40960 49152 57344 65536
DAC Code
D061
Figure 67. IOUT Quiescent Current vs Code, Bipolar Range
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2.5
2.5
2.0
2.0
1.5
1.5
VPOS/ VNEG IDD (mA)
VPOS/ VNEG IDD (mA)
Typical Characteristics (continued)
1.0
0.5
0.0
-0.5
-1.0
-1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
IDD-VNEG
IDD-VPOS
-2.0
-2.5
-40
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
IDD-VNEG
IDD-VPOS
-2.0
-2.5
12
110 125
13
14
15
VPOS (V)
D062
Figure 68. IOUT Quiescent Current vs Temperature
16
17
18
D063
Figure 69. IOUT Quiescent Current vs VPOS
5.005
IOUT (2 PA/div)
SCLK (5 V/div)
5.004
Reference Output (V)
5.003
5.002
5.001
5.000
4.999
4.998
4.997
4.996
4.995
-40
Time (4 Ps/div)
-25
-10
5
D065
5.005
5.005
5.004
5.004
5.003
5.003
5.002
5.001
5.000
4.999
4.998
4.997
95
110 125
D066
5.002
5.001
5.000
4.999
4.998
4.997
4.996
4.996
4.995
4.995
12
-5
-4
-3
-2
-1
0
1
Load Current (mA)
2
3
4
5
14
D067
Figure 72. Internal Reference Voltage vs Load
26
80
Figure 71. Internal Reference Voltage vs Temperature
Reference Output (V)
Reference Output (V)
Figure 70. IOUT Digital Feed-Through
20 35 50 65
Temperature (oC)
16
18
20
22 24 26
AVDD (V)
28
30
32
34
36
D068
Figure 73. Internal Reference Voltage vs AVDD
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1000
1000
900
900
Noise Spectral Density (nV/sqrt-Hz)
Noise Spectral Density (nV/sqrt-Hz)
Typical Characteristics (continued)
800
700
600
500
400
300
200
100
0
10
100
1k
10k
Frequency (Hz)
100k
800
700
600
500
400
300
200
100
0
10
1M
100
1k
10k
Frequency (Hz)
D070
Figure 74. Internal Reference Voltage Noise Spectral
Density (DC/DC Disabled)
100k
1M
D071
Figure 75. Internal Reference Voltage Noise Spectral
Density (DC/DC Enabled)
VPOS (20 mV/div)
VREF (5 mV/div)
VREF (10 PV/div)
Time (1 s/div)
Time (0.1 ms/div)
D072
D074
Figure 76. Internal Reference Voltage Noise (DC/DC
Disabled)
Figure 77. Internal Reference Voltage DC/DC Ripple
100
90
VPOS Efficiency (%)
80
VNEG (2 V/div))
VPOS (1 V/div)
SYNC (5 V/div))
70
60
50
12V, RL = 250:
24V, RL = 250:
36V, RL = 250:
12V, RL = 1k:
24V, RL = 1k:
36V, RL = 1k:
40
30
20
10
0
Time (2 ms/div)
0
2
D075
Figure 78. VPOS & VNEG Enable Settling Time
4
6
8
10 12 14
IOUT (mA)
16
18
20
22
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D077
Figure 79. IOUT VPOS Efficiency
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Typical Characteristics (continued)
100
100
12V, RL = 250:
24V, RL = 250:
36V, RL = 250:
12V, RL = 1k:
24V, RL = 1k:
36V, RL = 1k:
IOUT Efficiency (%)
80
70
60
90
80
VPOS Efficiency (%)
90
50
40
30
70
60
50
30
20
20
10
10
0
0
2
4
6
8
10 12 14
IOUT (mA)
16
18
20
22
12V, RL = 250:
24V, RL = 250:
36V, RL = 250:
12V, RL = 1k:
24V, RL = 1k:
36V, RL = 1k:
40
0
-40
24
Figure 80. IOUT DC/DC Efficiency
450
PVDD Power Dissipation (mW)
500
90
IOUT Efficiency (%)
80
70
60
50
40
30
12V, RL = 250:
24V, RL = 250:
36V, RL = 250:
10
0
-40
12V, RL = 1k:
24V, RL = 1k:
36V, RL = 1k:
20 35 50 65
Temperature (oC)
80
95
110 125
D079
400
350
300
250
200
150
100
50
0
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
0
2
4
6
8
D080
10 12 14
IOUT (mA)
16
18
20
22
24
D081
Figure 83. IOUT Power Dissipation vs Load
50
800
12V, RL = 250:
24V, RL = 250:
36V, RL = 250:
700
12V, RL = 1k:
24V, RL = 1k:
36V, RL = 1k:
45
40
600
Die Temperature (oC)
PVDD Power Dissipation (mW)
5
12V, RL = 250:
24V, RL = 250:
36V, RL = 250:
12V, RL = 1k:
24V, RL = 1k:
36V, RL = 1k:
Figure 82. IOUT DC/DC Efficiency vs Temperature
500
400
300
200
35
30
25
20
15
10
100
5
0
-40
12V, RL = 250:
24V, RL = 250:
36V, RL = 250:
12V, RL = 1k:
24V, RL = 1k:
36V, RL = 1k:
10 12 14
IOUT (mA)
18
0
-25
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
0
2
D082
Figure 84. IOUT Power Dissipation vs Temperature
28
-10
Figure 81. VPOS Efficiency vs Temperature
100
20
-25
D078
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4
6
8
16
20
22
24
D083
Figure 85. IOUT Die Temperature vs Load
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Typical Characteristics (continued)
VPOS Spectral Density (PV / sqrt-Hz)
50
IOUT = 0 mA
IOUT = 12 mA
IOUT = 24 mA
45
40
35
VNEG (5 V/div)
VPOS (5 V/div)
SYNC (5 V/div)
30
25
20
15
10
5
0
10
100
1k
10k
Frequency (Hz)
100k
Time (2 ms/div)
1M
D086
D085
Figure 87. VOUT Enable VPOS and VNEG Settling Time
Figure 86. IOUT VPOS Noise Spectral Density
100
100
PVDD = 12 V
PVDD = 24 V
PVDD = 36 V
90
80
VPOS Efficiency (%)
VPOS Efficiency (%)
80
70
60
50
40
30
70
60
50
40
30
20
20
10
10
0
-40
0
0
1
2
3
4
5
6
VOUT Load (mA)
7
8
9
10
-25
-10
5
D087
Figure 88. VOUT VPOS Efficiency vs Load
20 35 50 65
Temperature (oC)
80
95
110 125
D088
Figure 89. VOUT VPOS Efficiency vs Temperature
500
500
PVDD = 12 V
PVDD = 24 V
PVDD = 36 V
400
450
PVDD Power Dissipation (mW)
450
PVDD Power Dissipation (mW)
PVDD = 12 V
PVDD = 24 V
PVDD = 36 V
90
350
300
250
200
150
100
50
400
350
300
250
200
150
PVDD = 12 V
PVDD = 24 V
PVDD = 36 V
100
50
0
0
1
2
3
4
5
6
VOUT Load (mA)
7
8
9
10
0
-40
-25
D089
Figure 90. VOUT Power Dissipation vs Load
-10
5
20 35 50 65
Temperature (oC)
80
95
110 125
D090
Figure 91. VOUT Power Dissipation vs Temperature
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Typical Characteristics (continued)
250
50
Die Temperature (oC)
40
VPOS Spectral Density (PV / sqrt-Hz)
PVDD = 12 V
PVDD = 24 V
PVDD = 36 V
45
35
30
25
20
15
10
5
1
2
3
4
5
6
VOUT Load (mA)
7
8
9
200
175
150
125
100
75
50
25
0
10
0
0
10
1M
D093
Forward Sweep
Reverse Sweep
3.2
DVDD Current (mA)
VNEG Spectral Density (PV / sqrt-Hz)
100k
3.4
VOUT = 0 V
VOUT = 5 V
VOUT = 10 V
105
90
75
60
45
3.0
2.8
2.6
2.4
2.2
30
2.0
15
0
10
100
1k
10k
Frequency (Hz)
100k
1M
1.8
0.0
0.5
D094
Figure 94. VPOS VNEG Noise Spectral Density
30
1k
10k
Frequency (Hz)
Figure 93. VOUT VPOS Noise Spectral Density
150
120
100
D091
Figure 92. VOUT Die Temperature vs Load
135
VOUT = 0 V
VOUT = 5 V
VOUT = 10 V
225
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1.0
1.5
2.0 2.5 3.0 3.5
Logic Level (V)
4.0
4.5
5.0
5.5
D095
Figure 95. DVDD Iq vs Logic Level
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8 Detailed Description
8.1 Overview
The DAC8771 consists of a resistor-string digital-to-analog converter (DAC) followed by buffer amplifiers. The
output of the buffer drives the current output stage and the voltage output amplifier. The resistor-string section is
simply a string of resistors, each of value R, from REFIN to GND, as Functional Block Diagram illustrates. This
type of architecture ensures DAC monotonicity. The 16-bit binary digital code loaded to the DAC register
determines at which node on the string the voltage is tapped off before being fed into the output amplifier. The
current output stage converts the output from the string to current using a precision current source. The voltage
output provides a voltage output to the external load. When the current output stage is disabled the IOUT pin is
Hi-Z. When the voltage output stage is disabled, the output impedance is controlled by the POC bit, by default
set to 30 kΩ. After power-on, both output stages are disabled. The DAC8771 also contains a Buck-Boost
converter which can be used to generate the power supply for the current output stage and voltage output
amplifier.
8.2 Functional Block Diagram
REFIN
Buck-Boost
Converter
VPOS_IN
Current
Source
Current Out
Voltage Out
IOUT
VOUT
VNEG_IN
GND
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Figure 96. General Architecture
8.3 Feature Description
8.3.1 Current Output Stage
The current output stage consists of a pre-conditioner and a precision current source as shown in Figure 97. This
stage provides a current output according to the DAC code. The output range can be programmed as 0 mA - 20
mA, 0 mA - 24 mA, 4 mA - 20 mA, 3.5 mA - 23.5 mA, or ±24 mA. In the current output mode, the maximum
compliance voltage on pin IOUT is between (-|VNEG_IN| + 3 V) ≤ |VIOUT| ≤ (VPOS_IN – 3 V). When in unipolar
current output modes the low-side of the compliance voltage limit is replaced by GND. This compliance voltage is
automatically maintained when the Buck-Boost converter is used to generate these supplies (see Buck-Boost
Converter section). However, when using an external supply for VPOS_IN pin (Buck-Boost converter disabled),
the VPOS_IN and VNEG_IN supplies should be chosen such that this compliance voltage is maintained.
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Feature Description (continued)
VPOS_IN
Rsense
Sourcing
PMOS
DAC
IOUT
Sinking
NMOS
Iload
Rload
Rsense
VNEG_IN
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Figure 97. Current Output
The 16 bit data can be written to DAC8771 using address 0x05 (DAC data register, Table 4 and Table 5).
For a 0-mA to 20-mA output range:
+176 = 20I# T d
%1&'
h
20
(1)
For a 0-mA to 24-mA output range:
+176 = 24I# T d
%1&'
h
20
(2)
For a 3.5-mA to 23.5-mA output range:
%1&'
+176 = 20I# T d 0 h + 3.5I#
2
(3)
For a 4-mA to 20-mA output range:
%1&'
+176 = 16I# T d 0 h + 4I#
2
(4)
For a -24-mA to 24-mA output range:
%1&'
+176 = 40I# T d 0 h F 20I#
2
(5)
Where:
• CODE is the decimal equivalent of the code loaded to the DAC.
• N is the bits of resolution; 16
32
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Feature Description (continued)
8.3.2 Voltage Output Stage
The voltage output stage as conceptualized in Figure 98 provides the voltage output according to the DAC code
and the output range setting. The output range can be programmed as 0 V to +5 V or 0 V to +10 V for unipolar
output mode, and ±5 V or ±10V for bipolar output mode. In addition, an option is available to increase the output
voltage range by 20%. The output current drive can be up to 34 mA. The output stage has short-circuit current
protection that limits the output current to 16 mA, this limit can be changed to 8 mA, 20 mA or 24 mA via writing
bits 15 and 14 of address 0x04. The minimum headroom and foot-room for the voltage output stage is
automatically maintained when the Buck-Boost converter is used to generate these supplies. However, when
using an external supply for VPOS_IN and VNEG_IN pin (Buck-Boost converter disabled) the minimum
headroom and foot-room as per must be maintained. In this case, the Recommended Operating Conditions
shows the maximum allowable difference between VPOS_IN and VNEG_IN.
The voltage output is designed to drive capacitive loads of up to 1 μF. For loads greater than 20 nF, an external
compensation capacitor must be connected between CCOMP and VOUT to keep the output voltage stable at the
expense of reduced bandwidth and increased settling time. Note that, a step response (due to input code
change) on the voltage output pin loaded with large capacitive load (> 20 nF) triggers the short circuit limit circuit
of the output stage. This results in setting the short circuit alarm status bits. Therefore, it is recommended to use
slew rate control for large step change, when the voltage output pin is loaded with high capacitive loads.
R3
120K
VSENSEP
S1
R2
120K
VOUT
DAC
R0
120K
R2
17K t 24K
RFB
60K
R1
120K
REFIN
S3
R1
42K - Open
VSENSEN
S2
Copyright © 2018, Texas Instruments Incorporated
Figure 98. Voltage Output
The VSENSEP pin is provided to enable sensing of the load. Ideally, it is connected to VOUT at the terminals.
Additionally, it can also be used to connect remotely to points electrically "nearer" to the load. This allows the
internal output amplifier to ensure that the correct voltage is applied across the load as long as headroom is
available on the power supply. However, if this line is cut, the amplifier loop would be broken. Therefore, an
optional resistor can be used between VOUT and VSENSEP to prevent this.
The VSENSEN pin can be used to sense the remote ground and offset the VOUT pin accordingly. The
VSENSEN pin can sense a maximum of ±7 V difference from the GND pin of the DAC8771.
The 16 bit data can be written to DAC8771 as shown in DAC data registers,Table 4 and Table 5.
For unipolar output mode:
%1&'
8176 = 84'(+0 T )#+0 T d 0 h
2
(6)
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Feature Description (continued)
For bipolar output mode:
8176 = 84'(+0 T )#+0 T d
%1&'
)#+0 T 84'(+0
F
h
20
2
(7)
Where:
• CODE is the decimal equivalent of the code loaded to the DAC.
• N is the bits of resolution; 16
• VREFIN is the reference voltage; for internal reference, VREFIN = +5 V.
• GAIN is automatically selected for a desired voltage output range as shown in
8.3.3 Buck-Boost Converter
The DAC8771 includes a Buck-Boost Converter to minimize the power dissipation of the chip and provides
significant system integration. This Buck-Boost converter is based on a Single Inductor Multiple Output (SIMO)
architecture and requires a single inductor to simultaneously generate all the analog power supplies required by
the chip. The Buck-Boost converter uses three on-chip switches (shown in Figure 99) which are synchronously
controlled via current mode control logic. The DC/DC converter is designed to work in discontinuous conduction
mode (DCM) with an external inductor of value 100 µH connected between LN and LP pins (see Buck-Boost
Converter External Component Selection section). The peak inductor current inductor is limited to a value of 0.5
A internally.
LN
LP
PVDD
VPOS_IN
External Inductor
PVSS
External
Schottky
Diodes
PVSS
VNEG_IN
Figure 99. Buck-Boost Converter
The Buck-Boost converter employs a variable switching frequency technique. This technique increases the
converter efficiency at all loads by automatically reducing the switching frequency at light loads and increasing it
at heavy loads. At no load condition, the converter stops switching completely until the load capacitor discharges
by a preset voltage. At this point, the converter automatically starts switching and recharges the load
capacitor(s). In addition to saving power at all loads, this technique ensures low switching noise on the converter
outputs at light loads. The minimum load capacitor for the Buck-Boost converter is 10 µF. This capacitor must be
connected between the Schottky diode(s) and ground (0 V) for each arm of the Buck-Boost converter. The BuckBoost converter, when enabled, generates ripples on the supply pins (VPOS_IN and VNEG_IN). This ripple is
typically attenuated by the power supply rejection ratio of the output amplifiers (IOUT or VOUT) and appears as
noise on the output pin of the amplifiers (IOUT and VOUT). A larger load capacitor in combination with additional
filter (see application section) reduces the output ripple at the expense of increasing settling time of the converter
output.
The input voltage to the Buck-Boost converter (pin PVDD) can vary from +12 V to +36 V. These outputs can be
individually enabled or disabled via the user SPI interface (See Commands in Table 4 and Table 5).
8.3.3.1 Buck-Boost Converter Outputs
The Buck-Boost converter can be used to provide power to the current output stage or the voltage output stage
by enabling the Buck-Boost converter and connecting the power supplies as shown in Figure 100. Additional
passive filters can optionally be added between the Schottky diode and input supply pins (VPOS_IN and
VNEG_IN) to attenuate the ripple feeding into the VPOS_IN and VNEG_IN pin.
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Feature Description (continued)
D1
DAC8771
Rfilt1
LN
Cfilt1
Cload
AGND
PVSS
VPOS_IN
D2
Rfilt2
LP
Cfilt2
Cload
PVSS
VNEG_IN
AGND
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Figure 100. Buck-Boost Converter Positive and Negative Outputs
8.3.3.2 Selecting and Enabling Buck-Boost Converter
The analog outputs of the Buck-Boost converter can be enabled in two different ways: Current Output Mode or
Voltage Output Mode. The positive/negative arm of the selected Buck-Boost converter can be enabled via writing
to address 0x07 (Configuration Buck-Boost Register (address = 0x07) [reset = 0x0000]). Note that, VNEG_IN is
internally shorted to GND when the negative arm of Buck-Boost converter is not enabled.
When used in voltage output mode, the Buck-Boost converter generates a constant ±15.0 V for the positive and
negative power supplies.
When used in current output mode the Buck-Boost converter generates the positive and negative power supply
based on the RANGE setting, for example the negative power supply is only generated for ±24 mA range.
The minimum voltage that the Buck-Boost converter can generate on the VPOS_IN pin in 4.96 V with a typical
efficiency of 75% at PVDD = 12 V and a load current of 24 mA, thus significantly minimizing power dissipation on
chip. The maximum voltage that the Buck-Boost converter can generate on the VPOS_IN pin is 32 V. Similarly,
the minimum voltage that the Buck-Boost converter can generate on the VNEG_IN pin in -15.0 V. The maximum
voltage that the Buck-Boost converter can generate on the VNEG_IN pin in -5.0 V
8.3.3.3 Configurable Clamp Feature and Current Output Settling Time
A large signal step on the output pin IOUT (for example 0 mA to 24 mA) with a load of 1 KΩ would require that
the respective Buck-Boost converter change the output voltage on the VPOS_IN pin from 4.0 V to 27 V. Thus,
the current output settling time will be dominated by the settling time of the VPOS_IN voltage. A trade off can be
made to reduce the settling time at the expense of power saving by increasing the minimum voltage that the
respective Buck-Boost converter generates on the positive output.
The DAC8771 implements a configurable clamp feature. This feature allows multiple modes of operation based
on CCLP[1:0] and HSCLMP bits (Configuration Buck-Boost Register (address = 0x07) [reset = 0x0000]).
8.3.3.3.1 Default Mode - CCLP[1:0] = "00"
This is the default mode of operation, CCLP[1:0] = "00" for Buck-Boost converter is to be in full tracking mode.
The minimum voltage generated on VPOS_IN in this case is 4 V. The Buck-Boost converter varies the positive
and negative outputs adaptively such that the voltage across these outputs and IOUT pins is ≤ 3 V. This is
accomplished by internally feeding back the voltage across the current output PMOS and NMOS to the
respective Buck-Boost converter control circuit. For example, for a load current of 24 mA flowing through a load
resistance of 1 KΩ, the generated voltage at the VPOS_IN pin will be around 27V.
8.3.3.3.2 Fixed Clamp Mode - CCLP[1:0] = "01"
In this mode of operation, the user can over-rides the default operation by writing "01" to CCLP[1:0]. The
minimum voltage generated on VPOS_IN and VNEG_IN can be adjusted by writing to PCLMP[3:0] / NCLMP[3:0]
(address 0x07).
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Feature Description (continued)
8.3.3.3.3 Auto Learn Mode - CCLP[1:0] = "10"
In this mode ,the device automatically senses the load on the current output terminal and sets the minimum
voltage generated on VPOS_IN terminals to a fixed value. The value is calculated such that for any code
change, the settling time is dependent only on the DAC settling time. For example, with a load of 250 Ω and a
maximum current of 24 mA, the Buck-Boost output voltage is set as 9 - 12 V. This achieves the maximum power
saving without sacrificing settling time because the Buck-Boost output is fixed.
In order to ensure the correct operation of auto-learn mode, following steps below must be followed.
1. The device must be enabled in full tracking mode, CCLP[1:0] = "00".
2. Current output is enabled and a code greater then 4000h should be written to the DAC.
3. Write CCLP[1:0] = "10" to enable auto learn mode.
At this point, the clamp register (PCLMP - address 0x07) is populated with the appropriate settings. The clamp
status bit CLST (address 0x0B) is set once the clamp register is populated indicating the completion of this
process. In this mode the PCLMP bits are read only. Typically, this process of sensing the load is done only once
after power up. In order to re initiate this process, the CCLP bits must be rewritten with "10".
8.3.3.3.4 High Side Clamp (HSCLMP)
The default maximum positive voltage that the Buck-Boost converter can generate is 32 V. However, this voltage
can be reduced to 26 V by writing '1' to HSCLMP bit (address 0x0E Table 5). Note that this feature can be
enabled or disabled per channel by selecting the corresponding channel (address 0x03 )
8.3.4 Analog Power Supply
The DAC8771 is designed to operate with a single power supply (12 V to 36 V) using integrated Buck-Boost
converter. In this mode, pins PVDD and AVDD must be tied together and driven by the same power supply.
VPOS_IN and VNEG_IN will be enabled as programmed by the device registers. It is recommended that DVDD
is applied first to reduce output transients.
The DAC8771 can also be operated without using the integrated Buck-Boost converter. In this mode, pins PVDD,
AVDD, and VPOS_IN must be tied together and driven by the same power supply (12 V to 33 V). In this mode in
order to reduce output transients it is recommended that DVDD is applied first, followed by VPOS_IN / PVDD /
AVDD and finally REFIN.Note that in this mode, the minimum required head room and foot room for the output
amplifiers must be met.
Recommended Operating Conditions shows the maximum and minimum allowable limits for all the power
supplies when DAC8771 is powered using external power supplies.
8.3.5 Digital Power Supply
The digital power supply to DAC8771 can be internally generated or externally supplied. This is determined by
the status of DVDD_EN pin.
When the DVDD_EN pin is left floating, the voltage on DVDD pin is generated via an internal LDO. The typical
value of the voltage generated on DVDD pin is 5 V. In this mode, the DVDD pin can also be used to power other
digital components on the board. The maximum drive capability of this pin is 10mA. Please note that to ensure
stability the minimum load capacitance on this pin is limited to 100 pF, where as the maximum load capacitance
is limited to 0.2 µF.
When the DVDD_EN pin is tied to 0V, the internal LDO is disabled and the DVDD pin must be powered via an
external digital supply.
8.3.6 Internal Reference
The DAC8771 includes an integrated 5V reference with an initial accuracy of ±10 mV maximum and a
temperature drift coefficient of 10 ppm/°C maximum. A buffered output capable of driving up to 5 mA is available
on REFOUT. The internal reference for DAC8771 is disabled by default. To enable the internal reference,
REF_EN bit on address 0x02h must be set to '1' (Table 5).
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Feature Description (continued)
It is recommended to follow JEDEC standardized solder reflow parameters for surface mount devices, as is
typically provided by most contract PCB assembly services. Failure to adhere to suggested JEDEC standards
can result in excessively high temperatures in the solder process or excessive time exposed to high
temperatures, which can induce mechanical stress on thin-packages, such as QFNs, resulting in parametric
degradation in many band-gap reference topologies.
8.3.7 Power-On-Reset
The DAC8771 contain power on reset circuits which is based on AVDD and DVDD power supplies. After poweron, the power-on-reset circuit ensures that all registers are at their default values (Table 4). The current, voltage
output DAC, and the Buck-Boost converter are disabled. The current output pin is in high impedance state.
The voltage output pin is in a 30kΩ-to-GND state; however, the VSENSEP pin is an open circuit. If the VOUT
and VSENSEP pins are connected together, the VOUT pin would also be connected to GND through the same
resistor. The VOUT pin connection to GND can be reconfigured to high-impedance through the POC bit. This
resistor is disconnected when the voltage output is enabled. The Buck-Boost converter for each channel are
powered off at power-on reset.
8.3.8 ALARM Pin
The DAC8771 contains an ALARM pin. When one or more of following events occur, the ALARM pin is pulled
low:
1. The load on the IOUT pin is in open circuit (>500µsec); or
2. The voltage at IOUT, when enabled, reaches a level where the accuracy of the output current would be
compromised (>500µsec). This condition is detected by monitoring internal voltage levels of the IOUT
circuitry and will typically be below the specified compliance voltage minimum of 3V; or
3. The die temperature has exceeded +150°C; or
4. The SPI watchdog timer exceeded the timeout period (if enabled); or
5. The SPI frame error check (CRC) encountered an error (if enabled)
6. A short circuit current limit is reached (>500µsec) on any VOUT when enabled in voltage output mode
7. The Buck-Boost converter has reached the maximum output voltage (set by bit HSCLMP Table 5 address
0x0E)
When connecting the ALARM pins of multiple DAC8771 devices together, forming a wired-AND function, the host
processor should read the status register of each device to know all the fault conditions that are present.
The ALARM pin continuously monitors the above mentioned conditions and returns to open drain condition if the
alarm condition is removed (non-latched behavior - default). For condition (1) mentioned above and Buck-Boost
converter used to power the DAC, the ALARM pin if pulled low due to the alarm condition will remain pulled low
even after the alarm condition is removed (latched behavior). In this condition the alarm pin can be reset by
1. Resetting the corresponding fault bits in the status register (address 0x0B Table 5); or
2. Performing software reset (write to address 0x01 Table 5); or
3. Toggling hardware reset pin; or
4. Performing power on reset
Note that if the alarm action bits are programmed to "10" (AC_IOC[1:0], the Buck-Boost converter and the current
output amplifier are automatically disabled upon the event of open circuit on current output. In this case, the
ALARM automatically resets to the default behavior (non-latched behavior).
8.3.9 Power GOOD bit
The Buck-Boost converter in DAC8771 has a read only bit called power good (PG) (address 0x0B Table 5). This
bit is set to logic '1' when both of the following conditions are met
1. The VPOS_IN > 4V (if enabled) and
2. The VNEG_IN < -3V (if enabled)
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Feature Description (continued)
The PG bit indicates the status of the outputs of the enabled Buck-Boost converter. For example, if the positive
and negative outputs of the Buck-Boost converter are enabled, then the PGA bit is set to a logic '1' only after the
positive output pins of the Buck-Boost converter are ≥ 4 V and the negative output pin of Buck-boost converter is
≤ -3 V.
8.3.10 Status Register
Since, DAC8771 contains one ALARM pin for the entire chip, the status of individual fault condition can be
checked using the status register. This register (see ) consists of five types of ALARM status bits (Faults on
current and voltage outputs , Over temperature condition, CRC errors, Watchdog timeout and Buck-Boost
converter power good) and two status bit (User toggle, Auto Learn status). The device continuously monitors
these conditions. When an alarm occurs, the ALARM pin is pulled low and the corresponding status bit is set
('1'). Whenever one of these status bits is set, it remains set until the user clears it by writing '1' to corresponding
bit on address 0x0B. The status bit can also be cleared by performing a hardware reset, software reset, or
power-on reset, note that it takes a minimum of 8 µsec for the status register to get reset. These bits are
reasserted if the ALARM condition continues to exist in the next monitoring cycle.
8.3.11 Status Mask
The ALARM pin for DAC8771 is triggered by any of the alarm condition ALARM Pin . However, these different
alarm conditions can be masked from creating the alarm signal at the pin by using the status mask register. The
status mask register (address 0x0C ) has the same bit order as the status register except that it can be set to
mask any or all status bits that create the alarm signal.
8.3.12 Alarm Action
The DAC8771 implements an alarm action register (address 0x0D,). By writing to this register, the user can
select the action that the device takes automatically in case of a specific alarm condition. If different setting are
chosen for different alarm conditions, the following priority (high to low) is considered when taking action:
1. Over temperature alarm
2. Output fault alarm
3. CRC error/Watchdog timer fault alarm
This device also contains a 6 bit alarm code register (address 0x0E Table 5) which can be loaded to the DAC if
the alarm action register is set to "01". Note that the alarm code, once set, remains set even if the alarm
condition is removed. Also note that the alarm action change to the programmed code is a step function even if
slew rate control is enabled.
8.3.13 Watchdog Timer
This feature is useful to ensure that communication between the host processor and the DAC8771 has not been
lost. It can be enabled by setting the WEN (address 0x03) bit to '1', see . The watchdog timeout period can be
set using the WPD[1:0] address 0x03) bits. The timer period is based off an internal oscillator with a typical value
of 8 MHz
If enabled, the chip must have an SPI frame with 0x10 as the write address byte written to the device within the
programmed timeout period. Otherwise, the ALARM pin asserts low and the WDT bit (address 0x0B) of the
status register is set to '1'. The WDT bit is set to '0' with a software/hardware reset, or by disabling the watchdog
timer (WEN = '0'), or powering down the device.
When using multiple DAC8771 devices in a daisy-chain configuration, the open-drain ALARM pins of all devices
can be connected together to form a wired-AND network. The watchdog timer can be enabled in any number of
the devices in the chain although enabling it in one device in the chain should be sufficient. The wired-AND
ALARM pin may get pulled low because of the simultaneous presence of different trigger conditions in the
devices in the daisy-chain. The host processor should read the status register of each device to know all the fault
conditions present in the chain.
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Feature Description (continued)
8.3.14 Programmable Slew Rate
The slew rate control feature allows the user to control the rate at which the output voltage or current changes.
This feature is disabled by default and can be enabled for the selected channel by writing logic '1' to the SREN
bit at address 0x04 (see ). With the slew rate control feature disabled, the output changes smoothly at a rate
limited by the output drive circuitry and the attached load.
With this feature enabled, the output does not slew directly between the two values. Instead, the output steps
digitally at a rate defined by bits [2:0] (SR_STEP) and bits [3:0] (SRCLK_RATE) on address 0x04 (see).
SR_RATE defines the rate at which the digital slew updates; SRCLK_STEP defines the amount by which the
output value changes at each update. shows different settings for SRCLK_STEP and SR_RATE.
The time required for the output to slew over a given range can be expressed as Equation 8:
5HAS 6EIA =
1QPLQP %D=JCA
5PAL 5EVA T 7L@=PA %HK?G (NAMQAJ?U T .5$ 5EVA
(8)
Where:
• Slew Time is expressed in seconds
• Output Change is expressed in amps (A) for current output mode or volts (V) for voltage output mode
When the slew rate control feature is enabled, the output changes happen at the programmed slew rate. This
configuration results in a staircase formation at the output. If the CLR pin is asserted, the output slews to the
zero-scale value at the programmed slew rate. When a new DAC data is written, the output starts slewing to the
new value at the slew rate determined by the current DAC code and the new DAC data. The update clock
frequency for any given value is the same for all output ranges. The step size, however, varies across output
ranges for a given value of step size because the LSB size is different for each output range.
Note that disabling the slew rate feature while the DAC is executing the slew rate command will abort the slew
rate operation and the DAC output will stay at the last code after which the slew rate disable command was
acknowledged.
8.3.15 HART Interface
On the DAC8771, digital communication such as HART can be modulated onto the current output signal.
If the RANGE (address 0x04) bits are programmed such that the IOUT is enabled, the external HART signal (ac
voltage; 500 mVPP, 1200 Hz and 2200 Hz) can be capacitively coupled in through the HARTIN pin and
transferred to a current that is superimposed on the current output. The HARTIN pin has a typical input
impedance of 20 kΩ to 30 kΩ, depending on the selected current output range, which together with the input
capacitor used to couple the external HART signal into the HARTIN pin can be used to form a high-pass filter to
attenuate frequencies below the HART bandpass region. In addition to this filter, an external passive filter is
recommended to complete the filtering requirements of the HART specifications. Figure 101 illustrates the output
current vs time operation for a typical HART interface.
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Feature Description (continued)
Note:
DC current = 6 mA.
Figure 101. Output Current vs Time
The HART pin for the selected channel can be enabled by writing logic '1' to the HTEN bit at address 0x04
(Table 4 and Table 5).
8.4 Device Functional Modes
8.4.1 Serial Peripheral Interface (SPI)
The device is controlled over a versatile four-wire serial interface (SDIN, SDO, SCLK, and SYNC) that operates
at clock rates of up to 25 MHz and is compatible with SPI, QSPI™, Microwire™, and digital signal processing
(DSP) standards. The SPI communication command consists of a write address byte and a data word for a total
of 24 bits (when CRC is disabled). The timing for the digital interface is shown in the timing section.
8.4.1.1 Stand-Alone Operation
The serial clock SCLK can be a continuous or a gated clock. When SYNC is high, the SCLK and SDIN signals
are blocked and the SDO pin is in a HiZ state. Exactly 24 falling clock edges must be applied before SYNC is
brought high. If SYNC is brought high before the 24th falling SCLK edge, then the data written are not transferred
into the internal registers. If more than 24 falling SCLK edges are applied before SYNC is brought high, then the
last 24 bits are used. The device internal registers are updated from the Shift Register on the rising edge of
SYNC. In order for another serial transfer to take place, SYNC must be brought low again.
8.4.1.2 Daisy-Chain Operation
For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices
together. Daisy-chain operation can be useful for system diagnostics and in reducing the number of serial
interface lines. The daisy chain feature can be enabled by writing logic '0' to DSDO bit address 0x03 (), the SDO
pin is set to HiZ when DSDO bit is set to 1. By connecting the SDO of the first device to the SDIN input of the
next device in the chain, a multiple-device interface is constructed, as Figure 102 illustrates.
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Device Functional Modes (continued)
C
DAC8771
SDIN
B
DAC8771
SDIN
SDO
A
DAC8771
SDO
SDIN
SCLK
SCLK
SCLK
SYNC
SYNC
SYNC
LDAC
LDAC
LDAC
SDO
Figure 102. Three DAC8771s in Daisy-Chain Mode
The DAC8771 provides two modes for daisy-chain operation: normal and transparent. The TRN bit in the Reset
config register determines which mode is used. In Normal mode (TRN bit = '0'), the data clocked into the SDIN
pin are transferred into the shift register. The first falling edge of SYNC starts the operating cycle. SCLK is
continuously applied to the SPI Shift Register when SYNC is low. If more than 24 clock pulses are applied, the
data ripple out of the shift register and appear on the SDO line. These data are clocked out on the rising edge of
SCLK and are valid on the falling edge. By connecting the SDO pin of the first device to the SDIN input of the
next device in the chain, a multiple-device interface is constructed. Each device in the system requires 24 clock
pulses. Therefore, the total number of clock cycles must equal 24 × N, where N is the total number of DAC8771s
in the chain. When the serial transfer to all devices is complete, SYNC is taken high. This action latches the data
from the SPI Shift registers to the device internal registers synchronously for each device in the daisy-chain, and
prevents any further data from being clocked in. Note that a continuous SCLK source can only be used if SYNC
is held low for the correct number of clock cycles. For gated clock mode, a burst clock containing the exact
number of clock cycles must be used and SYNC must be taken high after the final clock in order to latch the
data.
In Transparent mode (address 0x02h, TRN bit = '1' Table 5), the data clocked into SDIN are routed to the SDO
pin directly; the Shift Register is bypassed. When SCLK is continuously applied with SYNC low, the data clocked
into the SDIN pin appear on the SDO pin almost immediately (with approximately a 12 ns delay); there is no 24
clock delay, as there is in normal operating mode. While in Transparent mode, no data bits are clocked into the
Shift Register, and the device does not receive any new data or commands. Putting the device into transparent
mode eliminates the 24 clock delay from SDIN to SDO caused by the Shift Register, thus greatly speeding up the
data transfer. For example, consider three DAC8771s (C, B, and A) in a daisy-chain configuration (Figure 102).
The data from the SPI controller are transferred first to C, then to B, and finally to A. In normal daisy-chain
operation, a total of 72 clocks are needed to transfer one word to A. However, if C and B are placed into Sleep
mode, the first 24 data bits are directly transferred to A (through C and B); therefore, only 24 clocks are needed.
To wake the device up from transparent mode and return to normal operation, the hardware RESET pin must be
toggled.
8.4.2 SPI Shift Register
The SPI Shift Register is 24 bits wide (refer to the Frame Error Checking section for 32-bit frame mode). The
default 24-bit input frame consists of an 8-bit address byte followed by a 16-bit data word as shown in Table 1.
Table 1. Default SPI Frame
BIT 23:BIT 16
BIT 15:BIT 0
Address byte
Data word
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8.4.3 Write Operation
A typical write to program a channel of the DAC8771 consists of writing to the following registers in the sequence
shown in Figure 12.
Select Buck-Boost
Register (x06h)
Config Buck-Boost
Register (x07h)
Select DAC Register
(x03h)
Config DAC Register
(x04h)
Program DAC Data
Register (x05h)
Figure 103. Typical Write to DAC8771
8.4.4 Read Operation
A read operation is accomplished when DB 23 is '1' (see Table 2). A no-operation (NOP) command should follow
the read operation in order to clock out an addressed register. The read register value is output MSB first on
SDO on successive falling edges of SCLK.
Table 2. Register Read Address Functions (1)
ADDRESS BYTE
(1)
DB23
DB 22: DB 16
Read/Write Bit
Register Addresses
'X' denotes don't care bits.
8.4.5 Updating the DAC Outputs and LDAC Pin
Depending on the status of both SYNC and LDAC, and after data have been transferred into the DAC Data
registers, the DAC outputs can be updated either in asynchronous mode or synchronous mode.
8.4.5.1 Asynchronous Mode
In this mode, the LDAC pin is set low before the rising edge of SYNC. This action places the DAC8771 into
Asynchronous mode, and the LDAC signal is ignored. The DAC latches are updated immediately when SYNC
goes high.
8.4.5.2 Synchronous Mode
To use this mode, set LDAC high before the rising edge of SYNC, and then take LDAC low after SYNC goes
high. In this mode, when LDAC stays high, the DAC latch is not updated; therefore, the DAC output does not
change. The DAC latch is updated by taking LDAC low any time after a certain delay from the rising edge of
SYNC (see Figure 1). If this delay requirement is not satisfied, invalid data are loaded. Refer to the Timing
Diagrams for details.
42
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8.4.6 Hardware RESET Pin
When the RESET pin is low, the device is in hardware reset. All the analog outputs (VOUT_A to VOUT_D and
IOUT_A to IOUT_D), all the registers except the POC register, and the DAC latches are set to the default reset
values. In addition, the Gain and Zero Registers are loaded with default values, communication is disabled, and
the signals on SYNC and SDIN are ignored (note that SDO is in a high-impedance state). When the RESET pin
is high, the serial interface returns to normal operation and all the analog outputs (VOUT_A to VOUT_D and
IOUT_A to IOUT_D) maintain the reset value until a new value is programmed.
8.4.7 Hardware CLR Pin
The CLR pin is an active high input that should be low for normal operation. When this pin is a logic '1', all the
outputs are cleared to either zero-scale code or midscale code depending on the status of the CLSLx bit (see
reset register). While CLR is high, all LDAC pulses are ignored. When CLR is taken low again, the DAC outputs
remain cleared until new data is written to the DAC. The contents of the offset Registers, Gain Registers and
DAC input registers are not affected by taking CLR high. Note that the clear action will result in the outputs
clearing to the default value instantaneously even if slew rate control is enabled.
8.4.8 Frame Error Checking
If the DAC8771 is used in a noisy environment, error checking can be used to check the integrity of SPI data
communication between the device and the host processor. This feature can be enabled by setting the CREN bit
address 0x03 .
The frame error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is,
100000111). When error checking is enabled, the SPI frame width is 32 bits, as shown in Table 3 . The normal
24-bit SPI data are appended with an 8-bit CRC polynomial by the host processor before feeding it to the device.
For a register readback, the CRC polynomial is output on the SDO pins by the device as part of the 32 bit frame.
Note that the user has to start with the default 24 bit frame and enable frame error checking through the CREN
bit and switch to the 32 bit frame. Alternatively, the user can use a 32 bit frame from the beginning and pad the 8
MSB bits as the device will only use the last 24 bits until the CRCEN bit is set. The frame length has to be
carefully managed, especially when using daisy-chaining in combination with CRC checking to ensure correct
operation.
Table 3. SPI Frame with Frame Error Checking Enabled
BIT 31:BIT 8
BIT 7:BIT 0
Normal SPI frame data
8-bit CRC polynomial
The DAC8771 decodes the 32-bit input frame data to compute the CRC remainder. If no error exists in the
frame, the CRC remainder is zero. When the remainder is non-zero (that is, the input frame has single- or
multiple-bit errors), the ALARM pin asserts low and the CRE bit of the status register (address 0x0B) is also set
to '1'. Note that the ALARM pin can be asserted low for any of the different conditions as explained in the
ALARM Pin section. The CRE bit is set to '0' with a software or hardware reset, or by disabling the frame error
checking, or by powering down the device. In the case of a CRC error, the specific SPI frame is blocked from
writing to the device.
Frame error checking can be enabled for any number of DAC8771 devices connected in a daisy-chain
configuration. However, it is recommended to enable error checking for none or all devices in the chain. When
connecting the ALARM pins of all combined devices, forming a wired-AND function, the host processor should
read the status register of each device to know all the fault conditions present in the chain. For proper operation,
the host processor must provide the correct number of SCLK cycles in each frame, taking care to identify
whether or not error checking is enabled in each device in the daisy-chain.
8.4.9 DAC Data Calibration
The DAC8771 contains a dedicated user calibration register set. This feature allows the user to trim the system
gain and offset errors. Both the voltage output and the current output have common user calibration registers
available. The user calibration feature is disabled by default. To enable this feature, the CLEN bit (DB0) on
address 0x08 must be set to logic '1 (see ).
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8.4.9.1 DAC Data Gain and Offset Calibration Registers
The DAC calibration register set includes one gain calibration and one offset calibration register (16 bits for
DAC8771). The range of gain adjustment is typically ±50% of full-scale with 1 LSB per step. The power-on value
of the gain register is 0x8000 which is equivalent to a gain of 1.0. The offset code adjustment is typically ±32,768
LSBs with 1 LSB per step. The input data format of the gain register is unsigned straight binary, and the input
data format of the offset register is twos complement. The gain and offset calibration is described by Equation 9.
%1&'_176 = H%1&' T F
7OAN_)=EJ + 215
G + 7OAN_
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