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DAC8881
SBAS422B – JULY 2007 – REVISED JANUARY 2018
DAC8881 16-Bit, Single-Channel, Low-Noise, Voltage-Output
Digital-To-Analog Converter
1 Features
3 Description
•
•
•
•
•
The DAC8881 is a 16-bit, single-channel, voltageoutput digital-to-analog converter (DAC) that offers
low-power operation and a flexible SPI serial
interface. It also features 16-bit monotonicity,
excellent linearity, and fast settling time. The on-chip
precision output amplifier allows rail-to-rail output
swing to be achieved over the full supply range of 2.7
V to 5.5 V.
1
•
•
•
•
•
•
•
Relative Accuracy: ±0.5 LSB
16-Bit Monotonic Over Temperature Range
Low-Noise: 24nV/√Hz
Fast Settling: 5μs
On-Chip Output Buffer Amplifier with Rail-to-Rail
Operation
Wide, Single Power Supply: +2.7V to +5.5V
DAC Loading Control
Selectable Power-On Reset to Zero-Scale or
Midscale
Power-Down Mode
Unipolar Straight Binary or
2's Complement Input Mode
Fast SPI™ Interface with Schmitt-Triggered
Inputs:
Up To 50MHz, 1.8V/3V/5V Logic
Small Package: QFN-24, 4x4mm
The device supports a standard SPI serial interface
capable of operating with input data clock frequencies
up to 50 MHz. The DAC8881 requires an external
reference voltage to set the output range of the DAC
channel. A programmable power-on reset circuit is
also incorporated into the device to ensure that the
DAC output powers up at zero-scale or midscale, and
remains there until a valid write command.
Additionally, the device has the capability to function
in either unipolar straight binary or 2's complement
mode. The DAC8881 provides a power-down feature,
accessed over the PDN pin, that reduces the current
consumption to 25 μA at 5 V. Power consumption is 6
mW at 5 V, reducing to 125 μW in power-down mode.
2 Applications
•
•
•
•
•
Industrial Process Control
Data Acquisition Systems
Automatic Test Equipment
Communications
Optical Networking
The DAC8881 is available in a 4 x 4 mm QFN-24
package with a specified operating temperature range
of –40°C to +105°C.
Device Information(1)
PART NUMBER
DAC8881
PACKAGE
BODY SIZE (NOM)
VQFN
4.00 mm x 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Block Diagram
DVDD
DGND
IOVDD
AGND
AVDD
VREFH-S VREFH-F
DAC8881
RST
Power-On
Reset
RSTSEL
Control
Logic
USB/BTC
Resistor
Network
SDI
CS
SCLK
SPI Interface
Shift Register
GAIN
PDN
Input
Register
DAC
Latch
VOUT
DAC
RFB(1)
RFB
SDOSEL
SDO
Serial Out
Control
NOTE: (1) RFB = 5kW for gain = 1,
RFB = 10kW for gain = 2.
LDAC
VREFL-S
VREFL-F
Copyright © 2018, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DAC8881
SBAS422B – JULY 2007 – REVISED JANUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 4
Electrical Characteristics........................................... 5
Timing Characteristics for Figure 1 .......................... 7
Timing Characteristics for Figure 2 and Figure 3 .... 8
Typical Characteristics: VDD = +5 V........................ 12
TYpical Characteristics: VDD = +2.7 V .................... 19
Detailed Description ............................................ 23
7.1 Overview ................................................................. 23
7.2 Functional Block Diagram ....................................... 25
7.3 Feature Description................................................. 25
7.4 Device Functional Modes........................................ 30
8
Application and Implementation ........................ 31
8.1 Application Information............................................ 31
8.2 Typical Application ................................................. 32
8.3 System Example ..................................................... 33
9 Power Supply Recommendations...................... 34
10 Layout................................................................... 34
10.1 Layout Guidelines ................................................. 34
10.2 Layout Example .................................................... 34
11 Device and Documentation Support ................. 35
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
35
35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2007) to Revision B
Page
•
Added Device Information table, ESD Ratings table, Recommended Operating Conditions table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section. .................................................................................................................... 1
•
Changed the text in the Input Data Format section.............................................................................................................. 28
•
Changed Table 3 .................................................................................................................................................................. 29
2
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SBAS422B – JULY 2007 – REVISED JANUARY 2018
5 Pin Configuration and Functions
(1)
SDO
DGND
DVDD
SDOSEL
CS
22
21
20
19
IOVDD
24
23
RGE Package
QFN-24
(Top View)
SCLK
1
18
PDN
SDI
2
17
RST
LDAC
3
16
USB/BTC
AGND
4
15
GAIN
AVDD
5
14
RSTSEL
VREFL-S
6
13
NC
DAC8881
10
11
12
NC
RFB
VREFL-F
9
VOUT
VREFH-F
7
8
VREFH-S
(Thermal Pad)
The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left
floating. Keep the thermal pad separate from the digital ground, if possible.
Pin Functions
PIN
NO.
NAME
I/O
1
SCLK
I
SPI bus serial clock input
DESCRIPTION
2
SDI
I
SPI bus serial data input
3
LDAC
I
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent, and the contents of the input
register are transferred to the DAC latch. The DAC output changes to the corresponding level simultaneously when the
DAC latch is updated.
4
AGND
I
Analog ground
5
AVDD
I
Analog power supply
6
VREFL-S
I
Reference low input sense
7
VREFH-S
I
Reference high input sense
8
VOUT
O
Output of output buffer
9
RFB
I
Feedback resistor connected to the inverting input of the output buffer.
10
VREFL-F
I
Reference low input force
11
VREFH-F
I
Reference high input force
12
NC
—
Do not connect.
13
NC
—
Do not connect.
14
RSTSEL
I
Selects the value of the output from the VOUT pin after power-on or hardware reset. If RSTSEL = IOVDD, then register data
= 8000h. If RSTSEL = DGND, then register data = 0000h.
15
GAIN
I
Buffer gain setting. Gain = 1 when the pin is connected to DGND; Gain = 2 when the pin is connected to IOVDD.
16
USB/BTC
I
Input data format selection. Input data are straight binary format when the pin is connected to IOVDD, and in two’s
complement format when the pin is connected to DGND.
17
RST
I
Reset input (active low). Logic low on this pin causes the device to perform a reset.
18
PDN
I
Power-down input (active high). Logic high on this pin forces the device into power-down status. In power-down, the VOUT
pin connects to AGND through 10kΩ resistor.
19
CS
I
SPI bus chip select input (active low). Data bits are not clocked into the serial shift register unless CS is low. When CS is
high, SDO is in high-impedance status.
20
SDOSEL
I
SPI serial data output selection. When SDOSEL is tied to IOVDD, the contents of the existing input register are shifted out
from the SDO pin; this is Stand-Alone mode. When SDOSEL is tied to DGND, the contents in the SPI input shift register
are shifted out from the SDO pin; this is Daisy-Chain mode for daisy chaining communication.
21
DVDD
I
Digital power supply (connect to AVDD, pin 5)
22
DGND
I
Digital ground
23
SDO
O
SPI bus serial data output. Refer to the Timing Diagrams for further detail.
24
IOVDD
I
Interface power. Connect to +1.8V for 1.8V logic, +3V for 3V logic, and to +5V for 5V logic.
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DAC8881
SBAS422B – JULY 2007 – REVISED JANUARY 2018
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
AVDD to AGND
–0.3
6
V
DVDD to DGND
–0.3
6
V
IOVDD to DGND
–0.3
6
V
Digital input voltage to DGND
–0.3
IOVDD + 0.3
V
VOUT to AGND
–0.3
AVDD + 0.3
V
Operating temperature range
–40
105
°C
Storage temperature range
–65
150
°C
150
°C
Storage temperature, Tstg
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±3000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. .
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
AVDD
Analog power supply
IOVDD
Interface power supply
NOM
2.7
1.7
MAX
UNIT
5.5
V
AVDD
V
AVDD = 5.5 V
1.25
5
AVDD
V
AVDD = 3 V
1.25
2.5
AVDD
V
0
VREFH
Reference high input voltage
VREFL
Reference low input voltage
–0.2
Specified performance
–40
0.2
V
105
°C
6.4 Thermal Information
DAC8881
THERMAL METRIC (1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
33.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
37.1
°C/W
RθJB
Junction-to-board thermal resistance
11.3
°C/W
ψJT
Junction-to-top characterization parameter
0.5
°C/W
ψJB
Junction-to-board characterization parameter
11.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBAS422B – JULY 2007 – REVISED JANUARY 2018
6.5 Electrical Characteristics
All specifications at TA = TMIN to TMAX, AVDD = DVDD = +2.7 V to +5.5 V, IOVDD = +1.8 V to +5.5 V, gain = 1X mode, unless
otherwise noted.
PARAMETER
CONDITIONS
DAC8881
MIN
TYP
MAX
UNIT
ACCURACY
Linearity error
Measured by line passing through codes 0200h and FE00h
±0.5
±1
LSB
Differential linearity error
Measured by line passing through codes 0200h and FE00h
±0.25
±1
LSB
±4
LSB
±8
LSB
Monotonicity
Zero-scale error
16
Bits
TA = +25°C, code = 0200h
TMIN to TMAX, code = 0200h
Zero-scale drift
Code = 0200h
±0.5
Gain error
TA = +25°C, Measured by line passing through codes
0200h and FE00h
Gain temperature drift
Measured by line passing through codes 0200h and FE00h
PSRR
VOUT = full-scale, AVDD = +5 V ±10%
±1 ppm/°C of FSR
±4
±8
LSB
±0.5
±1
ppm/°C
2
LSB/V
ANALOG OUTPUT (1)
Voltage output (2)
Output voltage drift vs time
0
AVDD
V
Device operating for 500 hours
5
ppm of FSR
Device operating for 1000 hours
8
ppm of FSR
Output current
2.5
Maximum load capacitance
200
pF
+31, –50
mA
Short-circuit current
mA
REFERENCE INPUT (1)
VREFH input voltage range
AVDD = +5.5 V
1.25
5.0
AVDD
AVDD = +3 V
1.25
2.5
AVDD
VREFH input capacitance
5
VREFH input impedance
–0.2
VREFL input capacitance
VREFL input impedance
0
V
pF
4.5
VREFL input voltage range
V
kΩ
+0.2
V
4.5
pF
5
kΩ
5
μs
DYNAMIC PERFORMANCE (1)
Settling time
To ±0.003% FS, RL = 10 kΩ, CL = 50 pF, code 1000h to
F000h
Slew rate
From 10% to 90% of 0 V to +5 V
Code change glitch
Code = 7FFFh to
8000h to 7FFFh
2.5
V/μs
VREFH = 5 V, gain = 1X mode
37
nV-s
VREFH = 2.5 V, gain = 1X mode
18
nV-s
VREFH = 1.25 V, gain = 1X mode
9
nV-s
VREFH = 2.5 V, gain = 2X mode
21
nV-s
VREFH = 1.25 V, gain = 2X mode
10
nV-s
1
nV-s
Digital feedthrough
Gain = 1
24
30
nV/√Hz
Gain = 2
40
48
nV/√Hz
Output noise voltage density
f = 1 kHz to 100 kHz,
full-scale output
Output noise voltage
f = 0.1Hz to 10Hz, full-scale output
(1)
(2)
2
μVPP
Specified by design. Not production tested.
The output from the VOUT pin = [(VREFH – VREFL)/65536] × CODE × Buffer GAIN + VREFL. The maximum range of VOUT is 0 V to AVDD.
The full-scale of the output must be less than AVDD; otherwise, output saturation occurs.
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Electrical Characteristics (continued)
All specifications at TA = TMIN to TMAX, AVDD = DVDD = +2.7 V to +5.5 V, IOVDD = +1.8 V to +5.5 V, gain = 1X mode, unless
otherwise noted.
PARAMETER
CONDITIONS
DAC8881
MIN
TYP
MAX
UNIT
DIGITAL INPUTS (1)
High-level input voltage, VIH
Low-level input voltage, VIL
IOVDD = 4.5 V to 5.5 V
3.8
IOVDD + 0.3
V
IOVDD = 2.7 V to 3.3 V
2.1
IOVDD + 0.3
V
IOVDD = 1.7 V to 2 V
1.5
IOVDD + 0.3
V
IOVDD = 4.5 V to 5.5 V
–0.3
0.8
V
IOVDD = 2.7 V to 3.3 V
–0.3
0.6
V
IOVDD = 1.7 V to 2 V
–0.3
0.3
V
±10
μA
Digital input current (IIN)
±1
Digital input capacitance
5
pF
DIGITAL OUTPUT (1)
High-level output voltage, VOH
Low-level output voltage, VOL
IOVDD = 2.7 V to 5.5 V, IOH = –1 mA
IOVDD – 0.2
V
IOVDD = 1.7 V to 2 V, IOH = –500 μA
IOVDD – 0.2
V
IOVDD = 2.7 V to 5.5 V, IOL = 1 mA
0.2
V
IOVDD = 1.7 V to 2 V, IOL = 500 μA
0.2
V
POWER SUPPLY
AVDD
+2.7
+5.5
V
DVDD
+2.7
+5.5
V
IOVDD
+1.7
DVDD
AIDD
VIH = IOVDD, VIL = DGND
DIDD
VIH = IOVDD, VIL = DGND
IOIDD
VIH = IOVDD, VIL = DGND
AIDD power-down
PDN = IOVDD
Power dissipation
AVDD = DVDD = 5.0V
V
1.5
mA
1
10
μA
1
10
μA
25
50
μA
6
7.5
mW
TEMPERATURE RANGE
Specified performance
6
–40
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+105
°C
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SBAS422B – JULY 2007 – REVISED JANUARY 2018
6.6 Timing Characteristics for Figure 1
(1) (2) (3)
At –40°C to +105°C, unless otherwise noted.
PARAMETER
fSCLK
Maximum clock frequency
t1
Minumum CS high time
t2
CS falling edge to SCLK rising edge
t3
SCLK falling edge to CS falling edge setup
time
t4
SCLK low time
t5
SCLK high time
t6
SCLK cycle time
t7
SCLK rising edge to CS rising edge
t8
Input data setup time
t9
Input data hold time
t14
CS rising edge to LDAC falling edge
t15
(1)
(2)
(3)
CONDITIONS
LDAC pulse width
MIN
MAX
UNIT
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
40
MHz
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
50
MHz
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
50
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
30
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
8
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
15
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
25
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
20
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
8
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6V, 2.7 ≤ IOVDD ≤ DVDD
15
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
Specified by design. Not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
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6.7 Timing Characteristics for Figure 2 and Figure 3
(1) (2) (3)
At –40°C to +105°C, unless otherwise noted.
PARAMETER
fSCLK
Maximum clock frequency
t1
Minumum CS high time
t2
CS falling edge to SCLK rising edge
t3
SCLK falling edge to CS falling edge setup
time
t4
SCLK low time
t5
SCLK high time
t6
SCLK cycle time
t7
SCLK rising edge to CS rising edge
t8
Input data setup time
t9
Input data hold time
t10
SDO active from CS falling edge
t11
SDO data valid from SCLK falling edge
t12
SDO data hold from SCLK rising edge
t13
SDO High-Z from CS rising edge
t14
CS rising edge to LDAC falling edge
t15
LDAC pulse width
(1)
(2)
(3)
8
CONDITIONS
MIN
MAX
UNIT
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
20
MHz
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
25
MHz
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
50
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
30
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
8
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
25
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
20
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
25
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
20
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
50
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
40
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
3.6 ≤ DVDD ≤ 5.5 , 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
15
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
20
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
15
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
25
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
20
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
ns
ns
8
ns
5
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
5
ns
2.7 ≤ DVDD < 3.6 V, 2.7 ≤ IOVDD ≤ DVDD
15
ns
3.6 ≤ DVDD ≤ 5.5 V, 2.7 ≤ IOVDD ≤ DVDD
10
ns
All input signals are specified with tR = tF = 2ns (10% to 90% of IOVDD) and timed from a voltage level of IOVDD/2.
Specified by design. Not production tested.
Sample tested during the initial release and after any redesign or process changes that may affect these parameters.
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SBAS422B – JULY 2007 – REVISED JANUARY 2018
Case 1: Standalone operation without SDO, LDAC tied low.
t1
t2
CS
t3
t4
t7
t6
t5
Input Register
and DAC Latch
Updated
SCLK
t8
Bit 15 (N)
SDI
LDAC
t9
Bit 14 (N)
Bit 1 (N)
Bit 0 (N)
Low
Case 2: Standalone operation without SDO, LDAC active.
t2
t1
CS
Input Register
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 15 (N)
SDI
LDAC
t9
Bit 14 (N)
Bit 1 (N)
Bit 0 (N)
t14
High
t15
DAC Latch
Updated
= Dont Care
Bit 15 = MSB
Bit 0 = LSB
Figure 1. Timing Diagram of Standalone Operation Without SDO
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Case 1: Standalone operation with output from SDO, LDAC tied low.
t1
t2
CS
Input Register
and DAC Latch
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 15 (N)
SDI
t9
Bit 14 (N)
Bit 1 (N)
t11
LDAC
Bit 15 (N - 1)
from Input Reg.
High-Z
SDO
Bit 14 (N - 1)
from Input Reg.
Bit 0 (N)
t12
Bit 1 (N - 1)
from Input Reg.
t13
Bit 0 (N - 1)
from Input Reg.
High-Z
t10
Low
Case 2: Standalone operation with output from SDO, LDAC active.
t2
t1
CS
Input Register
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 15 (N)
SDI
t9
Bit 14 (N)
Bit 1 (N)
t11
High-Z
SDO
LDAC
High
Bit 15 (N - 1)
from Input Reg.
Bit 14 (N - 1)
from Input Reg.
Bit 0 (N)
t12
Bit 1 (N - 1)
from Input Reg.
t13
Bit 0 (N - 1)
from Input Reg.
t10
t14
High-Z
t15
DAC Latch
Updated
= Dont Care
Bit 15 = MSB
Bit 0 = LSB
Figure 2. Timing Diagram of Standalone Operation With SDO
10
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SBAS422B – JULY 2007 – REVISED JANUARY 2018
Case 1: Daisy Chain, LDAC tied low.
t1
t2
CS
Input Register
and DAC Latch
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 15 (N)
SDI
t9
Bit 14 (N)
Bit 0 (N)
Bit 15 (N + 1)
t11
LDAC
t12
Bit 15 (N)
High-Z
SDO
Bit 0 (N + 1)
t13
Bit 0 (N)
High-Z
t10
Low
Case 2: Daisy Chain, LDAC active.
t1
t2
CS
Input Register
Updated
t3
t4
t7
t6
t5
SCLK
t8
Bit 15 (N)
SDI
t9
Bit 14 (N)
Bit 0 (N)
Bit 15 (N + 1)
t11
LDAC
High
t12
Bit 15 (N)
High-Z
SDO
t10
Bit 0 (N + 1)
t13
Bit 0 (N)
High-Z
t14
t15
DAC Latch
Updated
= Dont Care
Bit 15 = MSB
Bit 0 = LSB
Figure 3. Timing Diagram of Daisy Chain Mode, Two Cascaded Devices
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6.8 Typical Characteristics: VDD = +5 V
At TA = +25°C, VREFH = +5 V, VREFL = 0 V, and Gain = 1X Mode, unless otherwise noted.
1.0
0.6
0.6
0.4
0.4
0.2
0
-0.2
-0.4
-0.4
-0.6
-0.8
-1.0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 4. Linearity Error vs Digital Input Code
1.0
1.0
0.4
DNL Error (LSB)
0.6
0.4
0
-0.2
-0.4
TA = -40°C
0.8
0.6
0.2
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 5. Differential Linearity Error vs Digital Input Code
TA = -40°C
0.8
INL Error (LSB)
0
-0.2
-0.8
0
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 6. Linearity Error vs Digital Input Code
1.0
1.0
0.4
DNL Error (LSB)
0.6
0.4
0
-0.2
-0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
TA = +105°C
0.8
0.6
0.2
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 7. Differential Linearity Error vs Digital Input Code
TA = +105°C
0.8
INL Error (LSB)
0.2
-0.6
-1.0
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 8. Linearity Error vs Digital Input Code
12
TA = +25°C
0.8
DNL Error (LSB)
INL Error (LSB)
1.0
TA = +25°C
0.8
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 9. Differential Lineary Error vs Digital Input Code
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SBAS422B – JULY 2007 – REVISED JANUARY 2018
Typical Characteristics: VDD = +5 V (continued)
1.0
1.0
0.8
0.8
0.6
INL Max
0.4
DNL Error (LSB)
INL Error (LSB)
0.6
0.2
0
-0.2
INL Min
-0.4
0
-0.2
DNL Min
-0.4
-0.6
-0.8
-0.8
-1.0
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
-40
Figure 10. Linearity Error vs Temperature
-20
0
20
40
60
Temperature (°C)
80
100
120
Figure 11. Differential Linearity Error vs Temperature
1.0
1.0
VREFH = 2.5V
VREFL = 0V
0.8
VREFH = 2.5V
VREFL = 0V
0.8
0.6
0.6
INL Max
0.4
DNL Error (LSB)
INL Error (LSB)
DNL Max
0.2
-0.6
-1.0
0.2
0
-0.2
-0.4
INL Min
0.4
DNL Max
0.2
0
-0.2
DNL Min
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
-40
-20
0
20
40
60
Temperature (°C)
80
100
120
-40
Figure 12. Linearity Error vs Temperature
(Gain = 2X Mode)
-20
0
20
40
60
Temperature (°C)
80
100
120
Figure 13. Differential Linearity Error vs Temperature
(Gain = 2X Mode)
1.0
1.0
VREFH = 2.5V
VREFL = 0V
0.8
VREFH = 2.5V
VREFL = 0V
0.8
0.6
0.4
DNL Error (LSB)
0.6
INL Error (LSB)
0.4
INL Max
0.2
0
-0.2
INL Min
-0.4
0.4
0
-0.2
DNL Min
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
DNL Max
0.2
-1.0
2.5
3.0
3.5
4.0
4.5
5.0
Supply Voltage (V)
5.5
Figure 14. Linearity Error vs Supply Voltage
6.0
2.5
3.0
3.5
4.0
4.5
5.0
Supply Voltage (V)
5.5
6.0
Figure 15. Differential Linearity Error vs Supply Voltage
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1.0
1.0
0.8
0.8
0.6
0.6
0.4
DNL Error (LSB)
INL Error (LSB)
Typical Characteristics: VDD = +5 V (continued)
INL Max
0.2
0
-0.2
INL Min
-0.4
DNL Max
0.2
0
-0.2
DNL Min
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
1
2
3
4
Reference Voltage (V)
5
6
0
Figure 16. Linearity Error vs Reference Voltage
1.0
0.8
0.8
0.6
0.6
0.4
0.2
Plus Full-Scale Error
0
-0.2
Minus Full-Scale Error
-0.4
5
6
VREFH = 2.5V
VREFL = 0V
Plus Full-Scale Error
0.2
0
-0.2
Minus Full-Scale Error
-0.4
-0.6
-0.8
-0.8
-1.0
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
125
-55
Figure 18. Endpoint Error vs Temperature
1000
AVDD = 5.0V
VREFH = 2.5V
VREFL = 0V
900
800
700
AVDD = 2.7V
VREFH = 2.7V
VREFL = 0V
600
AVDD = 2.7V
VREFH = 2.5V
VREFL = 0V
500
400
300
-15
5
25
45
65
Temperature (°C)
85
105
125
AVDD = 5.0V
VREFH = 2.5V
VREFL = 0V
900
AVDD Supply Current (mA)
1000
AVDD = 5.0V
VREFH = 5.0V
VREFL = 0V
-35
Figure 19. Endpoint Error vs Temperature
(Gain = 2X Mode)
1100
AVDD Supply Current (mA)
2
3
4
Reference Voltage (V)
0.4
-0.6
-1.0
800
700
600
AVDD = 2.7V
VREFH = 1.25V
VREFL = 0V
500
400
300
200
100
0
200
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 20. AVDD Supply Current vs Digital Input Code
14
1
Figure 17. Differential Linearity Error vs Reference Voltage
1.0
Endpoint Error (mV)
Endpoint Error (mV)
0.4
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 21. AVDD Supply Current vs Digital Input Code
(Gain = 2X Mode)
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SBAS422B – JULY 2007 – REVISED JANUARY 2018
Typical Characteristics: VDD = +5 V (continued)
50
1000
AVDD Supply Current (mA)
AVDD Supply Current (mA)
1200
800
VREFH = 5.0V
VREFL = 0V
Gain = 1X Mode
600
VREFH = 2.5V
VREFL = 0V
Gain = 2X Mode
400
200
40
30
AVDD = 5.0V
20
AVDD = 2.7V
10
DAC Code Set to FC00h
0
0
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
125
-55
Figure 22. AVDD Supply Current vs Temperature
5
25
45
65
Temperature (°C)
1.5
VREFH Current
0.5
0
VREFL Current
-0.5
-1.0
85
105
125
VREFH = 2.5V
VREFL = 0V
1.0
Reference Current (mA)
1.0
VREFH Current
0.5
0
-0.5
VREFL Current
-1.0
-1.5
-1.5
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 24. Reference Current vs Digital Input Code
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 25. Reference Current vs Digital Input Code
(Gain = 2X Mode)
5.0
5.00
DAC Loaded with FFFFh
4.5
DAC Loaded with FFFFh
4.0
4.95
DAC Loaded with FE00h
3.5
3.0
VOUT (V)
VOUT (V)
-15
Figure 23. AVDD Power-Down Current vs Temperature
1.5
Reference Current (mA)
-35
2.5
2.0
4.90
DAC Loaded with FC00h
4.85
1.5
1.0
0.5
DAC Loaded with F800h
4.80
DAC Loaded with 0000h
0
4.75
0
3
6
9
I(SOURCE/SINK) (mA)
12
15
Figure 26. Output Voltage vs Drive Current Capability
0
1
2
3
ISOURCE (mA)
4
5
Figure 27. Output Voltage vs Drive Current Capability
(Operation Near AVDD Rail)
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Typical Characteristics: VDD = +5 V (continued)
200
0.25
IOVDD Supply Current (mA)
180
0.20
VOUT (V)
DAC Loaded with 0800h
0.15
DAC Loaded with 0400h
0.10
DAC Loaded with 0200h
0.05
IOVDD = 5V
160
140
120
100
80
60
40
IOVDD = 2.7V
20
DAC Loaded with 0000h
0
0
1
2
3
0
4
0
5
ISINK (mA)
Figure 28. Output Voltage vs Drive Current Capability
(Operation Near AGND Rail)
0.5
1.0
1.5 2.0 2.5 3.0 3.5
Logic Input Voltage (V)
4.0
4.5
5.0
Figure 29. IOVDD Supply Current vs Logic Input Voltage
Large-Signal Output
2V/div
Large-Signal Output
Small-Signal Error
2V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 0000h to FFFFh
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Time (2ms/div)
Code Change: FFFFh to 0000h
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 30. Large Signal Settling Time
Figure 31. Large Signal Settling Time
Large-Signal Output
2V/div
Large-Signal Output
2V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 1000h to F000h
Output Loaded with 10kW and
50pF to AGND
Small-Signal Error
5V/div
LDAC
Signal
Time (2ms/div)
Time (2ms/div)
Figure 32. Large Signal Settling Time
16
Code Change: F000h to 1000h
Output Loaded with 10kW and
50pF to AGND
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Figure 33. Large Signal Settling Time
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SBAS422B – JULY 2007 – REVISED JANUARY 2018
Typical Characteristics: VDD = +5 V (continued)
VREFH = 2.5V
Code Change: FFFFh to 0000h
Output Loaded with 10kW and
50pF to AGND
VREFH = 2.5V
Large-Signal Output
2V/div
Large-Signal Output
Small-Signal Error
2V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 0000h to FFFFh
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Time (2ms/div)
Time (2ms/div)
Figure 34. Large Signal Settling Time (Gain = 2X Mode)
Figure 35. Large Signal Settling Time (Gain = 2X Ml)
VREFH = 2.5V
VREFH = 2.5V
Large-Signal Output
2V/div
Large-Signal Output
Small-Signal Error
2V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 1000h to F000h
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Code Change: F000h to 1000h
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Time (2ms/div)
Figure 36. Large Signal Settling Time (Gain = 2X Mode)
Figure 37. Large Signal Settling Time (Gain = 2X Mode)
Code Change: 7FFFh to 8000h
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +5V
Gain = 1X Mode
VREFH = +5V
Integrated Glitch Energy (34nV-s)
100mV/div
VOUT Signal
100mV/div
VOUT Signal
Integrated Glitch Energy (37nV-s)
5V/div
LDAC
Signal
5V/div
Code Change: 8000h to 7FFFh
Output Loaded with 10kW and
50pF to AGND
LDAC
Signal
Time (2ms/div)
Time (2ms/div)
Figure 38. Major Carry Glitch
Figure 39. Major Carry Glitch
Code Change: 7FFFh to 8000h
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +2.5V
Gain = 1X Mode
VREFH = +2.5V
Integrated Glitch Energy (16nV-s)
100mV/div
VOUT Signal
100mV/div
VOUT Signal
Integrated Glitch Energy (18nV-s)
5V/div
LDAC
Signal
5V/div
Time (2ms/div)
LDAC
Signal
Code Change: 8000h to 7FFFh
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 40. Major Carry Glitch
Figure 41. Major Carry Glitch
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180
DAC Code Set to 8000h
Output Unloaded
160
140
120
2mV/div
Output Voltage Noise Density (nV/ÖHz)
Typical Characteristics: VDD = +5 V (continued)
100
80
60
Gain = 2X Mode
40
20
Gain = 1X Mode
0
1
10
100
1k
Frequency (Hz)
10k
Figure 42. Output Noise Density vs Frequency
18
Time (1s/div)
100k
Figure 43. Low-Frequency Output Noise (0.1Hz to 10Hz)
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SBAS422B – JULY 2007 – REVISED JANUARY 2018
6.9 TYpical Characteristics: VDD = +2.7 V
At TA = +25°C, VREFH = +2.5 V, VREFL = 0 V, and Gain = 1X Mode, unless otherwise noted.
1.0
0.6
0.6
0.4
0.4
0.2
0
-0.2
-0.4
0
-0.2
-0.4
-0.6
-0.8
-0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 44. Linearity Error vs Digital Input Code
1.0
1.0
0.4
DNL Error (LSB)
0.6
0.4
0
-0.2
-0.4
TA = -40°C
0.8
0.6
0.2
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 45. Differential Linearity Error vs Digital Input Code
TA = -40°C
0.8
INL Error (LSB)
0.2
-0.6
-1.0
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
0
Figure 46. Linearity Error vs Digital Input Code
1.0
1.0
0.4
DNL Error (LSB)
0.6
0.4
0
-0.2
-0.4
0.2
0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
TA = +105°C
0.8
0.6
0.2
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 47. Differential Linearity Error vs Digital Input Code
TA = +105°C
0.8
INL Error (LSB)
TA = +25°C
0.8
DNL Error (LSB)
INL Error (LSB)
1.0
TA = +25°C
0.8
-1.0
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 48. Linearity Error vs Digital Input Code
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 49. Differential Linearity Error vs Digital Input Code
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TYpical Characteristics: VDD = +2.7 V (continued)
1.0
1.0
0.8
0.8
0.6
0.6
INL Max
0.2
0
-0.2
0.4
DNL Error (LSB)
INL Error (LSB)
0.4
INL Min
-0.4
0
-0.2
-0.6
-0.6
-0.8
-0.8
-1.0
0
0.5
1.0
1.5
2.0
VREFH Reference Voltage (V)
2.5
3.0
0
Figure 50. Linearity Error vs
0.5
1.0
1.5
2.0
VREFH Reference Voltage (V)
2.5
3.0
Figure 51. Differential Linearity Error vs Reference Voltage
1000
1.00
900
0.75
VREF = 2.5V, Gain = 1X Mode
800
700
Reference Current (mA)
AVDD Supply Current (mA)
DNL Min
-0.4
-1.0
VREF = 1.25V, Gain = 2X Mode
600
500
400
300
200
100
VREFH Current
0.50
VREFH = 2.5V
VREFL = 0V
0.25
0
VREFL Current
-0.25
-0.50
-0.75
DAC Code Set to FFFFh
0
-1.00
-55
-35
-15
5
25
45
65
Temperature (°C)
85
105
0
125
Figure 52. AVDD Supply Current vs Temperature
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 53. Reference Current vs Digital Input Code
1.00
3.0
DAC Loaded with FFFFh, VREFH = 2.7V
VREFH = 1.25V
VREFL = 0V
0.75
2.5
0.50
VREFH Current
0.25
0
DAC Loaded with FFFFh, VREFH = 2.5V
2.0
VOUT (V)
Reference Current (mA)
DNL Max
0.2
VREFL Current
-0.25
1.5
1.0
-0.50
0.5
-0.75
DAC Loaded with 0000h
0
-1.00
0
8192 16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 54. Reference Current vs Digital Input Code
(Gain = 2X Mode)
20
0
3
6
9
I(SOURCE/SINK) (mA)
12
15
Figure 55. Output Voltage vs Drive Current Capability
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TYpical Characteristics: VDD = +2.7 V (continued)
0.25
2.70
DAC Loaded with FFFFh
2.65
VOUT (V)
2.60
DAC Loaded
with FE00h
2.55
DAC Loaded
with FC00h
2.50
VOUT (V)
0.20
DAC Loaded
with F800h
DAC Loaded
with 0400h
0.15
DAC Loaded
with 0800h
DAC Loaded
with 0200h
0.10
DAC Loaded with FFFFh, VREFH = 2.5V
0.05
2.45
VREFH = 2.7V, unless otherwise noted.
2.40
DAC Loaded with 0000h
0
0
1
2
3
ISOURCE (mA)
4
5
0
1
2
3
4
5
ISINK (mA)
Figure 56. Output Voltage vs Drive Current Capability
(Operation Near AVDD Rail)
Figure 57. Output Voltage vs Drive Current Capability
(Operation Near AGND Rail)
Code Change: FFFFh to 0000h
Output Loaded with 10kW and
50pF to AGND
Large-Signal Output
1V/div
Large-Signal Output
Small-Signal Error
1V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 0000h to FFFFh
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Time (2ms/div)
Time (2ms/div)
Figure 58. Large Signal Settling Time
Figure 59. Large Signal Settling Time
Large-Signal Output
Large-Signal Output
1V/div
Small-Signal Error
1V/div
1mV/div
1mV/div
Small-Signal Error
5V/div
LDAC
Signal
Code Change: 1000h to F000h
Output Loaded with 10kW and
50pF to AGND
5V/div
LDAC
Signal
Time (2ms/div)
Code Change: F000h to 1000h
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 60. Large Signal Settling Time
Figure 61. Large Signal Settling Time
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TYpical Characteristics: VDD = +2.7 V (continued)
Code Change: 7FFFh to 8000h
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +2.5V
Gain = 1X Mode
VREFH = +2.5V
Integrated Glitch Energy (17.5nV-s)
100mV/div
VOUT Signal
100mV/div
VOUT Signal
Integrated Glitch Energy (16.5nV-s)
5V/div
LDAC
Signal
5V/div
LDAC
Signal
Time (2ms/div)
Time (2ms/div)
Figure 62. Major Carry Glitch
Figure 63. Major Carry Glitch
Code Change: 7FFFh to 8000h
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +1.25V
Code Change: 8000h to 7FFFh
Output Loaded with 10kW and
50pF to AGND
Gain = 1X Mode
VREFH = +1.25V
Integrated Glitch Energy (9.4nV-s)
100mV/div
VOUT Signal
100mV/div
VOUT Signal
Integrated Glitch Energy (7.8nV-s)
5V/div
LDAC
Signal
5V/div
Time (2ms/div)
Code Change: 8000h to 7FFFh
Output Loaded with 10kW and
50pF to AGND
Time (2ms/div)
Figure 64. Major Carry Glitch
22
LDAC
Signal
Figure 65. Major Carry Glitch
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7 Detailed Description
7.1 Overview
The DAC8881 is a single-channel, 16-bit, serial-input, voltage-output digital-to-analog converter (DAC). The
architecture is an R-2R ladder configuration with the four MSBs segmented, followed by an operational amplifier
that serves as a buffer, as shown in Figure 66. The on-chip output buffer allows rail-to-rail output swings while
providing a low output impedance to drive loads. The DAC8881 operates from a single analog power supply that
ranges from 2.7 V to 5.5 V, and typically consumes 850 μA when operating with a 3-V supply. Data are written to
the device in a 16-bit word format, via an SPI serial interface. To enable compatibility with 1.8 V, 3 V, or 5 V logic
families, an IOVDD supply pin is provided. This pin allows the DAC8881 input and output logic to be powered
from the same logic supply used to interface signals to and from the device. Internal voltage translators are
included in the DAC8881 to interface digital signals to the device core. Separate AVDD and DVDD supply pins are
provided, but should be connected together. See Figure 67 for the basic configuration of the DAC8881.
To ensure a known power-up state, the DAC8881 is designed with a power-on reset function. Upon power-up,
the DAC8881 is reset to either zero-scale or midscale depending on the state of the RSTSEL pin. The device
can also be hardware reset by using the RST and RSTSEL pins.
RFB(1)
RFB
R
VOUT
2R
2R
2R
2R
2R
2R
2R
2R
2R
5kW
VREFH
5kW
NOTE: (1) RFB = 5kW for gain = 1
RFB = 10kW for gain = 2.
VREFH-F
VREFH-S
VREFL-F
VREFL-S
Figure 66. DAC8881 Architecture
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Overview (continued)
SDOSEL
Chip-Select
CS
19
SDOSEL
20
DVDD
21
22
SDO
4
15
5
14
(Thermal Pad)
VOUT
VREFH-S
13
RST
Reset DAC Registers
USB/BTC
GAIN
RSTSEL
NC
12
6
7
VREFL-S
16
DAC8881
PDN
NC
AVDD
3
11
AGND
17
VREFH-F
Load DAC Registers
2
10
LDAC
18
9
Serial Data In
1
VREFL-F
SDI
8
SCLK
Clock
23
1mF
IOVDD
+
24
0.1mF
DGND
1mF
RFB
+
1.8V to 5V
0.1mF
Serial Data Out
+5V
0V to +5.0V
External Reference
+5.0000V
Figure 67. Basic Configuration
24
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7.2 Functional Block Diagram
DVDD
DGND
IOVDD
AGND
AVDD
VREFH-S VREFH-F
DAC8881
RST
Power-On
Reset
RSTSEL
Control
Logic
USB/BTC
Resistor
Network
SDI
CS
SCLK
SPI Interface
Shift Register
GAIN
PDN
Input
Register
DAC
Latch
VOUT
DAC
RFB(1)
RFB
SDOSEL
SDO
Serial Out
Control
NOTE: (1) RFB = 5kW for gain = 1,
RFB = 10kW for gain = 2.
LDAC
VREFL-S
VREFL-F
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7.3 Feature Description
7.3.1 Analog Output
The DAC8881 offers a force and sense output configuration for the high open-loop gain output amplifier. This
feature allows the loop around the output amplifier to be closed at the load (as shown in Figure 68), thus
ensuring an accurate output voltage. The output buffer VOUT and RFB pins are provided so that the output op amp
buffer feedback can be connected at the load. Without a driven load, the DAC8881 output typically swings to
within 15mV of the AGND and AVDD supply rails. Because of the high accuracy of these DACs, system design
problems such as grounding and contact resistance become very important. A 16-bit converter with a 5 V fullscale range has a 1 LSB value of 76 μV. With a load current of 1 mA, a series wiring and connector resistance of
only 80mΩ (RW2) causes a voltage drop of 80 μV. In terms of a system layout, the resistivity of a typical 1-ounce
copper-clad printed circuit board is 0.5mΩ per square. For a 1mA load, a 0.25 mm wide printed circuit conductor
25 mm long results in a voltage drop of 50 μV.
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Feature Description (continued)
SDOSEL
Chip-Select
19
CS
DVDD
SDOSEL
20
23
21
SDO
4
15
5
14
(Thermal Pad)
8
VOUT
VREFH-S
RW2
13
RST
Reset DAC Registers
USB/BTC
GAIN
RSTSEL
NC
12
6
7
VREFL-S
16
DAC8881
PDN
NC
AVDD
3
11
AGND
17
VREFH-F
Load DAC Registers
2
10
LDAC
18
9
Serial Data In
1
VREFL-F
SDI
RFB
SCLK
Clock
22
1mF
IOVDD
+
24
0.1mF
DGND
1mF
RW1
+
1.8V to 5V
0.1mF
Serial Data Out
+5V
VOUT
External Reference
+5.0000V
Figure 68. Analog Output Closed-Loop Configuration
(RW1 and RW2 represent wiring resistance)
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Feature Description (continued)
7.3.2 Reference Inputs
The reference high input, VREFH, can be set to any voltage in the range of 1.25 V to AVDD. The reference low
input, VREFL, can be set to any voltage in the range of –0.2 V to +0.2 V (to provide a small offset to the output of
the DAC8881, if desired). The current into VREFH and out of VREFL depends on the DAC code, and can vary from
approximately 0.5mA to 1mA in the gain = 1X mode of operation. The reference high and low inputs appear as
varying loads to the external reference circuit. If the external references can source or sink the required current,
and if low impedance connections are made to the VREFH and VREFL pins, external reference buffers are not
required. Figure 67 shows a simple configuration of the DAC8881 using external references without force/sense
reference buffers.
Kelvin sense connections for the reference high and low are included on the DAC8881. When properly used with
external reference buffer op amps, these reference Kelvin sense pins ensure that the driven reference high and
low voltages remain stable versus varying reference load currents. Figure 69 shows an example of a reference
force/sense configuration of the DAC8881 operating from a single analog supply voltage. Both the VREFL and
VREFH reference voltages are set to levels of 100 mV from the DAC8881 supply rails, and are derived from a 5-V
external reference. Figure 71 and Figure 70 illustrate the effect of not using the reference force/sense buffers to
drive the DAC8881 VREFL and VREFH pins. A slight degradation in INL and DNL performance of approximately 0.1
LSB may be seen without the use of the force/sense buffer configuration.
SCLK
SDI
LDAC
+5V
AGND
External Reference
+5.0000V
AVDD
OPA2350
VREFL-S
3
4
DAC8881
5
6
11
9
12
NC
VREFH-F
96kW
RFB
VREFH-S
1000pF
10
+4.900V
VREFL-F
7
50W
8
2200pF
2
VOUT
2kW
1
+0.100V
50W
2kW
2200pF
1000pF
LE (LSB)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
DLE (LSB)
LE (LSB)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
DLE (LSB)
Figure 69. Buffered References (VREFH = +4.900 V and VREFL = 100 mV)
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
+25°C
+25°C
0
8192
16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 70. Linearity and Differential Linearity Error
for Figure 67 without Reference Buffers
+25°C
+25°C
0
8192
16384 24576 32768 40960 49152 57344 65536
Digital Input Code
Figure 71. Linearity and Differential Linearity Error
for Figure 69 with Reference Buffers
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Feature Description (continued)
7.3.3 Output Range
The maximum output range of the DAC8881 is VREFL to VREFH × G, where G is the output buffer gain set by the
GAIN pin. When the GAIN pin is connected to DGND, the output buffer gain = 1. When the GAIN pin is
connected to IOVDD, the output buffer gain = 2. The output range must not be greater than AVDD; otherwise,
output saturation occurs. The DAC8881 output transfer function is given in Equation 1:
V
- VREFL
VOUT = REFH
´ CODE ´ Buffer Gain + VREFL
65536
(1)
Where:
CODE = 0 to 65535. This is the digital code loaded to the DAC.
Buffer Gain = 1 or 2 (set by the GAIN pin).
VREFH = reference high voltage applied to the device.
VREFL = reference low voltage applied to the device.
7.3.4 Input Data Format
The USB/BTC pin defines the input data format.
When this pin is connected to IOVDD, the input data format is straight binary, as shown in Table 1.
When this pin is connected to DGND, the input data format is twos complement, as shown in Table 2.
Table 1. Output vs Straight Binary Code
USB CODE
5 V RANGE
DESCRIPTION
FFFFh
+4.99992
+Full-Scale – 1LSB
C000h
+3.75000
3/4-Scale
8000h
+2.50000
Midscale
4000h
+1.25000
1/4-Scale
0000h
0.00000
Zero-Scale
Table 2. Output vs Twos Complement Code
BTC CODE
5 V RANGE
DESCRIPTION
7FFFh
+4.99992
+Full-Scale – 1LSB
4000h
+3.75000
3/4-Scale
0000h
+2.50000
Midscale
FFFFh
+2.49992
Midscale – 1LSB
C000h
+1.25000
1/4-Scale
8000h
0.00000
Zero-Scale
7.3.5 Hardware Reset
When the RST pin is low, the device is in hardware reset mode, and the input register and DAC latch are set to
the value defined by the RSTSEL pin. After RST goes high, the device is in normal operating mode. When
USB/BTC is connected to DGND, the device is in twos complement mode. In this case, the LDAC pin cannot be
kept at logic level '0' or toggled when a hardware reset is issued before writing a valid DAC data.
7.3.6 Power-On Reset
The DAC8881 has a power-on reset function. After power-on, the value of the input register, the DAC latch, and
the output from the VOUT pin are set to the value defined by the RSTSEL pin.
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7.3.7 Program Reset Value
After a power-on reset or a hardware reset, the output voltage from the VOUT pin and the values of the input
register and DAC latch are determined by the status of the RSTSEL pin and the input data format, as shown in
Table 3.
Table 3. Reset Value
LDAC PIN
RSTSEL PIN
USB/BTC PIN
INPUT
FORMAT
VOUT
VALUE OF INPUT REGISTER
AND DAC LATCH
DGND or IOVDD
DGND
IOVDD
DGND or IOVDD
IOVDD
IOVDD
Straight Binary
0
0000h
Straight Binary
Midscale
8000h
0
0000h
Midscale
8000h
IOVDD
DGND
DGND
Twos
Complement
IOVDD
IOVDD
DGND
Twos
Complement
7.3.8 Power Down
The DAC8881 has a hardware power-down function. When the PDN pin is high, the device is in power-down
mode. The VOUT pin is connected to ground through an internal 10-kΩ resistor, but the contents of the input
register and the DAC latch do not change. In power-down mode, SPI communication is still active.
7.3.9 Double-Buffered Interface
The DAC8881 has a double-buffered interface consisting of two register banks: the input register and the DAC
latch. The input register is connected directly to the input shift register and the digital code is transferred to the
input register upon completion of a valid write sequence. The DAC latch contains the digital code used by the
resistor R-2R ladder. The contents of the DAC latch defines the output from the DAC.
Access to the DAC register is controlled by the LDAC pin. When LDAC is high, the DAC register is latched and
the input register can change state without affecting the contents of the DAC latch. When LDAC is low, however,
the DAC latch becomes transparent and the contents of the input register is transferred to the DAC register.
7.3.10 Load DAC Pin (LDAC)
LDAC transfers data from the input register to the DAC register and; therefore, updates the DAC output. The
contents of the DAC latch (and the output from DAC) can be changed in two ways, depending on the status of
LDAC.
7.3.10.1 Synchronous Mode
When LDAC is tied low, the DAC register updates as soon as new data are transferred into the input register
after the rising edge of CS.
7.3.10.2 Asynchronous Mode
When LDAC is high, the DAC latch is latched. The DAC latch (and DAC output) is not updated at the same time
that the input register is written to. When LDAC goes low, the DAC register updates with the contents of the input
register.
7.3.11 1.8 V to 5.5 V Logic Interface
All digital input and output pins are compatible with any logic supply voltage between 1.8 V and 5.5 V. Connect
the interface logic supply voltage to the IOVDD pin. Although timing is specified down to 2.7 V (see the Timing
Characteristics), IOVDD can operate as low as 1.8 V, but with degraded timing and temperature performance. For
the lowest power consumption, logic VIH levels should be as close as possible to IOVDD, and logic VIL levels
should be as close as possible to GND. Note that the DAC8881 core internal digital logic operates from the same
voltage as the 2.7V to 5.5V AVDD supply, so the DVDD pin must also be connected to the AVDD supply voltage.
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7.4 Device Functional Modes
7.4.1 Serial Interface
The DAC8881 is controlled by a versatile 3-wire serial interface that operates at clock rates of up to 50 MHz and
is compatible with SPI, QSPI™, MICROWIRE™, and DSP™ interface standards.
7.4.1.1 Input Shift Register
Data are loaded into the device as a 16-bit word under the control of the serial clock input, SCLK. The timing
diagrams for this operation are shown in the Timing Diagram section.
The CS input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be
transferred into the device only while CS is low. To start the serial data transfer, CS should be taken low,
observing the minimum CS falling edge to SCLK rising edge setup time, t2. After CS goes low, serial data are
clocked into the device input shift register on the rising edges of SCLK for 16 or more clock pulses. If a frame
contains less than 16 bits of data, the frame is invalid. Invalid data are not written into the input register and
DAC, although the input register and DAC will continue to hold data from the preceding valid data cycle. If more
than 16 bits of data are transmitted in one frame, the last 16 bits are written into the shift register and DAC. CS
may be taken high after the rising edge of the 16th SCLK pulse, observing the minimum SCLK rising edge to CS
rising edge time, t7. The contents of the shift register are transferred into the input register on the rising edge of
CS. When data have been transferred into the input register of the DAC, the corresponding DAC register and
DAC output can be updated by taking the LDAC pin low.
7.4.1.1.1 Stand-Alone Mode
When the SDOSEL pin is tied to IOVDD, the interface is in Stand-Alone mode. This mode provides serial
readback for diagnostic purposes. The new input data (16 bits) are clocked into the device shift register and the
existing data in the input register (16 bits) are shifted out from the SDO pin. If more than 16 SCLKs are clocked
when CS is low, the contents of the input register are shifted out from the SDO pin, followed by zeroes; the last
16 bits of input data remain in the shift register. If less than 16 SCLKs are clocked while CS is low, the data from
the SDO pin are part of the data in the input register and must be ignored. Refer to Figure 2 for further detail.
7.4.1.1.2 Daisy-Chain Mode
When the SDOSEL pin is tied to GND, the interface is in Daisy-Chain mode. For systems that contain several
DACs, the SDO pin may be used to daisy-chain several devices together.
In Daisy-Chain mode, SCLK is continuously applied to the input shift register while CS is low. If more than 16
clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. These data are
clocked out on the falling edge of SCLK and are valid on the rising edge. By connecting this line to the DIN input
on the next DAC in the chain, a multi-DAC interface is constructed. 16 clock pulses are required for each DAC in
the system. Therefore, the total number of clock cycles must be equal to (16 x N), where N is the total number of
devices in the chain. When the serial transfer to all devices is complete, CS should be taken high. This action
prevents any further data from being clocked into the input shift register. The contents in the shift registers are
transferred into the relevant input registers on the rising edge of the CS signal.
A continuous SCLK source may be used if CS can be held low for the correct number of clock cycles.
Alternatively, a burst clock containing the exact number of clock cycles can be used and CS can be taken high
some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC
registers, and all analog outputs update simultaneously.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The excellent linearity as well as low-noise and fast settling time makes the DAC8881 a strong performer in
applications such as automatic test equipment, precision instrumentation and data acquisition systems.
Additionally, the energy saving feature of the device, through the PDN pin, significantly reduces power
dissipation -- this mode reduces current consumption, as low as 25 µA with a 5-V supply.
8.1.1 Bipolar Operation Using The DAC8881
The DAC8881 is designed for single-supply operation; however, a bipolar output is also possible using the circuit
shown in Figure 72. This circuit gives a bipolar output voltage of VOUT. When GAIN = 1, VOUT can be
calculated using Equation 2:
V REFL
+15 V
DAC8881 V DAC
V REFH
R2
VOUT
OPA192
- 15 V
R1
R3
V REF
Copyright © 2017, Texas Instruments Incorporated
Some pins are omitted for clarity.
Figure 72. Bipolar Operation Using the DAC8881
VBIP(CODE) = 1 +
R3 R3
CODE
R
- 3 ´ VREF
+
´
R2 R1
65536
R1
(2)
Where:
VBIP(CODE) = bipolar output voltage versus CODE from the OPA211.
CODE = 0 to 262143. This is the digital code loaded to the DAC.
VREF = reference high voltage applied to the DAC8881.
As an example, a ±8-V output span can be achieved by using values of 5 V, 6.25 kΩ, 16.67 kΩ, and 10 kΩ for
Vref, R1, R2, and R3 respectively.
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8.2 Typical Application
8.2.1 DAC8881 Sample Hold Circuit
OPA192(A)
DAC8881
OPA192(B)
RS
+
RL Vout
+
Switch (NC)
TS12A4515
CH
CL
Copyright © 2017, Texas Instruments Incorporated
Figure 73. DAC8881 Sample and Hold Circuit
8.2.1.1 Design Requirements
The inherent architecture of the DAC8881, which consists of an R-2R architecture, enables great performance in
regards to noise and accuracy, but at a cost of large glitch area. Glitch area, also known as glitch impulse area,
is defined as the area associated with the overshoot or undershoot created by a code transition, and is generally
quantified in Volt-seconds. Different code-to-code transitions produce different levels of glitch impulses. DACs
with R-2R architectures produce large glitches during major-carry transitions.
There are two methods that can be used to reduce this glitch area:
1. Add an external RC Filter to the output of the DAC.
– The low-pass filter helps attenuate high-frequency glitches that would normally propagate to the DAC
output. Best practice is to use a small resistor value, as large resistance develops a large potential drop
and reduces the voltage seen at the load. Capacitor values can be determined from the desired cutoff
frequency of the low-pass filter, as well as settling time.
2. Another technique is to employ a Sample and Hold (S&H) circuit following the DAC output.
– In its simplest form, the sample and hold circuit can be constructed from the following components: a
capacitive element, output buffer, and switch. A schematic of the simplified S&H is shown in Figure 74.
RS
DAC
RL
+
Vout
Switch (NC)
CL
CH
Digital/Discrete
Switch Driver
Copyright © 2016, Texas Instruments Incorporated
Figure 74. Simplified Sample and Hold Circuit
8.2.1.2 Detailed Design Procedure
The Sample/Track and Hold modes of operation correspond to the state of the switch, which connects the DAC
output to the hold capacitor CH. In sample mode – also referred to as track mode -- the switch is closed, allowing
the capacitor to charge or discharge to the sampled DAC output voltage. The operational amplifier is configured
as a buffer, which tracks and relays the voltage seen across CH to the output of the circuit. In hold mode, the
switch opens, disconnecting CH from the DAC output. The DAC is updated while the circuit is in hold mode,
preventing any DAC major carry glitches from propagating to the S&H output. The capacitor retains the previous
sampled voltage, and this value is buffered to the output of the circuit. In real circuits, switch leakage and
operational amplifier input bias current must be considered as it will impact circuit performance. The switch is
generally controlled by an external discrete or digital driver.
32
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Typical Application (continued)
Once the DAC glitch relays the switch closes and re-enters sample or track mode.
More information related to this circuit can be found in Sample & Hold Glitch Reduction for Precision Outputs
Design Guide (TIDU022).
8.2.1.3 Application Curves
Glitch reduction and total unadjusted error (TUE) plots of the solution presented in Sample & Hold Glitch
Reduction for Precision Outputs Design Guide (TIDU022) is shown in the following plots. The glitch area is
reduced from 35.11 nVs to 2.01 nVs.
CH = 8.2 nF
Figure 75. DAC8881 Sample and Hold TUE Error %FSR
RS = 14.7 Ω
Figure 76. Measured Glitch Area
(20000h-1FFFFh 18-bit Data)
(Top) Digital Signal One-Shot Pulse; (Middle) DAC Output
Glitch; (Bottom) S&H Output Glitch
8.3 System Example
Figure 77 displays a typical serial interface that may be used when connecting the DAC8881 SPI serial interface
to a (master) microcontroller. The setup for the interface is as follows: The microcontroller output SPI CLK drives
the SCLK pin of the DAC8881, while the DAC8881 SDI pin is driven by the MOSI pin of the microcontroller. The
CS pin of the DAC8881 can be asserted from a general program input/output pin of the microcontroller. When
data are to be transmitted to the DAC8881, the CS pint is taken low. The data from the microcontroller is then
transmitted to the DAC8881, totaling 24 bits latched into the DAC8881 device through the negative edge of
SCLK. CS is then brought high after the completed write. The DAC8881 requires its data with the MSB as the
first bit received.
microcontroller
DAC8881
CS
CS
SCL
K
SCLK
MOSI
SDI
MISO
SDO
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Figure 77. Simplified Sample and Hold Circuit
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9 Power Supply Recommendations
The DAC8881 can operate within the specified supply voltage range of 2.7 V to 5.5 V. The power applied to
AVDD should be well regulated and low noise. Switching power supplies and DC-DC converters often have highfrequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high
frequency spikes. This noise can easily couple into the DAC output voltage through various paths between the
power connections and analog output. To further minimize noise from the power supply, a strong
recommendation is to include a 1-µF to 10-µF capacitor and 0.1-µF bypass capacitor. The current consumption
on the AVDD pin, the short-circuit current limit, and the load current for the device is listed in Electrical
Characteristics. The power supply must meet the aforementioned current requirements.
10 Layout
10.1 Layout Guidelines
A precision analog component requires careful layout, the list below provides some insight into good layout
practices.
• All Power Supply pins should be bypassed to ground with a low ESR ceramic bypass capacitor. The typical
recommended bypass capacitance is 0.1 to 0.22 µF ceramic with a X7R or NP0 dielectric.
• Power supplies and VrefH/L bypass capacitors should be placed close to terminals to minimize inductance
and optimize performance.
• A high-quality ceramic type NP0 or X7R is recommended for its optimal performance across temperature, and
very low dissipation factor.
• The digital and analog sections should have proper placement with respect to the digital pins and analog pins
of the DAC8881 device. The separation of analog and digital blocks will allow for better design and practice
as it will ensure less coupling into neighboring blocks, and will minimize the interaction between analog and
digital return currents.
10.2 Layout Example
Pullup Resistors
R1 R2 R3
IOVDD
GND
GND
GND
Supply Bypass
Capacitors C1
GND
Reference Bypass
Capacitors
GND
18
12
GND
C4
GND
24
1
6
GND
C2
GND
GND
C3
DIGITAL SIDE
GND
ANALOG SIDE
Figure 78. DAC8881 Basic Layout Example
34
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• DAC8881 Evaluation Module (SLAU257)
• Sample & Hold Glitch Reduction for Precision Outputs Design Guide (TIDU022)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
DSP, E2E are trademarks of Texas Instruments.
SPI, QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
DAC8881SRGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 105
DAC
8881
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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