DAC900
900
DAC
DAC9
00
SBAS093B – MAY 2002
10-Bit, 165MSPS
DIGITAL-TO-ANALOG CONVERTER
TM
FEATURES
DESCRIPTION
●
●
●
●
●
The DAC900 is a high-speed, Digital-to-Analog Converter (DAC)
offering a 10-bit resolution option within the SpeedPlus family of
high-performance converters. Featuring pin compatibility among
family members, the DAC908, DAC902, and DAC904 provide a
component selection option to an 8-, 12-, and 14-bit resolution,
respectively. All models within this family of DACs support update
rates in excess of 165MSPS with excellent dynamic performance,
and are especially suited to fulfill the demands of a variety of
applications.
SINGLE +5V OR +3V OPERATION
HIGH SFDR: 5MHz Output at 100MSPS: 68dBc
LOW GLITCH: 3pV-s
LOW POWER: 170mW at +5V
INTERNAL REFERENCE:
Optional Ext. Reference
Adjustable Full-Scale Range
Multiplying Option
The advanced segmentation architecture of the DAC900 is optimized to provide a high Spurious-Free Dynamic Range (SFDR) for
single-tone, as well as for multi-tone signals—essential when used
for the transmit signal path of communication systems.
APPLICATIONS
● COMMUNICATION TRANSMIT CHANNELS
WLL, Cellular Base Station
Digital Microwave Links
Cable Modems
● WAVEFORM GENERATION
Direct Digital Synthesis (DDS)
Arbitrary Waveform Generation (ARB)
● MEDICAL/ULTRASOUND
● HIGH-SPEED INSTRUMENTATION AND CONTROL
● VIDEO, DIGITAL TV
+VA
The DAC900 has a high impedance (200kΩ) current output with a
nominal range of 20mA and an output compliance of up to 1.25V.
The differential outputs allow for both a differential or singleended analog signal interface. The close matching of the current
outputs ensures superior dynamic performance in the differential
configuration, which can be implemented with a transformer.
Utilizing a small geometry CMOS process, the monolithic DAC900
can be operated on a wide, single-supply range of +2.7V to +5.5V.
Its low power consumption allows for use in portable and batteryoperated systems. Further optimization can be realized by lowering
the output current with the adjustable full-scale option.
For noncontinuous operation of the DAC900, a power-down mode
results in only 45mW of standby power.
+VD
BW
DAC900
FSA
Current
Sources
REFIN
IOUT
LSB
Switches
IOUT
BYP
The reference structure of the DAC900 allows for additional
flexibility by utilizing the on-chip reference, or applying an external reference. The full-scale output current can be adjusted over a
span of 2mA to 20mA, with one external resistor, while maintaining the specified dynamic performance.
PD
The DAC900 is available in SO-28 and TSSOP-28 packages.
Segmented
Switches
INT/EXT
Latches
The DAC900 comes with an integrated 1.24V bandgap reference
and edge-triggered input latches, offering a complete converter
solution. Both +3V and +5V CMOS logic families can be interfaced to the DAC900.
+1.24V Ref.
10-Bit Data Input
AGND
CLK
D9...D0
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
+VA to AGND ........................................................................ –0.3V to +6V
+VD to DGND ........................................................................ –0.3V to +6V
AGND to DGND ................................................................. –0.3V to +0.3V
+VA to +VD ............................................................................... –6V to +6V
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
CLK, PD to DGND ..................................................... –0.3V to VD + 0.3V
D0-D9 to DGND ......................................................... –0.3V to VD + 0.3V
IOUT, IOUT to AGND ........................................................ –1V to VA + 0.3V
BW, BYP to AGND ..................................................... –0.3V to VA + 0.3V
REFIN, FSA to AGND ................................................. –0.3V to VA + 0.3V
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
INT/EXT to AGND ...................................................... –0.3V to VA + 0.3V
Junction Temperature .................................................................... +150°C
Case Temperature ......................................................................... +100°C
Storage Temperature .................................................................... +125°C
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
DAC900U
SO-28
217
–40°C to +85°C
DAC900U
"
"
"
"
TSSOP-28
360
–40°C to +85°C
DAC900E
"
"
"
"
"
DAC900E
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
DAC900U
DAC900U/1K
DAC900E
DAC900E/2K5
Rails
Tape and Reel
Rails
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “DAC900E/2K5” will get a single 2500-piece Tape and Reel.
DEMO BOARD ORDERING INFORMATION
PRODUCT
DEMO BOARD
ORDERING NUMBER
DAC900U
DAC900E
DEM-DAC90xU
DEM-DAC900E
COMMENT
Populated evaluation board without DAC. Order sample of desired DAC90x model separately.
Populated evaluation board including the DAC900E.
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified.
DAC900U/E
PARAMETER
CONDITIONS
MIN
TYP
2.7V to 3.3V
4.5V to 5.5V
Ambient, TA
125
165
–40
–0.5
–1.0
±0.3
±0.5
70
76
75
68
68
62
62
53
59
53
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
78
78
dBc
dBc
–74
–73
dBc
dBc
60
30
dBc
ns
RESOLUTION
OUTPUT UPDATE RATE
Output Update Rate (fCLOCK)
Full Specified Temperature Range, Operating
STATIC ACCURACY(1)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
DYNAMIC PERFORMANCE
Spurious-Free Dynamic Range (SFDR)
fOUT = 1.0MHz, fCLOCK = 25MSPS
fOUT = 2.1MHz, fCLOCK = 50MSPS
fOUT = 5.04MHz, fCLOCK = 50MSPS
fOUT = 5.04MHz, fCLOCK = 100MSPS
fOUT = 20.2MHz, fCLOCK = 100MSPS
fOUT = 25.3MHz, fCLOCK = 125MSPS
fOUT = 41.5MHz, fCLOCK = 125MSPS
fOUT = 27.4MHz, fCLOCK = 165MSPS
fOUT = 54.8MHz, fCLOCK = 165MSPS
Spurious-Free Dynamic Range within a Window
fOUT = 5.04MHz, fCLOCK = 50MSPS
fOUT = 5.04MHz, fCLOCK = 100MSPS
Total Harmonic Distortion (THD)
fOUT = 2.1MHz, fCLOCK = 50MSPS
fOUT = 2.1MHz, fCLOCK = 125MSPS
Two Tone
fOUT1 = 13.5MHz, fOUT2 = 14.5MHz, fCLOCK = 100MSPS
Output Settling Time(2)
2
fCLOCK
TA = +25°C
= 25MSPS, fOUT = 1.0MHz
MAX
UNITS
10
Bits
165
200
+85
MSPS
MSPS
°C
+0.5
+1.0
LSB
LSB
TA = +25°C
To Nyquist
2MHz Span
4MHz Span
to 0.1%
DAC900
SBAS093B
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified.
DAC900U/E
PARAMETER
DYNAMIC PERFORMANCE (Cont.)
Output Rise Time(2)
Output Fall Time(2)
Glitch Impulse
DC-ACCURACY
Full-Scale Output Range(3)(FSR)
Output Compliance Range
Gain Error
Gain Error
Gain Drift
Offset Error
Offset Drift
Power-Supply Rejection, +VA
Power-Supply Rejection, +VD
Output Noise
Output Resistance
Output Capacitance
CONDITIONS
10% to 90%
10% to 90%
All Bits High, IOUT
With Internal Reference
With External Reference
With Internal Reference
With Internal Reference
With Internal Reference
POWER SUPPLY
Supply Voltages
+VA
+VD
Supply Current(6)
IVA
IVA, Power-Down Mode
IVD
Power Dissipation
Power Dissipation, Power-Down Mode
Thermal Resistance, θJA
SO-28
TSSOP-28
TYP
MAX
2
2
3
2.0
–1.0
–10
–10
±1
±2
±120
–0.025
IOUT = 20mA, RLOAD = 50Ω
20.0
+1.25
+10
+10
+0.025
+0.2
+0.025
50
200
12
IOUT, IOUT to Ground
+1.24
±10
±50
10
1
0.1
1.25
1.3
+VD
+VD
+VD
+VD
+VD
+VD
=
=
=
=
=
=
+5V
+5V
+3V
+3V
+5V
+5V
3.5
2
+2.7
+2.7
+5V, IOUT = 20mA
+3V, IOUT = 2mA
Straight Binary
Rising Edge of Clock
5
0
3
0
±20
±20
5
UNITS
ns
ns
pV-s
±0.1
–0.2
–0.025
REFERENCE
Reference Voltage
Reference Tolerance
Reference Voltage Drift
Reference Output Current
Reference Input Resistance
Reference Input Compliance Range
Reference Small-Signal Bandwidth(4)
DIGITAL INPUTS
Logic Coding
Latch Command
Logic High Voltage, VIH
Logic Low Voltage, VIL
Logic High Voltage, VIH
Logic Low Voltage, VIL
Logic High Current, IIH(5)
Logic Low Current, IIL
Input Capacitance
MIN
mA
V
%FSR
%FSR
ppmFSR/°C
%FSR
ppmFSR/°C
%FSR/V
%FSR/V
pA/√Hz
kΩ
pF
V
%
ppmFSR/°C
µA
MΩ
V
MHz
0.8
V
V
V
V
µA
µA
pF
+5
+5
+5.5
+5.5
V
V
24
1.1
8
170
50
45
30
2
15
230
mA
mA
mA
mW
mW
mW
75
50
1.2
°C/W
°C/W
NOTES: (1) At output IOUT, while driving a virtual ground. (2) Measured single-ended into 50Ω Load. (3) Nominal full-scale output current is 32x IREF; see Application
Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45µA for the PD pin, which has an
internal pull-down resistor. (6) Measured at fCLOCK = 50MSPS and fOUT = 1.0MHz.
DAC900
SBAS093B
3
PIN CONFIGURATION
PIN DESCRIPTIONS
Top View
SO, TSSOP
Bit 1
1
28
CLK
Bit 2
2
27
+VD
Bit 3
3
26
DGND
Bit 4
4
25
NC
Bit 5
5
24
+VA
Bit 6
6
23
BYP
Bit 7
7
22
IOUT
Bit 8
8
21
IOUT
Bit 9
9
20
AGND
Bit 10 10
19
BW
NC 11
18
FSA
NC 12
17
REFIN
NC 13
16
INT/EXT
NC 14
15
PD
DAC900
PIN
DESIGNATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
NC
NC
NC
NC
PD
16
INT/EXT
17
REFIN
18
19
FSA
BW
20
21
22
23
24
25
26
27
28
AGND
IOUT
IOUT
BYP
+VA
NC
DGND
+VD
CLK
DESCRIPTION
Data Bit 1 (D9), MSB
Data Bit 2 (D8)
Data Bit 3 (D7)
Data Bit 4 (D6)
Data Bit 5 (D5)
Data Bit 6 (D4)
Data Bit 7 (D3)
Data Bit 8 (D2)
Data Bit 9 (D1)
Data Bit 10 (D0), LSB
No Connection
No Connection
No Connection
No Connection
Power Down, Control Input; Active
HIGH. Contains internal pull-down circuit;
may be left unconnected if not used.
Reference Select Pin; Internal ( = 0) or
External ( = 1) Reference Operation.
Reference Input/Ouput. See Applications
section for further details.
Full-Scale Output Adjust
Bandwidth/Noise Reduction Pin:
Bypass with 0.1µF to +VA for Optimum
Performance.
Analog Ground
Complementary DAC Current Output
DAC Current Output
Bypass Node: Use 0.1µF to AGND
Analog Supply Voltage, 2.7V to 5.5V
No Connection
Digital Ground
Digital Supply Voltage, 2.7V to 5.5V
Clock Input
TYPICAL CONNECTION CIRCUIT
+5V
+5V
0.1µF
+VA
+VD
BW
DAC900
IOUT
LSB
Switches
FSA
Current
Sources
REFIN
RSET
0.1µF
1:1
IOUT
BYP
Segmented
MSB
Switches
0.1µF
50Ω
20pF
50Ω
20pF
INT/EXT
PD
Latches
+1.24V Ref.
10-Bit Data Input
AGND
4
CLK
D9.......D0
DGND
DAC900
SBAS093B
TIMING DIAGRAM
t2
t1
CLOCK
tS
D13 D0
Data Changes
tH
Stable Valid Data
Data Changes
tPD
tSET
Iout or
Iout
SYMBOL
t1
t2
tS
tH
tPD
tSET
DAC900
SBAS093B
DESCRIPTION
Clock Pulse HIGH Time
Clock Pulse LOW Time
Data Setup Time
Data Hold Time
Propagation Delay Time
Output Settling Time to 0.1%
MIN
TYP
3
3
1.5
1.0
1
30
MAX
UNITS
ns
ns
ns
ns
ns
ns
5
TYPICAL CHARACTERISTICS: VD = VA = +5V
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
TYPICAL INL
0.75
0.75
0.50
0.50
DAC Code
85
85
80
80
SFDR (dBc)
SFDR (dBc)
1000
1024
900
800
SFDR vs fOUT AT 50MSPS
90
–6dBFS
75
70
75
–6dBFS
70
65
0dBFS
65
0dBFS
60
60
55
0
2.0
4.0
6.0
8.0
Frequency (MHz)
10.0
12.0
0
5.0
10.0
15.0
Frequency (MHz)
20.0
25.0
SFDR vs fOUT AT 125MSPS
SFDR vs fOUT AT 100MSPS
85
85
80
80
75
75
SFDR (dBc)
SFDR (dBc)
700
DAC Code
SFDR vs fOUT AT 25MSPS
70
–6dBFS
65
60
55
70
–6dBFS
65
60
55
0dBFS
50
0dBFS
50
45
45
0
6
600
0
1000
1024
900
800
700
600
500
–1.00
400
–1.00
300
–0.75
200
–0.50
–0.75
100
–0.50
500
–0.25
400
–0.25
0
300
0
0.25
200
0.25
100
Error (LSBs)
1.00
0
Error (LSBs)
TYPICAL DNL
1.00
10.0
20.0
30.0
Frequency (MHz)
40.0
50.0
0
10.0
20.0
30.0
40.0
Frequency (MHz)
50.0
60.0
DAC900
SBAS093B
TYPICAL CHARACTERISTICS: VD = VA = +5V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
SFDR vs fOUT AT 165MSPS
SFDR vs fOUT AT 200MSPS
80
80
75
75
70
–6dBFS
65
SFDR (dBc)
SFDR (dBc)
70
60
55
65
–6dBFS
60
55
0dBFS
0dBFS
50
50
45
45
40
40
0
10.0
20.0
30.0 40.0 50.0
Frequency (MHz)
60.0
70.0
80.0
0
DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT
AT 100MSPS
30.0 40.0 50.0 60.0 70.0 80.0
Frequency (MHz)
90.0
SFDR vs IOUTFS and fOUT AT 100MSPS, 0dBFS
85
80
80
70
IOUT (–6dBFS)
SFDR (dBc)
X
70
Diff (–6dBFS)
65
2.1MHz
75
X
75
SFDR (dBc)
10.0 20.0
X
X
60
X
X
55
*
X
X
10.1MHz
IOUT (0dBFS)
*
5.04MHz
*
60
55
40.4MHz
50
X
50
65
*
X
X
10
20
45
Diff (0dBFS)
45
40
0
10.0
20.0
30.0
Frequency (MHz)
40.0
50.0
2
IOUTFS (mA)
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
THD vs fCLOCK AT fOUT = 2.1MHz
85
–70
80
–75
2.1MHz
75
–85
SFDR (dBc)
2HD
–80
THD (dBc)
5
3HD
–90
70
65
10.1MHz
60
55
40.4MHz
–95
50
–100
0
DAC900
SBAS093B
25
50
100
fCLOCK (MSPS)
125
150
X
X
45
–40
X
X
–20
0
X
25
50
Temperature (°C)
X
X
70
85
7
TYPICAL CHARACTERISTICS: VD = VA = +5V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
DUAL-TONE OUTPUT SPECTRUM
FOUR-TONE OUTPUT SPECTRUM
0
0
–10
–10
fCLOCK = 100MSPS
fOUT1 = 13.5MHz
fOUT2 = 14.5MHz
SFDR = 60dBc
Amplitude = 0dBFS
–30
–40
–50
–60
–70
–30
–40
–50
–60
–70
–80
–80
–90
–90
–100
–100
0
5
10
15
20
25
30
Frequency (MHz)
8
fCLOCK = 50MSPS
fOUT1 = 6.25MHz
fOUT2 = 6.75MHz
fOUT3 = 7.25MHz
fOUT4 = 7.75MHz
SFDR = 66dBc
Amplitude = 0dBFS
–20
Magnitude (dBm)
Magnitude (dBm)
–20
35
40
45
50
0
5
10
15
20
25
Frequency (MHz)
DAC900
SBAS093B
TYPICAL CHARACTERISTICS: VD = VA = +3V
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
SFDR vs fOUT AT 25MSPS
SFDR vs fOUT AT 50MSPS
85
85
80
80
75
SFDR (dBc)
SFDR (dBc)
–6dBFS
70
0dBFS
65
75
–6dBFS
70
65
60
60
55
55
0dBFS
0
2.0
4.0
6.0
8.0
Frequency (MHz)
10.0
12.0
0
5.0
10.0
15.0
Frequency (MHz)
85
80
80
75
75
–6dBFS
70
–6dBFS
65
60
70
65
60
0dBFS
55
55
0dBFS
50
50
45
45
0
10.0
20.0
30.0
Frequency (MHz)
40.0
50.0
0
10.0
20.0
30.0
40.0
Frequency (MHz)
50.0
60.0
DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT
AT 100MSPS
SFDR vs fOUT AT 165MSPS
80
85
75
80
70
75
X
X
65
SFDR (dBc)
SFDR (dBc)
25.0
SFDR vs fOUT AT 125MSPS
85
SFDR (dBc)
SFDR (dBc)
SFDR vs fOUT AT 100MSPS
20.0
–6dBFS
60
55
50
Diff (–6dBFS)
70
X
65
X
Diff (0dBFS)
60
X
55
0dBFS
45
IOUT (0dBFS)
50
40
0
DAC900
SBAS093B
10.0
20.0
30.0 40.0 50.0
Frequency (MHz)
60.0
70.0
80.0
X
X
IOUT (–6dBFS)
45
0
10.0
20.0
30.0
Frequency (MHz)
40.0
50.0
9
TYPICAL CHARACTERISTICS: VD = VA = +3V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
SFDR vs IOUTFS and fOUT AT 100MSPS
80
THD vs fCLOCK AT fOUT = 2.1MHz
–70
2.1MHz
2HD
75
5.04MHz
70
X
X
X
X
–80
10.1MHz
65
THD (dBc)
SFDR (dBc)
–75
60
55
50
*
–90
40.4MHz
*
3HD
–85
*
*
–95
45
40
–100
2
5
10
20
0
25
50
100
fCLOCK (MSPS)
IOUTFS (mA)
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
0
2.1MHz
–10
75
fCLOCK = 100MSPS
fOUT1 = 13.5MHz
fOUT2 = 14.5MHz
SFDR = 61.5dBc
Amplitude = 0dBFS
–20
Magnitude (dBm)
70
SFDR (dBc)
150
DUAL-TONE OUTPUT SPECTRUM
80
10.1MHz
65
60
55
40.4MHz
50
45
125
X
40
–40
X
X
X
X
X
X
–30
–40
–50
–60
–70
–80
–90
–100
–20
0
25
50
Temperature (°C)
70
85
0
5
10
15
20
25
30
35
40
45
50
Frequency (MHz)
FOUR-TONE OUTPUT SPECTRUM
0
–10
fCLOCK = 50MSPS
fOUT1 = 6.25MHz
fOUT2 = 6.75MHz
fOUT3 = 7.25MHz
fOUT4 = 7.75MHz
SFDR = 62.5dBc
Amplitude = 0dBFS
Magnitude (dBm)
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
25
Frequency (MHz)
10
DAC900
SBAS093B
APPLICATION INFORMATION
DAC TRANSFER FUNCTION
THEORY OF OPERATION
The total output current, IOUTFS, of the DAC900 is the
summation of the two complementary output currents:
The architecture of the DAC900 uses the current steering
technique to enable fast switching and a high update rate. The
core element within the monolithic DAC is an array of
segmented current sources, which are designed to deliver a
full-scale output current of up to 20mA, as shown in Figure 1.
An internal decoder addresses the differential current switches
each time the DAC is updated and a corresponding output
current is formed by steering all currents to either output
summing node, IOUT or IOUT. The complementary outputs
deliver a differential output signal that improves the dynamic
performance through reduction of even-order harmonics,
common-mode signals (noise), and double the peak-to-peak
output signal swing by a factor of two, compared to singleended operation.
IOUTFS = IOUT + IOUT
(1)
The individual output currents depend on the DAC code and
can be expressed as:
IOUT = IOUTFS • (Code/1024)
(2)
IOUT = IOUTFS • (1023 – Code/1024)
(3)
where ‘Code’ is the decimal representation of the DAC data
input word. Additionally, IOUTFS is a function of the reference current IREF, which is determined by the reference
voltage and the external setting resistor, RSET.
The segmented architecture results in a significant reduction
of the glitch energy, and improves the dynamic performance
(SFDR) and DNL. The current outputs maintain a very high
output impedance of greater than 200kΩ.
IOUTFS = 32 • IREF = 32 • VREF /RSET
The full-scale output current is determined by the ratio of the
internal reference voltage (1.24V) and an external resistor,
RSET. The resulting IREF is internally multiplied by a factor
of 32 to produce an effective DAC output current that can
range from 2mA to 20mA, depending on the value of RSET.
(4)
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
The DAC900 is split into a digital and an analog portion,
each of which is powered through its own supply pin. The
digital section includes edge-triggered input latches and the
decoder logic, while the analog section comprises the current source array with its associated switches and the reference circuitry.
VOUT = IOUT • RLOAD
(5)
VOUT = IOUT • RLOAD
(6)
+3V to +5V
Digital
+3V to +5V
Analog
0.1µF
Bandwidth
Control
+VA
DAC900
+VD
IOUT
Full-Scale
Adjust
Resistor
RSET
2kΩ
BW
FSA
Ref
Control
Amp
Ref
Input REFIN
400pF
PMOS
Current
Source
Array
0.1µF
LSB
Switches
1:1
VOUT
IOUT
Segmented
MSB
Switches
50Ω
0.1µF
20pF
50Ω
20pF
BYP
INT/EXT
Ref
Buffer
Latches and Switch
Decoder Logic
PD
Power Down
(internal pull-down)
+1.24V Ref
AGND
Analog
Ground
CLK
10-Bit Data Input
Clock
Input
DGND
D9...D0
Digital
Ground
NOTE: Supply bypassing not shown.
FIGURE 1. Functional Block Diagram of the DAC900.
DAC900
SBAS093B
11
The value of the load resistance is limited by the output
compliance specification of the DAC900. To maintain specified linearity performance, the voltage for IOUT and IOUT
should not exceed the maximum allowable compliance range.
The two single-ended output voltages can be combined to
find the total differential output swing:
VOUTDIFF = VOUT – VOUT =
(2 • Code – 1023)
• I OUTFS • R LOAD (7)
1024
ANALOG OUTPUTS
The DAC900 provides two complementary current outputs,
IOUT and IOUT. The simplified circuit of the analog output
stage representing the differential topology is shown in
Figure 2. The output impedance of 200kΩ || 12pF for IOUT
and IOUT results from the parallel combination of the differential switches, along with the current sources and associated parasitic capacitances.
IOUT and IOUT. Furthermore, using the differential output
configuration in combination with a transformer will be
instrumental for achieving excellent distortion performance.
Common-mode errors, such as even-order harmonics or
noise, can be substantially reduced. This is particularly the
case with high output frequencies and/or output amplitudes
below full-scale.
For those applications requiring the optimum distortion and
noise performance, it is recommended to select a full-scale
output of 20mA. A lower full-scale range down to 2mA may
be considered for applications that require a low power
consumption, but can tolerate a reduced performance level.
INPUT CODE (D9 - D0)
IOUT
IOUT
11 1111 1111
20mA
0mA
10 0000 0000
10mA
10mA
00 0000 0000
0mA
20mA
TABLE I. Input Coding vs Analog Output Current.
OUTPUT CONFIGURATIONS
+VA
DAC900
IOUT
IOUT
RL
RL
FIGURE 2. Equivalent Analog Output.
The signal voltage swing that may develop at the two
outputs, IOUT and IOUT, is limited by a negative and positive
compliance. The negative limit of –1V is given by the
breakdown voltage of the CMOS process, and exceeding it
will compromise the reliability of the DAC900, or even
cause permanent damage. With the full-scale output set to
20mA, the positive compliance equals 1.25V, operating with
+VD = 5V. Note that the compliance range decreases to
about 1V for a selected output current of IOUTFS = 2mA.
Care should be taken that the configuration of DAC900 does
not exceed the compliance range to avoid degradation of the
distortion performance and integral linearity.
Best distortion performance is typically achieved with the
maximum full-scale output signal limited to approximately
0.5V. This is the case for a 50Ω doubly-terminated load and
a 20mA full-scale output current. A variety of loads can be
adapted to the output of the DAC900 by selecting a suitable
transformer while maintaining optimum voltage levels at
12
The current output of the DAC900 allows for a variety of
configurations, some of which are illustrated below. As
mentioned previously, utilizing the converter’s differential
outputs will yield the best dynamic performance. Such a
differential output circuit may consist of an RF transformer
(see Figure 3) or a differential amplifier configuration (see
Figure 4). The transformer configuration is ideal for most
applications with ac coupling, while op amps will be suitable
for a DC-coupled configuration.
The single-ended configuration (see Figure 6) may be considered for applications requiring a unipolar output voltage.
Connecting a resistor from either one of the outputs to ground
will convert the output current into a ground-referenced voltage signal. To improve on the DC linearity, an I-to-V converter can be used instead. This will result in a negative signal
excursion and, therefore, requires a dual supply amplifier.
DIFFERENTIAL WITH TRANSFORMER
Using an RF transformer provides a convenient way of
converting the differential output signal into a single-ended
signal while achieving excellent dynamic performance (see
Figure 3). The appropriate transformer should be carefully
selected based on the output frequency spectrum and impedance requirements. The differential transformer configuration has the benefit of significantly reducing common-mode
signals, thus improving the dynamic performance over a
wide range of frequencies. Furthermore, by selecting a
suitable impedance ratio (winding ratio), the transformer can
be used to provide optimum impedance matching while
controlling the compliance voltage for the converter outputs.
The model shown in Figure 3 has a 1:1 ratio and may be used
to interface the DAC900 to a 50Ω load. This results in a 25Ω
load for each of the outputs, IOUT and IOUT. The output
signals are ac coupled and inherently isolated because of the
transformer's magnetic coupling.
DAC900
SBAS093B
As shown in Figure 3, the transformer’s center tap is connected to ground. This forces the voltage swing on IOUT and
IOUT to be centered at 0V. In this case the two resistors, RS,
may be replaced with one, RDIFF, or omitted altogether. This
approach should only be used if all components are close to
each other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can be
realized, but the output compliance range should be observed. Alternatively, if the center tap is not connected, the
signal swing will be centered at RS • IOUTFS/2. However, in
this case, the two resistors (RS) must be used to enable the
necessary DC-current flow for both outputs.
ADT1-1WT
(Mini-Circuits)
1:1
IOUT
RS
50Ω
Optional
RDIFF
DAC900
RL
IOUT
RS
50Ω
The OPA680 is configured for a gain of two. Therefore,
operating the DAC900 with a 20mA full-scale output will
produce a voltage output of ±1V. This requires the amplifier
to operate off of a dual power supply (±5V). The tolerance
of the resistors typically sets the limit for the achievable
common-mode rejection. An improvement can be obtained
by fine tuning resistor R4.
This configuration typically delivers a lower level of ac
performance than the previously discussed transformer solution because the amplifier introduces another source of
distortion. Suitable amplifiers should be selected based on
their slew-rate, harmonic distortion, and output swing capabilities. High-speed amplifiers like the OPA680 or OPA687
may be considered. The ac performance of this circuit may
be improved by adding a small capacitor, CDIFF, between the
outputs IOUT and IOUT, as shown in Figure 4. This will introduce a real pole to create a low-pass filter in order to slewlimit the DACs fast output signal steps that otherwise could
drive the amplifier into slew-limitations or into an overload
condition; both would cause excessive distortion. The difference amplifier can easily be modified to add a level shift for
applications requiring the single-ended output voltage to be
unipolar, i.e., swing between 0V and +2V.
DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION
FIGURE 3. Differential Output Configuration Using an RF
Transformer.
DIFFERENTIAL CONFIGURATION USING AN OP AMP
If the application requires a DC-coupled output, a difference
amplifier may be considered, as shown in Figure 4. Four
external resistors are needed to configure the voltage-feedback op amp OPA680 as a difference amplifier performing
the differential to single-ended conversion. Under the shown
configuration, the DAC900 generates a differential output
signal of 0.5Vp-p at the load resistors, RL. The resistor
values shown were selected to result in a symmetric 25Ω
loading for each of the current outputs since the input
impedance of the difference amplifier is in parallel to resistors RL, and should be considered.
The circuit example of Figure 5 shows the signal output
currents connected into the summing junction of the
OPA2680, which is set up as a transimpedance stage, or
I-to-V converter. With this circuit, the DAC’s output will be
kept at a virtual ground, minimizing the effects of output
impedance variations, and resulting in the best DC linearity
(INL). However, as mentioned previously, the amplifier
may be driven into slew-rate limitations, and produce unwanted distortion. This may occur especially at high DAC
update rates.
+5V
50Ω
1/2
OPA2680
RF1
DAC900
R2
402Ω
IOUT
R1
200Ω
CD1
IOUT
DAC900
IOUT
OPA680
CDIFF
RL
26.1Ω
R3
200Ω
RL
28.7Ω
–VOUT = IOUT • RF
CF1
RF2
VOUT
IOUT
CD2
CF2
–5V +5V
R4
402Ω
1/2
OPA2680
–VOUT = IOUT • RF
50Ω
FIGURE 4. Difference Amplifier Provides Differential to
Single-Ended Conversion and DC-Coupling.
–5V
FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680
Forms Differential Transimpedance Amplifier.
DAC900
SBAS093B
13
The DC gain for this circuit is equal to feedback resistor RF.
At high frequencies, the DAC output impedance (CD1, CD2)
will produce a zero in the noise gain for the OPA2680 that
may cause peaking in the closed-loop frequency response.
CF is added across RF to compensate for this noise-gain
peaking. To achieve a flat transimpedance frequency response, the pole in each feedback network should be set to:
1
GBP
=
2 πR F C F 4 πR F C D
The DAC900 has an on-chip reference circuit that comprises
a 1.24V bandgap reference and a control amplifier. Grounding pin 16, INT/EXT, enables the internal reference operation. The full-scale output current, IOUTFS, of the DAC900 is
determined by the reference voltage, VREF, and the value of
resistor RSET. IOUTFS can be calculated by:
IOUTFS = 32 • IREF = 32 • VREF / RSET
(8)
with GBP = Gain Bandwidth Product of OPA
which will give a corner frequency f-3dB of approximately:
f−3dB =
INTERNAL REFERENCE OPERATION
GBP
2πR F C D
(10)
As shown in Figure 7, the external resistor RSET connects to
the FSA pin (Full-Scale Adjust). The reference control amplifier operates as a V-to-I converter producing a reference
current, IREF, which is determined by the ratio of VREF and
RSET, as shown in Equation 10. The full-scale output current,
IOUTFS, results from multiplying IREF by a fixed factor of 32.
(9)
CCOMPEXT +5V
0.1µF
The full-scale output voltage is defined by the product of
IOUTFS • RF, and has a negative unipolar excursion. To
improve on the ac performance of this circuit, adjustment of
RF and/or IOUTFS should be considered. Further extensions of
this application example may include adding a differential
filter at the OPA2680’s output followed by a transformer, in
order to convert to a single-ended signal.
IREF =
+VA
VREF
RSET
FSA
REFIN
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to the one of the DAC
outputs, a simple current-to-voltage conversion can be accomplished. The circuit in Figure 6 shows a 50Ω resistor
connected to IOUT, providing the termination of the further
connected 50Ω cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of
0V to 0.5V into the 25Ω load.
BW
DAC900
RSET
2kΩ
Ref
Control
Amp
Current
Sources
CCOMP
400pF
0.1µF
INT/EXT
+1.24V Ref.
FIGURE 7. Internal Reference Configuration.
IOUTFS = 20mA
VOUT = 0V to +0.5V
IOUT
DAC900
50Ω
IOUT
50Ω
25Ω
FIGURE 6. Driving a Doubly-Terminated 50Ω Cable Directly.
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, IOUTFS, and the load resistor may be mutually
adjusted to provide the desired output signal swing and
performance.
14
Using the internal reference, a 2kΩ resistor value results in a
20mA full-scale output. Resistors with a tolerance of 1% or better
should be considered. Selecting higher values, the converter
output can be adjusted from 20mA down to 2mA. Operating the
DAC900 at lower than 20mA output currents may be desirable
for reasons of reducing the total power consumption, improving
the distortion performance, or observing the output compliance
voltage limitations for a given load condition.
It is recommended to bypass the REFIN pin with a ceramic chip
capacitor of 0.1µF or more. The control amplifier is internally
compensated, and its small signal bandwidth is approximately
1.3MHz. To improve the ac performance, an additional capacitor
(CCOMPEXT) should be applied between the BW pin and the
analog supply, +VA, as shown in Figure 7. Using a 0.1µF
capacitor, the small-signal bandwidth and output impedance of
the control amplifier is further diminished, reducing the noise that
is fed into the current source array. This also helps shunting
feedthrough signals more effectively, and improving the noise
performance of the DAC900.
DAC900
SBAS093B
EXTERNAL REFERENCE OPERATION
The internal reference can be disabled by applying a logic
HIGH (+VA) to pin INT/EXT. An external reference voltage
can then be driven into the REFIN pin, which in this case
functions as an input, as shown in Figure 8. The use of an
external reference may be considered for applications that
require higher accuracy and drift performance, or to add the
ability of dynamic gain control.
While a 0.1µF capacitor is recommended to be used with the
internal reference, it is optional for the external reference
operation. The reference input, REFIN, has a high input
impedance (1MΩ) and can easily be driven by various
sources. Note that the voltage range of the external reference
should stay within the compliance range of the reference
input (0.1V to 1.25V).
DIGITAL INPUTS
The digital inputs, D0 (LSB) through D9 (MSB) of the
DAC900 accepts standard-positive binary coding. The digital input word is latched into a master-slave latch with the
rising edge of the clock. The DAC output becomes updated
with the following falling clock edge (refer to the specification table and timing diagram for details). The best performance will be achieved with a 50% clock duty cycle,
however, the duty cycle may vary as long as the timing
specifications are met. Additionally, the setup and hold
times may be chosen within their specified limits.
All digital inputs are CMOS compatible. The logic thresholds depend on the applied digital supply voltage such that
they are set to approximately half the supply voltage;
Vth = +VD/2 (±20% tolerance). The DAC900 is designed to
operate over a supply range of 2.7V to 5.5V.
POWER-DOWN MODE
The DAC900 features a power-down function that can be
used to reduce the supply current to less than 9mA over the
specified supply range of 2.7V to 5.5V. Applying a logic
HIGH to the PD pin will initiate the power-down mode,
while a logic LOW enables normal operation. When left
unconnected, an internal active pull-down circuit will enable
the normal operation of the converter.
GROUNDING, DECOUPLING AND
LAYOUT INFORMATION
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer pc-boards are recommended
for best performance since they offer distinct advantages
such as minimization of ground impedance, separation of
signal layers by ground layers, etc.
The DAC900 uses separate pins for its analog and digital
supply and ground connections. The placement of the decoupling capacitor should be such that the analog supply (+VA)
is bypassed to the analog ground (AGND), and the digital
supply bypassed to the digital ground (DGND). In most
cases 0.1uF ceramic chip capacitors at each supply pin are
adequate to provide a low impedance decoupling path. Keep
in mind that their effectiveness largely depends on the
proximity to the individual supply and ground pins. Therefore, they should be located as close as physically possible
to those device leads. Whenever possible, the capacitors
should be located immediately under each pair of supply/
ground pins on the reverse side of the pc-board. This layout
approach will minimize the parasitic inductance of component leads and pcb runs.
CCOMPEXT +5V
0.1µF
BW
DAC900
IREF =
+VA
VREF
RSET
FSA
REFIN
External
Reference
Ref
Control
Amp
Current
Sources
CCOMP
400pF
RSET
+5V
INT/EXT
+1.24V Ref.
FIGURE 8. External Reference Configuration.
DAC900
SBAS093B
15
Further supply decoupling with surface mount tantalum
capacitors (1uF to 4.7uF) may be added as needed in
proximity of the converter.
Low noise is required for all supply and ground connections
to the DAC900. It is recommended to use a multilayer pcboard utilizing separate power and ground planes. Mixed
signal designs require particular attention to the routing of
the different supply currents and signal traces. Generally,
analog supply and ground planes should only extend into
analog signal areas, such as the DAC output signal and the
reference signal. Digital supply and ground planes must be
confined to areas covering digital circuitry, including the
digital input lines connecting to the converter, as well as the
clock signal. The analog and digital ground planes should be
joined together at one point underneath the DAC. This can
be realized with a short track of approximately 1/8" (3mm).
16
The power to the DAC900 should be provided through the
use of wide pcb runs or planes. Wide runs will present a
lower trace impedance, further optimizing the supply decoupling. The analog and digital supplies for the converter
should only be connected together at the supply connector of
the pc-board. In the case of only one supply voltage being
available to power the DAC, ferrite beads along with bypass
capacitors may be used to create an LC filter. This will
generate a low-noise analog supply voltage that can then be
connected to the +VA supply pin of the DAC900.
While designing the layout, it is important to keep the analog
signal traces separate from any digital line, in order to
prevent noise coupling onto the analog signal path.
DAC900
SBAS093B
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC900E
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC900E
DAC900E/2K5
ACTIVE
TSSOP
PW
28
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC900E
DAC900U
ACTIVE
SOIC
DW
28
20
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC900U
DAC900U/1K
ACTIVE
SOIC
DW
28
1000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC900U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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