DAC904
904
DAC
DAC9
04
SBAS095C – MAY 2002
14-Bit, 165MSPS
DIGITAL-TO-ANALOG CONVERTER
FEATURES
APPLICATIONS
●
●
●
●
●
● COMMUNICATION TRANSMIT CHANNELS
WLL, Cellular Base Station
Digital Microwave Links
Cable Modems
● WAVEFORM GENERATION
Direct Digital Synthesis (DDS)
Arbitrary Waveform Generation (ARB)
● MEDICAL/ULTRASOUND
● HIGH-SPEED INSTRUMENTATION AND
CONTROL
● VIDEO, DIGITAL TV
SINGLE +5V OR +3V OPERATION
HIGH SFDR: 20MHz Output at 100MSPS: 64dBc
LOW GLITCH: 3pV-s
LOW POWER: 170mW at +5V
INTERNAL REFERENCE:
Optional Ext. Reference
Adjustable Full-Scale Range
Multiplying Option
DESCRIPTION
The DAC904 is a high-speed, Digital-to-Analog Converter (DAC)
offering a 14-bit resolution option within the family of highperformance converters. Featuring pin compatibility among family members, the DAC908, DAC900, and DAC902 provide a
component selection option to an 8-, 10-, and 12-bit resolution,
respectively. All models within this family of DACs support
update rates in excess of 165MSPS with excellent dynamic
performance, and are especially suited to fulfill the demands of
a variety of applications.
The advanced segmentation architecture of the DAC904 is
optimized to provide a high Spurious-Free Dynamic Range
(SFDR) for single-tone, as well as for multi-tone signals—
essential when used for the transmit signal path of communication systems.
battery-operated systems. Further optimization can be realized
by lowering the output current with the adjustable full-scale
option.
For noncontinuous operation of the DAC904, a power-down
mode results in only 45mW of standby power.
The DAC904 comes with an integrated 1.24V bandgap reference and edge-triggered input latches, offering a complete
converter solution. Both +3V and +5V CMOS logic families can
be interfaced to the DAC904.
The reference structure of the DAC904 allows for additional
flexibility by utilizing the on-chip reference, or applying an
external reference. The full-scale output current can be adjusted
over a span of 2-20mA, with one external resistor, while maintaining the specified dynamic performance.
The DAC904 is available in SO-28 and TSSOP-28 packages.
The DAC904 has a high impedance (200kΩ) current output with
a nominal range of 20mA and an output compliance of up to
1.25V. The differential outputs allow for both a differential or
single-ended analog signal interface. The close matching of the
current outputs ensures superior dynamic performance in the
differential configuration, which can be implemented with a
transformer.
Utilizing a small geometry CMOS process, the monolithic DAC904
can be operated on a wide, single-supply range of +2.7V to
+5.5V. Its low power consumption allows for use in portable and
+VA
+VD
BW
DAC904
FSA
Current
Sources
REFIN
IOUT
LSB
Switches
IOUT
BYP
Segmented
Switches
INT/EXT
Latches
PD
+1.24V Ref.
14-Bit Data Input
AGND
CLK
D13...D0
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2002, Texas Instruments Incorporated
www.ti.com
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
+VA to AGND ......................................................................... –0.3V to +6V
+VD to DGND ........................................................................ –0.3V to +6V
AGND to DGND ................................................................. –0.3V to +0.3V
+VA to +VD ............................................................................... –6V to +6V
CLK, PD to DGND ....................................................... –0.3V to VD + 0.3V
D0-D13 to DGND ......................................................... –0.3V to VD + 0.3V
IOUT, IOUT to AGND .......................................................... –1V to VA + 0.3V
BW, BYP to AGND ....................................................... –0.3V to VA + 0.3V
REFIN, FSA to AGND ................................................... –0.3V to VA + 0.3V
INT/EXT to AGND ........................................................ –0.3V to VA + 0.3V
Junction Temperature .................................................................... +150°C
Case Temperature ......................................................................... +100°C
Storage Temperature ..................................................................... +125°C
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
DAC904U
DAC904U/1K
DAC904E
DAC904E/2K5
Rails, 28
Tape and Reel, 1000
Rails, 52
Tape and Reel, 2500
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
DAC904U
SO-28
DW
–40°C to +85°C
DAC904U
"
"
"
"
TSSOP-28
PW
–40°C to +85°C
DAC904E
"
"
"
"
"
DAC904E
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
DEMO BOARD ORDERING INFORMATION
PRODUCT
DEMO BOARD
ORDERING NUMBER
DAC904U
DAC904E
DEM-DAC90xU
DEM-DAC904E
COMMENT
Populated evaluation board without DAC. Order sample of desired DAC90x model separately.
Populated evaluation board including the DAC904E.
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified.
DAC904U, E
PARAMETER
CONDITIONS
MIN
TYP
2.7V to 3.3V
4.5V to 5.5V
Ambient, TA
125
165
–40
RESOLUTION
OUTPUT UPDATE RATE
Output Update Rate (fCLOCK)
Full Specified Temperature Range, Operating
STATIC ACCURACY(1)
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
DYNAMIC PERFORMANCE
Spurious-Free Dynamic Range (SFDR)
fOUT = 1.0MHz, fCLOCK = 25MSPS
fOUT = 2.1MHz, fCLOCK = 50MSPS
fOUT = 5.04MHz, fCLOCK = 50MSPS
fOUT = 5.04MHz, fCLOCK = 100MSPS
fOUT = 20.2MHz, fCLOCK = 100MSPS
fOUT = 25.3MHz, fCLOCK = 125MSPS
fOUT = 41.5MHz, fCLOCK = 125MSPS
fOUT = 27.4MHz, fCLOCK = 165MSPS
fOUT = 54.8MHz, fCLOCK = 165MSPS
Spurious-Free Dynamic Range within a Window
fOUT = 5.04MHz, fCLOCK = 50MSPS
fOUT = 5.04MHz, fCLOCK = 100MSPS
Total Harmonic Distortion (THD)
fOUT = 2.1MHz, fCLOCK = 50MSPS
fOUT = 2.1MHz, fCLOCK = 125MSPS
Two Tone
fOUT1 = 13.5MHz, fOUT2 = 14.5MHz, fCLOCK = 100MSPS
2
fCLOCK
TA = +25°C
= 25MSPS, fOUT = 1.0MHz
MAX
UNITS
14
Bits
165
200
+85
MSPS
MSPS
°C
±2.5
±3.0
LSB
LSB
79
76
68
68
64
60
55
60
55
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
82
82
dBc
dBc
–75
–74
dBc
dBc
63
dBc
TA = +25°C
To Nyquist
72
2MHz Span
4MHz Span
DAC904
www.ti.com
SBAS095C
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25°C, +VA = +5V, +VD = +5V, differential transformer coupled output, 50Ω doubly terminated, unless otherwise specified.
DAC904U, E
PARAMETER
DYNAMIC PERFORMANCE (Cont.)
Output Settling Time(2)
Output Rise Time(2)
Output Fall Time(2)
Glitch Impulse
DC-ACCURACY
Full-Scale Output Range(3)(FSR)
Output Compliance Range
Gain Error
Gain Error
Gain Drift
Offset Error
Offset Drift
Power-Supply Rejection, +VA
Power-Supply Rejection, +VD
Output Noise
Output Resistance
Output Capacitance
CONDITIONS
to 0.1%
10% to 90%
10% to 90%
All Bits HIGH, IOUT
With Internal Reference
With External Reference
With Internal Reference
With Internal Reference
With Internal Reference
POWER SUPPLY
Supply Voltages
+VA
+VD
Supply Current(6)
IVA
IVA, Power-Down Mode
IVD
Power Dissipation
TYP
MAX
30
2
2
3
2.0
–1.0
–10
–10
±1
±2
±120
–0.025
IOUT = 20mA, RLOAD = 50Ω
20.0
+1.25
+10
+10
+0.025
+0.2
+0.025
50
200
12
IOUT, IOUT to Ground
+1.24
±10
±50
10
1
0.1
1.25
1.3
+VD
+VD
+VD
+VD
+VD
+VD
=
=
=
=
=
=
+5V
+5V
+3V
+3V
+5V
+5V
3.5
2
+2.7
+2.7
+5V, IOUT = 20mA
+3V, IOUT = 2mA
Power Dissipation, Power-Down Mode
Thermal Resistance, θJA
SO-28
TSSOP-28
Straight Binary
Rising Edge of Clock
5
0
3
0
±20
±20
5
UNITS
ns
ns
ns
pV-s
±0.1
–0.2
–0.025
REFERENCE
Reference Voltage
Reference Tolerance
Reference Voltage Drift
Reference Output Current
Reference Input Resistance
Reference Input Compliance Range
Reference Small-Signal Bandwidth(4)
DIGITAL INPUTS
Logic Coding
Latch Command
Logic HIGH Voltage, VIH
Logic LOW Voltage, VIL
Logic HIGH Voltage, VIH
Logic LOW Voltage, VIL
Logic HIGH Current, IIH(5)
Logic LOW Current, IIL
Input Capacitance
MIN
mA
V
%FSR
%FSR
ppmFSR/°C
%FSR
ppmFSR/°C
%FSR/V
%FSR/V
pA/√Hz
kΩ
pF
V
%
ppmFSR/°C
µA
MΩ
V
MHz
0.8
V
V
V
V
µA
µA
pF
+5
+5
+5.5
+5.5
V
V
24
1.1
8
170
50
45
30
2
15
230
mA
mA
mA
mW
mW
mW
75
50
1.2
°C/W
°C/W
NOTES: (1) At output IOUT, while driving a virtual ground. (2) Measured single-ended into 50Ω Load. (3) Nominal full-scale output current is 32x IREF; see Application
Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45µA for the PD pin, which has an
internal pull-down resistor. (6) Measured at fCLOCK = 50MSPS and fOUT = 1.0MHz.
DAC904
SBAS095C
www.ti.com
3
PIN CONFIGURATION
PIN DESCRIPTIONS
Top View
SO, TSSOP
Bit 1
1
28
CLK
Bit 2
2
27
+VD
Bit 3
3
26
DGND
Bit 4
4
25
NC
Bit 5
5
24
+VA
Bit 6
6
23
BYP
Bit 7
7
22
IOUT
Bit 8
8
21
IOUT
Bit 9
9
20
AGND
Bit 10 10
19
BW
Bit 11 11
18
FSA
Bit 12 12
17
REFIN
Bit 13 13
16
INT/EXT
Bit 14 14
15
PD
DAC904
PIN
DESIGNATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
PD
16
INT/EXT
17
REFIN
18
19
FSA
BW
20
21
22
23
24
25
26
27
28
AGND
IOUT
IOUT
BYP
+VA
NC
DGND
+VD
CLK
DESCRIPTION
Data Bit 1 (D13), MSB
Data Bit 2 (D12)
Data Bit 3 (D11)
Data Bit 4 (D10)
Data Bit 5 (D9)
Data Bit 6 (D8)
Data Bit 7 (D7)
Data Bit 8 (D6)
Data Bit 9 (D5)
Data Bit 10 (D4)
Data Bit 11 (D3)
Data Bit 12 (D2)
Data Bit 13 (D1)
Data Bit 14 (D0), LSB
Power Down, Control Input; Active
HIGH. Contains internal pull-down circuit;
may be left unconnected if not used.
Reference Select Pin; Internal ( = 0) or
External ( = 1) Reference Operation
Reference Input/Ouput. See Applications
section for further details.
Full-Scale Output Adjust
Bandwidth/Noise Reduction Pin:
Bypass with 0.1µF to +VA for Optimum
Performance. (Optional)
Analog Ground
Complementary DAC Current Output
DAC Current Output
Bypass Node: Use 0.1µF to AGND
Analog Supply Voltage, 2.7V to 5.5V
No Internal Connection
Digital Ground
Digital Supply Voltage, 2.7V to 5.5V
Clock Input
TYPICAL CONNECTION CIRCUIT
+5V
+5V
0.1µF(1)
+VA
+VD
BW
DAC904
IOUT
LSB
Switches
FSA
Current
Sources
REFIN
RSET
0.1µF
1:1
IOUT
VOUT
BYP
Segmented
MSB
Switches
0.1µF
50Ω
20pF(1)
50Ω
20pF(1)
INT/EXT
PD
Latches
+1.24V Ref.
14-Bit Data Input
AGND
CLK
D13.......D0
DGND
NOTE: (1) Optional components.
4
DAC904
www.ti.com
SBAS095C
TIMING DIAGRAM
t2
t1
CLOCK
tS
D13 D0
Data Changes
tH
Stable Valid Data
Data Changes
tPD
tSET
Iout or
Iout
SYMBOL
t1
t2
tS
tH
tPD
tSET
DESCRIPTION
MIN
Clock Pulse HIGH Time
Clock Pulse LOW Time
Data Setup Time
Data Hold Time
Propagation Delay Time
Output Settling Time to 0.1%
DAC904
SBAS095C
www.ti.com
TYP
3
3
1.0
1.5
1
30
MAX
UNITS
ns
ns
ns
ns
ns
ns
5
TYPICAL CHARACTERISTICS: VD = VA = +5V
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
TYPICAL INL
10
8
8
6
6
4
4
0
DAC Code
0
16k
16384
14k
12k
10k
8k
6k
4k
2k
–10
0
–8
–10
DAC Code
SFDR vs fOUT AT 50MSPS
90
85
85
80
80
SFDR (dBc)
SFDR (dBc)
SFDR vs fOUT AT 25MSPS
16k
16384
–6
–8
14k
–4
–6
12k
–4
10k
–2
8k
–2
2
6k
0
4k
2
2k
Error (LSBs)
Error (LSBs)
TYPICAL DNL
10
–6dBFS
75
70
75
–6dBFS
70
65
0dBFS
65
0dBFS
60
60
55
0
2.0
4.0
6.0
8.0
Frequency (MHz)
10.0
12.0
0
5.0
20.0
25.0
SFDR vs fOUT AT 125MSPS
85
85
80
80
75
75
SFDR (dBc)
SFDR (dBc)
SFDR vs fOUT AT 100MSPS
10.0
15.0
Frequency (MHz)
70
–6dBFS
65
60
55
–6dBFS
70
65
60
0dBFS
55
0dBFS
50
50
45
45
0
6
10.0
20.0
30.0
Frequency (MHz)
40.0
50.0
0
10.0
20.0
30.0
40.0
Frequency (MHz)
50.0
60.0
DAC904
www.ti.com
SBAS095C
TYPICAL CHARACTERISTICS: VD = VA = +5V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
SFDR vs fOUT AT 165MSPS
SFDR vs fOUT AT 200MSPS
80
80
75
75
70
70
SFDR (dBc)
SFDR (dBc)
–6dBFS
65
60
55
–6dBFS
65
60
55
0dBFS
0dBFS
50
50
45
45
40
40
0
10.0
20.0
30.0 40.0 50.0
Frequency (MHz)
60.0
70.0
80.0
0
DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT
AT 100MSPS
80
80
75
SFDR (dBc)
SFDR (dBc)
Diff (–6dBFS)
X
X
65
IOUT (–6dBFS)
X
60
X
65
X
5.04MHz
X
40.4MHz
*
55
X
X
45
45
40
0
10.0
20.0
30.0
Frequency (MHz)
40.0
50.0
2
5
10
20
IOUTFS (mA)
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
THD vs fCLOCK AT fOUT = 2.1MHz
85
–70
80
–75
SFDR (dBc)
4HD
–85
X
X
X
2.1MHz
75
2HD
–80
THD (dBc)
*
20.2MHz
X
IOUT (0dBFS)
10.1MHz
50
X
50
*
*
60
Diff (0dBFS)
55
90.0
2.1MHz
70
X
70
30.0 40.0 50.0 60.0 70.0 80.0
Frequency (MHz)
SFDR vs IOUTFS and fOUT AT 100MSPS, 0dBFS
85
75
10.0 20.0
X
–90
70
65
10.1MHz
60
55
3HD
–95
40.4MHz
50
45
–40
–100
0
25
50
100
fCLOCK (MSPS)
125
150
DAC904
SBAS095C
X
www.ti.com
X
X
–20
0
X
X
25
50
Temperature (°C)
X
X
70
85
7
TYPICAL CHARACTERISTICS: VD = VA = +5V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
DUAL-TONE OUTPUT SPECTRUM
FOUR-TONE OUTPUT SPECTRUM
0
0
–10
–10
fCLOCK = 100MSPS
fOUT1 = 13.5MHz
fOUT2 = 14.5MHz
SFDR = 63dBc
Amplitude = 0dBFS
Magnitude (dBm)
–30
–40
–50
fCLOCK = 50MSPS
fOUT1 = 6.25MHz
fOUT2 = 6.75MHz
fOUT3 = 7.25MHz
fOUT4 = 7.75MHz
SFDR = 66dBc
Amplitude = 0dBFS
–20
–30
Magnitude (dBm)
–20
–60
–70
–40
–50
–60
–70
–80
–80
–90
–90
–100
–100
0
5
10
15
20
25
30
35
40
45
50
0
5
10
Frequency (MHz)
15
20
25
20.0
25.0
Frequency (MHz)
TYPICAL CHARACTERISTICS: VD = VA = +3V
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
SFDR vs fOUT AT 25MSPS
SFDR vs fOUT AT 50MSPS
85
85
80
80
–6dBFS
75
SFDR (dBc)
SFDR (dBc)
–6dBFS
70
0dBFS
65
75
70
65
0dBFS
60
60
55
55
0
2.0
4.0
6.0
8.0
Frequency (MHz)
10.0
12.0
0
5.0
SFDR vs fOUT AT 125MSPS
85
85
80
80
75
75
SFDR (dBc)
SFDR (dBc)
SFDR vs fOUT AT 100MSPS
70
–6dBFS
65
60
70
65
–6dBFS
60
55
55
0dBFS
0dBFS
50
50
45
45
0
8
10.0
15.0
Frequency (MHz)
10.0
20.0
30.0
Frequency (MHz)
40.0
50.0
0
10.0
20.0
30.0
40.0
Frequency (MHz)
50.0
60.0
DAC904
www.ti.com
SBAS095C
TYPICAL CHARACTERISTICS: VD = VA = +3V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
DIFFERENTIAL vs SINGLE-ENDED SFDR vs fOUT
AT 100MSPS
SFDR vs fOUT AT 165MSPS
80
85
75
80
75
Diff (–6dBFS)
–6dBFS
SFDR (dBc)
SFDR (dBc)
70
65
60
55
70
65
IOUT (–6dBFS)
60
Diff (0dBFS)
0dBFS
50
55
45
50
40
45
IOUT (0dBFS)
0
10.0
20.0
30.0 40.0 50.0
Frequency (MHz)
60.0
70.0
0
80.0
10.0
SFDR vs IOUTFS and fOUT AT 100MSPS
20.0
30.0
Frequency (MHz)
–70
2.1MHz
2HD
75
–75
5.04MHz
70
X
X
X
–80
10.1MHz
THD (dBc)
SFDR (dBc)
X
65
20.2MHz
60
55
*
*
4HD
–85
–90
40.4MHz
*
*
3HD
–95
45
40
–100
2
5
10
20
0
25
50
100
fCLOCK (MSPS)
IOUTFS (mA)
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
150
0
2.1MHz
–10
75
fCLOCK = 100MSPS
fOUT1 = 13.5MHz
fOUT2 = 14.5MHz
SFDR = 64dBc
Amplitude = 0dBFS
–20
Magnitude (dBm)
70
SFDR (dBc)
125
DUAL-TONE OUTPUT SPECTRUM
80
10.1MHz
65
60
55
40.4MHz
50
X
X
45
50.0
THD vs fCLOCK AT fOUT = 2.1MHz
80
50
40.0
X
X
40
–40
X
–40
–50
–60
–70
–80
X
X
–90
–100
–20
0
25
50
Temperature (°C)
70
85
0
5
10
15
20
25
30
35
40
45
50
Frequency (MHz)
DAC904
SBAS095C
–30
www.ti.com
9
TYPICAL CHARACTERISTICS: VD = VA = +3V (Cont.)
At TA = +25°C, Differential IOUT = 20mA, 50Ω double-terminated load, SFDR up to Nyquist, unless otherwise specified.
FOUR-TONE OUTPUT SPECTRUM
0
–10
fCLOCK = 50MSPS
fOUT1 = 6.25MHz
fOUT2 = 6.75MHz
fOUT3 = 7.25MHz
fOUT4 = 7.75MHz
SFDR = 67dBc
Amplitude = 0dBFS
Magnitude (dBm)
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
5
10
15
20
25
Frequency (MHz)
APPLICATION INFORMATION
The segmented architecture results in a significant reduction
of the glitch energy, and improves the dynamic performance
(SFDR) and DNL. The current outputs maintain a very high
output impedance of greater than 200kΩ.
THEORY OF OPERATION
The architecture of the DAC904 uses the current steering
technique to enable fast switching and a high update rate. The
core element within the monolithic DAC is an array of segmented current sources that are designed to deliver a full-scale
output current of up to 20mA, as shown in Figure 1. An internal
decoder addresses the differential current switches each time
the DAC is updated and a corresponding output current is
formed by steering all currents to either output summing node,
IOUT or IOUT. The complementary outputs deliver a differential
output signal that improves the dynamic performance through
reduction of even-order harmonics, common-mode signals
(noise), and double the peak-to-peak output signal swing by a
factor of two, compared to single-ended operation.
The full-scale output current is determined by the ratio of the
internal reference voltage (1.24V) and an external resistor,
RSET. The resulting IREF is internally multiplied by a factor of
32 to produce an effective DAC output current that can range
from 2mA to 20mA, depending on the value of RSET.
The DAC904 is split into a digital and an analog portion, each
of which is powered through its own supply pin. The digital
section includes edge-triggered input latches and the decoder logic, while the analog section comprises the current
source array with its associated switches and the reference
circuitry.
+3V to +5V
Digital
+3V to +5V
Analog
0.1µF(1)
Bandwidth
Control
+VA
DAC904
RSET
2kΩ
BW
+VD
IOUT
Full-Scale
Adjust
Resistor
FSA
Ref
Control
Amp
Ref
Input REFIN
400pF
PMOS
Current
Source
Array
0.1µF
LSB
Switches
1:1
VOUT
IOUT
Segmented
MSB
Switches
50Ω
0.1µF
20pF(1)
50Ω
20pF(1)
BYP
INT/EXT
Ref
Buffer
Latches and Switch
Decoder Logic
PD
Power Down
(internal pull-down)
+1.24V Ref
AGND
Analog
Ground
CLK
Clock
Input
14-Bit Data Input
D13...D0
NOTE: Supply bypassing not shown.
DGND
Digital
Ground
NOTE: (1) Optional.
FIGURE 1. Functional Block Diagram of the DAC904.
10
DAC904
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SBAS095C
DAC TRANSFER FUNCTION
The total output current, IOUTFS, of the DAC904 is the summation of the two complementary output currents:
+VA
DAC904
IOUTFS = IOUT + IOUT
(1)
The individual output currents depend on the DAC code and
can be expressed as:
IOUT = IOUTFS • (Code/16384)
(2)
IOUT = IOUTFS • (16383 – Code/16384)
(3)
where ‘Code’ is the decimal representation of the DAC data
input word. Additionally, IOUTFS is a function of the reference
current IREF, which is determined by the reference voltage
and the external setting resistor, RSET.
IOUTFS = 32 • IREF = 32 • VREF /RSET
(4)
In most cases the complementary outputs will drive resistive
loads or a terminated transformer. A signal voltage will
develop at each output according to:
VOUT = IOUT • RLOAD
(5)
VOUT = IOUT • RLOAD
(6)
The value of the load resistance is limited by the output
compliance specification of the DAC904. To maintain specified linearity performance, the voltage for IOUT and IOUT
should not exceed the maximum allowable compliance range.
The two single-ended output voltages can be combined to
find the total differential output swing:
(7)
VOUTDIFF = VOUT – VOUT =
(2 • Code – 16383)
• IOUTFS • RLOAD
16384
ANALOG OUTPUTS
The DAC904 provides two complementary current outputs,
IOUT and IOUT. The simplified circuit of the analog output
stage representing the differential topology is shown in
Figure 2. The output impedance of 200kΩ 12pF for IOUT
and IOUT results from the parallel combination of the differential switches, along with the current sources and associated
parasitic capacitances.
The signal voltage swing that may develop at the two
outputs, IOUT and IOUT, is limited by a negative and positive
compliance. The negative limit of –1V is given by the breakdown voltage of the CMOS process, and exceeding it will
compromise the reliability of the DAC904, or even cause
permanent damage. With the full-scale output set to 20mA,
the positive compliance equals 1.25V, operating with
IOUT
RL
RL
FIGURE 2. Equivalent Analog Output.
+VD = 5V. Note that the compliance range decreases to
about 1V for a selected output current of IOUTFS = 2mA.
Care should be taken that the configuration of the DAC904
does not exceed the compliance range to avoid degradation
of the distortion performance and integral linearity.
Best distortion performance is typically achieved with the
maximum full-scale output signal limited to approximately
0.5V. This is the case for a 50Ω doubly-terminated load and
a 20mA full-scale output current. A variety of loads can be
adapted to the output of the DAC904 by selecting a suitable
transformer while maintaining optimum voltage levels at
IOUT and IOUT. Furthermore, using the differential output
configuration in combination with a transformer will be instrumental for achieving excellent distortion performance. Common-mode errors, such as even-order harmonics or noise,
can be substantially reduced. This is particularly the case
with high output frequencies and/or output amplitudes below
full-scale.
For those applications requiring the optimum distortion and
noise performance, it is recommended to select a full-scale
output of 20mA. A lower full-scale range down to 2mA may
be considered for applications that require a low power
consumption, but can tolerate a reduced performance level.
INPUT CODE (D13 - D0)
IOUT
IOUT
11 1111 1111 1111
20mA
0mA
10 0000 0000 0000
10mA
10mA
00 0000 0000 0000
0mA
20mA
TABLE I. Input Coding versus Analog Output Current.
OUTPUT CONFIGURATIONS
The current output of the DAC904 allows for a variety of
configurations, some of which are illustrated below. As mentioned previously, utilizing the converter’s differential outputs
will yield the best dynamic performance. Such a differential
output circuit may consist of an RF transformer (see Figure 3)
or a differential amplifier configuration (see Figure 4). The
DAC904
SBAS095C
IOUT
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11
transformer configuration is ideal for most applications with ac
coupling, while op amps will be suitable for a DC-coupled
configuration.
The single-ended configuration (see Figure 6) may be considered for applications requiring a unipolar output voltage. Connecting a resistor from either one of the outputs to ground will
convert the output current into a ground-referenced voltage
signal. To improve on the DC linearity, an I-to-V converter can
be used instead. This will result in a negative signal excursion
and, therefore, requires a dual supply amplifier.
DIFFERENTIAL WITH TRANSFORMER
Using an RF transformer provides a convenient way of
converting the differential output signal into a single-ended
signal while achieving excellent dynamic performance, as
shown in Figure 3. The appropriate transformer should be
carefully selected based on the output frequency spectrum
and impedance requirements. The differential transformer
configuration has the benefit of significantly reducing common-mode signals, thus improving the dynamic performance
over a wide range of frequencies. Furthermore, by selecting
a suitable impedance ratio (winding ratio), the transformer
can be used to provide optimum impedance matching while
controlling the compliance voltage for the converter outputs.
The model shown in Figure 3 has a 1:1 ratio and may be
used to interface the DAC904 to a 50Ω load. This results in
a 25Ω load for each of the outputs, IOUT and IOUT. The output
signals are ac coupled and inherently isolated because of the
transformer's magnetic coupling.
As shown in Figure 3, the transformer’s center tap is connected to ground. This forces the voltage swing on IOUT and
IOUT to be centered at 0V. In this case the two resistors, RS,
may be replaced with one, RDIFF, or omitted altogether. This
approach should only be used if all components are close to
each other, and if the VSWR is not important. A complete
power transfer from the DAC output to the load can be
realized, but the output compliance range should be observed. Alternatively, if the center tap is not connected, the
signal swing will be centered at RS • IOUTFS /2. However, in
this case, the two resistors (RS) must be used to enable the
necessary DC-current flow for both outputs.
ADT1-1WT
(Mini-Circuits)
1:1
IOUT
Optional
RDIFF
DAC904
RS
50Ω
RL
IOUT
RS
50Ω
DIFFERENTIAL CONFIGURATION USING AN OP AMP
If the application requires a DC-coupled output, a difference
amplifier may be considered, as shown in Figure 4. Four
external resistors are needed to configure the voltage-feedback op amp OPA680 as a difference amplifier performing
the differential to single-ended conversion. Under the shown
configuration, the DAC904 generates a differential output
signal of 0.5Vp-p at the load resistors, RL. The resistor values
shown were selected to result in a symmetric 25Ω loading for
each of the current outputs since the input impedance of the
difference amplifier is in parallel to resistors RL, and should
be considered.
R2
402Ω
R1
200Ω
IOUT
DAC904
IOUT
OPA680
CDIFF
RL
26.1Ω
R3
200Ω
RL
28.7Ω
VOUT
–5V +5V
R4
402Ω
FIGURE 4. Difference Amplifier Provides Differential to SingleEnded Conversion and AC-Coupling.
The OPA680 is configured for a gain of 2. Therefore, operating the DAC904 with a 20mA full-scale output will produce
a voltage output of ±1V. This requires the amplifier to operate
off of a dual power supply (±5V). The tolerance of the
resistors typically sets the limit for the achievable commonmode rejection. An improvement can be obtained by fine
tuning resistor R4.
This configuration typically delivers a lower level of ac performance than the previously discussed transformer solution
because the amplifier introduces another source of distortion. Suitable amplifiers should be selected based on their
slew-rate, harmonic distortion, and output swing capabilities.
High-speed amplifiers like the OPA680 or OPA687 may be
considered. The ac performance of this circuit may be
improved by adding a small capacitor, CDIFF, between the
outputs IOUT and IOUT, as shown in Figure 4. This will introduce
a real pole to create a low-pass filter in order to slew-limit the
DAC’s fast output signal steps that otherwise could drive the
amplifier into slew-limitations or into an overload condition;
both would cause excessive distortion. The difference amplifier can easily be modified to add a level shift for applications
requiring the single-ended output voltage to be unipolar, i.e.,
swing between 0V and +2V.
FIGURE 3. Differential Output Configuration Using an RF
Transformer.
12
DAC904
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SBAS095C
DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION
The circuit example of Figure 5 shows the signal output
currents connected into the summing junction of the OPA2680,
which is set up as a transimpedance stage, or I-to-V converter. With this circuit, the DAC’s output will be kept at a
virtual ground, minimizing the effects of output impedance
variations, and resulting in the best DC linearity (INL). However, as mentioned previously, the amplifier may be driven
into slew-rate limitations, and produce unwanted distortion.
This may occur especially at high DAC update rates.
+5V
50Ω
1/2
OPA2680
RF1
DAC904
IOUT
–VOUT = IOUT • RF
CF1
CD1
The full-scale output voltage is defined by the product of
IOUTFS • RF, and has a negative unipolar excursion. To
improve on the ac performance of this circuit, adjustment of
RF and/or IOUTFS should be considered. Further extensions of
this application example may include adding a differential
filter at the OPA2680’s output followed by a transformer, in
order to convert to a single-ended signal.
SINGLE-ENDED CONFIGURATION
Using a single load resistor connected to the one of the DAC
outputs, a simple current-to-voltage conversion can be accomplished. The circuit in Figure 6 shows a 50Ω resistor
connected to IOUT, providing the termination of the further
connected 50Ω cable. Therefore, with a nominal output
current of 20mA, the DAC produces a total signal swing of
0V to 0.5V into the 25Ω load.
Different load resistor values may be selected as long as the
output compliance range is not exceeded. Additionally, the
output current, IOUTFS, and the load resistor may be mutually
adjusted to provide the desired output signal swing and
performance.
RF2
IOUT
IOUTFS = 20mA
CF2
CD2
VOUT = 0V to +0.5V
IOUT
DAC904
1/2
OPA2680
50Ω
IOUT
–VOUT = IOUT • RF
50Ω
25Ω
50Ω
–5V
FIGURE 6. Driving a Doubly-Terminated 50Ω Cable Directly.
FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680 Forms
Differential Transimpedance Amplifier.
The DC gain for this circuit is equal to feedback resistor RF.
At high frequencies, the DAC output impedance (CD1, CD2)
will produce a zero in the noise gain for the OPA2680 that
may cause peaking in the closed-loop frequency response.
CF is added across RF to compensate for this noise-gain
peaking. To achieve a flat transimpedance frequency response, the pole in each feedback network should be set to:
1
GBP
=
2πRF CF 4 πRF CD
(8)
with GBP = Gain Bandwidth Product of OPA,
which will give a corner frequency f-3dB of approximately:
f−3dB =
GBP
2πRF CD
INTERNAL REFERENCE OPERATION
The DAC904 has an on-chip reference circuit that comprises
a 1.24V bandgap reference and a control amplifier. Grounding pin 16, INT/EXT, enables the internal reference operation. The full-scale output current, IOUTFS, of the DAC904 is
determined by the reference voltage, VREF, and the value of
resistor RSET. IOUTFS can be calculated by:
IOUTFS = 32 • IREF = 32 • VREF / RSET
The external resistor RSET connects to the FSA pin (FullScale Adjust), see Figure 7. The reference control amplifier
operates as a V-to-I converter producing a reference current,
IREF, which is determined by the ratio of VREF and RSET, as
shown in Equation 10. The full-scale output current, IOUTFS,
results from multiplying IREF by a fixed factor of 32.
(9)
DAC904
SBAS095C
(10)
www.ti.com
13
Optional
Bandlimiting
Capacitor
CCOMPEXT +5V
0.1µF
CCOMPEXT +5V
0.1µF
BW
DAC904
+VA
BW
DAC904
V
IREF = REF
RSET
+VA
V
IREF = REF
RSET
FSA
FSA
REFIN
RSET
2kΩ
Ref
Control
Amp
Current
Sources
CCOMP
400pF
0.1µF
REFIN
External
Reference
Ref
Control
Amp
Current
Sources
CCOMP
400pF
RSET
+5V
INT/EXT
INT/EXT
+1.24V Ref.
+1.24V Ref.
FIGURE 7. Internal Reference Configuration.
FIGURE 8. External Reference Configuration.
Using the internal reference, a 2kΩ resistor value results in a
20mA full-scale output. Resistors with a tolerance of 1% or
better should be considered. Selecting higher values, the converter output can be adjusted from 20mA down to 2mA.
Operating the DAC904 at lower than 20mA output currents may
be desirable for reasons of reducing the total power consumption, improving the distortion performance, or observing the
output compliance voltage limitations for a given load condition.
DIGITAL INPUTS
It is recommended to bypass the REFIN pin with a ceramic chip
capacitor of 0.1µF or more. The control amplifier is internally
compensated, and its small signal bandwidth is approximately
1.3MHz. For optional ac performance, an additional capacitor
(CCOMPEXT) should be applied between the BW pin and the
analog supply, +VA, as shown in Figure 7. Using a 0.1µF
capacitor, the small-signal bandwidth and output impedance of
the control amplifier is further diminished, reducing the noise
that is fed into the current source array. This also helps shunting
feedthrough signals more effectively, and improving the noise
performance of the DAC904.
EXTERNAL REFERENCE OPERATION
The internal reference can be disabled by applying a logic
HIGH (+VA) to pin INT/EXT. An external reference voltage
can then be driven into the REFIN pin, which in this case
functions as an input, as shown in Figure 8. The use of an
external reference may be considered for applications that
require higher accuracy and drift performance, or to add the
ability of dynamic gain control.
While a 0.1µF capacitor is recommended to be used with the
internal reference, it is optional for the external reference
operation. The reference input, REFIN, has a high input
impedance (1MΩ) and can easily be driven by various
sources. Note that the voltage range of the external reference should stay within the compliance range of the reference input (0.1V to 1.25V).
14
The digital inputs, D0 (LSB) through D13 (MSB) of the
DAC904 accepts standard-positive binary coding. The digital
input word is latched into a master-slave latch with the rising
edge of the clock. The DAC output becomes updated with
the following falling clock edge (refer to the electrical characteristic table and timing diagram for details). The best performance will be achieved with a 50% clock duty cycle, however, the duty cycle may vary as long as the timing specifications are met. Additionally, the setup and hold times may
be chosen within their specified limits.
All digital inputs are CMOS compatible. The logic thresholds
depend on the applied digital supply voltage such that they
are set to approximately half the supply voltage;
V th = +VD / 2 (±20% tolerance). The DAC904 is designed to
operate over a supply range of 2.7V to 5.5V.
POWER-DOWN MODE
The DAC904 features a power-down function that can be
used to reduce the supply current to less than 9mA over the
specified supply range of 2.7V to 5.5V. Applying a logic HIGH
to the PD pin will initiate the power-down mode, while a logic
LOW enables normal operation. When left unconnected, an
internal active pull-down circuit will enable the normal operation of the converter.
GROUNDING, DECOUPLING, AND
LAYOUT INFORMATION
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer pc-boards are recommended
for best performance since they offer distinct advantages
such as minimization of ground impedance, separation of
signal layers by ground layers, etc.
DAC904
www.ti.com
SBAS095C
The DAC904 uses separate pins for its analog and digital
supply and ground connections. The placement of the decoupling capacitor should be such that the analog supply (+VA)
is bypassed to the analog ground (AGND), and the digital
supply bypassed to the digital ground (DGND). In most cases
0.1µF ceramic chip capacitors at each supply pin are adequate to provide a low impedance decoupling path. Keep in
mind that their effectiveness largely depends on the proximity
to the individual supply and ground pins. Therefore, they
should be located as close as physically possible to those
device leads. Whenever possible, the capacitors should be
located immediately under each pair of supply/ground pins
on the reverse side of the pc-board. This layout approach will
minimize the parasitic inductance of component leads and
pcb runs.
Further supply decoupling with surface mount tantalum capacitors (1µF to 4.7µF) may be added as needed in proximity
of the converter.
Low noise is required for all supply and ground connections
to the DAC904. It is recommended to use a multilayer pcboard utilizing separate power and ground planes. Mixed
signal designs require particular attention to the routing of the
different supply currents and signal traces. Generally, analog
supply and ground planes should only extend into analog
signal areas, such as the DAC output signal and the reference signal. Digital supply and ground planes must be
confined to areas covering digital circuitry, including the
digital input lines connecting to the converter, as well as the
clock signal. The analog and digital ground planes should be
joined together at one point underneath the DAC. This can be
realized with a short track of approximately 1/8 inch (3mm).
The power to the DAC904 should be provided through the
use of wide pcb runs or planes. Wide runs will present a
lower trace impedance, further optimizing the supply decoupling. The analog and digital supplies for the converter
should only be connected together at the supply connector of
the pc-board. In the case of only one supply voltage being
available to power the DAC, ferrite beads along with bypass
capacitors may be used to create an LC filter. This will
generate a low-noise analog supply voltage that can then be
connected to the +VA supply pin of the DAC904.
While designing the layout, it is important to keep the analog
signal traces separate from any digital line, in order to
prevent noise coupling onto the analog signal path.
DAC904
SBAS095C
www.ti.com
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
DAC904E
ACTIVE
TSSOP
PW
28
50
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC904E
DAC904E/2K5
ACTIVE
TSSOP
PW
28
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC904E
DAC904U
ACTIVE
SOIC
DW
28
20
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
DAC904U
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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