DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
DCR01 Series, 1-W, 1000-VRMS Isolated, Regulated DC/DC Converter Modules
1 Features
3 Description
•
•
The DCR01 family is a series of high-efficiency,
input-isolated, output-regulated DC/DC converters. In
addition to 1-W nominal, galvanically-isolated output
power capability, this range of DC/DC converters offer
very low output noise, thermal protection, and high
accuracy.
•
•
•
•
•
•
•
•
•
•
1-kV isolation (operational): 1-second test
Continuous voltage applied across isolation
barrier: 60 VDC, 42.5 VAC
UL1950 recognized component
10-pin PDIP and 12-pin SOP packages
Input voltage: 5 V, 12 V, or 24 V
Output voltage: 3.3 V or 5 V
Device-to-device synchronization
400-kHz switching frequency
Short-circuit protection
Thermal protection
High efficiency
125 FITs at 55°C
This combination of features and small size makes
the DCR01 series of devices suitable for a wide
range of applications, and is an easy-to-use solution
in applications requiring signal path isolation.
CAUTION
This product has operational isolation and
is intended for signal isolation only. It must
not be used as a part of a safety isolation
circuit requiring reinforced isolation. See
definitions in the feature description.
2 Applications
•
•
•
•
Point-of-use power conversion
Digital interface power
Ground loop elimination
Power-supply noise reduction
Device Information
Part Number
DCR01
(1)
+VS
Package(1)
Body Size (NOM)
PDIP (10)
22.86 mm × 6.61 mm
SOP (12)
17.90 mm × 7.50 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VREC
+VOUT
SYNC
Input
Controller
LDO
Regulator
ERROR
ENABLE
-VS
-VOUT
DCR01 Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Typical Characteristics................................................ 7
8 Detailed Description......................................................12
8.1 Overview................................................................... 12
8.2 Functional Block Diagram......................................... 12
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................15
9 Application and Implementation.................................. 16
9.1 Application Information............................................. 16
9.2 Typical Application.................................................... 18
10 Power Supply Recommendations..............................19
11 Layout........................................................................... 20
11.1 Layout Guidelines................................................... 20
11.2 Layout Examples.....................................................20
12 Device and Documentation Support..........................22
12.1 Receiving Notification of Documentation Updates..22
12.2 Support Resources................................................. 22
12.3 Trademarks............................................................. 22
12.4 Electrostatic Discharge Caution..............................22
12.5 Glossary..................................................................22
13 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
Changes from Revision D (June 2016) to Revision E (July 2022)
Page
• Updated the numbering format for tables, figures and cross-references throughout the document. .................1
• Added links to Section 2 .................................................................................................................................... 1
• Added Efficiency and Load Regulation plots for DCR011203P to Section 7.6 .................................................. 7
Changes from Revision C (May 2003) to Revision D (January 2016)
Page
• Added Device Information table, Device Comparison table, ESD Ratings table, Thermal Information table,
Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section.............................................................................. 1
• Removed Package/Ordering Information table, see POA at the end of the data sheet .................................... 1
• Added additional graphs to Section 7.6 ............................................................................................................. 7
• Added Isolation section to the Feature Description section .............................................................................12
• Added a typical application design to the Application Information section ...................................................... 16
2
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
5 Device Comparison Table
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2-µF ceramic, CFILTER = 1-µF ceramic, COUT = 0.1-µF ceramic
(unless otherwise noted)
Device Number (3)
Output
Voltage
VO (V)
Output
Current
(mA)
Ripple (1)
(mVp-p)
Noise (2)
(mVp-p)
IO = 0 mA
IO = 10 mA
IO = 100%
LOAD
Typical
Typical
Maximum
Typical
Typical
Typical
Typical
Typical
5
35
18
28
335
8
23
24
33
339
6
20
25
40
306
9
20
25
40
306
390
10
54
13
17
173
300
8
22
13
17
136
6
45
13
18
125
6
21
14
19
123
390
10
22
17
18
97
300
8
22
15
17
75
10
22
15
18
69
13
32
15
18
67
DCR010503P
DCR010503U
DCR010505P
3.3
5
DCR011203P
DCR011205P
3.3
12
5
DCR011205U
DCR012403P
DCR012403U
DCR012405P
3.3
24
5
DCR012405U
(1)
(2)
(3)
300
5
DCR010505U
DCR011203U
Supply Current (mA)
Input
Voltage
VS (V)
200
200
200
20-MHz bandwidth, 50% load
100-MHz bandwidth, 50% load
The last character in the part number denotes the package type (P = PDIP, U = SOP).
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
3
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
6 Pin Configuration and Functions
+VS
1
18
SYNC
+VS
1
28
SYNC
NC
2
17
-VS
+VS
2
27
-VS
NC
3
26
-VS
DCR01P
DCR01U
VREC
7
12
ERROR
VREC
12
17
ERROR
-VOUT
8
11
ENABLE
-VOUT
13
16
ENABLE
+VOUT
9
10
DNC
+VOUT
14
15
DNC
Figure 6-1. 10-Pin PDIP NVE Package (Top View)
Figure 6-2. 12-Pin SOP DVB Package (Top View)
Table 6-1. Pin Functions
Pin
Name
4
I/O
Description
PDIP
SOP
ENABLE
11
16
I
Output voltage enable
ERROR
12
17
O
Error flag active low
DNC
10
15
—
Do not connect.
NC
2
3
—
No connection
SYNC
18
28
I
Synchronization input
–VOUT
8
13
O
Output ground
+VOUT
9
14
O
Voltage output
VREC
7
12
O
Rectified output
–VS
17
26, 27
I
Input ground
+VS
1
1, 2
I
Voltage input
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
Input voltage
MAX
5-V input devices
7
12-V input devices
15
24-V input devices
29
UNIT
V
Lead temperature
PDIP package
Surface temperature of device body or pins
(maximum 10 s)
270
°C
Reflow solder temperature
SOP package
Surface temperature of device body or pins
260
°C
125
°C
Storage temperature, Tstg
(1)
(2)
–60
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
See the package option addendum at the end of the datasheet for additional package information.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
±250
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage
MIN
NOM
MAX
5-V input devices
4.5
5
5.5
12-V input devices
10.8
12
13.2
24-V input devices
21.6
24
26.4
Operating temperature
–40
85
UNIT
V
°C
7.4 Thermal Information
DCR01
THERMAL METRIC(1)
NVE (PDIP)
DVB (SOP)
UNIT
10 PINS
12 PINS
RθJA
Junction-to-ambient thermal resistance
60
60
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
26
26
°C/W
RθJB
Junction-to-board thermal resistance
24
24
°C/W
ψJT
Junction-to-top characterization parameter
7
7
°C/W
ψJB
Junction-to-board characterization parameter
24
24
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
5
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
7.5 Electrical Characteristics
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2-µF ceramic, CFILTER = 1-µF ceramic, COUT = 0.1-µF ceramic (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Nominal output voltage (+VOUT)
DCR01xx03
3.3
DCR01xx05
5
Setpoint accuracy
0.5%
Output short-circuit protected
Duration
V
2%
Infinite
Line regulation
1
Over line and load
IO = 10 mA to full load, over +VS range
1%
Temperature variation
–40°C ≤ TA ≤ +85°C
1%
mV/V
2.5%
INPUT
Nominal input voltage (+VS)
DCR0105xx
5
DCR0112xx
12
DCR0124xx
24
Voltage range
–10%
Reflected ripple current
V
20-MHz bandwidth, IO = 100% Load
10%
8
mAp-p
ISOLATION
Voltage
1-s flash test
Isolation
Continuous working
voltage across isolation
barrier
1
kVrms
dV/dt
500
V/s
Leakage current
30
nA
DC
60
VDC
AC
42.5
VAC
Barrier capacitance
25
pF
OUTPUT ENABLE CONTROL
Logic high input voltage
Logic high input current
2
2 < VENABLE < VREC
Logic low input voltage
Logic low input current
Rectified output, VREC
VREC
100
–0.2
100
All 3.3-V outputs
3.3
All 5-V outputs
nA
0.5
0 < VENABLE < 0.5
V
V
nA
V
5
ERROR FLAG
Logic high open-collector leakage
VERROR = 5 V
10
µA
Logic low output voltage
Sinking 2 mA
0.4
V
THERMAL SHUTDOWN
Junction temperature
Temperature activated
150
Temperature deactivated
130
°C
SYNCHRONIZATION PIN
Max external capacitance on SYNC pin
3
pF
880
kHz
720
880
kHz
2.5
3
V
0
0.4
V
–40
85
°C
Internal oscillator frequency
720
External synchronization frequency
External synchronization signal high
External synchronization signal low
800
TEMPERATURE RANGE
Operating
6
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
7.6 Typical Characteristics
70
70
60
60
50
50
Efficiency (%)
Efficiency (%)
at TA = 25°C, +VS = nominal, IO = 10 mA, CIN = 2.2 µF, CFILTER = 1 µF, COUT = 0.1 µF (unless otherwise noted)
40
30
20
30
20
Ambient Temp
85°C
25°C
-40°C
10
40
Ambient Temp
85°C
25°C
-40°C
10
0
0
0
10
20
30
40
50
60
Load (%)
70
80
90
100
0
10
20
30
DCR010503
70
80
90
100
D002
Figure 7-2. Efficiency vs Load
70
70
60
60
50
50
Efficiency (%)
Efficiency (%)
50
60
Load (%)
DCR010505
Figure 7-1. Efficiency vs Load
40
30
40
30
20
20
10
10
0
0
0
10
20
30
40
50
60
Load (%)
70
80
90
100
0
10
20
30
40
D003
DCR011203P
50
60
Load (%)
70
80
90
100
D004
DCR011205P
Figure 7-3. Efficiency vs Load
Figure 7-4. Efficiency vs Load
70
70
60
60
50
50
Efficiency (%)
Efficiency (%)
40
D001
40
30
40
30
20
20
10
10
0
0
0
10
20
30
40
50
60
Load (%)
70
80
90
DCR012403P
Figure 7-5. Efficiency vs Load
Copyright © 2022 Texas Instruments Incorporated
100
D005
0
10
20
30
40
50
60
Load (%)
70
80
90
100
D006
DCR012405P
Figure 7-6. Efficiency vs Load
Submit Document Feedback
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
7
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
5.06
5.016
Device Number
DCR012405
DCR011205
DCR010505
5.013
5.01
Output Voltage (V)
Output Voltage (V)
5.007
Ambient Temp
85°C
25°C
-40°C
5.04
5.004
5.001
4.998
4.995
4.992
4.989
5.02
5
4.98
4.96
4.986
4.983
0
10
20
30
40
50
60
Load (%)
70
80
90
4.94
100
0
10
20
30
D010
All 5-V Output Devices
50
60
Load (%)
70
80
90
100
D008
DCR010505P
Figure 7-7. 5-V Output Load Regulation
Figure 7-8. Load Regulation
3.32
3.305
Device Number
DCR010503
DCR012403
DCR011203
3.3025
3.3
3.31
3.295
3.2925
3.29
3.2875
3.285
3.305
3.3
3.295
3.29
3.285
3.2825
3.28
3.28
3.275
3.2775
0
10
20
30
40
50
60
Load (%)
70
80
90
Ambient Temp
85°C
25°C
-40°C
3.315
Output Voltage (V)
3.2975
Output Voltage (V)
40
3.27
100
0
10
20
30
D009
All 3.3-V Output Devices
40
50
60
Load (%)
70
80
90
100
D007
DCR010503P
Figure 7-9. 3.3-V Output Load Regulation
Figure 7-10. Load Regulation
30.0
18
16
Ripple Voltage (mVp-p)
Ripple Voltage (mVp-p)
25.0
14
12
10
8
6
4
20.0
15.0
10.0
5.0
2
0
0
0
20
40
60
80
100
0
20
All devices except
for DCR011203P and
DCR012403P
40
60
80
100
Load (%)
Load (%)
20-MHz Bandwidth
DCR011203P
DCR012403P
20-MHz Bandwidth
Figure 7-12. Output Voltage Ripple
Figure 7-11. Output Voltage Ripple
8
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
120.0
80
70
100.0
Noise (mVp-p)
Noise (mVp-p)
60
50
40
30
80.0
60.0
40.0
20
20.0
10
0
0
0
20
40
60
80
0
100
20
40
All 5-V Input Devices
60
80
100
Load (%)
Load (%)
DCR011203P
100-MHz Bandwidth
100-MHz Bandwidth
Figure 7-14. Output Voltage Noise
Figure 7-13. Output Voltage Noise
60.0
40.0
20mA/div
Noise (mVp-p)
50.0
30.0
20.0
10.0
0
0%
40%
20%
60%
80%
500ns/div
100%
20-MHz Bandwidth
Load%
DCR011205P
100-MHz Bandwidth
Figure 7-16. Input Current Reflected Ripple
5mV/div
40mA/div
Figure 7-15. Output Voltage Noise
500ns/div
100-MHz Bandwidth
Figure 7-17. Input Current Reflected Ripple
Copyright © 2022 Texas Instruments Incorporated
200ns/div
20-MHz Bandwidth
Figure 7-18. DCR010505P Output Voltage Ripple at
100% Load
Submit Document Feedback
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
9
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
5mV/div
20mV/div
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
200ns/div
200ns/div
100-MHz Bandwidth
20mV/div
Load Current
Figure 7-20. DCR010503P Output Voltage Ripple at
100% Load
30mA Changing
to 325mA
Figure 7-19. DCR010505P Output Voltage Noise at
100% Load
20-MHz Bandwidth
Load Current
200mV/div
Output Voltage
Output Voltage
200ns/div
100-MHz Bandwidth
20mA Changing
to 200mA
Load Current
Output Voltage
10µs/div
Figure 7-23. DCR010503P Load Transient
Response
10
Figure 7-22. DCR010503P Load Transient
Response
Submit Document Feedback
200mV/div
200mV/div
150mA Changing
to 300mA
Figure 7-21. DCR010503P Output Voltage Noise at
100% Load
10µs/div
Load Current
Output Voltage
10µs/div
Figure 7-24. DCR010505P Load Transient
Response
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
200mV/div
100mA Changing
to 200mA
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
Load Current
Output Voltage
10µs/div
Figure 7-25. DCR010505P Load Transient Response
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
11
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
8 Detailed Description
8.1 Overview
The DCR01 series of power modules offer isolation from a regulated power supply operating from a choice
of input voltages. The DCR01s provide a regulated 3.3-V or 5-V output voltage at a nominal output power of
1 W or above. The DCR01 devices include a low dropout linear regulator internal to the device to achieve a
well-regulated output voltage. The DCR01 devices are specified for operational isolation only. The circuit design
uses an advanced BiCMOS and DMOS process.
8.2 Functional Block Diagram
SYNC
Oscillator
800 kHz
+VS
+VOUT
Divide-by-2
Reset
Watchdog
Startup
Input
Controller
VREC
LDO
Regulator
Power
Stage
ERROR
ENABLE
PSU Thermal
Shutdown
-VS
-VOUT
8.3 Feature Description
8.3.1 Isolation
Underwriters Laboratories, UL™ defines several classes of isolation that are used in modern power supplies.
Safety extra low voltage (SELV) is defined by UL (UL1950 E199929) as a secondary circuit, which is so
designated and protected so that under normal and single fault conditions, the voltage between any two
accessible parts or between an accessible part and the equipment earthing terminal for operational isolation
does not exceed steady state 42.5-VRMS or 60-VDC peak for more than one second.
8.3.1.1 Operation or Functional Isolation
The type of isolation used in the DCR01 products is referred to as operational or functional isolation. Insulated
wire used in the construction of the transformer acts as the primary isolation barrier. A high-potential (hipot),
one-second duration test (dielectric voltage, withstand test) is a production test used to verify that the isolation
barrier is functioning. Products with operational isolation must never be used as an element in a safety-isolation
system.
8.3.1.2 Basic or Enhanced Isolation
Basic or enhanced isolation is defined by specified creepage and clearance limits between the primary and
secondary circuits of the power supply. Basic isolation is the use of an isolation barrier in addition to the
insulated wire in the construction of the transformer. Input and output circuits must also be physically separated
by specified distances.
12
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
Note
The DCR01 products do not provide basic or enhanced isolation.
8.3.1.3 Working Voltage
For a device with operational isolation, the continuous working voltage that can be applied across the device in
normal operation must be less than 42.5 VRMS or 60 VDC.
WARNING
Do not use the device as an element of a safety isolation system that exceeds the SELV limit.
If the device is expected to function correctly with more than 42.5 VRMS or 60 VDC applied continuously across
the isolation barrier, then the circuitry on both sides of the barrier must be regarded as operating at an unsafe
voltage, and further isolation or insulation systems must form a barrier between these circuits and any useraccessible circuitry according to safety standard requirements.
8.3.1.4 Isolation Voltage Rating
The terms Hipot test, flash-tested, withstand voltage, proof voltage, dielectric withstand voltage, and isolation
test voltage are all terms that relate to the same thing; a test voltage applied for a specified time across a
component designed to provide electrical isolation to verify the integrity of that isolation. TI’s DCR01 series of
DC/DC converters are all 100% production tested at 1.0 kVAC for one second.
8.3.1.5 Repeated High-Voltage Isolation Testing
Repeated high-voltage isolation testing of a barrier component can degrade the isolation capability, depending
on materials, construction, and environment. The DCR01 series of DC/DC converters have toroidal, enameled,
wire isolation transformers with no additional insulation between the primary and secondary windings. While a
device can be expected to withstand several times the stated test voltage, the isolation capability depends on the
wire insulation. Any material, including this enamel (typically polyurethane), is susceptible to eventual chemical
degradation when subject to very-high applied voltages. Therefore, strictly limit the number of high-voltage tests
and repeated high-voltage isolation testing. However, if it is absolutely required, reduce the voltage by 20% from
specified test voltage with a duration limit of one second per test.
8.3.2 Power Stage
The DCR01 series of devices use a push-pull, center-tapped topology. The DCR01 devices switch at 400 kHz
(divide-by-2 from an 800-kHz oscillator).
8.3.3 Rectification
The output of the transformer is full wave rectified and filtered by the external 1-μF ceramic capacitor connected
to VREC.
8.3.4 Regulator
The internal low dropout linear regulator provides a well-regulated output voltage throughout the operating range
of the device.
8.3.5 Oscillator and Watchdog
The onboard, 800-kHz oscillator generates the switching frequency through a divide-by-2 circuit. The oscillator
can be synchronized to other DCR01 device circuits or an external source, and is used to minimize system
noise.
A watchdog circuit monitors the operation of the oscillator circuit. The oscillator can be disabled by pulling the
SYNC pin low. When the SYNC pin goes low, the output pins transition into tri-state mode, which occurs within
2 μs.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
13
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
8.3.6 ERROR Flag
The DCR01 has an ERROR pin, which provides a power good flag, as long as the internal regulator is in
regulation. If the ERROR output is required, place a 10-kΩ resistor between the ERROR pin and the output
voltage.
8.3.7 Synchronization
When more than one DC/DC converter is switching in an application, beat frequencies and other electrical
interference can be generated. This interference occurs because of the small variations in switching frequencies
between the DC/DC converters.
The DCR01 series of devices overcome this interference by allowing devices to be synchronized to one
another. Synchronize up to eight devices by connecting the SYNC pins of each device, taking care to minimize
the capacitance of tracking. Stray capacitance (greater than 3 pF) reduces the switching frequency, or can
sometimes stop the oscillator circuit. The maximum recommended voltage applied to the SYNC pin is 3 V.
For an application that uses more than eight synchronized devices, use an external device to drive the SYNC
pins. The External Synchronization of the DCP01/02 Series of DC/DC Converters application report describes
this configuration.
Note
During the start-up period, all synchronized devices draw maximum current from the input
simultaneously. If the input voltage falls below approximately 4 V, the devices may not start up. A
ceramic capacitor must be connected close to the input pin of each device. Use a 2.2-μF capacitor for
5-V input devices, and a 0.47-μF capacitor for the 12-V and 24-V devices.
8.3.8 Construction
The basic construction of the DCR01 series of devices is the same as standard integrated circuits. The molded
package contains no substrate. The DCR01 series of devices are constructed using an IC, low dropout linear
regulator, rectifier diodes, and a wound magnetic toroid on a leadframe. Because the package contains no
solder, the devices do not require any special printed-circuit board (PCB) assembly processing. This architecture
results in an isolated DC/DC converter with inherently high reliability.
8.3.9 Thermal Considerations
Due to the high power density of this device, it is advisable to provide ground planes on the input and output
rails. The output regulator is mounted on a copper leadframe, and a ground plane serves as an efficient
heatsink.
8.3.10 Decoupling – Ripple Reduction
Due to the very low forward resistance of the DMOS switching transistors, high current demands are placed
upon the input supply for a short time. By using a good-quality low Equivalent Series Resistance (ESR) capacitor
of 2.2 μF (minimum) for the 5-V input devices and a 0.47-μF capacitor for the 12-V and 24-V devices, placed
close to the IC supply input pins, the effects on the power supply can be minimized.
The high switching frequency of 400 kHz allows relatively small values of capacitors to be used for filtering the
rectified output voltage. A good-quality, low-ESR, 1-μF ceramic capacitor placed close to the VREC pin and
output ground is required and reduces the ripple. The output at VREC is full wave rectified and produces a ripple
of 800 kHz.
TI recommends that a 0.1-μF, low-ESR, ceramic capacitor is connected close to the output pin and ground to
reduce noise on the output. The capacitor values listed are minimum values. If lower ripple is required, the filter
capacitor must be increased in value to 2.2 μF.
As with all switching power supplies, the best performance is obtained with low-ESR, ceramic capacitors
connected close to the device pins. If low-ESR, ceramic capacitors are not used, the ESR generates a voltage
drop when the capacitor is supplying the load power. Often a larger capacitor is chosen for this purpose, when a
low-ESR, smaller capacitor performs as well.
14
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
Note
TI does not recommend that the DCR01 be fitted using an IC socket, as this degrades performance.
8.4 Device Functional Modes
8.4.1 Device Disable and Enable
Each of the DCR01 series devices can be disabled or enabled by driving the SYNC pin using an open-drain
CMOS gate. If the SYNC pin is pulled low, the DCR01 becomes disabled. The disable time depends upon the
external loading. The internal disable function is implemented in 2 μs. Removal of the pulldown causes the
DCR01 to be enabled.
Capacitive loading on the SYNC pin must be minimized (≤ 3 pF) to prevent a reduction in the oscillator
frequency. The External Synchronization of the DCP01/02 Series of DC/DC Converters application report
describes disable and enable control circuitry. This document contains information on how to null the effects
of additional capacitance on the SYNC pin. The frequency of the oscillator can be measured at VREC, since this
is the fundamental frequency of the ripple component.
8.4.2 Regulated Output Disable and Enable
The regulated output of the DCR01 can be disabled by pulling the ENABLE pin LOW. Disabling the output
voltage this way still produces a voltage on the VREC pin. When using the ENABLE control, TI recommends
placing a 10-kΩ resistor between the VREC and ENABLE pins. The ENABLE pin only controls the internal linear
regulator.
If disabling the regulated output is not required, pull the ENABLE pin HIGH by shorting it directly to the VREC pin,
which enables the regulated output voltage, thus allowing the output to be controlled from the isolated side.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
15
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.1.1 DCR01 Single Voltage Output
The DCR01 can be used to provide a single voltage output by connecting it as shown in Figure 9-1. The ERROR
output signal is pulled up to the value of VOUT. The value of RERR depends on the loading on the ERROR line,
however, the total load on the ERROR line must not exceed the value given in the Electrical Charcteristics.
The output can be permanently enabled by connecting the ENABLE pin to the VREC pin. The DCR01 can be
enabled remotely by connecting the ENABLE pin to VREC through a pullup resistor (REN); the value of this
resistor is not critical for the DCR01 as only a small current flows. The switch SW1 can be used to pull the
ENABLE pin LOW, thus disabling the output. The switching devices can be a bipolar transistor, FET, or a
mechanical device; the main load that it sees is REN.
SYNC
VIN
+VOUT
ERROR
+VS
+VOUT
RERR
10 k
ERROR
VREC
DCR01
(1)
CIN
ENABLE
10k
SW1
±VS
A.
±VOUT
COUT
0.1 µF
REN
CFILTER
1 µF
±VOUT
CIN = 2.2 μF for 5-V input devices and 0.47 μF for 12-V and 24-V input devices. Low-ESR, ceramic capacitors are required.
Figure 9-1. DCR01 Single Output Voltage
16
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
9.1.2 Generating Two Positive Output Voltages
Two DCR01s can be used to create output voltages of +3.3 V and +5 V, as shown in Figure 9-2. The two
DCR01s are connected in self-synchronization, thus locking the oscillators of both devices to a single frequency.
The ERROR and ENABLE facilities can be used in a similar configuration for a single DCR01. The filter
capacitors connected to the VREC pins (CFILTER) must be kept separate from each other and connected in close
proximity to their respective DCR01.
VIN
+VOUT
+VS
CIN
ERROR
(1)
+VOUT1
RERR
10 k
ERROR1
VREC
DCR01
ENABLE
CFILTER
1 µF
±VS
SYNC
COUT
0.1 µF
±VOUT
-VOUT
+VOUT
SYNC
VIN
ERROR
+VS
+VOUT2
RERR
10 k
ERROR2
VREC
CIN
DCR01
(1)
±VS
A.
ENABLE
CFILTER
1 µF
COUT
0.1 µF
±VOUT
CIN = 2.2 μF for 5-V input devices and 0.47 μF for 12-V and 24-V input devices. Low-ESR, ceramic capacitors are required.
Figure 9-2. Two Positive Voltages from Self-Synchronized DCR01s
9.1.3 Generation of Dual Polarity Voltages from Two Self-Synchronized DCR01s
Two DCR01s can be configured to produce a dual polarity supply (that is, ±5 V); the circuit must be connected
as shown in Figure 9-3.
Observe that both devices are producing a positive regulated output; therefore the ERROR, ENABLE, and
VREC are all relative to the –VOUT pin of that particular device and must not be directly connected together, or in
the case of the negative output device, connected to the common 0-V output.
VIN
+VOUT
+VS
CIN
VPOS O/P
ERROR
(1)
VREC
DCR01
ENABLE
±VS
SYNC
CFILTER
1 µF
COUT
0.1 µF
±VOUT
0V
+VOUT
SYNC
VIN
ERROR
+VS
VREC
CIN
DCR01
(1)
±VS
A.
ENABLE
CFILTER
1 µF
COUT
0.1 µF
±VOUT
VNEG O/P
CIN = 2.2 μF for 5-V input devices and 0.47 μF for 12-V and 24-V input devices. Low-ESR, ceramic capacitors are required.
Figure 9-3. Dual Polarity Voltage Generation
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
17
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
9.2 Typical Application
SYNC
DCR010505
+VOUT = 5V
+VOUT
RERR
10 k
VIN = 5V
+VS
ERROR
CIN
2.2 µF
COUT
0.1 µF
VREC
ENABLE
CFILTER
1.0 µF
±VS
±VOUT
±VOUT
Copyright © 2016, Texas Instruments Incorporated
Figure 9-4. DCR01 Typical Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 9-1 and follow the design procedure.
Table 9-1. Design Example Parameters
Design Parameter
Value
Input voltage, VIN
5 V typical
Output voltage, VOUT
5 V regulated
Output current rating
200 mA
Isolation
1000-V operational
9.2.2 Detailed Design Procedure
9.2.2.1 Input Capacitor
For this design, a 2.2-μF ceramic capacitor is required for the input decoupling capacitor.
9.2.2.2 Output Capacitor
For this design, a 0.1-μF ceramic capacitor is required for between +VOUT and –VOUT.
9.2.2.3 Filter Capacitor
A high-quality, low-ESR, 1-μF ceramic capacitor placed close to the VREC pin and output ground is required to
reduce output voltage ripple.
9.2.2.4 ERROR Flag
Place a 10-kΩ resistor between the ERROR pin and the output voltage to provide a power good signal when the
internal regulator is in regulation.
18
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
9.2.3 Application Curves
70
5.06
60
5.04
Output Voltage (V)
50
Efficiency (%)
Ambient Temp
85°C
25°C
-40°C
40
30
20
Ambient Temp
85°C
25°C
-40°C
10
10
20
30
40
50
60
Load (%)
70
80
90
Figure 9-5. DCR010505 Efficiency
5
4.98
4.96
4.94
0
0
5.02
100
D002
0
10
20
30
40
50
60
Load (%)
70
80
90
100
D008
Figure 9-6. DCR010505 Load Regulation
10 Power Supply Recommendations
The DCR01 is a switching power supply, and as such, can place high peak current demands on the input supply.
To avoid the supply falling momentarily during the fast switching pulses, ground and power planes must be
used to connect the power to the input of DCR01. If this connection is not possible, then the supplies must be
connected in a star formation with the traces made as wide as possible.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
19
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
11 Layout
11.1 Layout Guidelines
Carefully consider the layout of the PCB for the best results to be obtained.
Input and output power and ground planes provide a low-impedance path for the input and output power. For the
output, the positive and negative voltage outputs conduct through wide traces to minimize losses.
A good-quality, low-ESR, ceramic capacitor placed as close as practical across the input reduces reflected ripple
and ensure a smooth start-up.
A good-quality, low-ESR, ceramic capacitor placed as close as practical across the rectifier output terminal and
output ground to provide the best ripple and noise performance.
The location of the decoupling capacitors in close proximity to their respective pins ensures low losses due to
the effects of stray inductance, thus improving the ripple performance. This location is of particular importance
to the input decoupling capacitor, because this capacitor supplies the transient current associated with the fast
switching waveforms of the power drive circuits.
If the SYNC pin is being used, the tracking between device SYNC pins must be short to avoid stray capacitance.
Never connect a capacitor to the SYNC pin. If the SYNC pin is not being used it is advisable to place a guard
ring (connected to input ground) around this pin to avoid any noise pick-up. Ensure that no other trace is in close
proximity to this trace SYNC trace to decrease the stray capacitance on this pin. The stray capacitance affects
the performance of the oscillator.
Figure 11-1 shows a schematic for a single DCR01, SOP package device. Figure 11-2 and Figure 11-3 show a
typical layout for the SOP package DCR01 device. The layout shows proper placement of capacitors and power
planes.
11.2 Layout Examples
+VS
1
DCR01U
+VS
2
+VS
C1
U1
SYNC 28
-VS
26 ±VS
27 ±VS
VREC
ERROR 17
12 VREC
C2
ENABLE 16
-VOUT
C3
+VOUT
13 ±VOUT
14 +VOUT
Figure 11-1. DCR01 PCB Schematic, U Package
20
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
U1
SYNC
+VS
SYNC
+VS
-VS
C1
-VS
VREC
C2
VREC
ERROR
ERROR
ENABLE
-VOUT
+VOUT
ENABLE
-VOUT
C3
Figure 11-2. PCB Layout Example, ComponentSide View
Copyright © 2022 Texas Instruments Incorporated
+VOUT
Figure 11-3. PCB Layout Example, NonComponent-Side View
Submit Document Feedback
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
21
DCR010503, DCR012405, DCR010505, DCR011203, DCR011205, DCR012403
www.ti.com
SBVS013E – OCTOBER 2001 – REVISED JULY 2022
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
Underwriters Laboratories, UL™ is a trademark of UL LLC.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
22
Submit Document Feedback
Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: DCR010503 DCR012405 DCR010505 DCR011203 DCR011205 DCR012403
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
DCR010503P
ACTIVE
PDIP
NVE
10
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 85
DCR010503P
Samples
DCR010503U
ACTIVE
SOP
DVB
12
28
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010503U
Samples
DCR010503U/1K
ACTIVE
SOP
DVB
12
1000
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010503U
Samples
DCR010503UE4
ACTIVE
SOP
DVB
12
28
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010503U
Samples
DCR010505P
ACTIVE
PDIP
NVE
10
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 85
DCR010505P
Samples
DCR010505U
ACTIVE
SOP
DVB
12
28
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010505U
Samples
DCR010505U/1K
ACTIVE
SOP
DVB
12
1000
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010505U
Samples
DCR010505U/1KE4
ACTIVE
SOP
DVB
12
1000
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010505U
Samples
DCR010505UE4
ACTIVE
SOP
DVB
12
28
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR010505U
Samples
DCR011203P
ACTIVE
PDIP
NVE
10
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 85
DCR011203P
Samples
DCR011203U
ACTIVE
SOP
DVB
12
28
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR011203U
Samples
DCR011203U/1K
ACTIVE
SOP
DVB
12
1000
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR011203U
Samples
DCR011203UE4
ACTIVE
SOP
DVB
12
28
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR011203U
Samples
DCR011205P
ACTIVE
PDIP
NVE
10
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 85
DCR011205P
Samples
DCR011205U
ACTIVE
SOP
DVB
12
28
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR011205U
Samples
DCR011205U/1K
ACTIVE
SOP
DVB
12
1000
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR011205U
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jul-2022
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
DCR011205UE4
ACTIVE
SOP
DVB
12
28
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR011205U
Samples
DCR012403P
ACTIVE
PDIP
NVE
10
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 85
DCR012403P
Samples
DCR012403U
ACTIVE
SOP
DVB
12
28
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR012403U
Samples
DCR012405P
ACTIVE
PDIP
NVE
10
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 85
DCR012405P
Samples
DCR012405U
ACTIVE
SOP
DVB
12
28
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR012405U
Samples
DCR012405U/1K
ACTIVE
SOP
DVB
12
1000
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR012405U
Samples
DCR012405UE4
ACTIVE
SOP
DVB
12
28
RoHS &
Non-Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
DCR012405U
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
