User's Guide
SBOU162A – March 2017 – Revised May 2017
DIYAMP-SOIC-EVM
This user's guide contains support documentation for the DIYAMP-SOIC evaluation module (EVM).
Included is a description of how to set up and configure the EVM, printed circuit board (PCB) layout,
schematic, and bill of materials (BOM) of the DIYAMP-SOIC-EVM.
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Contents
Introduction ................................................................................................................... 3
Hardware Setup .............................................................................................................. 4
Schematic and PCB Layout ................................................................................................ 7
Connections ................................................................................................................. 27
Bill of Materials and Reference ........................................................................................... 30
List of Figures
1
Location of Circuit Configurations ......................................................................................... 4
2
Detach Desired Circuit Configuration ..................................................................................... 5
3
Detach Configuration With Attached IC and Passive Components ................................................... 5
4
Terminal Strip (TS-132-G-AA) Broken Into 4-Pin Lengths ............................................................. 5
5
4-Pin Length Terminal Strips Inserted in DIP Socket ................................................................... 6
6
Detached Board Configuration Position Over Terminal Pins
7
Fully-Assembled Circuit Configuration From DIYAMP-SOIC-EVM.................................................... 6
8
Silk Screen Circuit Schematic .............................................................................................. 7
9
Single-Supply, Multiple Feedback Filter Schematic ..................................................................... 7
10
Single-Supply, MFB Filter Top Layer
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14
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6
..................................................................................... 8
Single-Supply, MFB Filter Bottom Layer.................................................................................. 8
Single-Supply, Sallen-Key Filter Schematic .............................................................................. 9
Single-Supply, Sallen-Key Filter Top Layer .............................................................................. 9
Single-Supply, Sallen-Key Filter Bottom Layer ......................................................................... 10
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15
Single-Supply, Non-Inverting Amplifier Schematic..................................................................... 10
16
Single-Supply, Non-Inverting Amplifier Top Layer ..................................................................... 12
17
Single-Supply, Non-Inverting Amplifier Bottom Layer ................................................................. 12
18
Single-Supply, Inverting Amplifier Schematic
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..........................................................................
Single-Supply, Inverting Amplifier Top Layer ...........................................................................
Single-Supply, Inverting Amplifier Bottom Layer .......................................................................
Difference Amplifier Schematic ...........................................................................................
Difference Amplifier Top Layer ...........................................................................................
Difference Amplifier Bottom Layer .......................................................................................
Dual-Supply, Multiple Feedback Filter Schematic .....................................................................
Dual-Supply, Multiple Feedback Filter Top Layer ......................................................................
Dual-Supply, Multiple Feedback Bottom Layer.........................................................................
Dual-Supply, Sallen-Key Filter Schematic ..............................................................................
Dual-Supply, Sallen-Key Top Layer .....................................................................................
Dual-Supply, Sallen-Key Bottom Layer .................................................................................
Inverting Comparator Schematic .........................................................................................
Inverting Comparator Top Layer .........................................................................................
Inverting Comparator Bottom Layer .....................................................................................
Non-Inverting Comparator Schematic ...................................................................................
Non-inverting Comparator Top Layer....................................................................................
Non-Inverting Comparator Bottom Layer................................................................................
Riso with Dual-Feedback Schematic ......................................................................................
Example of fZERO, Where AOL_Loaded = 20 dB ..............................................................................
Riso Dual-Feedback Top Layer ............................................................................................
Riso Dual-Feedback Bottom Layer ........................................................................................
Dual-Supply, Non-Inverting Amplifier Schematic.......................................................................
Dual-Supply, Non-Inverting Amplifier Top Layer .......................................................................
Dual-Supply, Non-Inverting Amplifier Bottom Layer ...................................................................
Dual-Supply, Inverting Amplifier Schematic ............................................................................
Dual-Supply, Inverting Amplifier Top Layer .............................................................................
Dual-Supply, Inverting Amplifier Bottom Layer .........................................................................
SMA Vertical Connectors .................................................................................................
SMA Horizontal Connectors ..............................................................................................
Wire Connections ..........................................................................................................
Through-Hole Test Points .................................................................................................
Input and Output Pins in Terminal Area .................................................................................
Wire Alternative for Terminal Area .......................................................................................
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List of Tables
1
DIYAMP-SOIC-EVM Kit Contents ......................................................................................... 3
2
Location of Circuit Legend .................................................................................................. 4
3
MFB Filter Type Component Selection ................................................................................... 8
4
Sallen-Key Filter Component Type Selection ............................................................................ 9
5
MFB Filter Type Component Selection .................................................................................. 16
6
Sallen-Key Filter Component Type Selection
7
..........................................................................
Bill of Materials .............................................................................................................
18
30
Trademarks
FilterPro, TINA-TI are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
2
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Introduction
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1
Introduction
The DIYAMP-SOIC-EVM is an EVM developed to give users the ability to easily evaluate their design
concepts. This break-apart EVM has several popular op-amp configurations including: amplifiers, filters,
and stability compensation configurations for both single and dual supply. The EVM is designed for 0805
and 0603 package size surface mount components enabling easy prototyping. This board gives the user
the ability to build anything from a simple amplifier to complex signal chains by combining different
configurations.
For more information about power supply voltages and input/output limitations, consult TI Precision Labs –
Op Amps videos.
1.1
DIYAMP-SOIC-EVM Kit Contents
Table 1 details the contents included in the DIYAMP-SOIC-EVM kit.
Table 1. DIYAMP-SOIC-EVM Kit Contents
1.2
Item
Description
Quantity
DIYAMP-SOIC-EVM
PCB
1
Header Strip
100 mil (2.54 mm) spacing, 32 position, through hole
2
EVM Features
This EVM supports the following features:
• Multiple circuit configurations
• Dual- and single-supply configurations
• Breadboard compatible
• Schematic provided in silk screen on the PCB
• Multiple connector options for input and output connections: SMA, test point, and wires.
1.3
List of Circuits on the EVM
•
•
•
•
•
•
•
•
•
•
•
•
Single-supply multiple feedback (MFB) filter
Single-supply Sallen-Key filter
Single-supply non-inverting amplifier
Single-supply inverting amplifier
Difference amplifier
Dual-supply multiple feedback (MFB) filter
Dual-supply Sallen-Key filter
Riso with dual feedback
Non-Inverting Comparator
Inverting Comparator
Dual-supply non-inverting amplifier
Dual-supply inverting amplifier
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Hardware Setup
2
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Hardware Setup
Assembly of the DIYAMP-SOIC-EVM involves identifying and breaking out the desired circuit configuration
from the EVM, soldering components, header pins, and inputs and outputs connections. This section
presents the details of these procedures.
2.1
EVM Circuit Locations
Figure 1 and Table 2 map the location of each circuit configuration on the EVM. Figure 1 labels each
circuit configuration with a letter ranging from A to L. Table 2 matches the circuit configuration to a letter in
Figure 1 and also provides the name of each individual circuit written in silk screen on the EVM.
Figure 1. Location of Circuit Configurations
Table 2. Location of Circuit Legend
Circuit Name
Single-supply multiple feedback filter
Single-supply Sallen Key filter
Single-supply non-inverting amplifier
Single-supply inverting amplifier
Difference amplifier
Dual-supply multiple feedback filter
Dual-supply Sallen Key filter
Inverting comparator
Non-inverting comparator
Riso with dual feedback
Dual-supply non-inverting amplifier
Dual-supply inverting amplifier
4
Silk Screen Label
Letter in
Figure 1
Single-Supply MFB Filter
A
Single-Supply SK Filter
B
Single-Supply Non-Inverting Amp
C
Single-Supply Inverting Amp
D
Difference Amp
E
MFB Filter
F
SK Filter
G
Inverting Comparator
H
Non-Inverting Comparator
I
Riso Dual Feedback
J
Non-Inverting Amp
K
Inverting Amp
L
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Hardware Setup
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2.2
EVM Assembly Instructions
This section has step-by-step instructions on how to assemble a circuit configuration from the EVM.
Step 1. Choose the desired circuit configuration. See Section 2.1 for the location of each circuit
configuration.
Step 2. Gently flex the PCB panel at the score lines to separate the desired circuit configuration from
the EVM.
Figure 2. Detach Desired Circuit Configuration
Step 3.
Solder device and surface mount passive components to the separated PCB.
Figure 3. Detach Configuration With Attached IC and Passive Components
Step 4.
Use long-nose pliers to break header strips, provided in the EVM kit, into 4-position lengths.
Figure 4. Terminal Strip (TS-132-G-AA) Broken Into 4-Pin Lengths
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Step 5.
Insert header strips into a spare DIP socket as shown in Figure 5.
Figure 5. 4-Pin Length Terminal Strips Inserted in DIP Socket
Step 6.
Position separated PCB over pins and solder the connections. Carefully remove from the DIP
socket.
Figure 6. Detached Board Configuration Position Over Terminal Pins
Step 7.
Attach SMA connectors, test points, or wires to the input and output of the separated PCB.
Figure 7. Fully-Assembled Circuit Configuration From DIYAMP-SOIC-EVM
6
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3
Schematic and PCB Layout
This section provides the schematic and PCB layout of each circuit configuration provided on the EVM.
3.1
Schematic PCB Drawing
Each circuit board has a silk screen of its schematic for easy reference.
Figure 8. Silk Screen Circuit Schematic
3.2
Single-Supply, Multiple Feedback Filter
Figure 9 shows the schematic for the single-supply, multiple feedback (MFB) filter circuit configuration.
Figure 9. Single-Supply, Multiple Feedback Filter Schematic
The MFB topology (sometimes called infinite gain or Rauch) is often preferred, due to low sensitivity to
component variations. The MFB topology creates an inverting second-order stage. This inversion may, or
may not, be a concern in the filter application.
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The single-supply, MFB filter circuit can be configured as a low-pass filter, high-pass filter, or band-pass
filter based on the component selection of Z1 through Z5. Table 3 displays the type of passive component
that should be chosen for Z1 through Z5 for each filter configuration.
Table 3. MFB Filter Type Component Selection
Pass-Band
Filter Type
Type of
Component (Z1)
Type of
Component (Z2)
Type of
Component (Z3)
Type of
Component (Z4)
Type of
Component (Z5)
Low Pass
R1
C2
R3
R4
C5
High Pass
C1
R2
C3
C4
R5
Band Pass
R1
R2
C3
C4
R5
For additional guidance in designing a filter, download FilterPro™ active filter design software.
Capacitor C2 provides the option to filter noise that may be introduced from the Vref input. calculates the
cutoff frequency due to C2.
1
fc _ Vref =
2p ´ R1 / / R2 ´ C2
(1)
The PCB layout of the top layer of the single-supply, MFB filter configuration is displayed in Figure 10.
Figure 10. Single-Supply, MFB Filter Top Layer
The PCB layout of the bottom layer of the single-supply, MFB filter configuration is displayed in Figure 11.
Figure 11. Single-Supply, MFB Filter Bottom Layer
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3.3
Single-Supply, Sallen-Key Filter
Figure 12 shows the schematic for the single-supply, Sallen-Key filter circuit configuration.
Figure 12. Single-Supply, Sallen-Key Filter Schematic
Sallen-Key is one of the most commonly applied active filter topologies. The Sallen-Key is a non-inverting,
voltage-controlled, voltage-source (VCVS) able to attain larger Qs with a stable response than other filter
topologies. Because Sallen-Key is non-inverting, it might be preferable over the MFB topology.
The single-supply, Sallen-Key filter can be configured as a low-pass filter, high-pass filter, or band-pass
filter based on the component selection of Z1 through Z5. Table 4 displays the type of passive component
that should be chosen for Z1 through Z5 for each filter configuration.
Table 4. Sallen-Key Filter Component Type Selection
Pass-Band
Filter Type
Type of
Component (Z1)
Type of
Component (Z2)
Type of
Component (Z3)
Type of
Component (Z4)
Type of
Component (Z5)
Low Pass
R1
R2
C3
C4
Not populated
High Pass
C1
C2
R3
R4
Not populated
Band Pass
R1
C2
R3
R4
C5
For additional guidance in designing a filter, download the FilterPro active filter design software.
The PCB layout of the top layer of the single-supply, Sallen-Key filter circuit configuration is displayed in
Figure 13.
Figure 13. Single-Supply, Sallen-Key Filter Top Layer
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The PCB layout of the bottom layer of the single-supply, Sallen-Key filter configuration is displayed in
Figure 14.
Figure 14. Single-Supply, Sallen-Key Filter Bottom Layer
3.4
Single-Supply, Non-Inverting Amplifier
Figure 15 shows the schematic for the single-supply, non-inverting amplifier circuit configuration.
Figure 15. Single-Supply, Non-Inverting Amplifier Schematic
The non-inverting op-amp configuration takes an input signal that is applied directly to the high
impedance, non-inverting input terminal and outputs a signal that is the same polarity as the input signal.
The load resistance for this topology is the sum of R1 and R2. The values of the resistors in the feedback
network will determine the amount of gain to amplify the input signal.
There are multiple ways to configure the single-supply, non-inverting amplifier. The following cases show
three primary use case configurations for this circuit.
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Case 1: Standard non-inverting circuit
This circuit board can be configured into a standard non-inverting circuit by shorting C3 and C4 with a 0-Ω
resistor and leaving R3 and R4 unpopulated.
Equation 2 displays the transfer function for the standard single-supply, non-inverting amplifier circuit
configuration.
æ
R ö
Vout = ç 1 + 1 ÷ Vin
R2 ø
è
where
•
•
•
•
C3 is
C4 is
R3 is
R4 is
shorted with a 0-Ω resistor
shorted with a 0-Ω resistor
unpopulated
unpopulated
(2)
Capacitor C2 provides the option to filter the output. The cutoff frequency of the filter can be calculated
using Equation 3.
1
fc =
2p´ R1 ´ C2
(3)
Case 2: AC coupled, single-supply, non-inverting circuit
This circuit board can be configured into an AC coupled non-inverting circuit by populating C3 and C4 with
capacitors and populating R3 or R4 with resistors. R3 and R4 are used to set the DC output in the
following two ways:
Option 1: VREF is directly applied to the input IN+
• R3 is populated with the desired biasing resistor
• R4 is unpopulated
Option 2: VREF is divided down and applied to the input IN+
• R3 and R4 are populated with resistors, see Equation 4
æ R4
ö
VIN+ = ç
÷ Vref
è R3 + R 4 ø
(4)
The AC response of the input signal is high-passed through C4, R3 + R4. The op-amp noise-gain is unitygain until the gain begins to rise at the zero frequency defined in Equation 5.
1
FZERO =
2p´ C3 (R1 + R2 )
(5)
The gain flattens off to the same gain defined in Equation 2 at the frequency defined in Equation 6.
1
Fpole =
2p´ C3 ´ R2
(6)
For more information on the AC coupled non-inverting circuit, see e2e.ti.com.
Case 3: Non-inverting signal scaling circuit
This circuit board can be configured into a non-inverting signal scaling circuit by shorting C3 with a 0-Ω
resistor and populating C4 with a resistor. This forms a 3-resistor divider with R3 and R4 on the input to
scale or shift the input signal level. The op amp is typically configured as a unity-gain buffer.
Step 1. Choose a value for the resistor installed in place of C4
Step 2. Compute R3
æ
R1 ö
ç1 +
÷ C ´ Vref
R2 ø 4
è
R3 =
Voffset
(7)
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Step 3.
Compute R2
- Voffset ´ C4 ´ R3
R2 =
Voffset ´ R3 + Voffset ´ C4 - Vref ´ C4
(8)
For more information on the AC coupled non-inverting circuit, see e2e.ti.com.
The PCB layout of the top layer of the single-supply, non-inverting circuit configuration is displayed in
Figure 16.
Figure 16. Single-Supply, Non-Inverting Amplifier Top Layer
The PCB layout of the bottom layer of the single-supply, non-inverting circuit configuration is displayed in
Figure 17.
Figure 17. Single-Supply, Non-Inverting Amplifier Bottom Layer
3.5
Single-Supply, Inverting Amplifier
Figure 18 shows the schematic for the single-supply, inverting amplifier circuit configuration.
Figure 18. Single-Supply, Inverting Amplifier Schematic
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The inverting op-amp configuration takes an input signal that is applied directly to the inverting input
terminal and outputs a signal that is the opposite polarity as the input signal. The benefit of this topology is
that it avoids common mode limitations. The load resistance for this topology is equal to R2. The values of
the resistors in the feedback network will determine the amount of gain to amplify the input signal.
The single-supply, inverting amplifier circuit provides the option to AC couple the input, filter the output,
and bias the output of the amplifier to a desired value.
Equation 9 displays the dc transfer function of the single-supply, inverting amplifier circuit configuration.
ö
æ R ö
æ
R öæ
R4
Vout = ç - 1 ÷ Vin + ç 1 + 1 ÷ ç
÷ Vref
R 2 ø è R3 + R 4 ø
è R2 ø
è
where
•
C3 is shorted with a 0-Ω resistor
(9)
Capacitor C3 provides the option to AC couple the input of the single-supply, inverting amplifier by
creating a high-pass filter. Equation 10 displays the dc transfer function of the single-supply, inverting
amplifier circuit configuration.
æ R4
ö
Vout = ç
÷ Vref
è R3 + R 4 ø
where
•
The input is AC coupled with C3
(10)
The cutoff frequency of the high-pass filter can be calculated using Equation 11.
1
fc _ highpass =
2p´ C3 ´ R2
(11)
Equation 12 displays the transfer function when the frequency of the input signal is above the cutoff
frequency calculated in Equation 11.
æ
ö
æ R ö
R4
Vout = ç - 1 ÷ Vin + ç
÷ Vref
è R2 ø
è R3 + R 4 ø
(12)
Capacitor C2 filters noise that may be introduced from the Vref input. Equation 13 calculates the cutoff
frequency due to C2.
1
fc _ Vref =
2p ´ R 3 / / R 4 ´ C2
(13)
Capacitor C4 provides the option to filter the output. The cutoff frequency of the filter can be calculated
using Equation 14.
1
fc _ Vout =
2p ´ R1 ´ C4
(14)
The PCB layout of the top layer of the single-supply, inverting amplifier circuit configuration is displayed in
Figure 19.
Figure 19. Single-Supply, Inverting Amplifier Top Layer
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The PCB layout of the bottom layer of the single-supply, inverting amplifier circuit configuration is
displayed in Figure 20.
Figure 20. Single-Supply, Inverting Amplifier Bottom Layer
3.6
Difference Amplifier
Figure 21 shows the schematic for the difference amplifier circuit configuration.
Figure 21. Difference Amplifier Schematic
The difference amplifier utilizes both inverting and non-inverting inputs and produces an output that is
equal to the difference between the inputs. The gain of the difference amplifier is dependent on the ratio of
the resistor values selected.
Equation 15 displays the transfer function of the difference amplifier circuit configuration.
æ R4
öæ
æ R3
öæ
R1 ö
R1 ö
R1
Vout = ç
VIN÷ ç1 +
÷ ç1 +
÷ VIN+ + ç
÷ Vref +
R
R
R
R
R
R
R
+
+
4 øè
2 ø
4 øè
2 ø
2
è 3
è 3
If R1 = R4 and R2 = R3, Equation 15 can be simplified to Equation 16.
R
Vout = 1 (VIN+ - VIN- ) + Vref
R2
14
DIYAMP-SOIC-EVM
(15)
(16)
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Capacitors C1 and C4 provide the option to filter the output of the amplifier. The cutoff frequency of the
filter can be calculated using Equation 17.
1
fc =
2p´ R1 ´ C1
where
•
R1 = R4, R2 = R3, and C1 = C4
(17)
The PCB layout of the top layer of the difference amplifier circuit configuration is displayed in Figure 22.
Figure 22. Difference Amplifier Top Layer
The PCB layout of the bottom layer of the difference amplifier circuit configuration is displayed in
Figure 23.
Figure 23. Difference Amplifier Bottom Layer
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3.7
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Dual-Supply, Multiple Feedback Filter
Figure 24 shows the schematic for the dual-supply, multiple feedback filter circuit configuration.
Figure 24. Dual-Supply, Multiple Feedback Filter Schematic
The MFB topology (sometimes called infinite gain or Rauch) is often preferred due to low sensitivity to
component variations. The MFB topology creates an inverting second-order stage. This inversion may, or
may not, be a concern in the filter application.
The dual-supply, MFB filter circuit can be configured as a low-pass filter, high-pass filter, or band-pass
filter based on the component selection of Z1 through Z5. Table 5 displays the type of passive component
that should be chosen for Z1 through Z5 for each filter configuration.
Table 5. MFB Filter Type Component Selection
Pass-Band
Filter Type
Type of
Component (Z1)
Type of
Component (Z2)
Type of
Component (Z3)
Type of
Component (Z4)
Type of
Component (Z5)
Low Pass
R1
C2
R3
R4
C5
High Pass
C1
R2
C3
C4
R5
Band Pass
R1
R2
C3
C4
R5
For additional guidance in designing a filter, download the FilterPro active filter design software.
The PCB layout of the top layer of the dual-supply, multiple feedback filter circuit configuration is displayed
in Figure 25.
Figure 25. Dual-Supply, Multiple Feedback Filter Top Layer
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The PCB layout of the bottom layer of the dual-supply, multiple feedback filter circuit configuration is
displayed in Figure 26.
Figure 26. Dual-Supply, Multiple Feedback Bottom Layer
3.8
Dual-Supply, Sallen-Key Filter
Figure 27 shows the schematic for the dual-supply, Sallen-Key Filter circuit configuration.
Figure 27. Dual-Supply, Sallen-Key Filter Schematic
Sallen-Key is one of the most commonly applied active filter topologies. The Sallen-Key is a non-inverting,
voltage-controlled, voltage-source (VCVS) able to attain larger Qs with a stable response than other filter
topologies. Because Sallen-Key is non-inverting, it might be preferable over the MFB topology.
For this EVM, the Sallen-key filter can be configured for unity-gain by populating R1 with a short and
leaving R2 open. Gain can be added by adding the appropriate resistors to R2 and R1 as explained in
FilterPro.
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The dual-supply, Sallen-Key filter can be configured as a low-pass filter, high-pass filter, or band-pass
filter based on the component selection of Z1 through Z5. Table 6 displays the type of passive component
that should be chosen for Z1 through Z5 for each filter configuration.
Table 6. Sallen-Key Filter Component Type Selection
Pass-Band
Filter Type
Type of
Component (Z1)
Type of
Component (Z2)
Type of
Component (Z3)
Type of
Component (Z4)
Type of
Component (Z5)
Low Pass
R1
R2
C3
C4
Not populated
High Pass
C1
C2
R3
R4
Not populated
Band Pass
R1
C2
R3
R4
C5
For additional guidance in designing a filter, download the FilterPro active filter design software.
The PCB layout of the top layer of the dual-supply, Sallen-Key filter circuit configuration is displayed in
Figure 28.
Figure 28. Dual-Supply, Sallen-Key Top Layer
The PCB layout of the bottom layer of the dual-supply, Sallen-Key filter circuit configuration is displayed in
Figure 29.
Figure 29. Dual-Supply, Sallen-Key Bottom Layer
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3.9
Inverting Comparator
Figure 30 shows the schematic for the inverting comparator circuit configuration.
Figure 30. Inverting Comparator Schematic
It is important to note that this circuit layout is meant for SOIC package op amps or push-pull output type
comparators. This configuration uses a voltage divider R1 and R2 to set up the threshold voltage when no
hysteresis is added. The comparator will compare the input signal (Vin) to the threshold voltage (Vth).
æ R2 ö
Vth = ç
÷ Vref
è R1 + R2 ø
where
•
R3 is unpopulated
(18)
The comparator input signal is applied to the inverting input, so the output will have an inverted polarity.
When Vin > Vth, the output will drive to the negative supply (GND or logic low). When Vin < Vth, the
output will drive to the positive supply (V+ or logic high).
R3 can be populated to implement hysteresis which uses two different threshold voltages to avoid the
multiple transitions. The input signal must exceed the upper threshold (VH) to transition low or below the
lower threshold (VL) to transition high. Equation 19 and Equation 20 will calculate the value of R2 and R3
for the two desired thresholds.
æ VL ö
R3 = ç
÷ R1
è VH - VL ø
(19)
æ VL ö
R2 = ç
÷ R1
è V+ - VH ø
(20)
The PCB layout of the top layer of the inverting comparator circuit configuration is displayed in Figure 31.
Figure 31. Inverting Comparator Top Layer
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The PCB layout of the bottom layer of the inverting comparator circuit configuration is displayed in
Figure 32.
Figure 32. Inverting Comparator Bottom Layer
3.10 Non-Inverting Comparator
Figure 33 shows the schematic for the non-inverting comparator circuit configuration.
VREF
R3
R4
V+
C1
±
VOUT
+
R1
R2
VIN
Figure 33. Non-Inverting Comparator Schematic
It is important to note that this circuit layout is meant for SOIC package op amp or push-pull output type
comparators. This configuration uses a voltage divider R3 and R4 to set up the threshold voltage. The
comparator will compare the input signal (Vin) to the threshold voltage (Vth).
æ R4
Vth = ç
è R3 + R 4
ö
÷ Vref
ø
(21)
The comparator input signal is applied to the non-inverting input, so the output will have a non-inverted
polarity. When Vin > Vth, the output will drive to the positive supply (V+ or logic high). When Vin < Vth, the
output will drive to the negative supply (GND or logic low).
R2 can be populated to implement hysteresis which uses two different threshold voltages to avoid the
multiple transitions. The input signal must exceed the upper threshold (VH) to transition high or below the
lower threshold (VL) to transition low. Equation 22 and Equation 23 will calculate the value of R1 and R2
for the two desired thresholds.
R1 =
R2 =
20
(Vh - Vth )
Vth
R2
(22)
(Vth + V+ )
R
(Vl - Vth ) 1
(23)
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The PCB layout of the top layer of the non-inverting comparator circuit configuration is displayed in
Figure 34.
Figure 34. Non-inverting Comparator Top Layer
The PCB layout of the top layer of the non-inverting comparator circuit configuration is displayed in
Figure 35.
Figure 35. Non-Inverting Comparator Bottom Layer
3.11 Riso With Dual Feedback
Figure 36 shows the schematic for the Riso with dual-feedback circuit configuration.
Figure 36. Riso with Dual-Feedback Schematic
The dc gain of the Riso with dual-feedback circuit configuration can be calculated using Equation 24.
ö
æ
R öæ
R4
Vout = ç 1 + 1 ÷ ç
÷ Vin
R 2 ø è R 4 + R5 ø
è
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In situations where stability is affected by capacitive loads, the Riso dual-feedback configuration has the
ability to stabilize the circuit by compensating the contribution of the capacitive load to circuit instability.
This capacitive load compensation technique uses an isolation resistor that compensates the circuit by
adding a zero to cancel the pole from the output impedance and capacitive load. Refer to the TI Precision
Labs - Op Amps: Stability 5 video for detailed information on this technique.
The design steps for the Riso method follow:
1. Use TINA-TI™ to find the zero frequency, fZERO, where AOL_Loaded = 20 dB (example shown in Figure 37).
Figure 37. Example of fZERO, Where AOL_Loaded = 20 dB
2. Calculate Riso to set the zero at fZERO – this will yield between 60° and 90° of phase margin
1
Riso =
2p ´ fZERO ´ CLoad
where
•
•
Riso = R3
CLoad = C4
(25)
While the Riso circuit is both simple to implement and design, it has a big disadvantage in precision
circuits. The voltage drop from Riso is dependent on the output current or output load, and may be
significant compared to the desired signal.
The second capacitive load compensation technique uses the Riso with dual-feedback stability
compensation method. The Riso dual-feedback circuit solves the voltage drop disadvantage of the
previously stated Riso. Refer to the TI Precision Labs - Op Amps: Stability 6 video for detailed information
on this technique.
Design steps for the Riso method follow:
1. Riso using Method 1: Riso techniques
2. Set R1: R1 ≥ (Riso × 100)
6Riso ´ CLoad
10Riso ´ CLoad
£ C1 £
R1
R1
Using this range ensures that the two feedback paths, R2 and C3, will never create a resonance that would
cause instability. Smaller values of C3 will result in faster settling time at the expense of overshoot for
certain load ranges. While the Riso dual-feedback circuit solves the dc accuracy issue with the Riso circuit, it
has some disadvantages as well. The disadvantage of this method is that the circuit is not as tolerant to
changes in the output capacitance and can quickly become unstable. Therefore, the Riso dual-feedback
circuit is best for situations where the output capacitance is known and will not vary significantly. This
method generally results in a slower settling time than the Riso circuit as well.
3. Set C1:
22
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The PCB layout of the top layer of the Riso dual-feedback amplifier circuit configuration is displayed in
Figure 38
Figure 38. Riso Dual-Feedback Top Layer
The PCB layout of the bottom layer of the Riso dual-feedback amplifier circuit configuration is displayed in
Figure 39.
Figure 39. Riso Dual-Feedback Bottom Layer
3.12 Dual-Supply, Non-Inverting Amplifier
Figure 40 shows the schematic for the dual-supply, non-inverting amplifier circuit configuration.
Figure 40. Dual-Supply, Non-Inverting Amplifier Schematic
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The non-inverting op-amp configuration takes an input signal that is applied directly to the high impedance
non-inverting input terminal and outputs a signal that is the same polarity as the input signal. The load
resistance for this topology is the sum of R1 and R2. The values of the resistors in the feedback network
will determine the amount of gain to amplify the input signal.
Equation 26 displays the transfer function of the dual-supply, non-inverting amplifier circuit configuration
shown in Figure 40.
æ
R ö
Vout = ç 1 + 1 ÷ Vin
è R2 ø
(26)
Capacitor C3 provides the option to filter the output. The cutoff frequency of the filter can be calculated
using Equation 27.
1
fc =
2p ´ R1 ´ C3
(27)
The PCB layout of the top layer of the dual-supply, non-inverting amplifier circuit configuration is displayed
in Figure 41
Figure 41. Dual-Supply, Non-Inverting Amplifier Top Layer
The PCB layout of the bottom layer of the dual-supply, non-inverting amplifier circuit configuration is
displayed in Figure 42.
Figure 42. Dual-Supply, Non-Inverting Amplifier Bottom Layer
24
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3.13 Dual-Supply, Inverting Amplifier
Figure 43 shows the schematic for the dual-supply, inverting amplifier circuit configuration.
Figure 43. Dual-Supply, Inverting Amplifier Schematic
The inverting op-amp configuration takes an input signal that is applied directly to the inverting input
terminal and outputs a signal that is the opposite polarity as the input signal. The benefit of this topology is
that it avoids common mode limitations. The load resistance for this topology is equal to R2. The values of
the resistors in the feedback network will determine the amount of gain to amplify the input signal.
Equation 28 displays the transfer function for the dual-supply, inverting amplifier circuit configuration
shown in Figure 43.
R
Vout = - 1 Vin
R2
(28)
Capacitor C3 provides the option to filter the output. The cutoff frequency of the filter can be calculated
using Equation 29.
1
fc =
2p ´ R1 ´ C3
(29)
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The PCB layout of the top layer of the dual-supply, inverting amplifier circuit configuration is displayed in
Figure 44.
Figure 44. Dual-Supply, Inverting Amplifier Top Layer
The PCB layout of the bottom layer of the dual-supply, inverting amplifier circuit configuration is displayed
in Figure 45.
Figure 45. Dual-Supply, Inverting Amplifier Bottom Layer
26
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Connections
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4
Connections
This section provides a description for each connection available on the EVM.
4.1
Inputs and Outputs
The input/output connection slots were designed to fit the following connections: vertical SMA, horizontal
SMA, wires, or through-hole test points. Examples of these four connectors are shown in this section.
The SMA recommended for this board is TE Connectivity part number 5-1814400-1.
Figure 46 shows SMA vertical connectors attached to both the input and output terminal.
Figure 46. SMA Vertical Connectors
Figure 47 shows SMA horizontal connectors attached to the input signal terminal.
Figure 47. SMA Horizontal Connectors
Figure 48 shows a wire attached to the input and output terminal.
Figure 48. Wire Connections
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Connections
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Figure 49 shows a through-hole test point connector attached to the output and Vref terminal.
Figure 49. Through-Hole Test Points
The input and output connections can also be accessed from the header strip. The input connections are
labeled IN+ and IN- for the non-inverting and inverting inputs, respectively. The output connection is
labeled VOUT. An example highlighting the input and output is shown in Figure 50.
Figure 50. Input and Output Pins in Terminal Area
28
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4.2
Power
This EVM features both dual- and single-supply, op-amp configurations. Power can only be applied using
the header pins located at the top and bottom of the PCB. The positive supply is labeled V+, the negative
supply is labeled V–, and ground is labeled GND. As an alternative, wire can be used in place of the
included terminals strips to power the board directly. Figure 51 shows an all-wire assembly for a multiple
feedback filter configuration.
Figure 51. Wire Alternative for Terminal Area
4.3
Enable and Disable Feature
The DIYAMP-SOIC-EVM provides a means to test the shutdown feature for op-amp devices equipped
with a shutdown pin. The access to the shutdown pin, labeled SD, is located on the terminal area.
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Bill of Materials and Reference
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5
Bill of Materials and Reference
5.1
Bill of Materials
Table 7 lists the bill of materials.
Table 7. Bill of Materials
Designator
5.2
QTY Value Description
Package
Reference
Part Number
Manufacturer
PCB
1
Printed-Circuit Board
PA031
Any
TS1, TS2
2
Header, 2.54mm,32x1,Gold,TH
TS-132-G-AA
Samtec
Reference
1.
2.
3.
4.
5.
Comparator with Hysteresis Reference Design (TIDU020)
TI Precision Labs Training https://training.ti.com/ti-precision-labs-op-amps
Analysis of the Sallen-Key Architecture (SLOA024)
AC Coupled, Single-Supply, Inverting and Non-inverting Amplifier Reference Design (TIDU871)
FilterPro Design Tool
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2017) to A Revision ....................................................................................................... Page
•
•
30
Added two circuits to the List of Circuits on the EVM section. ...................................................................... 3
Expanded user's guide beginning with the Hardware Setup section. .............................................................. 4
Revision History
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