DLP2010NIRFQJ

DLP2010NIR DLPS119B – DECEMBER 2018 – REVISED MAY 2022 DLP2010NIR (.2 WVGA Near-Infrared DMD) 1 Features 2 Applications • • • • • • 0.2-inch (5.29-mm) Diagonal Micromirror Array – 854 × 480 Array of Aluminum Micrometer-Sized Mirrors, in an Orthogonal Layout – 5.4-µm Micromirror Pitch – ±17° Micromirror Tilt (Relative to Flat Surface) – Side Illumination for Optimal Efficiency and Optical Engine Size Highly Efficient Steering of NIR light – Window Transmission Efficiency 96% Nominal (700 to 2000 nm, Single Pass Through Two Window Surfaces) – Window Transmission Efficiency 90% Nominal (2000 to 2500 nm, Single Pass Through Two Window Surfaces) – Polarization Independent Aluminum Micromirrors Dedicated DLPC150/DLPC3470 Controllers for Reliable Operation – Binary Pattern Rates up to 2880 Hz – Pattern Sequence Mode for Control over Each Micromirror in Array Dedicated Power Management Integrated Circuit (PMIC) DLPA2000 or DLPA2005 for Reliable Operation 15.9-mm × 5.3-mm × 4-mm Body Size for Portable Instruments Spectrometers (Chemical Analysis): – Portable Process Analyzers – Portable Equipment Compressive Sensing (Single Pixel NIR Cameras) 3D Biometrics Machine Vision Infrared Scene Projection Microscopes Laser Marking Optical Choppers Optical Networking • • • • • • • • 3 Description The DLP2010NIR digital micromirror device (DMD) acts as a spatial light modulator (SLM) to steer nearinfrared (NIR) light and create patterns with speed, precision, and efficiency. Featuring high resolution in a compact form factor, the DLP2010NIR DMD is often combined with a grating single element detector to replace expensive InGaAs linear arraybased detector designs, leading to high performance, cost-effective portable NIR Spectroscopy solutions. The DLP2010NIR DMD enables wavelength control and programmable spectrum and is well suited for low power mobile applications such as 3D biometrics, facial recognition, skin analysis, material identification and chemical sensing. ™ PART NUMBER(1) DLP2010NIR (1) DLPC150 Display Controller 600-MHz SubLVDS DDR Interface FQJ (40) VOFFSET D_P(1) D_N(1) VRESET D_P(2) D_N(2) D_P(3) D_N(3) LS_WDATA LS_CLK LS_RDATA DMD_DEN_ARSTZ BODY SIZE (NOM) 15.9-mm × 5.3- mm For all available packages, see the orderable addendum at the end of the data sheet. D_P(0) D_N(0) DCLK_P DCLK_N 120-MHz SDR Interface PACKAGE VBIAS DLP2010 DMD or DLP2010NIR DMD DLPA2000 DLPA2005 (PMIC and LED Driver) Digital Micromirror Device VDDI VDD VSS (System signal routing omitted for clarity) Figure 3-1. Simplified Application An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 6 6.1 Absolute Maximum Ratings ....................................... 6 6.2 Storage Conditions..................................................... 6 6.3 ESD Ratings............................................................... 7 6.4 Recommended Operating Conditions.........................7 6.5 Thermal Information....................................................9 6.6 Electrical Characteristics.............................................9 6.7 Timing Requirements................................................ 10 6.8 Switching Characteristics .........................................15 6.9 System Mounting Interface Loads............................ 15 6.10 Physical Characteristics of the Micromirror Array... 17 6.11 Micromirror Array Optical Characteristics............... 18 6.12 Window Characteristics.......................................... 19 6.13 Chipset Component Usage Specification............... 19 6.14 Typical Characteristics............................................ 20 7 Detailed Description......................................................21 7.1 Overview................................................................... 21 7.2 Functional Block Diagram......................................... 21 7.3 Feature Description...................................................22 7.4 Device Functional Modes..........................................22 7.5 Optical Interface and System Image Quality Considerations............................................................ 22 7.6 Micromirror Array Temperature Calculation.............. 23 7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 24 8 Application and Implementation.................................. 26 8.1 Application Information............................................. 26 8.2 Typical Application.................................................... 26 9 Power Supply Recommendations................................29 9.1 Power Supply Power-Up Procedure ........................ 29 9.2 Power Supply Power-Down Procedure ....................29 9.3 Power Supply Sequencing Requirements................ 30 10 Layout...........................................................................32 10.1 Layout Guidelines................................................... 32 10.2 Layout Example...................................................... 32 11 Device and Documentation Support..........................34 11.1 Device Support........................................................34 11.2 Related Links.......................................................... 34 11.3 Receiving Notification of Documentation Updates.. 34 11.4 Support Resources................................................. 35 11.5 Trademarks............................................................. 35 11.6 Electrostatic Discharge Caution.............................. 35 11.7 Glossary.................................................................. 35 12 Mechanical, Packaging, and Orderable Information.................................................................... 35 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (November 2021) to Revision B (May 2022) Page • Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 6 • Updated Micromirror Array Optical Characteristics ......................................................................................... 18 • Added Third-Party Products Disclaimer ...........................................................................................................34 Changes from Revision * (December 2018) to Revision A (November 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated |TDELTA| MAX from 30°C to 15°C..........................................................................................................7 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 5 Pin Configuration and Functions Figure 5-1. FQJ Package. 40-Pin CLGA. Bottom View. PIN NAME NO. TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET TRACE LENGTH(2) (mm) DATA INPUTS, SUBLVDS INTERFACE D_N(0) G4 I SubLVDS Double Input data pair 0, negative 7.03 D_P(0) G3 I SubLVDS Double Input data pair 0, positive 7.03 D_N(1) G8 I SubLVDS Double Input data pair 1, negative 7.03 D_P(1) G7 I SubLVDS Double Input data pair 1, positive 7.03 D_N(2) H5 I SubLVDS Double Input data pair 2, negative 7.02 D_P(2) H6 I SubLVDS Double Input data pair 2, positive 7.02 D_N(3) H1 I SubLVDS Double Input data pair 3, negative 7.00 D_P(3) H2 I SubLVDS Double Input data pair 3, positive 7.00 DCLK_N H9 I SubLVDS Double Clock, negative 7.03 DCLK_P H10 I SubLVDS Double Clock, positive 7.03 CONTROL INPUTS, LPSDR INTERFACE Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 3 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 PIN NAME NO. TYPE SIGNAL DATA RATE DESCRIPTION PACKAGE NET TRACE LENGTH(2) (mm) Active low asynchronous DMD reset signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode. 5.72 DMD_DEN_ARSTZ G12 I LPSDR (1) LS_CLK G19 I LPSDR Single Clock for low-speed interface 3.54 LS_WDATA G18 I LPSDR Single Write data for low-speed interface 3.54 LS_RDATA G11 O LPSDR Single Read data for low-speed interface 8.11 H17 Power Supply voltage for micromirror positive bias level POWER VBIAS (3) VOFFSET (3) H13 Power Supply voltage for high voltage CMOS (HVCMOS) core logic. Includes: Supply voltage for stepped high level at micromirror address electrodes and supply voltage for offset level at micromirrors. VRESET (3) H18 Power Supply voltage for micromirror negative reset level VDD (3) G20 Power VDD H14 Power VDD H15 Power VDD H16 Power VDD H19 Power VDD H20 Power VDDI (3) G1 Power VDDI G2 Power VDDI G5 Power VDDI G6 Power VSS (3) G9 Power VSS G10 Power VSS G13 Power VSS G14 Power VSS G15 Power VSS G16 Power VSS G17 Power VSS H3 Power VSS H4 Power VSS H7 Power VSS H8 Power VSS H11 Power VSS H12 Power Supply voltage for low voltage CMOS (LVCMOS) core logic. Includes supply voltage for LPSDR inputs and supply voltage for normal high level at micromirror address electrodes. Supply voltage for SubLVDS receivers Ground. Common return for all power. RESERVED 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 PIN NAME NO. TYPE SIGNAL DATA RATE PACKAGE NET TRACE LENGTH(2) (mm) DESCRIPTION No connect A2, A3, A4, A5, A6 A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18, A19 Reserved pins. For proper device operation, leave these pins unconnected. No connect B2, B3, B17, B18 Reserved pins. For proper device operation, leave these pins unconnected. No connect C2, C3, C17, C18 Reserved pins. For proper device operation, leave these pins unconnected. No connect D2, D3, D17, D18 Reserved pins. For proper device operation, leave these pins unconnected. No connect E2, E3, E17, E18 Reserved pins. For proper device operation, leave these pins unconnected. No connect F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19 Reserved pins. For proper device operation, leave these pins unconnected. (1) (2) (3) Low speed interface is LPSDR and adheres to the electrical characteristics and AC/DC operating conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B. Net trace lengths inside the package: Relative dielectric constant for the FQJ ceramic package is 9.8. Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns. Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm. The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 5 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 6 Specifications 6.1 Absolute Maximum Ratings (see (1)) –0.5 2.3 V VDDI Supply voltage for SubLVDS receivers(2) –0.5 2.3 V VOFFSET Supply voltage for HVCMOS and micromirror electrode(2) (3) –0.5 10.6 V –0.5 19 V –15 0.3 V Supply voltage for micromirror electrode bias circuits (2) 0.3 V |VBIAS–VOFFSET| Supply voltage delta (absolute value)(5) 11 V value)(6) 34 V –0.5 VDD + 0.5 V Input voltage for other inputs SubLVDS(2) (7) –0.5 VDDI + 0.5 V |VID| SubLVDS input differential voltage (absolute value)(7) 810 mV IID SubLVDS input differential current 8.1 mA ƒclock Clock frequency for low speed interface LS_CLK 130 MHz ƒclock Clock frequency for high speed interface DCLK 620 MHz –20 90 °C –40 90 °C Dew point (operating and non-operating) 81 °C Absolute Temperature delta between any point on the window edge and the ceramic test point TP1 (9) 30 °C |TDELTA| (3) (4) (5) (6) (7) (8) (9) Supply voltage delta (absolute Input voltage for other inputs LPSDR(2) Environmental TDP (2) (2) Supply voltage delta (absolute value)(4) TARRAY and TWINDOW (1) Supply voltage for micromirror electrode reset circuit |VDDI–VDD| |VBIAS–VRESET| Clock frequency UNIT Supply voltage for LVCMOS core logic and LPSDR low speed interface(2) VRESET Input pins MAX VDD Supply voltage VBIAS Input voltage MIN Temperature – operational (8) Temperature – non-operational (8) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET. VOFFSET supply transients must fall within specified voltages. Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw. Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw. Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw. This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors. The highest temperature of the active array (as calculated by the Section 7.6), or of any point along the Window Edge as defined in href="Micromirror-Array-Temperature-Calculation-DLPS0008740.dita#DLPS0008740/DLPS0001803"/>. The locations of thermal test points TP2 and TP3 in href="Micromirror-Array-Temperature-Calculation-DLPS0008740.dita#DLPS0008740/DLPS0001803"/> are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that test point should be used. Temperature delta is the highest difference from the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 19. The window test points TP2 and TP3 shown in Figure 19 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used. 6.2 Storage Conditions Applicable for the DMD as a component or non-operating in a system. TDMD 6 DMD storage temperature Submit Document Feedback MIN MAX UNIT –40 85 °C Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 MIN Average dew point temperature, (non-condensing)(1) TDP-AVG (non-condensing)(2) TDP-ELR Elevated dew point temperature range, CTELR Cumulative time in elevated dew point temperature range (1) (2) 28 MAX UNIT 24 °C 36 °C 6 Months The average over time (including storage and operating) that the device is not in the elevated dew point temperature range. Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative time of CTELR. 6.3 ESD Ratings V(ESD) (1) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) VALUE UNIT ±1000 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.4 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted)(1) (2) SUPPLY VOLTAGE MIN NOM MAX UNIT RANGE(3) VDD Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface 1.65 1.8 1.95 V VDDI Supply voltage for SubLVDS receivers 1.65 1.8 1.95 V VOFFSET Supply voltage for HVCMOS and micromirror electrode(4) 9.5 10 10.5 V VBIAS Supply voltage for mirror electrode VRESET Supply voltage for micromirror electrode 17.5 18 18.5 V –14.5 –14 –13.5 V |VDDI–VDD| Supply voltage delta (absolute value)(5) 0.3 V |VBIAS–VOFFSET| Supply voltage delta (absolute value)(6) 10.5 V value)(7) 33 V |VBIAS–VRESET| Supply voltage delta (absolute OUTPUT TERMINALS IOH High-level output current at Voh = 0.8 × VDD –30 mA IOL Low-level output current at Vol = 0.2 × VDD 30 mA CLOCK FREQUENCY ƒclock Clock frequency for low speed interface LS_CLK(8) 108 120 MHz ƒclock Clock frequency for high speed interface DCLK(9) 300 600 MHz 44% 56% Duty cycle distortion DCLK SUBLVDS INTERFACE(9) |VID| SubLVDS input differential voltage (absolute value) Figure 6-8, Figure 6-9 150 250 VCM Common mode voltage Figure 6-8, Figure 6-9 700 900 VSUBLVDS SubLVDS voltage Figure 6-8, Figure 6-9 575 ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω ZIN Internal differential termination resistance Figure 6-10 80 100 120 Ω 100-Ω differential PCB trace 6.35 Line differential impedance (PWB/trace) 61.2 350 mV 1100 mV 1225 mV 152.4 mm 74.8 Ω LPSDR INTERFACE(10) ZLINE 68 ENVIRONMENTAL Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 7 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 MIN TARRAY Array temperature – long-term operational(11) (12) (13) Array temperature – short-term operational, 25 hr max(13) (14) Array temperature – short-term operational, 500hr max (13) (14) Array temperature – short-term operational, 500hr max (13) (14) MAX 40 to 70(11) –20 -10 -10 0 70 75 UNIT °C TWINDOW Window temperature – operational(15) (17) 90 °C |TDELTA| Absolute temperature difference between any point on the window edge and the ceramic test point TP1(16) 15 °C CTELR Cumulative time in elevated dew point temperature range 6 Months ILLUV Illumination, wavelength < 420 nm 0.68 mW/cm2 ILLVIS Illumination wavelengths between 420 nm and 700 nm ILLNIR Illumination, wavelength 700 - 2500 nm 2000 mW/cm2 ILLIR Illumination, wavelength > 2500 nm 10 mW/cm2 55 deg ILLθ (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) 8 NOM 0 Illumination marginal ray angle(17) Thermally limited Recommended Operating Conditions are applicable after the DMD is installed in the final product. The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits. All voltage values are with respect to the ground pins (VSS). VOFFSET supply transients must fall within specified max voltages. To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than the specified limit. LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands. Refer to the SubLVDS timing requirements in Section 6.7. Refer to the LPSDR timing requirements in Section 6.7. Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Section 7.7 for a definition of micromirror landed duty cycle. Long-term is defined as the usable life of the device. The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 7-1 and the package thermal resistance using Section 7.6. Short-term is the total cumulative time over the useful life of the device. Window temperature is the highest temperature on the window edge shown in Figure 7-1. The locations of thermal test points TP2 and TP3 in Figure 7-1 are intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, a test point should be added to that location. Temperature delta is the highest difference from the ceramic test point 1 (TP1) and anywhere on the window edge shown in Figure 7-1. The window test points TP2 and TP3 shown in Figure 7-1 are intended to result in the worst case delta temperature. If a particular application causes another point on the window edge to result in a larger delta temperature, that point should be used. The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com Max Recommended Array Temperature – Operational (°C) DLPS119B – DECEMBER 2018 – REVISED MAY 2022 80 70 60 50 40 30 0/100 5/95 10/90 15/85 20/80 25/75 30/70 35/65 40/60 45/55 50/50 100/0 95/5 90/10 85/15 80/20 75/25 70/30 65/35 60/40 55/45 D001 Micromirror Landed Duty Cycle Figure 6-1. Maximum Recommended Array Temperature – Derating Curve 6.5 Thermal Information DLP2010NIR FQJ (CLGA) THERMAL METRIC (1) UNIT 40 PINS MIN TYP MAX Thermal resistance Active area to test point TP1(1) (1) 7.9 °C/W The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device. Over operating free-air temperature range (unless otherwise noted)(10) 6.6 Electrical Characteristics PARAMETER TEST CONDITIONS(2) MIN TYP MAX UNIT CURRENT IDD Supply current: VDD(3) (5) IDDI Supply current: VDDI(3) (5) IOFFSET Supply current: VOFFSET(4) (6) IBIAS Supply current: VBIAS(4) (6) IRESET Supply current: VRESET(6) VDD = 1.95 V VDD = 1.8 V 34.7 27.5 VDDI = 1.95 V VDD = 1.8 V 9.4 6.6 VOFFSET = 10.5 V VOFFSET = 10 V 1.7 0.9 VBIAS = 18.5 V VBIAS = 18 V 0.4 0.2 VRESET = –14.5 V VRESET = –14 V 2 1.2 mA mA mA mA mA POWER(1) PDD Supply power dissipation: VDD(3) (5) PDDI Supply power dissipation: VDDI(3) (5) POFFSET Supply power dissipation: VOFFSET(4) (6) VDD = 1.95 V VDD = 1.8 V 67.7 49.5 VDDI = 1.95 V VDD = 1.8 V 18.3 11.9 VOFFSET = 10.5 V VOFFSET = 10 V 17.9 9 mW mW mW Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 9 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 6.6 Electrical Characteristics (continued) TEST CONDITIONS(2) PARAMETER PBIAS Supply power dissipation: VBIAS(4) (6) PRESET Supply power dissipation: VRESET(6) PTOTAL Supply power dissipation: Total MIN TYP VBIAS = 18.5 V MAX 7.4 VBIAS = 18 V 3.6 VRESET = –14.5 V 29 VRESET = –14 V 16.8 90.8 140.3 UNIT mW mW mW LPSDR INPUT(7) VIH(DC) DC input high voltage(9) VIL(DC) DC input low voltage(9) voltage(9) VIH(AC) AC input high VIL(AC) AC input low voltage(9) ∆VT Hysteresis ( VT+ – VT– ) Figure 6-10 IIL Low–level input current VDD = 1.95 V; VI = 0 V IIH High–level input current VDD = 1.95 V; VI = 1.95 V 0.7 × VDD VDD + 0.3 V –0.3 0.3 × VDD V 0.8 × VDD VDD + 0.3 V –0.3 0.2 × VDD V 0.1 × VDD 0.4 × VDD –100 V nA 100 nA LPSDR OUTPUT(8) VOH DC output high voltage IOH = –2 mA 0.8 × VDD V VOL DC output low voltage IOL = 2 mA 0.2 × VDD V Input capacitance LPSDR ƒ = 1 MHz 10 pF Input capacitance SubLVDS ƒ = 1 MHz 20 pF COUT Output capacitance ƒ = 1 MHz 10 pF CRESET Reset group capacitance ƒ = 1 MHz; (480 × 108) micromirrors 113 pF CAPACITANCE CIN 95 (1) (2) (3) (4) (5) (6) (7) (8) (9) The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, VRESET. All voltage values are with respect to the ground pins (VSS). To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit. Supply power dissipation based on non–compressed commands and data. Supply power dissipation based on 3 global resets in 200 µs. LPSDR specifications are for pins LS_CLK and LS_WDATA. LPSDR specification is for pin LS_RDATA. Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B. (10) Device electrical characteristics are over Section 6.4 unless otherwise noted. Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted. 6.7 Timing Requirements MIN NOM MAX UNIT 1 3 V/ns (70% to 20%) × VDD, Figure 6-3 1 3 V/ns (20% to 80%) × VDD, Figure 6-3 0.25 (80% to 20%) × VDD, Figure 6-3 0.25 LPSDR Rise slew rate(1) tR rate(1) tV Fall slew tR Rise slew rate(2) rate(2) (30% to 80%) × VDD, Figure 6-3 tF Fall slew tC Cycle time LS_CLK, Figure 6-2 tW(H) Pulse duration LS_CLK high 50% to 50% reference points,Figure 6-2 tW(L) Pulse duration LS_CLK low 50% to 50% reference points, Figure 6-2 tSU Setup time tH Hold time tWINDOW 10 Window time(1) (4) 7.7 V/ns V/ns 8.3 ns 3.1 ns 3.1 ns LS_WDATA valid before LS_CLK ↑, Figure 6-2 1.5 ns LS_WDATA valid after LS_CLK ↑, Figure 6-2 1.5 ns 3 ns Setup time + Hold time, Figure 6-2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 6.7 Timing Requirements (continued) MIN tDERATING NOM MAX 0.35 UNIT Window time derating(1) (4) For each 0.25 V/ns reduction in slew rate below 1 V/ns, Figure 6-5 ns tR Rise slew rate 20% to 80% reference points, Figure 6-4 tF Fall slew rate 80% to 20% reference points, Figure 6-4 tC Cycle time LS_CLK, Figure 6-6 tW(H) Pulse duration DCLK high 50% to 50% reference points, Figure 6-6 0.71 ns tW(L) Pulse duration DCLK low 50% to 50% reference points, Figure 6-6 0.71 ns tSU Setup time D(0:3) valid before DCLK ↑ or DCLK ↓, Figure 6-6 tH Hold time D(0:3) valid after DCLK ↑ or DCLK ↓, Figure 6-6 tWINDOW Window time Setup time + Hold time, Figure 6-6,Figure 6-7 tLVDS- Power-up receiver(3) SubLVDS ENABLE+REFGEN (1) (2) (3) (4) 0.7 1 V/ns 0.7 1 V/ns 1.61 1.67 ns 3 ns 2000 ns Specification is for LS_CLK and LS_WDATA pins. Refer to LPSDR input rise slew rate and fall slew rate in Figure 6-3. Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-3. Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding. Window time derating example: 0.5-V/ns slew rate increases the window time by 0.7 ns, from 3 to 3.7 ns. tc tw(H) LS_CLK 50% tw(L) 50% 50% th tsu LS_ WDATA 50% 50% twindow Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR) JESD209B. Figure 6-2. LPSDR Switching Parameters Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 11 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 LS_CLK, LS_WDATA DMD_DEN_ARSTZ 1.0 * VDD 1.0 * VDD 0.8 * VDD 0.7 * VDD VIH(AC) VIH(DC) 0.3 * VDD 0.2 * VDD VIL(DC) VIL(AC) 0.8 * VDD 0.2 * VDD 0.0 * VDD 0.0 * VDD tr tf tr tf Figure 6-3. LPSDR Input Rise and Fall Slew Rate VDCLK_P , VDCLK_N VD_P(0:3) , VD_N(0:3) 1.0 * VID 0.8 * VID VCM 0.2 * VID 0.0 * VID tr tf Figure 6-4. SubLVDS Input Rise and Fall Slew Rate VIH MIN LS_CLK Midpoint VIL MAX tSU tH VIH MIN LS_WDATA Midpoint VIL MAX tWINDOW VIH MIN LS_CLK Midpoint VIL MAX tDERATING tSU tH VIH MIN LS_WDATA Midpoint VIL MAX tWINDOW Figure 6-5. Window Time Derating Concept 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 tc tw(L) DCLK _ P DCLK _ N tw(H) 50% 50% 50% th tsu D_P (0:3) D_N(0:3) 50% 50% twindow Figure 6-6. SubLVDS Switching Parameters High Speed Training Scan Window tc DCLK _ P DCLK _ N ¼ tc ¼ tc D_P (0:3) D_N(0:3) Note: Refer to High-Speed Interface for details. Figure 6-7. High-Speed Training Scan Window (VIP + V IN) / 2 DCLK _P , D_P(0:3) SubLVDS Receiver VID DCLK _N , D_N(0:3) VCM VIP VIN Figure 6-8. SubLVDS Voltage Parameters Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 13 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 1.225V V SubLVDS max = V CM max + | 1/2 * V ID max | VCM VID VSubLVDS min = VCM min – | 1/2 * VID max | 0.575V Figure 6-9. SubLVDS Waveform Parameters DCLK _P , D_P(0:3) ESD Internal Termination SubLVDS Receiver DCLK _N , D_N(0:3) ESD Figure 6-10. SubLVDS Equivalent Input Circuit Not to Scale VIH VT+ Δ VT VT- VIL LS_CLK LS_WDATA Figure 6-11. LPSDR Input Hysteresis LS_CLK LS_WDATA Stop Start tPD LS_RDATA Acknowledge Figure 6-12. LPSDR Read Out 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 Data Sheet Timing Reference Point Device Pin Output Under Test Tester Channel CL See Timing for more information. Figure 6-13. Test Load Circuit for Output Propagation Measurement 6.8 Switching Characteristics Over operating free-air temperature range (unless otherwise noted)(1) PARAMETER TEST CONDITIONS Output propagation, Clock to Q, rising edge of LS_CLK input to LS_RDATA output. Figure 6-12 tPD TYP CL = 45 pF Slew rate, LS_RDATA MAX 15 0.5 Output duty cycle distortion, LS_RDATA (1) MIN UNIT ns V/ns 40% 60% Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted. 6.9 System Mounting Interface Loads PARAMETER MIN NOM MAX UNIT Maximum system mounting interface load to be applied to the: • Connector area (see Figure 6-14) • DMD mounting area uniformly distributed over 4 areas (see Figure 6-14) 45 N 100 N Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 15 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 šµu Z [ Œ (3 places) šµu Z [ Œ (1 place) (4 ‰o • }‰‰}•]š DMD Mounting Area šµu• Z [ v Z [) Connector Area Figure 6-14. System Interface Loads 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 6.10 Physical Characteristics of the Micromirror Array ε UNIT Number of active columns See Figure 6-15 854 micromirrors Number of active rows See Figure 6-15 480 micromirrors Micromirror (pixel) pitch See Figure 6-16 5.4 µm Micromirror active array width Micromirror pitch × number of active columns; see Figure 6-15 4.6116 mm Micromirror active array height Micromirror pitch × number of active rows; see Figure 6-15 2.592 mm 20 micromirrors/side Micromirror active border (1) VALUE Pond of micromirror (POM)(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM. These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF. Not To Scale Width Mirror Mirror Mirror Mirror 479 478 477 476 Height Illumination DMD Active Mirror Array 854 Mirrors * 480 Mirrors 3 2 1 0 Mirror Mirror Mirror Mirror Mirror Mirror Mirror Mirror 850 851 852 853 0 1 2 3 Mirror Mirror Mirror Mirror Figure 6-15. Micromirror Array Physical Characteristics ε ε ε ε Figure 6-16. Mirror (Pixel) Pitch Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 17 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 6.11 Micromirror Array Optical Characteristics PARAMETER TEST CONDITIONS Micromirror tilt angle DMD landed Micromirror tilt angle tolerance(1) Micromirror crossover time Typical Performance 1.5 Micromirror switching time Typical Performance 6 Gray 10 Screen (10) 0 (10) 1 Unstable pixel(s) in active area (14) Any Screen (8) (9) (10) (11) (12) (13) (14) 18 1.4 270 Bright pixel(s) in the POM Gray 10 Screen Image (12) White Screen Dark pixel(s) in the active area performance(8) Adjacent pixel(s) (13) Any Screen UNIT degrees Landed OFF state (11) (7) 17 180 Bright pixel(s) in active area (9) (6) MAX Landed ON state Micromirror tilt direction(3) (7) (4) (5) NOM –1.4 (2) (4) (5) (6) (1) (2) (3) MIN state(1) degrees degrees 4 4 μs micromirrors 0 0 Measured relative to the plane formed by the overall micromirror array. Additional variation exists between the micromirror array and the package datums. When the micromirror array is landed (not parked), the tilt direction of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of 1 results in a micromirror landing in the ON State direction. A binary value of 0 results in a micromirror landing in the OFF State direction. Represents the landed tilt angle variation relative to the nominal landed tilt angle. Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices. For some applications, it is critical to account for the micromirror tilt angle variation in the overall system optical design. With some system optical designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some system optical designs, the micromirror tilt angle variation between devices may result in colorimetry variations, system efficiency variations or system contrast variations. Micromirror tilt direction is measured as in a typical polar coordinate system: measuring counter-clockwise from a 0° reference which is aligned with the +X Cartesian axis. Conditions of Acceptance: All DMD image quality returns will be evaluated using the following projected image test conditions: Test set degamma shall be linear Test set brightness and contrast shall be set to nominal The diagonal size of the projected image shall be a minimum of 20 inches The projections screen shall be 1X gain The projected image shall be inspected from a 38 inch minimum viewing distance The image shall be in focus during all image quality tests Bright pixel definition: A single pixel or mirror that is stuck in the ON position and is visibly brighter than the surrounding pixels Gray 10 screen definition: All areas of the screen are colored with the following settings: Red = 10/255 Green = 10/255 Blue = 10/255 POM definition: Rectangular border of off-state mirrors surrounding the active area Dark pixel definition: A single pixel or mirror that is stuck in the OFF position and is visibly darker than the surrounding pixels Adjacent pixel definition: Two or more stuck pixels sharing a common border or common point, also referred to as a cluster Unstable pixel definition: A single pixel or mirror that does not operate in sequence with parameters loaded into memory. The unstable pixel appears to be flickering asynchronously with the image Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 (0,479) (853,479) Incident Illumination Light Path Tilted Axis of Pixel Rotation On-State Landed Edge Off-State Landed Edge (853,0) (0,0) Off-State Light Path Figure 6-17. Landed Pixel Orientation and Tilt 6.12 Window Characteristics PARAMETER(3) MIN Window material designation Window refractive index NOM at wavelength 546.1 nm UNIT 1.5119 Window aperture(1) Illumination MAX Corning Eagle XG See (1) overfill(2) See (2) Window transmittance, single-pass through both surfaces and glass Minimum within the wavelength range 700 to 2000 nm. at 0° angle of incidence. 92 96 % Window transmittance, single-pass through both surfaces and glass Minimum within the wavelength range 2000 to 2500 nm. at 0° angle of incidence. 85 90 % (1) (2) (3) See the package mechanical characteristics for details regarding the size and location of the window aperture. The active area of the DLP2010NIR device is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The illumination optical system should be designed to limit light flux incident outside the active array to less than 10% of the average flux level in the active area. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may cause system performance degradation. See Optical Interface and System Image Quality Considerations for more information. 6.13 Chipset Component Usage Specification The DLP2010NIR is a component of one or more DLP chipsets. Reliable function and operation of the DLP2010NIR requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DLP DMD. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 19 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 Note TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously. 6.13.1 Software Requirements Note The DLP2010NIR DMD has mandatory software requirements. Refer to Software Requirements for TI DLP™Pico™ TRP Digital Micromirror Devices application report for additional information. Failure to use the specified software will result in failure at power up. 6.14 Typical Characteristics 100 95 Transmittance (%) 90 85 80 75 70 65 60 700 Nominal Minimum 900 1100 1300 1500 1700 1900 2100 2300 2500 Wavelength (nm) D001 Figure 6-18. DLP2010NIR DMD Window Transmittance 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 7 Detailed Description 7.1 Overview The DLP2010NIR is a 0.2 inch diagonal spatial light modulator designed for near-infrared applications. Pixel array size is 854 columns by 480 rows in a square grid pixel arrangement. The electrical interface is Sub Low Voltage Differential Signaling (SubLVDS) data. DLP2010NIR is one device in a chipset, which includes the DLP2010NIR DMD, the DLPC150/3470 controller and the DLPA200X (DLPA2000 or DLPA2005) PMIC. To ensure reliable operation, the DLP2010NIR DMD must always be used with a DLPC150/3470 controller and a DLPA200X PMIC. VSS VDD VDDI VOFFSET VBIAS VRESET D_P(0:3) D_N(0:3) DCLK_P DCLK_N 7.2 Functional Block Diagram High Speed Interface Misc Column Write Control Bit Lines (0,0) Voltage Generators Voltages SRAM Word Lines Row (479, 853) Control Column Read Control VSS VDD VOFFSET VBIAS VRESET LS_RDATA LS_WDATA LS_CLK DMD_DEN_ARSTZ Low Speed Interface Note Details omitted for clarity. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 21 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 7.3 Feature Description 7.3.1 Power Interface The power management IC, DLPA200X, contains 3 regulated DC supplies for the DMD reset circuitry: VBIAS, VRESET and VOFFSET, as well as the 2 regulated DC supplies for the DLPC150/3470 controller. 7.3.2 Low-Speed Interface The Low Speed Interface handles instructions that configure the DMD and control reset operation. LS_CLK is the low–speed clock, and LS_WDATA is the low speed data input. 7.3.3 High-Speed Interface The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed DDR transfer and compression techniques to save power and time. The high-speed interface is composed of differential SubLVDS receivers for inputs, with a dedicated clock. 7.3.4 Timing The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. Figure 6-13 shows an equivalent test load circuit for the output under test. Timing reference loads are not intended as a precise representation of any particular system environment or depiction of the actual load presented by a production test. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 7.4 Device Functional Modes DMD functional modes are controlled by the DLPC150/3470 controller. See the DLPC150/DLPC3470 controller data sheet or contact a TI applications engineer. 7.5 Optical Interface and System Image Quality Considerations Note TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously. 7.5.1 Optical Interface and System Image Quality TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters. Although it is not possible to anticipate every conceivable application, projector image quality and optical performance is contingent on compliance to the optical system operating conditions described in the following sections: 7.5.1.1 Numerical Aperture and Stray Light Control The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any other light path, including undesirable flat–state specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts in the display’s border and/or active area could occur. 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 7.5.1.2 Pupil Match TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border and/or active area, which may require additional system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle. 7.5.1.3 Illumination Overfill The active area of the device is surrounded by an aperture on the inside DMD window surface that masks structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the average flux level in the active area. Depending on the particular system’s optical architecture, overfill light may have to be further reduced below the suggested 10% level in order to be acceptable. 7.6 Micromirror Array Temperature Calculation Illumination Direction Off-state Light Figure 7-1. DMD Thermal Test Points Micromirror array temperature can be computed analytically from measurement points on the outside of the package, the ceramic package thermal resistance, the electrical power dissipation, and the illumination heat load. The relationship between micromirror array temperature and the reference ceramic temperature is provided by the following equations: TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC) (1) QARRAY = QELECTRICAL + QILLUMINATION (2) QILLUMINATION = (AILLUMINATION × PNIR X DMD absorption factor) (3) where • • TARRAY = Computed DMD array temperature (°C) TCERAMIC = Measured ceramic temperature (°C), TP1 location in Figure 7-1 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 23 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 • • • • • RARRAY–TO–CERAMIC = DMD package thermal resistance from array to outside ceramic (°C/W) specified in Section 6.5 QARRAY = Total DMD power; electrical, specified in Electrical Characteristics, plus absorbed (calculated) (W) QELECTRICAL = Nominal DMD electrical power dissipation (W), specified in Electrical Characteristics AILLUMINATION = Illumination area (assumes 83.7% on the active array and 16.3% overfill) PNIR = Illumination Power Density (W/cm2) Electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating frequencies. Refer to the specifications in Electrical Characteristics. Absorbed power from the illumination source is variable and depends on the operating state of the mirrors and the intensity of the light source. The DMD absorption constant of 0.42 assumes nominal operation with an illumination distribution of 83.7% on the DMD active array, and 16.3% on the DMD array border and window aperture. A sample calculation is detailed below: TCERAMIC = 35 °C, assumed system measurement; see Recommended Operating Conditions for specification limits PNIR= 2 W/cm2 QELECTRICAL = 0.0908 W; See the table notes in Recommended Operating Conditions for details. AILLUMINATION = 0.143 cm2 QARRAY = QELECTRICAL + (QILLUMINATION X DMD absoprtion factor) = 0.0908 W + (2 W/cm2 X 0.143 cm2 X 0.42) = 0.211 W TARRAY = 35 °C + (0.211 W × 7.9°C/W) = 36.67 °C 7.7 Micromirror Landed-On/Landed-Off Duty Cycle 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a percentage) that an individual micromirror is landed in the ON state versus the amount of time the same micromirror is landed in the OFF state. As an example, a landed duty cycle of 75/25 indicates that the referenced pixel is in the ON state 75% of the time and in the OFF state 25% of the time, whereas 25/75 would indicate that the pixel is in the ON state 25% of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time. Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other state (OFF or ON) is considered negligible and is thus ignored. Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages) nominally add to 100. 7.7.2 Landed Duty Cycle and Useful Life of the DMD Knowing the long-term average landed duty cycle (of the end product or application) is important because subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed duty cycle for a prolonged period of time can reduce the DMD’s usable life. Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical. 7.7.3 Landed Duty Cycle and Operational DMD Temperature Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s usable life. This is quantified in the de-rating curve shown in Figure 6-1. The importance of this curve is that: • • • 24 All points along this curve represent the same usable life. All points above this curve represent lower usable life (and the further away from the curve, the lower the usable life). All points below this curve represent higher usable life (and the further away from the curve, the higher the usable life). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at for a give long-term average Landed Duty Cycle. 7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being displayed by that pixel. For example, in binary pattern display with value '1' or when displaying pure-white on a given pixel for a given time period, that pixel will experience a 100/0 Landed Duty Cycle during that time period. Likewise, a binary pattern display with value '0' or when displaying pure-black, the pixel will experience a 0/100 Landed Duty Cycle. Table 7-1. Binary Pattern Mode Example: Binary Value and Landed Duty Cycle BINARY VALUE NOMINAL LANDED DUTY CYCLE 0 0/100 1 100/0 During a given period of time, the landed duty cycle of a given pixel can be calculated as follows: Landed Duty Cycle = ∑{Pattern[i]_Binary_Value} / {Total_Patterns} (4) where • Pattern[i]_Binary_Value represent a pixel's pattern and its corresponding binary value over all patterns in the pattern sequence: Total_Patterns. For example, assume a pattern sequence with three patterns using pixel x. In this sequence the first pattern has pixel x on, the second pattern has pixel x off, and the third pattern has pixel x off. Thus, the Landed Duty Cycle is 33%. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 25 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two directions, with the primary direction being into a projection or collection optic. Each application is derived primarily from the optical architecture of the system and the format of the data coming into the DLPC150/3470 controller. The new high tilt pixel in the side illuminated DMD increases device efficiency and enables a compact optical system. The DLP2010NIR DMD can be combined with a grating and single element detector to replace expensive InGaAs linear array detector designs, leading to high performance, cost-effective portable NIR Spectroscopy solutions. Applications of interest include machine vision systems, spectrometers, medical systems, skin analysis, material identification, chemical sensing, infrared projection, and compressive sensing. DMD power-up and power-down sequencing is strictly controlled by the DLPA2000 or DLPA2005. Refer to Power Supply Recommendations for power-up and power-down specifications. DLP2010NIR DMD reliability is only specified when used with DLPC150/3470 controller and DLPA2000 or DLPA2005 PMIC/LED Driver. 8.2 Typical Application A typical embedded system application using the DLPC150/3470 controller and DLP2010NIR is shown in Figure 8-1. In this configuration, the DLPC150/3470 controller supports a 24-bit parallel RGB input, typical of LCD interfaces, from an external source or processor. The DLPC150/3470 controller processes the digital input image and converts the data into the format needed by the DLP2010NIR. The DLP2010NIR steers light by setting specific micromirrors to the on position, directing light to the detector, while unwanted micromirrors are set to "off" position, directing light away from the detector. The microprocessor sends binary images to the DMD to steer specific wavelengths of light into the detector. The microprocessor uses an analog-to-digital converter to sample the signal received by the detector into a digital value. By sequentially selecting different wavelengths of light and capturing the values at the detector, the microprocessor can then plot a spectral response to the light. 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com Power Management On/Off + Charger DC_IN BAT – DLPS119B – DECEMBER 2018 – REVISED MAY 2022 2.3 to 5.5 V 1.8 V Other Supplies VIN SYSPWR VDD 1.1 V 1.1-V Reg 1.8 V 1.8S V LS_IN PROJ_ON PROJ_ON USB DLPA2000 or DLPA2005 PROJ_ON Detector ADC FLASH FLASH, SDRAM 4 SPI_0 SPI_1 4 PARKZ RESETZ INTZ Microprocessor HOST_IRQ Bluetooth Illumination Optics CMP_OUT Parallel RGB I/F (28) SD Card Current Sense CMP_PWM DLPC150 TRIG_OUT (2) RED BIAS, RST, OFS 3 LED_SEL(2) TRIG_IN Keypad VLED Thermistor I2C 1.8S V Sub-LVDS DATA LPSDR CTRL VIO VCC_INTF VCC_FLSH 1.1 V DLP2010NIR WVGA (WVGA DDR DMD DMD) Projection Optics VCORE ADC + Amplifier NIR Detector DLP® Chip Set Figure 8-1. Typical Application Diagram 8.2.1 Design Requirements All applications using DLP 0.2-inch WVGA chipset require the DLPC150/3470 controller, DLPA2000 or DLPA2005 PMIC, and DLP2010NIR DMD components for operation. The system also requires an external SPI flash memory device loaded with the DLPC150/3470 Configuration and Support Firmware. The chipset has several system interfaces and requires some support circuitry. The following interfaces and support circuitry are required for the DLP2010NIR: • • DMD Interfaces: – DLPC150/3470 to DLP2010NIR SubLVDS Digital Data – DLPC150/3470 to DLP2010NIR LPSDR Control Interface DMD Power: – DLPA2000 or DLPA2005 to DLP2010NIR VBIAS Supply – DLPA2000 or DLPA2005 to DLP2010NIR VOFFSET Supply – DLPA2000 or DLPA2005 to DLP2010NIR VRESET Supply – DLPA2000 or DLPA2005 to DLP2010NIR VDDI Supply – DLPA2000 or DLPA2005 to DLP2010NIR VDD Supply The illumination light that is applied to the DMD is typically from an infrared LED or lamp. 8.2.2 Detailed Design Procedure For connecting together the DLPC150/3470, the DLPA2005, and the DLP2010NIR DMD, see the TI DLP NIRscan Nano EVM reference design schematic. 8.2.3 Application Curve In a reflective spectroscopy application, a broadband light source illuminates a sample and the reflected light spectrum is dispersed onto the DLP2010NIR. A microprocessor in conjunction with the DLPC150/3470 controls individual DLP2010NIR micromirrors to reflect specific wavelengths of light to a single point detector. The microprocessor uses an analog-to-digital converter to sample the signal received by the detector into a digital Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 27 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 value. By sequentially selecting different wavelengths of light and capturing the values at the detector, the microprocessor can then plot a spectral response to the light. This systems allows the measurement of the collected light and derive the wavelengths absorbed by the sample. This process leads to the absorption spectrum shown in Figure 8-2. SPACE Figure 8-2. Sample DLP2010NIR Based Spectrometer Output 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 9 Power Supply Recommendations The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET. DMD power-up and power-down sequencing is strictly controlled by the DLPAxxxx device. Note For reliable operation of the DMD, the following power supply sequencing requirements must be followed. Failure to adhere to the prescribed power-up and power-down procedures may affect device reliability. VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during power-up and power-down operations. Failure to meet any of the below requirements will result in a significant reduction in the DMD’s reliability and lifetime. Refer to Figure 9-2. VSS must also be connected. 9.1 Power Supply Power-Up Procedure • • • • During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are applied to the DMD. During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended Operating Conditions. Refer to Table 9-1 and the Layout Example for power-up delay requirements. During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have settled at operating voltage. During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the requirements listed previously and in Figure 9-1. 9.2 Power Supply Power-Down Procedure • • • • • Power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground. During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement that the delta between VBIAS and VOFFSET must be within the specified limit shown in Recommended Operating Conditions (Refer to Note 2 for Figure 9-1). During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in Recommended Operating Conditions. During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS. Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements listed previously and in Figure 9-1. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 29 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 9.3 Power Supply Sequencing Requirements Mirror park sequence (4) VDD / VDDI VDD and VDDI VDD and VDDI VSS VSS VBIAS VBIAS VBIAS 9'' ” 9%,$6 < 6 V VSS VBIAS < 4 V ûV < Specification ûV < Specification (1)(2) VOFFSET 9'' ” 92))6(7 < 6 V VOFFSET VSS (2) VOFFSET VOFFSET < 4 V ûV < Specification(3) VSS VSS VRESET < 0.5 V VSS VSS VRESET > ±4 V VRESET VRESET VRESET VDD DMD_DEN_ARSTZ VDD VSS VSS Initialization LS_CLK LS_WDATA VSS D_P(0:3), D_N(0:3) DCLK_P, DCLK_N VSS VDD VDD VSS VID VSS t1 A. B. C. D. E. t2 t3 t4 Refer to Table 9-1 and Figure 9-2 for critical power-up sequence delay requirements. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down. Refer to Table 9-1 and Figure 9-2 for power-up delay requirements. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit shown in Recommended Operating Conditions. When system power is interrupted, the ASIC driver initiates hardware power-down that disables VBIAS, VRESET and VOFFSET after the Micromirror Park Sequence. Software power-down disables VBIAS, VRESET, and VOFFSET after the Micromirror Park Sequence through software control. Drawing is not to scale and details are omitted for clarity. Figure 9-1. Power Supply Sequencing Requirements (Power Up and Power Down) Table 9-1. Power-Up Sequence Delay Requirement PARAMETER MIN MAX Delay requirement from VOFFSET power up to VBIAS power up VOFFSET Supply voltage level during power–up sequence delay (see Figure 9-2) 6 V VBIAS Supply voltage level during power–up sequence delay (see Figure 9-2) 6 V 30 Submit Document Feedback 2 UNIT tDELAY ms Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com VOFFSET Voltage (V) DLPS119B – DECEMBER 2018 – REVISED MAY 2022 12 VOFFSET 8 9'' ” 92))6(7 ” 6 V 4 0 VSS tDELAY VBIAS VBIAS Voltage (V) 20 16 12 8 9'' ” 9%,$6 ” 6 V 4 0 VSS Time Note Refer to Table 9-1 for VOFFSET and VBIAS supply voltage levels during power-up sequence delay. Figure 9-2. Power-Up Sequence Delay Requirement Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 31 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 10 Layout 10.1 Layout Guidelines There are no specific layout guidelines for the DMD as typically DMD is connected using a board or board-toboard connector to a flex cable. For detailed layout guidelines refer to the layout design files. Some layout guideline for the flex cable interface with DMD are: • • • • • • • • Match lengths for the LS_WDATA and LS_CLK signals. Minimize vias, layer changes, and turns for the HS bus signals. Refer Figure 10-1. Minimum of 100-nF decoupling capacitor close to VBIAS. Capacitor C4 in Figure 10-2. Minimum of 100-nF decoupling capacitor close to VRESET. Capacitor C6 in Figure 10-2. Minimum of 220-nF decoupling capacitor close to VOFFSET. Capacitor C7 in Figure 10-2. Optional minimum 200- to 220-nF decoupling capacitor to meet the ripple requirements of the DMD. C5 in Figure 10-2. Minimum of 100-nF decoupling capacitor close to VCCI. Capacitor C1 in Figure 10-2. Minimum of 100-nF decoupling capacitor close to both groups of VCC pins, for a total of 200 nF for VCC. Capacitor C2/C3 in Figure 10-2. 10.2 Layout Example Figure 10-1. High-Speed (HS) Bus Connections 32 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 Figure 10-2. Power Supply Connections Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 33 DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.1.2 Device Nomenclature DLP2010 NIRA FQJ Package Type NIR DMD Device Descriptor Figure 11-1. Part Number Description 11.1.3 Device Markings Device Marking will include the human–readable character string GHJJJJK VVVV on the electrical connector. GHJJJJK is the lot trace code. VVVV is a 4 character encoded device part number GHJJJJKHVVVV Figure 11-2. DMD Marking 11.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 11-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY DLPC150 Click here Click here Click here Click here Click here DLPC3470 Click here Click here Click here Click here Click here DLPA2000 Click here Click here Click here Click here Click here DLPA2005 Click here Click here Click here Click here Click here 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 34 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR DLP2010NIR www.ti.com DLPS119B – DECEMBER 2018 – REVISED MAY 2022 11.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.5 Trademarks DLP™, Pico™, and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP2010NIR 35 PACKAGE OPTION ADDENDUM www.ti.com 28-Sep-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) DLP2010NIRAFQJ ACTIVE CLGA FQJ 40 120 RoHS & Green Call TI N / A for Pkg Type 0 to 70 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of