DLP4500NIRFQE

DLP4500NIR DLPS147B – JANUARY 2019 – REVISED MAY 2022 DLP4500NIR .45 WXGA Near-Infrared DMD 1 Features 2 Applications • • • • • • • • • • • • • Spectrometers (Chemical Analysis): – Process Analyzers – Laboratory Equipment – Dedicated Analyzers Compressive Sensing (Single-Pixel NIR Cameras) 3-D Biometrics Machine Vision Infrared Scene Projection Laser Marking Optical Choppers Microscopes Optical Networking 3 Description The DLP4500NIR digital micromirror device (DMD) acts as a spatial light modulator (SLM) to steer nearinfrared (NIR) light and create patterns with speed, precision, and efficiency. Featuring high resolution in a compact form factor, the DLP4500NIR DMD is often combined with a single element detector to replace expensive InGaAs array-based detector designs, leading to high performance, cost-effective portable solutions. PACKAGE(1) PART NUMBER DLP4500NIR (1) LCCC (98) THERMAL INTERFACE AREA 7.00 mm x 7.00 mm For all available packages, see the orderable addendum at the end of the data sheet. DC Power Lamp Driver NIR Lamp RGB Interface Control Processor 2 I C Interface GPIO Interface Oscillator DLPC350 FAN JTAG Control VRST Hardware Triggers VBIAS System Control DMD Voltage Supplies USB Interface VOFF Digital Pattern Creation LVDS Interface EN • 0.45-Inch Diagonal Micromirror Array – 912 × 1140 Resolution Array (>1 Million Micromirrors) – Diamond Array Orientation Supports Side Illumination for Simplified, Efficient Optics Designs – Capable of WXGA Resolution Display – 7.6-µm Micromirror Pitch – ±12° Tilt Angle – 5-µs Micromirror Crossover Time (Nominal) Highly Efficient Steering of NIR Light – Window Transmission Efficiency 96% Nominal (700 to 2000 nm, Single Pass Through Two Window Surfaces) – Window Transmission Efficiency 90% Nominal (2000 to 2500 nm, Single Pass Through Two Window Surfaces) – Polarization-Independent Aluminum Micromirrors – Array Fill Factor 92% (Nominal) Dedicated DLPC350 Controller for Reliable Operation – Binary Pattern Rates Up to 4 kHz – Pattern Sequence Mode for Control Over Each Micromirror in Array Integrated Micromirror Driver Circuitry 9.1-mm × 20.7-mm for Portable Instruments – FQD Package With Enhanced Thermal Interface DLP4500NIR Data Simplified Application An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DLP4500NIR www.ti.com DLPS147B – JANUARY 2019 – REVISED MAY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Chipset Component Usage Specification..................... 3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 8 7.1 Absolute Maximum Ratings........................................ 8 7.2 Storage Conditions..................................................... 8 7.3 ESD Ratings............................................................... 9 7.4 Recommended Operating Conditions.........................9 7.5 Thermal Information..................................................10 7.6 Electrical Characteristics...........................................11 7.7 Timing Requirements................................................ 12 7.8 System Mounting Interface Loads............................ 14 7.9 Micromirror Array Physical Characteristics............... 15 7.10 Micromirror Array Optical Characteristics............... 16 7.11 Typical Characteristics............................................ 17 8 Detailed Description......................................................18 8.1 Overview................................................................... 18 8.2 Functional Block Diagram......................................... 18 8.3 Feature Description...................................................19 8.4 Device Functional Modes..........................................21 8.5 Micromirror Array Temperature Calculation.............. 21 8.6 Micromirror Landed-on/Landed-Off Duty Cycle........ 23 9 Applications and Implementation................................ 26 9.1 Application Information............................................. 26 9.2 Typical Application.................................................... 26 10 Power Supply Recommendations..............................31 10.1 Power Supply Sequencing Requirements.............. 31 10.2 DMD Power Supply Power-Up Procedure.............. 31 10.3 DMD Power Supply Power-Down Procedure......... 31 11 Layout........................................................................... 33 11.1 Layout Guidelines................................................... 33 11.2 Layout Example...................................................... 38 12 Device and Documentation Support..........................42 12.1 Device Support....................................................... 42 12.2 Documentation Support.......................................... 42 12.3 Receiving Notification of Documentation Updates..43 12.4 Support Resources................................................. 43 12.5 Trademarks............................................................. 43 12.6 Electrostatic Discharge Caution..............................43 12.7 Glossary..................................................................43 13 Mechanical, Packaging, and Orderable Information.................................................................... 43 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2021) to Revision B (May 2022) Page • Updated Absolute Maximum Ratings disclosure to the latest TI standard......................................................... 8 • Updated Micromirror Array Optical Characteristics ......................................................................................... 16 • Added Third-Party Products Disclaimer ...........................................................................................................42 Changes from Revision * (January 2019) to Revision A (December 2021) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated |TDELTA| MAX from 30°C to 15°C..........................................................................................................9 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4500NIR DLP4500NIR www.ti.com DLPS147B – JANUARY 2019 – REVISED MAY 2022 5 Chipset Component Usage Specification Note TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously. The DLP4500NIR is a component of one or more DLP® chipsets. Reliable function and operation of the DLP4500NIR requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DLP DMD. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4500NIR 3 DLP4500NIR www.ti.com DLPS147B – JANUARY 2019 – REVISED MAY 2022 6 Pin Configuration and Functions Figure 6-1. FQD Package LCCC (98) Bottom View 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4500NIR DLP4500NIR www.ti.com DLPS147B – JANUARY 2019 – REVISED MAY 2022 Table 6-1. Connector Pins for FQD PIN NAME NO. TYPE SIGNAL DATA RATE (1) INTERNAL TERMINATION DESCRIPTION PACKAGE NET LENGTH (mm) (2) DATA INPUTS DATA(0) A1 Input LVCMOS DDR none Input data bus, bit 0, LSB 3.77 DATA(1) A2 Input LVCMOS DDR none Input data bus, bit 1 3.77 DATA(2) A3 Input LVCMOS DDR none Input data bus, bit 2 3.73 DATA(3) A4 Input LVCMOS DDR none Input data bus, bit 3 3.74 DATA(4) B1 Input LVCMOS DDR none Input data bus, bit 4 3.79 DATA(5) B3 Input LVCMOS DDR none Input data bus, bit 5 3.75 DATA(6) C1 Input LVCMOS DDR none Input data bus, bit 6 3.72 DATA(7) C3 Input LVCMOS DDR none Input data bus, bit 7 3.75 DATA(8) C4 Input LVCMOS DDR none Input data bus, bit 8 3.78 DATA(9) D1 Input LVCMOS DDR none Input data bus, bit 9 3.75 DATA(10) D4 Input LVCMOS DDR none Input data bus, bit 10 3.77 DATA(11) E1 Input LVCMOS DDR none Input data bus, bit 11 3.75 DATA(12) E4 Input LVCMOS DDR none Input data bus, bit 12 3.71 DATA(13) F1 Input LVCMOS DDR none Input data bus, bit 13 3.76 DATA(14) F3 Input LVCMOS DDR none Input data bus, bit 14 3.73 DATA(15) G1 Input LVCMOS DDR none Input data bus, bit 15 3.72 DATA(16) G2 Input LVCMOS DDR none Input data bus, bit 16 3.77 DATA(17) G4 Input LVCMOS DDR none Input data bus, bit 17 3.73 DATA(18) H1 Input LVCMOS DDR none Input data bus, bit 18 3.74 DATA(19) H2 Input LVCMOS DDR none Input data bus, bit 19 3.76 DATA(20) H4 Input LVCMOS DDR none Input data bus, bit 20 3.70 DATA(21) J1 Input LVCMOS DDR none Input data bus, bit 21 3.77 DATA(22) J3 Input LVCMOS DDR none Input data bus, bit 22 3.76 DATA(23) J4 Input LVCMOS DDR none Input data bus, bit 23, MSB 3.77 DCLK K1 Input LVCMOS DDR none Input data bus clock 3.74 DATA CONTROL INPUTS LOADB K2 Input LVCMOS DDR none Parallel-data load enable 3.74 TRC K4 Input LVCMOS DDR none Input-data toggle rate control 4.70 SCTRL K3 Input LVCMOS DDR none Serial-control bus 3.75 3.77 SAC_BUS C20 Input LVCMOS — none Stepped address-control serialbus data SAC_CLK C22 Input LVCMOS — none Stepped address-control serialbus clock 1.49 LVCMOS — none DMD reset-control serial bus 3.73 3.74 3.73 MIRROR RESET CONTROL INPUTS DRC_BUS B21 Input DRC_OE A20 Input LVCMOS — none Active-low output enable signal for internal DMD reset driver circuitry DRC_STROBE A22 Input LVCMOS — none Strobe signal for DMD resetcontrol inputs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4500NIR 5 DLP4500NIR www.ti.com DLPS147B – JANUARY 2019 – REVISED MAY 2022 Table 6-1. Connector Pins for FQD (continued) PIN NAME NO. TYPE SIGNAL DATA RATE (1) INTERNAL TERMINATION DESCRIPTION PACKAGE NET LENGTH (mm) (2) POWER INPUTS (3) 6 VBIAS C19 Power VBIAS D19 Power VOFFSET A19 Power VOFFSET K19 Power VRESET E19 Power VRESET F19 Power VREF B19 Power VREF J19 Power VCC B22 Power VCC C2 Power VCC D21 Power VCC E2 Power VCC E20 Power VCC E22 Power VCC F21 Power VCC G3 Power VCC G19 Power VCC G20 Power VCC G22 Power VCC H19 Power VCC H21 Power VCC J20 Power VCC J22 Power VCC K21 Power Mirror-reset bias voltage Mirror-reset offset voltage Mirror-reset voltage Power supply for LVCMOS double-data-rate (DDR) interface Power supply for LVCMOS logic Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4500NIR DLP4500NIR www.ti.com DLPS147B – JANUARY 2019 – REVISED MAY 2022 Table 6-1. Connector Pins for FQD (continued) PIN NAME NO. TYPE VSS A21 Power VSS B2 Power VSS B4 Power VSS B20 Power VSS C21 Power VSS D2 Power VSS D3 Power VSS D20 Power VSS D22 Power VSS E3 Power VSS E21 Power VSS F2 Power VSS F4 Power VSS F20 Power VSS F22 Power VSS G21 Power VSS H3 Power VSS H20 Power VSS H22 Power VSS J2 Power VSS J21 Power VSS K20 Power (1) SIGNAL DATA RATE (1) INTERNAL TERMINATION DESCRIPTION PACKAGE NET LENGTH (mm) (2) Ground – Common return for all power inputs (2) • DDR = Double data rate • SDR = Single data rate • Refer to Section 7.7 for specifications and relationships. Net trace lengths inside the package: (3) • Relative dielectric constant for the FQD ceramic package is 9.8. • Propagation speed = 11.8 / sqrt(9.8) = 3.769 inches/ns. • Propagation delay = 0.265 ns/inch = 265 ps/inch = 10.43 ps/mm. The following power supplies are all required to operate the DMD: VSS, VCC, VOFFSET, VBIAS, VRESET. Table 6-2. Test Pads for FQD Package NAME PIN SIGNAL DESCRIPTION UNUSED A5, A18, B5, B18, C5, C18, D5, D18, E5, E18, F5, F18, G5, G18, H5, H18, J5, J18, K22 Test pads Do not connect Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP4500NIR 7 DLP4500NIR www.ti.com DLPS147B – JANUARY 2019 – REVISED MAY 2022 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT SUPPLY VOLTAGES (2) VCC Supply voltage for LVCMOS core logic –0.5 4 V VREF Supply voltage for LVCMOS DDR interface –0.5 4 V VOFFSET Supply voltage for high voltage CMOS and micromirror electrode –0.5 8.75 V VBIAS (3) Supply voltage for micromirror electrode –0.5 17 V VRESET Supply voltage for micromirror electrode –11 |VBIAS - VOFFSET| (3) Supply voltage delta (absolute value) INPUT VOLTAGES 0.5 V 8.75 V VREF + 0.5 V (2) Input voltage to all other input pins –0.5 INPUT CURRENTS Current required from a high-level output VOH = 1.4 V –9 mA Current required from a low-level output VOL = 0.4 V 18 mA 80 120 MHz –20 90 °C –40 90 °C 81 °C 95 %RH CLOCKS fCLK DCLK clock frequency ENVIRONMENTAL TCASE TDP Case temperature - operational (4) Case temperature - non-operational (4) Dew Point (operation and non-operational) Operating Relative Humidity (non-condensing) (1) (2) (3) (4) 0 Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. All voltage values are referenced to common ground VSS. Supply voltages VCC, VREF, VOFFSET, VBIAS, and VRESET are all required for proper DMD operation. VSS must also be connected. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than the specified limit. DMD Temperature is the worst-case of any test point shown in or Figure 8-3, or the active array as calculated by the Micromirror Array Temperature Calculation, or any point along the Window Edge as defined in or Figure 8-3. The locations of thermal test point TP2 is intended to measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, a test point should be added to that location. 7.2 Storage Conditions applicable before the DMD is installed in the final product MIN Storage temperature Tstg (1) (2) (3) 8 (1) MAX UNIT –40 85 °C 0 95% RH Long-term storage dew point (1) (2) 24 °C Short-term storage dew point (1) (3) 28 °C Storage humidity, non-condensing (1) As a best practice, TI recommends storing the DMD in a temperature and humidity controlled environment. Long-term is defined as the average over the usable life. Short-term is defined as 1 V/ns. For slow slew rates >0.5 V/ns and