Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
DLP470TE
DLPS161 – APRIL 2019
DLP470TE 0.47 4K UHD DMD
1 Features
3 Description
•
The TI DLP470TE digital micromirror device (DMD) is
a digitally controlled micro-electromechanical system
(MEMs) spatial light modulator (SLM) that enables
bright, full 4K UHD display solutions. When coupled
with the appropriate optical system, the DLP470TE
DMD displays true 4K UHD resolution (over 8 million
pixels on screen) and is capable of delivering
accurate, detailed images to a variety of surfaces.
The DLP470TE DMD, together with the DLPC4422
display controller and DLPA100 power and motor
driver, comprise the DLP® 0.47 4K UHD chipset. This
solution is a great fit for many high brightness 4K
UHD display systems.
1
•
•
0.47-Inch Diagonal micromirror Array
– 4K UHD (3840 × 2160) display resolution
– 5.4-micron micromirror pitch
– ±17° micromirror tilt (relative to flat surface)
– Bottom Illumination
2xLVDS input data bus
Dedicated DLPC4422 display controller, DLPA100
power management IC and motor driver for
reliable operation
2 Applications
•
•
•
•
•
•
Device Information(1)
4K UHD display
Laser TV
Business and education
Digital signage
Gaming
Home cinema
PART NUMBER
DLP470TE
PACKAGE
FXJ (257)
BODY SIZE (NOM)
32.2 mm × 22.3 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
DAD CTRL
DAD CTRL
SCP CTRL
DLPC4422
Display
Controller
3.3V to 1.8V
Translator
SCP CTRL
C/D DMD DATA
C/D DMD CLK
C/D SCTRL
VOFFSET
VBIAS
TPS65145
(Voltage
Regultor)
3.3V
VRESET
PG_OFFSET
DLP470TE
DMD
EN_OFFSET
VREG
DLPC4422
Display
Controller
1.8V
A/B DMD DATA
A/B DMD CLK
A/B SCTRL
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
7.4 Device Functional Modes........................................
7.5 Optical Interface and System Image Quality
Considerations .........................................................
7.6 Micromirror Array Temperature Calculation............
7.7 Micromirror Landed-On/Landed-Off Duty Cycle .....
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 3
Specifications....................................................... 10
8
25
26
27
Application and Implementation ........................ 30
8.1 Application Information............................................ 30
8.2 Typical Application ................................................. 30
8.3 DMD Die Temperature Sensing.............................. 31
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings .................................... 10
Storage Conditions.................................................. 11
ESD Ratings............................................................ 11
Recommended Operating Conditions..................... 11
Thermal Information ................................................ 14
Electrical Characteristics......................................... 15
Capacitance at Recommended Operating
Conditions ................................................................ 15
6.8 Timing Requirements .............................................. 16
6.9 System Mounting Interface Loads .......................... 19
6.10 Micromirror Array Physical Characteristics ........... 20
6.11 Micromirror Array Optical Characteristics ............. 22
6.12 Window Characteristics......................................... 23
6.13 Chipset Component Usage Specification ............. 23
7
25
9
Power Supply Recommendations...................... 33
9.1 DMD Power Supply Power-Up Procedure .............. 33
9.2 DMD Power Supply Power-Down Procedure ......... 33
10 Layout................................................................... 36
10.1 Layout Guidelines ................................................. 36
10.2 Layout Example .................................................... 36
11 Device and Documentation Support ................. 38
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Detailed Description ............................................ 24
7.1 Overview ................................................................. 24
7.2 Functional Block Diagram ....................................... 24
7.3 Feature Description................................................. 25
Device Support......................................................
Documentation Support .......................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
39
39
39
39
39
39
12 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
2
DATE
REVISION
NOTES
April 2019
*
Initial release.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
5 Pin Configuration and Functions
Series 410 Package
257-pin FXJ
Bottom View
2
1
4
3
6
5
8
7
9
10 12 14 16 18 20 22 24 26 28 30
11 13 15 17 19 21 23 25 27 29
Z
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
CAUTION
To ensure reliable, long-term operation of the .47-inch 4K UHD S410 DMD, it is
critical to properly manage the layout and operation of the signals identified in the
table below. For specific details and guidelines, refer to the PCB Design
Requirements for TI DLP Standard TRP Digital Micromirror Devices application report
before designing the board.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
3
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
Pin Functions (1)
PIN
NAME
NO.
D_AN(0)
C6
D_AN(1)
C3
D_AN(2)
E1
D_AN(3)
C4
D_AN(4)
D1
D_AN(5)
B8
D_AN(6)
F4
D_AN(7)
E3
D_AN(8)
C11
D_AN(9)
F3
D_AN(10)
K4
D_AN(11)
H3
D_AN(12)
J3
D_AN(13)
C13
D_AN(14)
A5
D_AN(15)
A3
D_AP(0)
C7
D_AP(1)
C2
D_AP(2)
E2
D_AP(3)
B4
D_AP(4)
C1
D_AP(5)
B7
D_AP(6)
E4
D_AP(7)
D3
D_AP(8)
C12
D_AP(9)
F2
D_AP(10)
J4
D_AP(11)
G3
D_AP(12)
J2
D_AP(13)
C14
D_AP(14)
A6
D_AP(15)
A4
(1)
(2)
4
INTERNAL
TERMINATION
TRACE
LENGTH
(mil)
I/O (2)
SIGNAL
DATA
RATE
I
LVDS
DDR
Differential
Data negative
805.0
I
LVDS
DDR
Differential
Data positive
805.0
DESCRIPTION
The .47-inch 4K UHD TRP 2xLVDS series 410 DMD is a component of one or more DLP® chipsets. Reliable function and operation of
the .47” 4K UHD TRP 2xLVDS series 410 DMD requires that it be used in conjunction with the other components of the applicable DLP®
chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI
technology and devices for operating or controlling a DLP® DMD.
I = Input, O = Output, P = Power, G = Ground, NC = No connect
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
Pin Functions(1) (continued)
PIN
NAME
NO.
D_BN(0)
N4
D_BN(1)
Z11
D_BN(2)
W4
D_BN(3)
W10
D_BN(4)
L1
D_BN(5)
V8
D_BN(6)
W6
D_BN(7)
M1
D_BN(8)
R4
D_BN(9)
W1
D_BN(10)
U4
D_BN(11)
V2
D_BN(12)
Z5
D_BN(13)
N3
D_BN(14)
Z2
D_BN(15)
L4
D_BP(0)
M4
D_BP(1)
Z12
D_BP(2)
Z4
D_BP(3)
Z10
D_BP(4)
L2
D_BP(5)
V9
D_BP(6)
W7
D_BP(7)
N1
D_BP(8)
P4
D_BP(9)
V1
D_BP(10)
T4
D_BP(11)
V3
D_BP(12)
Z6
D_BP(13)
N2
D_BP(14)
Z3
D_BP(15)
L3
INTERNAL
TERMINATION
TRACE
LENGTH
(mil)
I/O (2)
SIGNAL
DATA
RATE
I
LVDS
DDR
Differential
Data negative
805.0
I
LVDS
DDR
Differential
Data positive
805.0
DESCRIPTION
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
5
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
Pin Functions(1) (continued)
PIN
NAME
NO.
D_CN(0)
H27
D_CN(1)
A20
D_CN(2)
H28
D_CN(3)
K28
D_CN(4)
K30
D_CN(5)
C23
D_CN(6)
G27
D_CN(7)
J30
D_CN(8)
B24
D_CN(9)
A21
D_CN(10)
A27
D_CN(11)
C29
D_CN(12)
A26
D_CN(13)
C25
D_CN(14)
A29
D_CN(15)
C30
D_CP(0)
J27
D_CP(1)
A19
D_CP(2)
H29
D_CP(3)
K27
D_CP(4)
K29
D_CP(5)
C22
D_CP(6)
F27
D_CP(7)
H30
D_CP(8)
B25
D_CP(9)
B21
D_CP(10)
B27
D_CP(11)
C28
D_CP(12)
A25
D_CP(13)
C24
D_CP(14)
A28
D_CP(15)
B30
6
INTERNAL
TERMINATION
TRACE
LENGTH
(mil)
I/O (2)
SIGNAL
DATA
RATE
I
LVDS
DDR
Differential
Data negative
805.0
I
LVDS
DDR
Differential
Data positive
805.0
DESCRIPTION
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
Pin Functions(1) (continued)
PIN
NAME
NO.
D_DN(0)
V25
D_DN(1)
V28
D_DN(2)
T30
D_DN(3)
V27
D_DN(4)
U30
D_DN(5)
W23
D_DN(6)
R27
D_DN(7)
T28
D_DN(8)
V20
D_DN(9)
R28
D_DN(10)
L27
D_DN(11)
N28
D_DN(12)
M28
D_DN(13)
V18
D_DN(14)
Z26
D_DN(15)
Z28
D_DP(0)
V24
D_DP(1)
V29
D_DP(2)
T29
D_DP(3)
W27
D_DP(4)
V30
D_DP(5)
W24
D_DP(6)
T27
D_DP(7)
U28
D_DP(8)
V19
D_DP(9)
R29
D_DP(10)
M27
I/O (2)
SIGNAL
DATA
RATE
INTERNAL
TERMINATION
DESCRIPTION
TRACE
LENGTH
(mil)
805.0
I
LVDS
DDR
Differential
Data negative
805.0
I
LVDS
DDR
Differential
Data positive
D_DP(11)
P28
D_DP(12)
M29
D_DP(13)
V17
D_DP(14)
Z25
D_DP(15)
Z27
SCTRL_AN
G1
I
LVDS
DDR
Differential
Serial control negative (3)
805.0
SCTRL_AP
F1
I
LVDS
DDR
Differential
Serial control negative (3)
805.0
SCTRL_BN
V5
I
LVDS
DDR
Differential
Serial control negative (3)
805.0
SCTRL_BP
V4
I
LVDS
DDR
Differential
Serial control negative (3)
805.0
(3)
805.0
SCTRL_CN
C26
I
LVDS
DDR
Differential
Serial control negative
SCTRL_CP
C27
I
LVDS
DDR
Differential
Serial control positive (3)
805.0
SCTRL_DN
P30
I
LVDS
DDR
Differential
Serial control negative (3)
805.0
DDR
(3)
SCTRL_DP
R30
I
LVDS
Differential
Serial control positive
DCLK_AN
H2
I
LVDS
Differential
Clock negative (3)
805.0
DCLK_AP
H1
I
LVDS
Differential
Clock positive (3)
805.0
(3)
DCLK_BN
V6
I
LVDS
Differential
Clock negative
DCLK_BP
V7
I
LVDS
Differential
Clock positive (3)
(3)
805.0
805.0
805.0
These signals are very sensible to noise or intermittent power connections, which can cause irreversible DMD micromirror array damage
or, to a lesser extent, image disruption. Consider this precaution during DMD board design and manufacturer handling of the DMD subassemblies.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
7
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
Pin Functions(1) (continued)
PIN
NAME
NO.
I/O (2)
SIGNAL
DATA
RATE
INTERNAL
TERMINATION
DESCRIPTION
TRACE
LENGTH
(mil)
DCLK_CN
D27
I
LVDS
Differential
Clock negative (3)
805.0
DCLK_CP
E27
I
LVDS
Differential
Clock positive (3)
805.0
(3)
DCLK_DN
N29
I
LVDS
Differential
Clock negative
DCLK_DP
N30
I
LVDS
Differential
Clock positive (3)
Pull down
Serial communications port clock. Active only
when SCPENZ is logic low. (3)
Pull down
Serial communications port data input.
Synchronous to SCPCLK rising edge. (3)
Pull down
Serial communications port enable active
low. (3)
SCPCLK
A10
I
LVCMOS
SCPDI
A12
I
LVCMOS
SCPENZ
C10
I
LVCMOS
SCPDO
A11
O
LVCMOS
RESET_ADDR(0)
Z13
RESET_ADDR(1)
W13
RESET_ADDR(2)
V10
I
LVCMOS
RESET_ADDR(3)
W14
RESET_MODE(0)
W9
RESET_SEL(0)
V14
RESET_SEL(1)
Z8
RESET_STROBE
Z9
I
LVCMOS
Pull down
Rising edge latches in RESET_ADDR,
RESET_MODE, & RESET_SEL. (3)
PWRDNZ
A8
I
LVCMOS
Pull down
Active low device reset. (3)
RESET_OEZ
W15
I
LVCMOS
Pull up
Active low output enable for internal reset
driver circuits. (3)
RESET_IRQZ
V16
O
LVCMOS
Active low output interrupt to DLP® display
controller
EN_OFFSET
C9
O
LVCMOS
Active high enable for external VOFFSET
regulator
PG_OFFSET
A9
I
LVCMOS
TEMP_N
B18
Analog
Temperature sensor diode cathode
B17
Analog
Temperature sensor diode anode
TEMP_P
I
NC
No Connect
U16, U17,
U18, U19
NC
W11
B11
RESERVED_BC
Z20
RESERVED_BD
C18
RESERVED_PFE
A18
RESERVED_TM
C8
RESERVED_TP0
Z19
RESERVED_TP1
W20
RESERVED_TP2
W19
VBIAS (4)
(4)
8
C15, C16,
V11, V12
Serial communications port output.
Pull down
Reset driver address select. (3)
LVCMOS
Pull down
Reset driver level select. (3)
Reset driver level select. (3)
RESERVED
**MUST VERIFY
WITH SRC DATA
SHEET
RESERVED_BB
SDR
805.0
Reset driver mode select. (3)
D12, D13,
D14, D15,
D16, D17,
D18, D19,
U12, U13,
U14, U15
RESERVED_BA
SDR
805.0
Analog
Pull up
Pull Down
Active low fault from external VOFFSET
regulator (3)
Do not connect on DLP® system board. No
connect. No electrical connections from
CMOS bond pad to package pin.
No connect. No electrical connection from
CMOS bond pad to package pin.
Do not connect on DLP® system board
O
LVCMOS
I
LVCMOS
I
Analog
Do not connect on DLP® system board
P
Analog
Supply voltage for positive bias level of
micromirror reset signal.
Pull down
Connect to ground on DLP® system board
VBIAS, VCC, VOFFSET, and VRESET power supplies must be connected for proper DMD operation.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
Pin Functions(1) (continued)
PIN
NAME
NO.
I/O (2)
SIGNAL
DATA
RATE
INTERNAL
TERMINATION
DESCRIPTION
VRESET (4)
G4, H4,
J1, K1
P
Analog
Supply voltage for negative reset level of
micromirror reset signal
VOFFSET (4)
A30, B2,
M30, Z1,
Z30
P
Analog
Supply voltage for HVCMOS logic. Supply
voltage for positive offset level of micromirror
reset signal. Supply voltage for stepped high
voltage at micromirror address electrodes.
Analog
Supply voltage for LVCMOS core. Supply
voltage for positive offset level of micromirror
reset signal during power down. Supply
voltage for normal high level at micromirror
address electrodes.
VCC (4)
A24, A7,
B10, B13,
B16, B19,
B22, B28,
B5, C17,
C20, D4,
J29, K2,
L29, M2,
N27, U27,
V13, V15,
V22, W17,
W21,
W26,
W29, W3,
Z18, Z23,
Z29, Z7
P
VSS (5)
A13, A22,
A23, B12,
B14, B15,
B20, B23,
B26, B29,
B3, B6,
B9, C19,
C21, C5,
D2, G2,
J28, K3,
L28, L30,
M3, P27,
P29, U29,
V21, V23,
V26, W12,
W16,
W18, W2,
W22,
W25,
W28,
W30, W5,
W8, Z21,
Z22, Z24
G
(5)
TRACE
LENGTH
(mil)
Device ground. Common return for all power.
VSS must be connected for proper DMD operation.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
9
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted). Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is
not implied at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure
above or below the Recommended Operating Conditions for extended periods may affect device reliability.
MIN
MAX
UNIT
SUPPLY VOLTAGES
VCC
Supply voltage for LVCMOS core logic (1)
–0.5
2.3
V
VOFFSET
Supply voltage for HVCMOS and micromirror electrode (1) (2)
–0.5
11
V
VBIAS
Supply voltage for micromirror electrode
(1)
–0.5
19
V
VRESET
Supply voltage for micromirror electrode (1)
–15
–0.3
V
|VBIAS – VOFFSET|
Supply voltage difference (absolute value) (3)
11
V
(4)
34
V
–0.5
VCC + 0.5
V
–0.5
VCC + 0.5
V
|VBIAS – VRESET|
Supply voltage difference (absolute value)
INPUT VOLTAGES
Input voltage for all other LVCMOS input pins (1)
Input voltage for all other LVDS input pins
(1) (5)
(6)
|VID|
Input differential voltage (absolute value)
500
mV
IID
Input differential current (5)
6.3
mA
ƒCLOCK
Clock frequency for LVDS interface, DCLK_A
400
MHz
ƒCLOCK
Clock frequency for LVDS interface, DCLK_B
400
MHz
ƒCLOCK
Clock frequency for LVDS interface, DCLK_C
400
MHz
ƒCLOCK
Clock frequency for LVDS interface, DCLK_D
400
MHz
0
90
°C
–40
90
°C
Clocks
ENVIRONMENTAL
TARRAY and
TWINDOW
Temperature, operating (7)
Temperature, non–operating (7)
|TDELTA|
Absolute temperature delta between any point on the window edge and the
ceramic test point TP1 (8)
30
°C
TDP
Dew point temperature, operating and non–operating (non-condensing)
81
°C
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
10
All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD
operation. VSS must also be connected.
VOFFSET supply transients must fall within specified voltages.
Exceeding the recommended allowable voltage difference between VBIAS and VOFFSET may result in excessive current draw.
Exceeding the recommended allowable voltage difference between VBIAS and VRESET may result in excessive current draw.
LVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
This maximum LVDS input voltage rating applies when each input of a differential pair is at the same voltage potential.
The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along the
window edge as defined in Figure 10. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 10 are intended to
measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher
temperature, that point should be used.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
Figure 10. The window test points TP2, TP3, TP4, and TP5 shown in Figure 10 are intended to result in the worst case delta. If a
particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system.
TDMD
DMD storage temperature
TDP-AVG
Average dew point temperature (non-condensing)
TDP-ELR
Elevated dew point temperature range (non-condensing)
CTELR
Cumulative time in elevated dew point temperature range
(1)
(2)
MIN
MAX
–40
80
°C
28
°C
(1)
(2)
28
UNIT
36
°C
24
months
The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total cumulative
time of CTELR.
6.3 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this
data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied
when operating the device above or below these limits.
MIN NOM
MAX
UNIT
1.65
1.8
1.95
V
9.5
10
10.5
V
17.5
18
18.5
V
–14.5
–14
VOLTAGE SUPPLY
VCC
LVCMOS logic supply voltage (1)
VOFFSET
Mirror electrode and HVCMOS voltage (1) (2)
VBIAS
Mirror electrode voltage (1)
VRESET
Mirror electrode voltage
(1)
–13.5
V
|VBIAS –
VOFFSET|
Supply voltage difference (absolute value)
(3)
10.5
V
|VBIAS –
VRESET|
Supply voltage difference (absolute value) (4)
33
V
0.7 × VCC
VCC + 0.3
V
LVCMOS INTERFACE
VIH(DC)
DC input high voltage (5)
(5)
VIL(DC)
DC input low voltage
VIH(AC)
AC input high voltage (5)
VIL(AC)
AC input low voltage (5)
tPWRDNZ
(1)
(2)
(3)
(4)
(5)
(6)
PWRDNZ pulse duration
(6)
–0.3
0.3 × VCC
V
0.8 × VCC
VCC + 0.3
V
–0.3
0.2 × VCC
V
10
ns
All voltages are referenced to common ground VSS. VBIAS, VCC, VOFFSET, and VRESET power supplies are all required for proper DMD
operation. VSS must also be connected.
VOFFSET supply transients must fall within specified max voltages.
To prevent excess current, the supply voltage difference |VBIAS – VOFFSET| must be less than the specified limit. See Power Supply
Recommendations, Figure 14, and Table 8.
To prevent excess current, the supply voltage difference |VBIAS – VRESET| must be less than the specified limit. See Power Supply
Recommendations, Figure 14, and Table 8.
Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard
No. 209B, “Low-Power Double Data Rate (LPDDR)” JESD209B. Tester conditions for VIH and VIL.
(a) Frequency = 60 MHz. Maximum rise time = 2.5 ns at 20/80
(b) Frequency = 60 MHz. Maximum fall time = 2.5 ns at 80/20
PWRDNZ input pin resets the SCP and disables the LVDS receivers. PWRDNZ input pin overrides SCPENZ input pin and tristates the
SCPDO output pin.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
11
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this
data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied
when operating the device above or below these limits.
MIN NOM
MAX
UNIT
500
kHz
900
ns
SCP INTERFACE
ƒSCPCLK
SCP clock frequency (7)
tSCP_PD
Propagation delay, clock to Q, from rising-edge of SCPCLK to valid
SCPDO (8)
0
tSCP_NEG_ENZ
Time between falling-edge of SCPENZ and the first rising-edge of SCPCLK
1
µs
tSCP_POS_ENZ
Time between falling-edge of SCPCLK and the rising-edge of SCPENZ
1
µs
tSCP_DS
SCPDI clock setup time (before SCPCLK falling edge) (8)
800
ns
tSCP_DH
SCPDI hold time (after SCPCLK falling edge) (8)
900
ns
tSCP_PW_ENZ
SCPENZ inactive pulse duration (high level)
2
µs
ƒCLOCK
Clock frequency for LVDS interface (all channels), DCLK (9)
|VID|
Input differential voltage (absolute value) (10)
VCM
Common mode voltage (10)
(10)
400
MHz
300
440
mV
1100 1200
1300
mV
1520
mV
2000
ns
150
VLVDS
LVDS voltage
tLVDS_RSTZ
Time required for LVDS receivers to recover from PWRDNZ
ZIN
Internal differential termination resistance
80
100
120
Ω
ZLINE
Line differential impedance (PWB/trace)
90
100
110
Ω
(7)
(8)
(9)
(10)
12
880
The SCP clock is a gated clock. Duty cycle must be 50% ± 10%. SCP parameter is related to the frequency of DCLK.
See Figure 2.
See LVDS timing requirements in Timing Requirements and Figure 6.
See LVDS waveform requirements in Figure 5.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
Recommended Operating Conditions (continued)
Over operating free-air temperature range (unless otherwise noted). The functional performance of the device specified in this
data sheet is achieved when operating the device within the limits defined by this table. No level of performance is implied
when operating the device above or below these limits.
MIN NOM
MAX
UNIT
ENVIRONMENTAL
TARRAY
Array temperature, long–term operational (11) (12) (13) (14)
10
40 to 70 (14)
°C
0
10
°C
TWINDOW
Window temperature – operational (16) (17)
85
°C
|TDELTA|
Absolute temperature delta between any point on the window edge and the
ceramic test point TP1 (18) (19)
14
°C
TDP-AVG
Average dew point temperature (non–condensing) (20)
28
°C
TDP-ELR
Elevated dew point temperature range (non-condensing) (21)
CTELR
Cumulative time in elevated dew point temperature range
L
Operating system luminance
ILLUV
Illumination wavelengths < 395 nm (11)
ILLVIS
Illumination wavelengths between 395 nm and 800 nm
ILLIR
Illumination wavelengths > 800 nm
ILLθ
Array temperature, short–term operational
(12) (15)
28
(19)
Illumination marginal ray angle
(17)
0.68
36
°C
24
months
4000
lm
2.00
mW/cm2
mW/cm2
Thermally limited
10
mW/cm2
55
deg
(11) Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination reduces
device lifetime.
(12) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1
(TP1) shown in Figure 10 and the package thermal resistance (Thermal Information) using the Micromirror Array Temperature
Calculation.
(13) Long-term is defined as the usable life of the device.
(14) Per Figure 1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the DMD
experiences in the end application. See Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle.
(15) Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is
defined as the cumulative time over the usable life of the device and is less than 500 hours.
(16) The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 10 are intended to measure the highest window edge
temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular
application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
(17) The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including the pond of
micromirrors (POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not
necessarily been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance
has not been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including
POM) will contribute to thermal limitations described in this document, and may negatively affect lifetime.
(18) Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
Figure 10. The window test points TP2, TP3, TP4, and TP5 shown in Figure 10 are intended to result in the worst case delta
temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point
should be used.
(19) DMD is qualified at the combination of the maximum temperature and maximum lumens specified. Operation of the DMD outside of
these limits has not been tested.
(20) The average over time (including storage and operating) that the device is not in the elevated dew point temperature range.
(21) Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
13
DLP470TE
Maximum Recommended Array Temperature - Operational (¹C)
DLPS161 – APRIL 2019
www.ti.com
80
70
60
50
40
30
0/100
5/95
10/90
15/85
20/80
25/75
30/70
35/65
40/60
45/55 50/50
100/0
95/5
90/10
85/15
80/20
75/25
70/30
65/35
60/40
55/45
50/50
Micromirror Landed Duty Cycle
Figure 1. Maximum Recommended Array Temperature - Derating Curve
6.5 Thermal Information
DLP470TE
THERMAL METRIC
FXJ Package
UNIT
257 PINS
Thermal resistance, active area to test point 1 (TP1) (1)
(1)
14
0.90
°C/W
The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate
heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the
Recommended Operating Conditions.
The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include
light energy absorbed by the window aperture and electrical power dissipation of the array.
Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal
load in this area can significantly degrade the reliability of the device.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
6.6 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VOH
High level output voltage
VCC = 1.8 V, IOH = –2 mA
VOL
Low level output voltage
VCC = 1.95 V, IOL = 2 mA
IOZ
High impedance output current VCC = 1.95 V
IIL
Low level input current
VCC = 1.95 V, VI = 0
(1)
IIH
High level input current
ICC
Supply current VCC
IOFFSET
Supply current VOFFSET
(2)
(2) (3)
UNIT
0.8 x VCC
V
–40
0.2 x VCC
V
25
µA
–1
µA
110
µA
1500
mA
VOFFSET = 10.5 V
13.2
mA
VBIAS = 18.5 V
3.6
mA
VRESET = –14.5 V
–9
mA
2925.0
mW
138.6
mW
66.6
mW
130.5
mW
3260.7
mW
Supply current VBIAS
Supply current VRESET
PCC
Supply power dissipation VCC
VCC = 1.95 V
POFFSET
Supply power dissipation
VOFFSET (2)
VOFFSET = 10.5 V
PBIAS
Supply power dissipation
VBIAS (2) (3)
VBIAS = 18.5 V
PRESET
Supply power dissipation
VRESET (3)
VRESET = –14.5 V
PTOTAL
Supply power dissipation
VTOTAL
(3)
MAX
VCC = 1.95 V
IRESET
(1)
(2)
TYP
VCC = 1.95 V, VI = VCC
IBIAS
(3)
MIN
Applies to LVCMOS pins only. Excludes LVDS pins and MBRST (15:0) pins.
To prevent excess current, the supply voltage difference |VBIAS – VOFFSET| must be less than the specified limits listed in the
Recommended Operating Conditions table.
To prevent excess current, the supply voltage difference |VBIAS – VRESET| must be less than specified limit in Recommended Operating
Conditions.
6.7 Capacitance at Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CI_lvds
LVDS input capacitance 2xLVDS
ƒ = 1 MHz
20
pF
CI_nonlvds
Non-LVDS input capacitance
2xLVDS
ƒ = 1 MHz
20
pF
CI_tdiode
Temperature diode input
capacitance 2xLVDS
ƒ = 1 MHz
30
pF
CO
Output capacitance
ƒ = 1 MHz
20
pF
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
15
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
6.8 Timing Requirements
MIN
NOM
MAX
UNIT
SCP (1)
tr
Rise slew rate
20% to 80% reference points
1
3
V/ns
tf
Fall slew rate
80% to 20% reference points
1
3
V/ns
tr
Rise slew rate
20% to 80% reference points
0.7
1
V/ns
tf
Fall slew rate
80% to 20% reference points
0.7
1
V/ns
DCLK_A, LVDS pair
2.5
ns
DCLK_B, LVDS pair
2.5
ns
DCLK_C, LVDS pair
2.5
ns
LVDS
tC
(2)
Clock cycle
tW
Pulse duration
DCLK_D, LVDS pair
2.5
DCLK_A, LVDS pair
1.19
1.25
ns
DCLK_B, LVDS pair
1.19
1.25
ns
DCLK_C, LVDS pair
1.19
1.25
ns
1.19
1.25
ns
DCLK_D, LVDS pair
tSu
Setup time
th
Hold time
D_A(15:0) before DCLK_A, LVDS pair
0.275
ns
D_B(15:0) before DCLK_B, LVDS pair
0.275
ns
D_C(15:0) before DCLK_C, LVDS pair
0.275
ns
D_D(15:0) before DCLK_D, LVDS pair
0.275
ns
SCTRL_A before DCLK_A, LVDS pair
0.275
ns
SCTRL_B before DCLK_B, LVDS pair
0.275
ns
SCTRL_C before DCLK_C, LVDS pair
0.275
ns
SCTRL_D before DCLK_D, LVDS pair
0.275
ns
D_A(15:0) after DCLK_A, LVDS pair
0.195
ns
D_B(15:0) after DCLK_B, LVDS pair
0.195
ns
D_C(15:0) after DCLK_C, LVDS pair
0.195
ns
D_D(15:0) after DCLK_D, LVDS pair
0.195
ns
SCTRL_A after DCLK_A, LVDS pair
0.195
ns
SCTRL_B after DCLK_B, LVDS pair
0.195
ns
SCTRL_C after DCLK_C, LVDS pair
0.195
ns
SCTRL_D after DCLK_D, LVDS pair
0.195
(3) (4)
–1.25
1.25
ns
–1.25
1.25
ns
tSKEW
Skew time
Channel B relative to channel A
tSKEW
Skew time
Channel D relative to channel C (5) (6), LVDS pair
(1)
(2)
(3)
(4)
(5)
(6)
16
ns
ns
See Figure 3 for rise time and fall time for SCP.
See Figure 5 for timing requirements for LVDS.
Channel A (Bus A) includes the following LVDS pairs: DCLK_AN and DCLK_AP, SCTRL_AN and SCTRL_AP, D_AN(15:0) and
D_AP(15:0).
Channel B (Bus B) includes the following LVDS pairs: DCLK_BN and DCLK_BP, SCTRL_BN and SCTRL_BP, D_BN(15:0) and
D_BP(15:0).
Channel C (Bus C) includes the following LVDS pairs: DCLK_CN and DCLK_CP, SCTRL_CN and SCTRL_CP, D_CN(15:0) and
D_CP(15:0).
Channel D (Bus D) includes the following LVDS pairs: DCLK_DN and DCLK_DP, SCTRL_DN and SCTRL_DP, D_DN(15:0) and
D_DP(15:0).
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
SCPCLK falling–edge capture for SCPDI.
tSCP_NEG_ENZ
tSCP_POS_ENZ
SCPCLK rising–edge launch for SCPDO.
SCPENZ
50%
50%
tSCP_DS
SCPDI
000000000000000000000000000000000000000000000000
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
000000000000000000000000000000000000000000000000
DI
tSCP_DH
50%
00000000000000000000
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00000000000000000000
50%
tC
SCPCLK
fSCPCLK = 1 / tC
50%
50%
50%
50%
tSCP_PD
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000000000000000000000000000000000000000000000000000000000000000000000
SCPDO 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0000000000000000000000000000000000000000000000000000000000000000000000
DO
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50%
Figure 2. SCP Timing Requirements
Voltage (V)
See Recommended Operating Conditions for fSCPCLK, tSCP_DS, tSCP_DH and tSCP_PD specifications.
VCC
0
tRISE
tFALL
Time
(Not to scale)
Figure 3. SCP Requirements for Rise and Fall
See Timing Requirements for tr and tf specifications and conditions.
Device pin
output under test
Tester channel
CLOAD
Figure 4. Test Load Circuit for Output Propagation Measurement
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
17
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.
System designers should use IBIS or other simulation tools to correlate the timing reference load to a system
environment.
VLVDS max = VCM max + | 1/2 * VID max |
tf
VCM
VID
tr
VLVDS min = VCM min ± | 1/2 * VID max |
Figure 5. LVDS Waveform Requirements
See Recommended Operating Conditions for VCM, VID, and VLVDS specifications and conditions.
18
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
tc
tw
tw
DCLK_P
DCLK_N
50%
th
th
tsu
tsu
D_P(?:0)
D_N(?:0)
50%
th
th
tsu
tsu
SCTRL_P
SCTRL_N
50%
tskew
tc
tw
tw
DCLK_P
DCLK_N
50%
th
th
tsu
tsu
D_P(?:0)
D_N(?:0)
50%
th
th
tsu
tsu
SCTRL_P
SCTRL_N
50%
Figure 6. Timing Requirements
See Timing Requirements for timing requirements and LVDS pairs per channel (bus) defining D_P(?:0) and
D_N(?:0).
6.9 System Mounting Interface Loads
Table 1. System Mounting Interface Loads
PARAMETER
Thermal interface area
(1)
Electrical interface area (1)
(1)
MIN
NOM
MAX
UNIT
12
kg
25
kg
Uniformly distributed within area shown in Figure 7.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
19
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
Electrical Interface Area
Thermal Interface Area
Figure 7. System Mounting Interface Loads
6.10 Micromirror Array Physical Characteristics
Table 2. Micromirror Array Physical Characteristics
PARAMETER DESCRIPTION
Number of active columns
Number of active rows
(1)
(1)
Micromirror (pixel) pitch
(1)
Micromirror active array width
(1)
Micromirror active array height
(1)
Micromirror active border (top / bottom)
Micromirror active border (right / left)
(1)
(2)
20
(2)
(2)
VALUE
UNIT
M
1920
micromirrors
N
1080
micromirrors
P
5.4
µm
Micromirror pitch × number of active columns
10.368
mm
Micromirror pitch × number of active rows
5.832
mm
Pond of micromirrors (POM)
80
micromirrors/side
Pond of micromirrors (POM)
84
micromirrors/side
See Figure 8.
The structure and qualities of the border around the active array includes a band of partially functional micromirrors referred to as the
pond of micromirrors (POM). These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state
but still require an electrical bias to tilt toward the OFF state.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
0
1
2
3
M
M
M
M
±
±
±
±
4
3
2
1
Off-State
Light Path
0
1
2
3
Active Micromirror Array
NxP
M x N Micromirrors
N± 4
N± 3
N± 2
N± 1
MxP
P
Incident
Illumination
Light Path
P
P
Pond Of Micromirrors (POM) omitted for clarity.
Details omitted for clarity.
Not to scale.
P
Figure 8. Micromirror Array Physical Characteristics
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
21
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
6.11 Micromirror Array Optical Characteristics
Table 3. Micromirror Array Optical Characteristics
PARAMETER
Mirror tilt angle, variation device to device (1) (2)
MIN
(3) (4)
NOM
15.6
Adjacent micromirrors
Number of out-of-specification micromirrors
(1)
(2)
(3)
(4)
(5)
(5)
17.0
MAX
UNIT
18.4
degrees
0
Non-Adjacent
micromirrors
micromirrors
10
Measured relative to the plane formed by the overall micromirror array.
Variation can occur between any two individual mircromirrors located on the same device or located on different devices.
Additional variation exists between the micromirror array and the package datums. See package drawing.
See Figure 9.
An out-of-specification micromirror is defined as a micromirror that is unable to transition between the two landed states.
Off State
Light Path
Not to scale.
0
1
2
3
M
M
M
M
±
±
±
±
Details omitted for clarity.
4
3
2
1
Border micromirrors omitted for clarity
0
1
2
3
Tilted Axis of
Pixel Rotation
Off-State
Landed Edge
On-State
Landed Edge
N± 4
N± 3
N± 2
N± 1
Incident
Illumination
Light Path
(1)
Pond of micromirrors (POM) omitted for clarity.
(2)
Refer to section Micromirror Array Physical Characteristics table for M, N, and P specifications.
Figure 9. Micromirror Landed Orientation and Tilt
22
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
6.12 Window Characteristics
Table 4. DMD Window Characteristics
DESCRIPTION
MIN
Window material
Window refractive index at 546.1 nm
1.5119
Window transmittance, minimum within the wavelength range 420-680 nm. Applies to all angles 0°-30°
AOI. (1) (2)
Window transmittance, average over the wavelength range 420-680 nm. Applies to all angles 30°-45° AOI.
(1) (2)
(1)
(2)
NOM
Corning Eagle XG
97%
97%
Single-pass through both surfaces and glass.
Angle of incidence (AOI) is the angle between an incident ray and the normal to a reflecting or refracting surface.
6.13 Chipset Component Usage Specification
Reliable function and operation of the DLP470TE DMD requires that it be used in conjunction with the other
components of the applicable DLP chipset, including those components that contain or implement TI DMD
control technology. TI DMD control technology consists of the TI technology and devices used for operating or
controlling a DLP DMD.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
23
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
7 Detailed Description
7.1 Overview
The DMD is a 0.47-inch diagonal spatial light modulator which consists of an array of highly reflective aluminum
micromirrors. The DMD is an electrical input, optical output micro-electrical-mechanical system (MEMS). The
electrical interface is low voltage differential signaling (LVDS). The DMD consists of a two-dimensional array of 1bit CMOS memory cells. The array is organized in a grid of M memory cell columns by N memory cell rows.
Refer to the Functional Block Diagram. The positive or negative deflection angle of the micromirrors can be
individually controlled by changing the address voltage of underlying CMOS addressing circuitry and micromirror
reset signals (MBRST).
The DLP470TE DMD is part of the chipset is comprised of the DLP470TE DMD, the DLPC4422 display
controller, and the DLPA100 power and motor driver. To ensure reliable operation, the DLP470TE DMD must
always be used with the DLPC4422 display controller and the DLPA100 power and motor driver.
DATA_A
SCTRL_A
DCLK_A
VSS
VCC
VOFFSET
VRESET
VBIAS
MBRST
PWRDNZ
SCP
7.2 Functional Block Diagram
Channel A Interface
Column Read and Write
Control
Bit Lines
Control
(0,0)
Voltages
Word Lines
Micromirror Array
Bit Lines
Row
(M-1, N-1)
Bit Lines
Voltage
Generators
Column Read and Write
Control
Control
DATA_B
SCTRL_B
DCLK_B
VSS
VCC
VOFFSET
VRESET
VBIAS
MBRST
RESET_CTRL
Channel B Interface
Channels C and D not shown. For pin details on channels A, B, C, and D, refer to the Pin Configurations and
Functions table and the LVDS interface section of Timing Requirements.
24
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
7.3 Feature Description
7.3.1 Power Interface
The DMD requires five DC voltages: DMD_P3P3V, DMD_P1P8V, VOFFSET, VRESET, and VBIAS. DMD_P3P3V is
created by the DLPA100 power and motor driver and is used on the DMD board to create the other 4 DMD
voltages, as well as powering various peripherals (TMP411, I2C, and TI level translators). DMD_P1P8V is
created by the TI PMIC LP38513S and provides the VCC voltage required by the DMD. VOFFSET (10 V), VRESET
(–14 V), and VBIAS (18 V) are made by the TI PMIC TPS65145 and are supplied to the DMD to control the
micromirrors.
7.3.2 Timing
The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. Figure 4 shows an equivalent test load circuit for the output
under test. Timing reference loads are not intended as a precise representation of any particular system
environment or depiction of the actual load presented by a production test. System designers should use IBIS or
other simulation tools to correlate the timing reference load to a system environment. The load capacitance value
stated is only for characterization and measurement of AC timing signals. This load capacitance value does not
indicate the maximum load the device is capable of driving.
7.4 Device Functional Modes
DMD functional modes are controlled by the DLPC4422 display controller. See the DLPC4422 display controller
data sheet or contact a TI applications engineer.
7.5 Optical Interface and System Image Quality Considerations
TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment
optical performance involves making trade-offs between numerous component and system design parameters.
System optical performance and image quality strongly relate to optical system design parameter trade offs.
Although it is not possible to anticipate every conceivable application, projector image quality and optical
performance is contingent on compliance to the optical system operating conditions described in the following
sections.
7.5.1 Numerical Aperture and Stray Light Control
The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area
should be the same. This angle should not exceed the nominal device micromirror tilt angle unless appropriate
apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the
projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any
other light path, including undesirable flat-state specular reflections from the DMD window, DMD border
structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture
exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger
than the illumination numerical aperture angle (and vice versa), contrast degradation, and objectionable artifacts
in the display border and/or active area could occur.
7.5.2 Pupil Match
TI’s optical and image quality specifications assume that the exit pupil of the illumination optics is nominally
centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable
artifacts in the display border or active area, which may require additional system apertures to control, especially
if the numerical aperture of the system exceeds the pixel tilt angle.
7.5.3 Illumination Overfill
The active area of the device is surrounded by an aperture on the inside DMD window surface that masks
structures of the DMD chip assembly from normal view, and is sized to anticipate several optical operating
conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window
aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system
should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately
10% of the average flux level in the active area. Depending on the particular system optical architecture, overfill
light may have to be further reduced below the suggested 10% level in order to be acceptable.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
25
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
7.6 Micromirror Array Temperature Calculation
Array
TP2
2X 11.75
TP5
TP4
2X 16.10
TP3
Window Edge
(4 surfaces)
TP3 (TP2)
TP4
TP5
TP1
5.05
16.10
TP1
Figure 10. DMD Thermal Test Points
26
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
Micromirror Array Temperature Calculation (continued)
Micromirror array temperature can be computed analytically from measurement points on the outside of the
package, the package thermal resistance, the electrical power, and the illumination heat load. The relationship
between micromirror array temperature and the reference ceramic temperature is provided by the following
equations:
TARRAY = TCERAMIC + (QARRAY × RARRAY-TO-CERAMIC)
QARRAY = QELECTRICAL + QILLUMINATION)
where
•
•
•
•
•
•
•
•
TARRAY = computed array temperature (°C)
TCERAMIC = measured ceramic temperature (°C) (TP1 location)
RARRAY-TO-CERAMIC = thermal resistance of package from array to ceramic TP1 (°C/Watt)
QARRAY = Total DMD power on the array (Watts) (electrical + absorbed)
QELECTRICAL = nominal electrical power
QILLUMINATION = (CL2W × SL)
CL2W = Conversion constant for screen lumens to power on DMD (Watts/Lumen)
SL = measured screen lumens
The electrical power dissipation of the DMD is variable and depends on the voltages, data rates and operating
frequencies. A nominal electrical power dissipation to use when calculating array temperature is 0.9 Watts. The
absorbed power from the illumination source is variable and depends on the operating state of the micromirrors
and the intensity of the light source. The equations shown above are valid for a 1-Chip DMD system with
projection efficiency from the DMD to the screen of 87%.
The conversion constant CL2W is based on array characteristics. It assumes a spectral efficiency of 300
lumens/Watt for the projected light and illumination distribution of 83.7% on the active array, and 16.3% on the
array border.
Sample calculations for typical projection application:
QELECTRICAL = 0.9 W
CL2W = 0.00266
SL = 4000 lm
TCERAMIC = 55.0°C
QARRAY = 0.9 W + (0.00266 × 4000 lm) = 11.54 W
TARRAY = 55.0°C + (11.54 W × 0.90°C/W) = 65.39°C
7.7 Micromirror Landed-On/Landed-Off Duty Cycle
7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a
percentage) that an individual micromirror is landed in the ON state versus the amount of time the same
micromirror is landed in the OFF state.
As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the ON state 100% of the
time (and in the OFF state 0% of the time), whereas 0/100 would indicate that the pixel is in the OFF state 100%
of the time. Likewise, 50/50 indicates that the pixel is ON for 50% of the time (and OFF for 50% of the time).
Note that when assessing the landed duty cycle, the time spent switching from one state (ON or OFF) to the
other state (OFF or ON) is considered negligible and is thus ignored.
Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages)
always add to 100.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
27
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
Micromirror Landed-On/Landed-Off Duty Cycle (continued)
7.7.2 Landed Duty Cycle and Useful Life of the DMD
Knowing the long-term average landed duty cycle (of the end product or application) is important because
subjecting all (or a portion) of the DMD micromirror array (also called the active array) to an asymmetric landed
duty cycle for a prolonged period of time can reduce the DMD usable life.
Note that it is the symmetry or asymmetry of the landed duty cycle that is of relevance. The symmetry of the
landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a
landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly
asymmetrical.
7.7.3 Landed Duty Cycle and Operational DMD Temperature
Operational DMD temperature and landed duty cycle interact to affect DMD usable life, and this interaction can
be exploited to reduce the impact that an asymmetrical landed duty cycle has on the DMD usable life. This is
quantified in the de-rating curve shown in Figure 1. The importance of this curve is that:
• All points along this curve represent the same usable life.
• All points above this curve represent lower usable life (and the further away from the curve, the lower the
usable life).
• All points below this curve represent higher usable life (and the further away from the curve, the higher the
usable life).
In practice, this curve specifies the maximum operating DMD temperature at a given long-term average landed
duty cycle.
7.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
During a given period of time, the landed duty cycle of a given pixel follows from the image content being
displayed by that pixel.
For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel
operates under a 100/0 landed duty cycle during that time period. Likewise, when displaying pure-black, the pixel
operates under a 0/100 landed duty cycle.
Between the two extremes (ignoring for the moment color and any image processing that may be applied to an
incoming image), the landed duty cycle tracks one-to-one with the; gray scale value, as shown in Table 5.
Table 5. Grayscale Value and Landed Duty Cycle
28
GRAYSCALE VALUE
LANDED DUTY CYCLE
0%
0/100
10%
10/90
20%
20/80
30%
30/70
40%
40/60
50%
50/50
60%
60/40
70%
70/30
80%
80/20
90%
90/10
100%
100/0
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from
0% to 100%) for each constituent primary color (red, green, or blue) for the given pixel as well as the color cycle
time for each primary color, where “color cycle time” is the total percentage of the frame time that a given primary
must be displayed in order to achieve the desired white point.
Use the following equation to calculate the landed duty cycle of a given pixel during a specified time period
Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_%
× Blue_Scale_Value)
where
•
•
•
Red_Cycle_% represents the percentage of the frame time that red is displayed to achieve the desired white
point
Green_Cycle_% represents the percentage of the frame time that green is displayed to achieve the desired
white point
Blue_Cycle_% represents the percentage of the frame time that blue is displayed to achieve the desired white
point
For example, assume that the red, green, and blue color cycle times are 50%, 20%, and 30% respectively (in
order to achieve the desired white point), then the landed duty cycle for various combinations of red, green, and
blue color intensities would be as shown in Table 6 and Table 7.
Table 6. Example Landed Duty Cycle for Full-Color,
Color Percentage
CYCLE PERCENTAGE
RED
GREEN
BLUE
50%
20%
30%
Table 7. Example Landed Duty Cycle for Full-Color
SCALE VALUE
RED
GREEN
BLUE
LANDED DUTY
CYCLE
0%
0%
0%
0/100
100%
0%
0%
50/50
0%
100%
0%
20/80
0%
0%
100%
30/70
12%
0%
0%
6/94
0%
35%
0%
7/93
0%
0%
60%
18/82
100%
100%
0%
70/30
0%
100%
100%
50/50
100%
0%
100%
80/20
12%
35%
0%
13/87
0%
35%
60%
25/75
12%
0%
60%
24/76
100%
100%
100%
100/0
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
29
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
8 Application and Implementation
NOTE
Information in the following application section is not part of the TI component
specifications, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Texas Instruments DLP® technology is a micro-electro-mechanical systems (MEMS) technology that modulates
light using a digital micromirror device (DMD). The DMD is a spatial light modulator, which reflects incoming light
from an illumination source to one of two directions, towards the projection optics or collection optics. The new
TRP pixel with a higher tilt angle increases brightness performance and enables smaller system electronics for
size constrained applications. Typical applications using the DLP470NE include home theater, digital signage,
interactive displays, low-latency gaming displays, and portable smart displays.
The most recent class of chipsets from Texas Instruments is based on a breakthrough micromirror technology
called TRP. With a smaller pixel pitch of 5.4 µm and increased tilt angle of 17 degrees, TRP chipsets enable
higher resolution in a smaller form factor and enhanced image processing features while maintaining high optical
efficiency. DLP® chipsets are a great fit for any system that requires high resolution and high brightness displays.
8.2 Typical Application
The DLP470TE DMD combined with two display controllers (DLPC4422), an FPGA, a power management
device (DLPA100), and other electrical, optical, and mechanical components, enables bright, affordable, full 4K
UHD display solutions. A typical 4K UHD system application using the DLP470TE DMD is shown in Figure 11.
1.1V
1.8V
DLPA100 2.5V
(Asic
3.3V
CTRL Voltages) 5V
Signals
Colorwheel 2 Motor CTRL
FLASH
1.1V
1.8V
DLPA100 2.5V
(Asic
3.3V
CTRL Voltages) 5V
Signals
Colorwheel 1 Motor CTRL
Lamp Ballast
DATA
ADDR
Connector
MUX
FPGA
BD, Field, CLK,
DE, H/V-Synch
DLPC4422
Master Asic
HBT
SPI
LVDS West
(960x1080 @ 240Hz)
DAD CTRL and
SCP CTRL
I2C
Flex
ASIC TPs
TEST GPIO
GPIO Lines
Config. Lines
DATA
DLPC4422
Master Asic
DATA
DDR3
LVDS East
(960x1080 @ 240Hz)
Flex
ADDR
3.3V
TSP65145
(DMD
Voltages)
Level
Translators
JTAG
DATA
ASIC TPs
Test GPIO
FE Bypass
Input from Front End Board
Vx1 3840x2160 @ 60Hz
FE CTRL
10V
-14V
18V
DLP470TE
DMD
TMP411
Temperature
Sensor
JTAG
FLASH
DATA
ADDR
Optical
Actuator
Electronics
Optical
Actuator
Figure 11. Typical 4K UHD Application Diagram
30
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
8.2.1 Design Requirements
A DLP470TE projection system is created by using the DMD chipset, including the DLP470TE, DLPC4422, and
DLPA100. The DLP470TE is used as the core imaging device in the display system and contains a 0.47-inch
array of micromirrors. The DLPC4422 controller is the digital interface between the DMD and the rest of the
system, taking digital input from front end receiver and driving the DMD over a high speed interface. The
DLPA100 power management device provides voltage regulators for the DMD, controller, and illumination
functionality.
Other core components of the display system include an FPGA, illumination source, an optical engine for the
illumination and projection optics, other electrical and mechanical components, and software. The illumination
source options include lamp, LED, laser, or laser phosphor. The type of illumination used and desired brightness
will have a major effect on the overall system design and size.
8.2.2 Detailed Design Procedure
For a complete DLP® system, an optical module or light engine is required that contains the DLP470TE DMD,
associated illumination sources, optical elements, and necessary mechanical components.
To ensure reliable operation, the DLP470TE DMD must always be used with the DLPC4422 display controller
and the DLPA100 PMIC driver. Refer to the PCB design requirements to see DLP® standard TRP digital
micromirror devices for the DMD board design and manufacturer handling of the DMD sub-assemblies.
8.2.3 Application Curves
When LED illumination is utilized, the typical LED-current-to-luminance relationship is shown in Figure 12.
Figure 12. Luminance vs. Current
8.3 DMD Die Temperature Sensing
The DMD features a built-in thermal diode that measures the temperature at one corner of the die outside the
micromirror array. The thermal diode can be interfaced with the TMP411 temperature sensor as shown in
Figure 13. The serial bus from the TMP411 can be connected to the DLPC4422 display controller to enable its
temperature sensing features. See the DLPC4422 Programmers’ Guide for instructions on installing the
DLPC4422 controller support firmware bundle and obtaining the temperature readings.
The software application contains functions to configure the TMP411 to read the DMD temperature sensor diode.
This data can be leveraged to incorporate additional functionality in the overall system design such as adjusting
illumination, fan speeds, and so forth. All communication between the TMP411 and the DLPC4422 controller will
be completed using the I2C interface. The TMP411 connects to the DMD via pins B17 and B18 as outlined in Pin
Configuration and Functions.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
31
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
DMD Die Temperature Sensing (continued)
3.3V
R2
To Application Controller
R1
TMP411
DLP470TE
SCL
VCC
SDA
D+
R3
R5
TEMP_P
ALERT
C1
THERM
R4
GND
R6
DTEMP_N
GND
(1)
Details omitted for clarity, see the TI Reference Design for connections to the DLPC4422 controller.
(2)
See the TMP411 datasheet for system board layout recommendation.
(3)
See the TMP411 datasheet and the TI reference design for suggested component values for R1, R2, R3, R4, and C1.
(4)
R5 = 0 Ω. R6 = 0 Ω. Zero ohm resistors should be located close to the DMD package pins.
Figure 13. TMP411 Sample Schematic
32
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
9 Power Supply Recommendations
The following power supplies are all required to operate the DMD:
• VSS
• VBIAS
• VCC
• VOFFSET
• VRESET
DMD power-up and power-down sequencing is strictly controlled by the DLP® display controller.
CAUTION
For reliable operation of the DMD, the following power supply sequencing
requirements must be followed. Failure to adhere to any of the prescribed power-up
and power-down requirements may affect device reliability. See Figure 14.
VBIAS, VCC, VOFFSET, and VRESET power supplies must be coordinated during power-up
and power-down operations. Failure to meet any of the below requirements will result
in a significant reduction in the DMD reliability and lifetime. Common ground VSS must
also be connected.
9.1 DMD Power Supply Power-Up Procedure
•
•
•
•
•
During power-up, VCC must always start and settle before VOFFSET plus Delay1 specified in Table 8, VBIAS, and
VRESET voltages are applied to the DMD.
During power-up, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in Recommended Operating Conditions.
During power-up, there is no requirement for the relative timing of VRESET with respect to VBIAS.
Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the
requirements specified in the Absolute Maximum Ratings, in the Recommended Operating Conditions, and in
Figure 14.
During power-up, LVCMOS input pins must not be driven high until after VCC have settled at operating
voltages listed in the Recommended Operating Conditions.
9.2 DMD Power Supply Power-Down Procedure
•
•
•
•
•
During power-down, VCC must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within the
specified limit of ground. See Table 8.
During power-down, it is a strict requirement that the voltage difference between VBIAS and VOFFSET must be
within the specified limit shown in the Recommended Operating Conditions.
During power-down, there is no requirement for the relative timing of VRESET with respect to VBIAS.
Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the
requirements specified in the Absolute Maximum Ratings, in the Recommended Operating Conditions, and in
Figure 14.
During power-down, LVCMOS input pins must be less than specified in the Recommended Operating
Conditions.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
33
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
DMD Power Supply Power-Down Procedure (continued)
Not to scale. Details omitted for clarity
Note 1
VCC
VSS
VOFFSET
Note 4
Delay 1
Note 2
ûV < Specification
VSS
VBIAS
VSS
Note 3
ûV < Specification
VRESET
VSS
EN_OFFSET
VSS
Note 9
Delay 2
PG_OFFSET
Note 5
Note 7
VSS
RESET_OEZ
VSS
Note 6
Note 8
PWRDNZ
and RESETZ
VSS
(1)
See Recommended Operating Conditions, and the Pin Functions table.
(2)
To prevent excess current, the supply voltage difference |VOFFSET – VBIAS| must be less than the specified limit in the
Recommended Operating Conditions
(3)
To prevent excess current, the supply difference |VBIAS – VRESET| must be less than the specified limit in the
Recommended Operating Conditions.
(4)
VBIAS should power up after VOFFSET has powered up, per the Delay1 specification in Table 8
(5)
PG_OFFSET should turn off after EN_OFFSET has turned off, per the Delay2 specification in Table 8.
(6)
DLP® controller software enables the DMD power supplies VBIAS, VRESET, VOFFSET with VCC active after RESET_OEZ
is at logic high.
(7)
DLP® controller software initiates the global VBIAS command.
(8)
After the DMD micromirror park sequence is complete, the DLP® controller software initiates a hardware power-down
that activates PWRDNZ and disables VBIAS, VRESET, and VOFFSET.
(9)
Under power-loss conditions where emergency DMD micromirror park procedures are being enacted by the DLP®
controller hardware, EN_OFFSET may turn off after PG_OFFSET has turned off. The OEZ signal goes high prior to
PG_OFFSET turning off to indicate the DMD micromirror has completed the emergency park procedures.
Figure 14. DMD Power Supply Requirements
34
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
DMD Power Supply Power-Down Procedure (continued)
Table 8. DMD Power-Supply Requirements
PARAMETER
DESCRIPTION
Delay1
Delay from VOFFSET settled at recommended operating voltage to
VBIAS and VRESET power up
Delay2
PG_OFFSET hold time after EN_OFFSET goes low
MIN
NOM
1
2
MAX
100
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
UNIT
ms
ns
35
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
10 Layout
10.1 Layout Guidelines
The DLP470TE DMD is part of a chipset that is controlled by the DLPC4422 display controller in conjunction with
the DLPA100 power and motor driver. These guidelines are targeted at designing a PCB board with the
DLP470TE DMD. The DLP470TE DMD board is a high-speed multi-layer PCB, with primarily high-speed digital
logic utilizing dual edge clock rates up to 400MHz for DMD LVDS signals. The remaining traces are comprised of
low speed digital LVTTL signals. TI recommends that mini power planes are used for VOFFSET, VRESET, and
VBIAS. Solid planes are required for DMD_P3P3V(3.3V), DMD_P1P8V and Ground. The target impedance for
the PCB is 50 Ω ±10% with the LVDS traces being 100 Ω ±10% differential. TI recommends using an 8 layer
stack-up as described in Table 9.
10.2 Layout Example
10.2.1 Layers
The layer stack-up and copper weight for each layer is shown in Table 9. Small sub-planes are allowed on signal
routing layers to connect components to major sub-planes on top/bottom layers if necessary.
Table 9. Layer Stack-Up
LAYER
NO.
COPPER WT.
(oz.)
LAYER NAME
1.5
COMMENTS
1
Side A - DMD only
2
Ground
1
3
Signal
0.5
4
Ground
1
Solid ground plane (net GND)
5
DMD_P3P3V
1
+3.3-V power plane (net DMD_P3P3V)
6
Signal
0.5
7
Ground
1
8
Side B - All other Components
1.5
DMD, escapes, low frequency signals, power sub-planes.
Solid ground plane (net GND).
50 Ω and 100 Ω differential signals
50 Ω and 100 Ω differential signals
Solid ground plane (net GND).
Discrete components, low frequency signals, power sub-planes
10.2.2 Impedance Requirements
TI recommends that the board has matched impedance of 50 Ω ±10% for all signals. The exceptions are listed in
Table 10.
Table 10. Special Impedance Requirements
Signal Type
Signal Name
Impedance (ohms)
D_AP(0:15), D_AN(0:15)
A channel LVDS differential pairs
DCLKA_P, DCLKA_N
100 ±10% differential across
each pair
SCTRL_AP, SCTRL_AN
D_BP(0:15), D_BN(0:15)
B channel LVDS differential pairs
DCLKB_P, DCLKB_N
100 ±10% differential across
each pair
SCTRL_BP, SCTRL_BN
D_CP(0:15), D_CN(0:15)
C channel LVDS differential pairs
DCLKC_P, DCLKC_N
100 ±10% differential across
each pair
SCTRL_CP, SCTRL_CN
D_DP(0:15), D_DN(0:15)
D channel LVDS differential pairs
DCLKD_P, DCLKD_N
100 ±10% differential across
each pair
SCTRL_DP, SCTRL_DN
36
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
10.2.3 Trace Width, Spacing
Unless otherwise specified, TI recommends that all signals follow the 0.005”/0.005” design rule. Minimum trace
clearance from the ground ring around the PWB has a 0.1” minimum. An analysis of impedance and stack-up
requirements determine the actual trace widths and clearances.
10.2.3.1 Voltage Signals
Table 11. Special Trace Widths, Spacing Requirements
SIGNAL NAME
MINIMUM TRACE WIDTH TO
PINS (MIL)
LAYOUT REQUIREMENT
GND
15
Maximize trace width to connecting pin
DMD_P3P3V
15
Maximize trace width to connecting pin
DMD_P1P8V
15
Maximize trace width to connecting pin
VOFFSET
15
Create mini plane from U2 to U3
VRESET
15
Create mini plane from U2 to U3
VBIAS
15
Create mini plane from U2 to U3
All U3 control
connections
10
Use 10 mil etch to connect all signals/voltages to DMD pads
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
37
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
DLP470TE AA FXJ
Package
TI Internal Numbering
Device Descriptor
Figure 15. Part Number Description
11.1.2 Device Markings
The device marking includes both human-readable information and a 2-dimensional matrix code. The humanreadable information is described in Figure 16. The 2-dimensional matrix code is an alpha-numeric character
string that contains the DMD part number, part 1 of the serial number, and part 2 of the serial number. The first
character of the DMD serial number (part 1) is the manufacturing year. The second character of the DMD serial
number (part 1) is the manufacturing month. The last character of the DMD Serial Number (part 2) is the bias
voltage bin letter.
Example: *1910-553AB GHXXXXX LLLLLLM
2-Dimension Matrix Code
(Part Number and Serial Number)
DMD Part Number
*1910-553xB
GHXXXXX LLLLLLM
Part 1 of Serial Number
(7 characters)
Part 2 of Serial Number
(7 characters)
Figure 16. DMD Marking Locations
38
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
DLP470TE
www.ti.com
DLPS161 – APRIL 2019
11.2 Documentation Support
11.2.1 Related Documentation
The following documents contain additional information related to the chipset components used with the
DLP470TE.
• DLPC4422 Display Controller Data Sheet
• DLPA100 Power Management and Motor Driver Data Sheet
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
39
DLP470TE
DLPS161 – APRIL 2019
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
40
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Product Folder Links: DLP470TE
PACKAGE OPTION ADDENDUM
www.ti.com
18-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
DLP470TEAAFXJ
ACTIVE
CLGA
FXJ
257
33
RoHS &
non-Green
Call TI
Call TI
DLP470TEFXJ
LIFEBUY
CLGA
FXJ
257
33
RoHS &
non-Green
Call TI
N / A for Pkg Type
Op Temp (°C)
Device Marking
(4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
