DLP471TP
DLPS173B – AUGUST 2020 – REVISED JULY 2023
DLP471TP .47 4K UHD DMD
1 Features
3 Description
•
The DLP471TP digital micromirror device (DMD) is
a digitally controlled micro-electro-mechanical system
(MEMS) spatial light modulator (SLM) that enables
bright 4K UHD display systems. The TI DLP®
products 0.47” 4K UHD chipset is composed of the
DMD, DLPC6540 display controller, and DLPA3005
PMIC and LED driver. The compact physical size of
the chipset provides a complete system solution that
enables small form factor 4K UHD displays.
•
•
•
•
0.47-Inch diagonal micromirror array
– 4K UHD (3840 × 2160) display resolution
– 5.4-µm micromirror pitch
– ±17° micromirror tilt (relative to flat surface)
– Bottom illumination
High-speed serial interface (HSSI) input data bus
Supports 4K UHD at 60 Hz
Supports 1080p up to 240 Hz
LED operation supported by DLPC6540 display
controller, DLPA3005 power management IC
(PMIC) and LED driver
Device Information(1)
PART NUMBER
2 Applications
•
•
•
DLP471TP
Mobile smart TV
Mobile projector
Digital signage
(1)
PACKAGE
FQQ (270)
BODY SIZE (NOM)
25.65 mm × 16.9 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
LS_Interface
HSSI Macro A Data Pair
8
DMD DCLKA
HSSI Macro B Data Pair
8
DMD DCLKB
Vx1
DLPC6540
Display Controller
VOFFSET
2
I C/SPI
Power
Management
DLP471TP
HSSI DMD
VBIAS
VRESET
VREG
1.8 V
Simplified Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLP471TP
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DLPS173B – AUGUST 2020 – REVISED JULY 2023
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 8
6.1 Absolute Maximum Ratings........................................ 8
6.2 Storage Conditions..................................................... 9
6.3 ESD Ratings............................................................... 9
6.4 Recommended Operating Conditions.........................9
6.5 Thermal Information.................................................. 11
6.6 Electrical Characteristics...........................................11
6.7 Switching Characteristics..........................................13
6.8 Timing Requirements................................................ 14
6.9 System Mounting Interface Loads............................ 17
6.10 Micromirror Array Physical Characteristics............. 18
6.11 Micromirror Array Optical Characteristics............... 19
6.12 Window Characteristics.......................................... 21
6.13 Chipset Component Usage Specification............... 21
7 Detailed Description......................................................22
7.1 Overview................................................................... 22
7.2 Functional Block Diagram......................................... 22
7.3 Feature Description...................................................23
7.4 Device Functional Modes..........................................23
7.5 Optical Interface and System Image Quality
Considerations............................................................ 23
7.6 Micromirror Array Temperature Calculation.............. 24
7.7 Micromirror Power Density Calculation.....................25
7.8 Micromirror Landed-On/Landed-Off Duty Cycle....... 28
8 Application and Implementation.................................. 31
8.1 Application Information............................................. 31
8.2 Typical Application.................................................... 31
8.3 Temperature Sensor Diode....................................... 32
9 Power Supply Recommendations................................33
9.1 DMD Power Supply Power-Up Procedure................ 33
9.2 DMD Power Supply Power-Down Procedure........... 33
10 Layout...........................................................................35
10.1 Layout Guidelines................................................... 35
10.2 Impedance Requirements.......................................35
10.3 Layers..................................................................... 35
10.4 Trace Width, Spacing..............................................36
10.5 Power......................................................................36
10.6 Trace Length Matching Recommendations............ 37
11 Device and Documentation Support..........................38
11.1 Third-Party Products Disclaimer............................. 38
11.2 Device Support........................................................38
11.3 Documentation Support.......................................... 39
11.4 Support Resources................................................. 39
11.5 Trademarks............................................................. 39
11.6 Electrostatic Discharge Caution.............................. 39
11.7 Glossary.................................................................. 39
12 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (June 2022) to Revision B (July 2023)
Page
• Added section "ILLUMINATION" to Recommended Operating Conditions ....................................................... 9
• Updated Micromirror Array Temperature Calculation ...................................................................................... 24
• Added Micromirror Power DensityCalculation ................................................................................................. 25
Changes from Revision * (August 2020) to Revision A (June 2022)
Page
• This document is updated per the latest Texas Instruments and industry standards......................................... 1
• Updated |TDELTA| MAX from 14°C to 15°C..........................................................................................................9
• Updated Micromirror Array Optical Characteristics ......................................................................................... 19
• Updated Figure 9-1 ..........................................................................................................................................33
2
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5 Pin Configuration and Functions
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
3
1
2
5
4
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
25
24
Figure 5-1. FQQ Package 270-Pin CLGA (Bottom View)
Table 5-1. Pin Functions
PIN(2)
NAME
PAD ID
TYPE(1)
DESCRIPTION
TERMINATION
TRACE
LENGTH
(mm)
D_AP(0)
A8
I
High-speed Differential Data Pair lane A0
Differential 100 Ω
2.15873
D_AN(0)
A7
I
High-speed Differential Data Pair lane A0
Differential 100 Ω
2.16135
D_AP(1)
B2
I
High-speed Differential Data Pair lane A1
Differential 100 Ω
8.33946
D_AN(1)
C2
I
High-speed Differential Data Pair lane A1
Differential 100 Ω
8.34121
D_AP(2)
A6
I
High-speed Differential Data Pair lane A2
Differential 100 Ω
6.41271
D_AN(2)
A5
I
High-speed Differential Data Pair lane A2
Differential 100 Ω
6.41305
D_AP(3)
A10
I
High-speed Differential Data Pair lane A3
Differential 100 Ω
1.8959
D_AN(3)
A9
I
High-speed Differential Data Pair lane A3
Differential 100 Ω
1.8959
D_AP(4)
D1
I
High-speed Differential Data Pair lane A4
Differential 100 Ω
12.11543
D_AN(4)
E1
I
High-speed Differential Data Pair lane A4
Differential 100 Ω
12.11539
D_AP(5)
D3
I
High-speed Differential Data Pair lane A5
Differential 100 Ω
12.01561
D_AN(5)
E3
I
High-speed Differential Data Pair lane A5
Differential 100 Ω
12.0164
D_AP(6)
F3
I
High-speed Differential Data Pair lane A6
Differential 100 Ω
12.98403
D_AN(6)
G3
I
High-speed Differential Data Pair lane A6
Differential 100 Ω
12.98177
D_AP(7)
A12
I
High-speed Differential Data Pair lane A7
Differential 100 Ω
2.29773
D_AN(7)
A11
I
High-speed Differential Data Pair lane A7
Differential 100 Ω
2.29773
DCLK_AP
A3
I
High-speed Differential Clock A
Differential 100 Ω
11.75367
DCLK_AN
A4
I
High-speed Differential Clock A
Differential 100 Ω
11.57432
D_BP(0)
A14
I
High-speed Differential Data Pair lane B0
Differential 100 Ω
2.10786
D_BN(0)
A15
I
High-speed Differential Data Pair lane B0
Differential 100 Ω
2.10711
D_BP(1)
F23
I
High-speed Differential Data Pair lane B1
Differential 100 Ω
12.79448
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Table 5-1. Pin Functions (continued)
PIN(2)
NAME
4
PAD ID
TYPE(1)
DESCRIPTION
TRACE
LENGTH
(mm)
TERMINATION
D_BN(1)
G23
I
High-speed Differential Data Pair lane B1
Differential 100 Ω
12.79438
D_BP(2)
E24
I
High-speed Differential Data Pair lane B2
Differential 100 Ω
13.00876
D_BN(2)
E23
I
High-speed Differential Data Pair lane B2
Differential 100 Ω
13.00932
D_BP(3)
A22
I
High-speed Differential Data Pair lane B3
Differential 100 Ω
11.21886
D_BN(3)
A23
I
High-speed Differential Data Pair lane B3
Differential 100 Ω
11.21881
D_BP(4)
D25
I
High-speed Differential Data Pair lane B4
Differential 100 Ω
10.79038
D_BN(4)
D24
I
High-speed Differential Data Pair lane B4
Differential 100 Ω
10.78946
D_BP(5)
A20
I
High-speed Differential Data Pair lane B5
Differential 100 Ω
5.75986
D_BN(5)
A21
I
High-speed Differential Data Pair lane B5
Differential 100 Ω
5.75928
D_BP(6)
B24
I
High-speed Differential Data Pair lane B6
Differential 100 Ω
9.01461
D_BN(6)
B25
I
High-speed Differential Data Pair lane B6
Differential 100 Ω
9.01416
D_BP(7)
A18
I
High-speed Differential Data Pair lane B7
Differential 100 Ω
2.08767
D_BN(7)
A19
I
High-speed Differential Data Pair lane B7
Differential 100 Ω
2.08767
DCLK_BP
A17
I
High-speed Differential Clock B
Differential 100 Ω
2.12928
DCLK_BN
A16
I
High-speed Differential Clock B
Differential 100 Ω
2.30933
LS_WDATA_P
T16
I
LVDS Data
Differential 100 Ω
0
LS_WDATA_N
R16
I
LVDS Data
Differential 100 Ω
0.27407
LS_CLK_P
T14
I
LVDS CLK
Differential 100 Ω
2.43086
LS_CLK_N
R14
I
LVDS CLK
Differential 100 Ω
2.40852
LS_RDATA_A_BISTA
R18
O
LVCMOS Output
2.00263
BIST_B
T20
O
LVCMOS Output
4.61261
AMUX_OUT
C21
O
Analog Test Mux
3.03604
DMUX_OUT
R20
O
Digital Test Mux
DMD_DEN_ARSTZ
T18
I
ARSTZ
TEMP_N
R12
I
Temp Diode N
4.02546
TEMP_P
T12
I
Temp Diode P
3.62598
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2.88361
17.5-kΩ pulldown
1.89945
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Table 5-1. Pin Functions (continued)
PIN(2)
NAME
PAD ID
TYPE(1)
DESCRIPTION
TERMINATION
TRACE
LENGTH
(mm)
VDD
B13, C5,
C9, C12,
C15, C18,
C22, D6,
D7, D14,
D16, D19,
D20, E21,
G21, J4,
J21, J23,
K3, K22,
L2, L4,
L22, M1,
M3, M21,
M23, M25,
N2, N4, N6,
N8, N16,
N18, N20,
N22, N24,
P3, P5, P7,
P9, P11,
P13, P15,
P17, P19,
P21, P23,
P25, R2,
R4, R6, R8,
R10, T3,
T5, T7, T9,
T11, T13,
T15, T17,
T19, T21,
T23
P
Digital core supply voltage
Plane
VDDA
A24, B3,
B5, B7, B9,
B11, B14,
B16, B18,
B20, B22,
C1, C24,
D4, D23,
E2, F4,
F22, H3,
H22
P
HSSI supply voltage
Plane
VRESET
A2, R1
P
Supply voltage for negative bias of
micromirror reset signal
Plane
VBIAS
B1, P1
P
Supply voltage for positive bias of
micromirror reset signal
Plane
VOFFSET
A1, A25,
T1, T25
P
Supply voltage for HVCMOS logic, stepped
up logic level
Plane
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Table 5-1. Pin Functions (continued)
PIN(2)
NAME
6
PAD ID
TYPE(1)
DESCRIPTION
TERMINATION
TRACE
LENGTH
(mm)
VSS
C4, C6, C8,
C10, C13,
C14, C17,
C19, C23,
D5, D8,
D15, D17,
D18, D21,
D22, F21,
H4, H21,
J3, J22, K4,
K21, K23,
L3, L21,
L23, M2,
M4, M22,
M24, N1,
N3, N5, N7,
N17, N19,
N21, N23,
N25, P2,
P4, P6, P8,
P10, P12,
P14, P16,
P18, P20,
P22, P24,
R3, R5, R7,
R9, R11,
R13, R15,
R17, R19,
R21, R23,
R25, T2,
T4, T8, T10
G
Ground
Plane
VSSA
A13, B4,
B6, B8,
B10, B12,
B15, B17,
B19, B21,
B23, C3,
C7, C11,
C16, C20,
C25, D2,
E4, E22,
E25, F2,
G4, G22,
H23
G
Ground
Plane
DMD_Detect
T6
DMD detection
None
NC
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Table 5-1. Pin Functions (continued)
PIN(2)
NAME
N/C
(1)
(2)
PAD ID
D9, D10,
D11, D12,
D13, E10,
E11, E12,
E13, E14,
E15, E16,
E17, E18,
F24, G2,
K2, L24,
M12, M13,
M14, M15,
M16, M17,
M18, N9,
N10, N11,
N12, N13,
N14, N15,
R22,
R24 ,T22,
T24
TYPE(1)
NC
DESCRIPTION
No connect pin
TERMINATION
TRACE
LENGTH
(mm)
None
I=Input, O=Output, P=Power, G=Ground, NC = No Connect
Only 238 pins are electrically connected for functional use.
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6 Specifications
6.1 Absolute Maximum Ratings
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not
imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating
Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
MIN
MAX
UNIT
SUPPLY VOLTAGE
VDD
Supply voltage for LVCMOS core logic and LVCMOS low speed interface
(LSIF)(1)
–0.5
2.3
V
VDDA
Supply voltage for high speed serial interface (HSSI) receivers(1)
–0.3
2.2
V
VOFFSET
Supply voltage for HVCMOS and micromirror electrode(1) (2)
–0.5
11
V
VBIAS
Supply voltage for micromirror
electrode(1)
–0.5
19
V
VRESET
Supply voltage for micromirror electrode(1)
–15
0.5
V
| VDDA – VDD |
Supply voltage delta (absolute
value)(3)
0.3
V
| VBIAS – VOFFSET |
Supply voltage delta (absolute value)(4)
11
V
value)(5)
34
V
–0.5
2.45
V
–0.2
VDDA
V
| VBIAS – VRESET |
Supply voltage delta (absolute
INPUT VOLTAGE
Input voltage for other inputs – LSIF and LVCMOS(1)
Input voltage for other inputs –
HSSI(1) (6)
LOW SPEED INTERFACE (LSIF)
fCLOCK
LSIF clock frequency (LS_CLK)
130
MHz
| VID |
LSIF differential input voltage magnitude(6)
810
mV
IID
LSIF differential input current
10
mA
HIGH SPEED SERIAL INTERFACE (HSSI)
fCLOCK
HSSI clock frequency (DCLK)
1.65
GHz
| VID |
HSSI differential input voltage magnitude Data Lane(6)
700
mV
700
mV
0
90
°C
–40
90
°C
| VID |
HSSI differential input voltage magnitude Clock
Lane(6)
ENVIRONMENTAL
TWINDOW and TARRAY
Temperature, non-operating(7)
|TDELTA|
Absolute temperature delta between any point on the window edge and the
ceramic test point TP1(8)
30
°C
TDP
Dew point temperature, operating and non–operating (noncondensing)
81
°C
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
8
Temperature, operating(7)
All voltage values are with respect to the ground terminals (VSS). The following required power supplies must be connected for proper
DMD operation: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
VOFFSET supply transients must fall within specified voltages.
Exceeding the recommended allowable absolute voltage difference between VDDA and VDD may result in excessive current draw.
Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. LVDS and HSSI
differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
The highest temperature of the active array (as calculated using Micromirror Array Temperature Calculation) or of any point along the
window edge as defined in Figure 7-1. The locations of thermal test points TP2, TP3, TP4 and TP5 in Figure 7-1 are intended to
measure the highest window edge temperature. If a particular application causes another point on the window edge to be at a higher
temperature, that point should be used.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst case delta. If a
particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.
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6.2 Storage Conditions
Applicable for the DMD as a component or non-operating in a system.
TDMD
DMD temperature
TDP-AVG
Average dew point temperature, non-condensing(1)
non-condensing(2)
TDP-ELR
Elevated dew point temperature range,
CTELR
Cumulative time in elevated dew point temperature range
(1)
(2)
MIN
MAX
–40
85
°C
24
°C
28
UNIT
36
°C
6
months
The average temperature over time (including storage and operating temperatures) that the device is not in the elevated dew point
temperature range.
Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.
6.3 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic
discharge
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V
Charged device model (CDM), per JEDEC specification ANSI/ESDA/JEDEC
JS-002(2)
±500
V
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.4 Recommended Operating Conditions
Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the
device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended
Operating Conditions. No level of performance is implied when operating the device above or below the Recommended
Operating Conditions limits.
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGES (1) (2)
VDD
Supply voltage for LVCMOS core logic and low speed
interface (LSIF)
1.71
1.8
1.95
V
VDDA
Supply voltage for high speed serial interface (HSSI) receivers
1.71
1.8
1.95
V
VOFFSET
Supply voltage for HVCMOS and micromirror electrode(3)
9.5
10
10.5
V
VBIAS
Supply voltage for micromirror electrode
17.5
18
18.5
V
VRESET
Supply voltage for micromirror electrode
–14.5
–14
–13.5
V
value(4)
0.3
V
| VBIAS – VOFFSET | Supply voltage delta, absolute value(5)
10.5
V
33
V
| VDDA – VDD |
| VBIAS – VRESET |
Supply voltage delta, absolute
Supply voltage delta, absolute value
LVCMOS INPUT
VIH
High level input voltage(6)
VIL
Low level input voltage(6)
0.7 × VDD
V
0.3 × VDD
V
LOW SPEED SERIAL INTERFACE (LSIF)
fCLOCK
LSIF clock frequency (LS_CLK)(7)
DCDIN
LSIF duty cycle distortion (LS_CLK)
| VID |
LSIF differential input voltage magnitude(7)
150
VLVDS
LSIF voltage(7)
575
voltage(7)
108
120
44%
130
MHz
56%
350
440
mV
1520
mV
mV
VCM
Common mode
700
900
1300
ZLINE
Line differential impedance (PWB/trace)
90
100
110
Ω
ZIN
Internal differential termination resistance
80
100
120
Ω
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6.4 Recommended Operating Conditions (continued)
Over operating free-air temperature range and supply voltages (unless otherwise noted). The functional performance of the
device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended
Operating Conditions. No level of performance is implied when operating the device above or below the Recommended
Operating Conditions limits.
MIN
TYP
MAX
UNIT
1.6
GHz
56
%
100
600
mV
295
600
mV
HIGH SPEED SERIAL INTERFACE (HSSI)
fCLOCK
HSSI clock frequency (DCLK)(8)
1.2
DCDIN
HSSI duty cycle distortion (DCLK)
44
Lane(8)
| VID | Data
HSSI differential input voltage magnitude Data
| VID | CLK
HSSI differential input voltage magnitude Clock Lane(8)
Lane(8)
VCMDC Data
Input common mode voltage (DC) Data
VCMDC CLK
Input common mode voltage (DC) Clk Lane(8)
VCMACp-p
AC peak to peak (ripple) on common mode voltage of Data
Lane and Clock Lane(8)
ZLINE
Line differential impedance (PWB/trace)
ZIN
Internal differential termination resistance. ( RXterm )
80
Array temperature, long–term operational(9) (10) (11) (12)
50
200
600
800
mV
200
600
800
mV
100
mV
100
100
Ω
120
Ω
10
40 to 70 (11)
°C
0
ENVIRONMENTAL
TARRAY
Array temperature, short-term operational, 500 hr
max(10) (13)
10
°C
TWINDOW
Window temperature, operational(14)
85
°C
|TDELTA|
Absolute temperature delta between any point on the window
edge and the ceramic test point TP1(15)
15
°C
TDP-AVG
Average dew point temperature (non–condensing)(16)
24
°C
TDP-ELR
Elevated dew point temperature range (non-condensing)(17)
36
°C
CTELR
Cumulative time in elevated dew point temperature range
6
months
10
mW/cm2
28
ILLUMINATION
Illumination power at wavelengths < 410 nm(9)
ILLUV
ILLVIS
Illumination power at wavelengths ≥ 410 nm and ≤ 800
ILLIR
Illumination power at wavelengths > 800 nm
nm(19)
20.5
W/cm2
10
mW/cm2
ILLBLU
Illumination power at wavelengths ≥ 410 nm and ≤ 475
nm(19)
6.5
W/cm2
ILLBLU1
Illumination power at wavelengths ≥ 410 nm and ≤ 445 nm(19)
1.2
W/cm2
55
deg
ILLθ
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
10
Illumination marginal ray
angle(18)
All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are
required to operate the DMD.
All voltage values are with respect to the VSS ground pins.
VOFFSET supply transients must fall within specified max voltages.
To prevent excess current, the supply voltage delta | VDDA – VDD | must be less than specified limit.
To prevent excess current, the supply voltage delta | VBIAS – VOFFSET | must be less than specified limit.
LVCMOS input pin is DMD_DEN_ARSTZ.
See the low speed interface (LSIF) timing requirements in Timing Requirements.
See the high speed serial interface (HSSI) timing requirements in Timing Requirements.
Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will
reduce device lifetime.
The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point
(TP1) shown in Figure 7-1 and the package thermal resistance using the Micromirror Array Temperature Calculation.
Per Figure 6-1, the maximum operational array temperature should be derated based on the micromirror landed duty cycle that the
DMD experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed
duty cycle.
Long-term is defined as the usable life of the device.
Short-term is the total cumulative time over the useful life of the device.
The locations of thermal test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to measure the highest window edge
temperature. For most applications, the locations shown are representative of the highest window edge temperature. If a particular
application causes additional points on the window edge to be at a higher temperature, test points should be added to those locations.
Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in
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(16)
(17)
(18)
Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst case delta
temperature. If a particular application causes another point on the window edge to result in a larger delta in temperature, that point
should be used.
The average over time (including storage and operating) that the device is not in the ‘elevated dew point temperature range'.
Exposure to dew point temperatures in the elevated range during storage and operation should be limited to less than a total
cumulative time of CTELR.
The maximum marginal ray angle of the incoming illumination light at any point in the micromirror array, including Pond of Micromirrors
(POM), should not exceed 55 degrees from the normal to the device array plane. The device window aperture has not necessarily
been designed to allow incoming light at higher maximum angles to pass to the micromirrors, and the device performance has not
been tested nor qualified at angles exceeding this. Illumination light exceeding this angle outside the micromirror array (including POM)
will contribute to thermal limitations described in this document, and may negatively affect lifetime.
The maximum allowable optical power incident on the DMD is limited by the maximum optical power density for each wavelength
range specified and the micromirror array temperature (TARRAY).
Maximum Recommended Array Temperature - Operational (¹C)
(19)
DLPS173B – AUGUST 2020 – REVISED JULY 2023
80
70
60
50
40
30
0/100
5/95
10/90
15/85
20/80
25/75
30/70
35/65
40/60
45/55 50/50
100/0
95/5
90/10
85/15
80/20
75/25
70/30
65/35
60/40
55/45
50/50
Micromirror Landed Duty Cycle
Figure 6-1. Maximum Recommended Array Temperature—Derating Curve
6.5 Thermal Information
DLP471TP
THERMAL METRIC
Unit
FQQ PACKAGE
270 PIN
Thermal Resistance, active area to test point 1 (TP1)(1)
(1)
1.0
°C/W
The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of
maintaining the package within the temperature range specified in the Section 6.4. The total heat load on the DMD is largely driven by
the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and
electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window
clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.
6.6 Electrical Characteristics
Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETER (1) (2)
TEST CONDITIONS (1)
MIN
TYP
MAX UNIT
800
1200
CURRENT – TYPICAL
IDD
Supply current VDD (3)
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mA
11
DLP471TP
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DLPS173B – AUGUST 2020 – REVISED JULY 2023
6.6 Electrical Characteristics (continued)
Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETER (1) (2)
TEST CONDITIONS (1)
MIN
Supply current VDDA (3)
IDDA
(4) (5)
IOFFSET
Supply current VOFFSET
IBIAS
Supply current VBIAS (4) (5)
IRESET
Supply current VRESET
(5)
-9.3
TYP
MAX UNIT
1000
1200
mA
20
25
mA
2.5
4.0
mA
-6.9
mA
POWER – TYPICAL
PDD
Supply power dissipation VDD (3)
1440
2437.5
mW
PDDA
Supply power dissipation VDDA (3)
1620
2340
mW
230
367.5
mW
43.2
70.3
mW
107.8
152.25
mW
3441
5367.55
mW
(4) (5)
POFFSET
Supply power dissipation VOFFSET
PBIAS
Supply power dissipation VBIAS (4) (5)
PRESET
Supply power dissipation VRESET
PTOTAL
Supply power dissipation Total
(5)
LVCMOS INPUT
IIL
Low level input current (6)
IIH
(6)
High level input current
VDD = 1.95 V, VI = 0 V
–100
nA
VDD = 1.95 V, VI = 1.95 V
135
uA
LVCMOS OUTPUT
VOH
DC output high voltage (7)
IOH = -2 mA
VOL
DC output low voltage (7)
IOL = 2 mA
0.8 x VDD
V
0.2 x VDD
V
RECEIVER EYE CHARACTERISTICS
Minimum data eye opening (8) (9)
A1
100
(8) (9)
400
600
mV
A2
Maximum data signal swing
600
mV
X1
Maximum data eye closure (8)
0.275
UI
X2
Maximum data eye closure
(8)
0.4
UI
| tDRIFT |
Drift between Clock and Data between
Training Patterns
20
ps
CAPACITANCE
CIN
Input capacitance LVCMOS
f = 1 MHz
10
pF
CIN
Input capacitance LSIF (low speed
interface)
f = 1 MHz
20
pF
CIN
Input capacitance HSSI (high speed serial
f = 1 MHz
interface)
20
pF
COUT
Output capacitance
10
pF
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
12
f = 1 MHz
All power supply connections are required to operate the DMD: VDD, VDDA, VOFFSET, VBIAS, and VRESET. All VSS connections are
required to operate the DMD.
All voltage values are with respect to the ground pins (VSS).
To prevent excess current, the supply voltage delta | VDDA – VDD | must be less than specified limit.
To prevent excess current, the supply voltage delta | VBIAS – VOFFSET | must be less than specified limit.
Supply power dissipation based on 3 global resets in 200 µs.
LVCMOS input specifications are for pin DMD_DEN_ARSTZ.
LVCMOS output specification is for pins LS_RDATA_A and LS_RDATA_B.
Refer to Figure 6-11, Receiver Eye Mask (1e-12 BER).
Defined in Recommended Operating Conditions.
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DLPS173B – AUGUST 2020 – REVISED JULY 2023
6.7 Switching Characteristics
Over operating free-air temperature range and supply voltages (unless otherwise noted)
PARAMETER
tpd
(1)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output propagation, Clock to Q (C2Q), rising edge of
LS_CLK (differential clock signal) input to LS_RDATA
output. (1)
CL = 5 pF
11.1
ns
CL = 10 pF
11.3
ns
Slew rate, LS_RDATA
20%–80%, CL
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