DLP5530SAFYSQ1

DLP5530S-Q1 DLPS200B – JULY 2020 – REVISED APRIL 2021 DLP5530S-Q1 0.55-Inch 1.3-Megapixel DMD for Automotive Interior Display 1 Features 3 Description • The DLP5530S-Q1 automotive DMD, combined with the DLPC230S-Q1 DMD controller and TPS99000SQ1 system management and illumination controller, provides the capability to achieve a high performance augmented reality HUD. The 2:1 aspect ratio supports very wide aspect ratio designs, and the 1.3-MP resolution enables retinal limited displays to be achieved in HUD applications. The DLP5530S-Q1 has more than 3 times the optical throughput of the preceding DLP3030-Q1 automotive DMD enabling wider field of view and larger driver eye box for enhanced user experience. This chipset, coupled with LEDs and an optical system, enables deep saturated colors of 125% NTSC, extremely high brightness of more than 15,000 cd/m2, high dynamic dimming ratio more than 5000:1, and high solar load tolerance. The DLP5530S-Q1 automotive DMD micromirror array is configured for bottom illumination which enables highly efficient and more compact optical engine designs. The S450 package has low thermal resistance to the DMD array to enable more efficient thermal solutions. • • • • • • Qualified for automotive applications – –40°C to 105°C operating DMD array temperature range Functional Safety Quality-Managed – Documentation available to aid ISO 26262 functional safety system design up to ASIL-B The DLP5530S-Q1 automotive chipset includes: – DLP5530S-Q1 DMD – DLPC230S-Q1 – TPS99000S-Q1 system management and illumination controller 0.55-inch diagonal micromirror array – 7.6-μm micromirror pitch – ±12° micromirror tilt angle (relative to flat state) – Bottom illumination for optimal efficiency and optical engine size – Supports 1152 × 576 input resolution – Up to 2304 x 1152 resolution with external GPU based diamond pre-processing – Compatible with LED or laser illumination 600-MHz sub-LVDS DMD interface for low power and emission 10-kHz DMD refresh rate over temperature extremes Built-in self test of DMD memory cells Device Information PART NUMBER DLP5530S-Q1 2 Applications (1) • (2) • Wide field of view and augmented reality head-up display (HUD) Digital cluster, navigation, and infotainment windshield displays Voltage Monitor and Enables Power Regulation PACKAGE(1) (2) FYS (149) BODY SIZE (NOM) 22.30 mm × 32.20 mm For all available packages, see the orderable addendum at the end of the data sheet. This data sheet pertains to the specifications and application of this DMD in the head-up display application. Please see the DLP5531A-Q1 data sheet (DLPS075) for headlight specifications and application information. TPS99000S-Q1 1.1V 1.8V 3.3V 6.5V LED dimming SPI DLPC230S-Q1 ARM® Cortex®-R4F DMD power management VRESET DLP5530S-Q1 SubLVDS DMD video processing & control Video memory VOFFSET VBIAS Video LED ENABLE System diagnostics SPI TMP411 Temperature Sensor I2C SPI 0.55" DMD 2:1 aspect ratio 1.3M pixels Flash DLP5530S-Q1 DLP® Chipset System Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Pin Configuration and Functions...................................3 6 Specifications.................................................................. 8 6.1 Absolute Maximum Ratings ....................................... 8 6.2 Storage Conditions .................................................... 8 6.3 ESD Ratings .............................................................. 8 6.4 Recommended Operating Conditions ........................9 Illumination Overfill Diagram............................................. 9 6.5 Thermal Information .................................................10 6.6 Electrical Characteristics ..........................................10 6.7 Timing Requirements ............................................... 11 Electrical and Timing Diagrams.......................................11 6.8 Switching Characteristics .........................................14 LPSDR and Test Load Circuit Diagrams.........................14 6.9 System Mounting Interface Loads ........................... 15 System Interface Loads Diagram....................................15 6.10 Physical Characteristics of the Micromirror Array .. 15 Array Physical Characteristics Diagram..........................16 6.11 Micromirror Array Optical Characteristics .............. 17 6.12 Window Characteristics ......................................... 17 6.13 Chipset Component Usage Specification............... 17 7 Detailed Description......................................................18 7.1 Overview................................................................... 18 7.2 Functional Block Diagram......................................... 18 7.3 Feature Description...................................................19 7.4 System Optical Considerations.................................20 7.5 DMD Image Performance Specification....................22 7.6 Micromirror Array Temperature Calculation.............. 22 7.7 Micromirror Landed-On/Landed-Off Duty Cycle....... 24 8 Application and Implementation.................................. 25 8.1 Application Information............................................. 25 8.2 Typical Application.................................................... 25 9 Power Supply Recommendations................................28 9.1 Power Supply Power-Up Procedure......................... 28 9.2 Power Supply Power-Down Procedure.....................28 9.3 Power Supply Sequencing Requirements................ 29 10 Layout...........................................................................30 10.1 Layout Guidelines................................................... 30 11 Device and Documentation Support..........................31 11.1 Device Support........................................................31 11.2 Receiving Notification of Documentation Updates.. 31 11.3 Support Resources................................................. 31 11.4 Trademarks............................................................. 31 11.5 Electrostatic Discharge Caution.............................. 32 11.6 DMD Handling.........................................................32 11.7 Glossary.................................................................. 32 12 Mechanical, Packaging, and Orderable Information.................................................................... 32 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (October 2020) to Revision B (April 2021) Page • Updated Current and Power Consumption in Electrical Characteristics section................................................ 8 Changes from Revision * (August 2020) to Revision A (October 2020) Page • Changed device status from Advance Information to Production Data.............................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 5 Pin Configuration and Functions Figure 5-1. FYS Package 149-Pin CPGA Bottom View Pin Functions - Connector Pins PIN NAME NO. TYPE SIGNAL DATA RATE DESCRIPTION DATA INPUTS D_AN(0) L2 I SubLVDS Double Data, Negative D_AN(1) K2 I SubLVDS Double Data, Negative D_AN(2) J2 I SubLVDS Double Data, Negative D_AN(3) H2 I SubLVDS Double Data, Negative D_AN(4) F2 I SubLVDS Double Data, Negative D_AN(5) E2 I SubLVDS Double Data, Negative D_AN(6) D2 I SubLVDS Double Data, Negative D_AN(7) C2 I SubLVDS Double Data, Negative D_AP(0) L1 I SubLVDS Double Data, Positive D_AP(1) K1 I SubLVDS Double Data, Positive D_AP(2) J1 I SubLVDS Double Data, Positive D_AP(3) H1 I SubLVDS Double Data, Positive D_AP(4) F1 I SubLVDS Double Data, Positive D_AP(5) E1 I SubLVDS Double Data, Positive D_AP(6) D1 I SubLVDS Double Data, Positive D_AP(7) C1 I SubLVDS Double Data, Positive D_BN(0) K19 I SubLVDS Double Data, Negative D_BN(1) J19 I SubLVDS Double Data, Negative D_BN(2) H19 I SubLVDS Double Data, Negative D_BN(3) G19 I SubLVDS Double Data, Negative D_BN(4) E19 I SubLVDS Double Data, Negative D_BN(5) D19 I SubLVDS Double Data, Negative D_BN(6) C19 I SubLVDS Double Data, Negative D_BN(7) B19 I SubLVDS Double Data, Negative Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 3 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 Pin Functions - Connector Pins (continued) PIN TYPE SIGNAL DATA RATE K20 I SubLVDS Double Data, Positive J20 I SubLVDS Double Data, Positive D_BP(2) H20 I SubLVDS Double Data, Positive D_BP(3) G20 I SubLVDS Double Data, Positive D_BP(4) E20 I SubLVDS Double Data, Positive D_BP(5) D20 I SubLVDS Double Data, Positive D_BP(6) C20 I SubLVDS Double Data, Positive D_BP(7) B20 I SubLVDS Double Data, Positive DCLK_AN G2 I SubLVDS Double Clock, Negative DCLK_AP G1 I SubLVDS Double Clock, Positive DCLK_BN F19 I SubLVDS Double Clock, Negative DCLK_BP F20 I SubLVDS Double Clock, Positive LS_CLKN R3 I SubLVDS Single Clock for Low Speed Interface, Negative LS_CLKP T3 I SubLVDS Single Clock for Low Speed Interface, Positive LS_WDATAN R2 I SubLVDS Single Write Data for Low Speed Interface, Negative LS_WDATAP T2 I SubLVDS Single Write Data for Low Speed Interface, Positive DMD_DEN_ARSTZ T10 I LPSDR LS_RDATA_A T5 O LPSDR Single Read Data for Low Speed Interface LS_RDATA_B T6 O LPSDR Single Read Data for Low Speed Interface NAME NO. D_BP(0) D_BP(1) DESCRIPTION CONTROL INPUTS Asynchronous Reset Active Low. Logic High Enables DMD. TEMPERATURE SENSE DIODE TEMP_N P1 O TEMP_P N1 I VCCH A8 Ground VCCH A9 Ground VCCH A10 Ground VCCH B8 Ground VCCH B9 Ground VCCH B10 Ground VSSH A11 Ground VSSH A12 Ground VSSH A13 Ground VSSH B11 Ground VSSH B12 Ground VSSH B13 Ground Calibrated temperature diode used to assist accurate temperature measurements of DMD die. RESERVED PINS 4 Reserved Pin. Connect to Ground. Reserved Pin. Connect to Ground. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 Pin Functions - Connector Pins (continued) PIN NAME NO. TYPE SIGNAL DATA RATE DESCRIPTION POWER VBIAS T7 Power VBIAS T15 Power VOFFSET T9 Power VOFFSET T13 Power VOFFSET A5 Power VOFFSET B5 Power VOFFSET A16 Power VOFFSET B16 Power VRESET T8 Power VRESET T14 Power VDD R4 Power VDD R10 Power VDD R11 Power VDD R20 Power VDD N2 Power VDD M20 Power VDD L3 Power VDD K18 Power VDD H3 Power VDD G18 Power VDD E3 Power VDD D18 Power VDD C3 Power VDD A6 Power VDD A18 Power VDDI T4 Power VDDI R1 Power VDDI M3 Power VDDI L18 Power VDDI J3 Power VDDI H18 Power VDDI F3 Power VDDI E18 Power VDDI B3 Power VDDI B18 Power Supply voltage for positive bias level at micromirrors. Supply voltage for High Voltage CMOS core logic. Supply voltage for offset level at micromirrors. Supply voltage for negative reset level at micromirrors. Supply voltage for Low Voltage CMOS core logic; for LPSDR inputs; for normal high level at micromirror address electrodes. Supply voltage for SubLVDS receivers. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 5 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 Pin Functions - Connector Pins (continued) PIN NAME 6 NO. TYPE VSS T1 Ground VSS T16 Ground VSS T19 Ground VSS T20 Ground VSS R5 Ground VSS R6 Ground VSS R7 Ground VSS R8 Ground VSS R9 Ground VSS R13 Ground VSS R14 Ground VSS R15 Ground VSS P2 Ground VSS P3 Ground VSS P20 Ground VSS N19 Ground VSS N20 Ground VSS M1 Ground VSS M2 Ground VSS L19 Ground VSS L20 Ground VSS K3 Ground VSS J18 Ground VSS G3 Ground VSS F18 Ground VSS D3 Ground VSS C18 Ground VSS B2 Ground VSS B4 Ground VSS B15 Ground VSS B17 Ground VSS A3 Ground VSS A4 Ground VSS A7 Ground VSS A15 Ground VSS A17 Ground VSS A19 Ground VSS A20 Ground SIGNAL DATA RATE DESCRIPTION Common return. Ground for all power. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 Pin Functions - Test Pads NUMBER SYSTEM BOARD T11 Do not connect T12 Do not connect T17 Do not connect T18 Do not connect R12 Do not connect R16 Do not connect R17 Do not connect R18 Do not connect R19 Do not connect P18 Do not connect P19 Do not connect N3 Do not connect N18 Do not connect M18 Do not connect M19 Do not connect B6 Do not connect B7 Do not connect B14 Do not connect A14 Do not connect Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 7 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 6 Specifications 6.1 Absolute Maximum Ratings see (1) MIN NOM MAX UNIT SUPPLY VOLTAGE VDD Supply voltage for LVCMOS core logic Supply voltage for LPSDR low speed interface –0.5 VDDI Supply voltage for SubLVDS receivers VOFFSET Supply voltage for HVCMOS and micromirror electrode VBIAS 2.3 V –0.5 2.3 V –0.5 8.75 V Supply voltage for micromirror electrode –0.5 17 V VRESET Supply voltage for micromirror electrode –11 0.5 V | VDDI–VDD | Supply voltage delta (absolute value) 0.3 V | VBIAS–VOFFSET | Supply voltage delta (absolute value) 8.75 V | VBIAS–VRESET | Supply voltage delta (absolute value) 28 V INPUT VOLTAGE Input voltage for other inputs LPSDR –0.5 VDD + 0.5 V Input voltage for other inputs SubLVDS –0.5 VDDI + 0.5 V INPUT PINS | VID | SubLVDS input differential voltage (absolute value) IID SubLVDS input differential current 810 mV 10 mA 120 μA 37 mW/mm2 105 °C TEMPERATURE DIODE ITEMP_DIODE Max current source into temperature diode ENVIRONMENTAL ILLOVERFILL Illumination overfill maximum heat load in area shown in Figure 6-1 TARRAY Operating DMD array temperature (1) –40 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device is not implied at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure above or below the Recommended Operating Conditions for extended periods may affect device reliability. 6.2 Storage Conditions Applicable for the DMD as a component or non-operating in a system. Tstg DMD storage temperature MIN MAX UNIT –40 125 °C 6.3 ESD Ratings VALUE V(ESD) (1) 8 Electrostatic discharge UNIT Human body model (HBM), per AEC Q100-002(1) ±2000 Charged device model (CDM), per AEC Q100-011 ±750 V AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 6.4 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted)(1) MIN NOM MAX UNIT 1.7 1.8 1.95 V SUPPLY VOLTAGE RANGE VDD Supply voltage for LVCMOS core logic Supply voltage for LPSDR low-speed interface VDDI Supply voltage for SubLVDS receivers 1.7 1.8 1.95 V VOFFSET Supply voltage for HVCMOS and micromirror electrode 8.25 8.5 8.75 V VBIAS Supply voltage for mirror electrode 15.5 16 16.5 V VRESET Supply voltage for micromirror electrode –9.5 –10 –10.5 V | VDDI–VDD | Supply voltage delta (absolute value) 0.3 V | VBIAS–VOFFSET | Supply voltage delta (absolute value) 8.75 V ƒmax Clock frequency for low speed interface LS_CLK 120 MHz ƒmax Clock frequency for high speed interface DCLK 600 MHz CLOCK FREQUENCY Duty cycle distortion DCLK 44% 56% SUBLVDS INTERFACE SubLVDS input differential voltage (absolute value)(2) | VID | (2) 150 250 350 mV VCM Common mode voltage 700 900 1100 mV ZLINE Line differential impedance (PWB/trace) 90 100 110 Ω ZIN Internal differential termination resistance(3) 80 100 120 Ω ENVIRONMENTAL TARRAY Operating DMD array temperature(5) ILLUV Illumination, wavelength < 395 nm (4) ILLOVERFILL Illumination overfill maximum heat load in area shown in Figure 6-1 (1) (2) (3) (4) (5) –40 105 2 °C mW/cm 2 28 mW/mm 2 Recommended Operating Conditions are applicable after the DMD is installed in the final product. See Figure 6-6 and Figure 6-7 See Figure 6-8 The maximum operation conditions for operating temperature and UV illumination shall not be implemented simultaneously. Operating profile information for device micromirror landed duty-cycle and temperature may be provided if requested. Illumination Overfill Diagram Figure 6-1. Illumination Overfill Diagram Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 9 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 6.5 Thermal Information DLP5530A-Q1 THERMAL METRIC FYS (CPGA) UNIT 149 PINS Thermal resistance (1) Active area-to-test point 1 (TP1) (1) 1.1 °C/W The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area, although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device. 6.6 Electrical Characteristics Over operating free-air temperature range (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT IDD Supply current: VDD(2) VDD = 1.95 V 310 mA IDDI Supply current: VDDI(2) VDDI = 1.95 V 55 mA IOFFSET Supply current: VOFFSET VOFFSET = 8.75 V 6 mA IBIAS Supply current: VBIAS VBIAS = 16.5 V 1 mA IRESET Supply current: VRESET VRESET = -10.5 V -4.5 mA PDD Supply power dissipation: VDD(2) VDD = 1.95 V 604.5 mW PDDI Supply power dissipation: VDDI(2) VDDI = 1.95 V 107.25 mW POFFSET Supply power dissipation: VOFFSET VOFFSET = 8.75 V 52.5 mW PBIAS Supply power dissipation: VBIAS VBIAS = 16.5 V 16.5 mW PRESET Supply power dissipation: VRESET VRESET = -10.5 V 47.25 mW PTOTAL Supply power dissipation: Total 828 mW POWER LPSDR INPUT (3) VIH(DC) DC input high voltage VIL(DC) DC input low voltage VIH(AC) AC input high voltage VIL(AC) AC input low voltage ∆VT Hysteresis (VT+ – VT–) See Figure 6-9 IIL Low–level input current VDD = 1.95 V; VI = 0 V IIH High–level input current VDD = 1.95 V; VI = 1.95 V LPSDR OUTPUT 0.7 × VDD VDD + 0.3 V –0.3 0.3 × VDD V 0.8 × VDD VDD + 0.3 V –0.3 0.2 × VDD V 0.1 × VDD 0.4 × VDD –100 V nA 300 nA (4) VOH DC output high voltage IOH = -2mA VOL DC output low voltage IOL = 2mA 0.8 × VDD 0.2 × VDD V Input capacitance LPSDR ƒ = 1 MHz 10 Input capacitance SubLVDS ƒ = 1 MHz 20 Output capacitance ƒ = 1 MHz 10 pF CRESET Reset group capacitance ƒ = 1 MHz (1152 X 144 micromirrors) 450 pF CTEMP Temperature sense diode capacitance ƒ = 1 MHz 20 pF V CAPACITANCE CIN COUT (1) (2) (3) (4) 10 350 400 pF Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted. Supply power dissipation based on non–compressed commands and data. LPSDR input specifications are for pin DMD_DEN_ARSTZ. LPSDR output specification is for pins LS_RDATA_A and LS_RDATA_B. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 6.7 Timing Requirements Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted MIN NOM MAX UNIT LPSDR tr Rise slew rate (1) (20% to 80%) × VDD 0.25 V/ns tf Fall slew rate (1) (80% to 20%) × VDD 0.25 V/ns tW(H) Pulse duration LS_CLK high(3) 50% to 50% reference points 0.75 ns 50% to 50% reference points low(3) tW(L) Pulse duration LS_CLK 0.75 ns tsu Setup time(3) LS_WDATA valid before LS_CLK ↑ or LS_CLK ↓ 1.5 ns th Hold time(3) LS_WDATA valid after LS_CLK ↑ or LS_CLK ↓ 1.5 ns Rise slew rate(2) 20% to 80% reference points 0.7 SubLVDS tr rate(2) 80% to 20% reference points 1 V/ns 0.7 1 V/ns 1.61 1.67 tf Fall slew tc Cycle time DCLK(3) tW(H) Pulse duration DCLK high(3) 50% to 50% reference points 0.75 ns tW(L) Pulse duration DCLK low(3) 50% to 50% reference points 0.75 ns tWINDOW Window time(3) (4) Setup time + Hold time tLVDS-ENABLE+REFGEN Power-up receiver(5) (1) (2) (3) (4) (5) ns 0.3 ns 2000 ns Specification is for DMD_DEN_ARSTZ pin. Refer to LPSDR input rise and fall slew rate in Figure 6-2 See Figure 6-3 See Figure 6-4 See Figure 6-5 Specification is for SubLVDS receiver time only and does not take into account commanding and latency after commanding. Electrical and Timing Diagrams Figure 6-2. LPSDR Input Rise and Fall Slew Rate Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 11 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 Figure 6-3. SubLVDS Input Rise and Fall Slew Rate Figure 6-4. SubLVDS Switching Parameters Figure 6-5. High-Speed Training Scan Window 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 Figure 6-6. SubLVDS Voltage Parameters Figure 6-7. SubLVDS Waveform Parameters DCLK_AP DCLK_BP D_AP(7:0) D_BP(7:0) DCLK_AN DCLK_BN D_AN(7:0) D_BN(7:0) ESD Internal Termination SubLVDS Receiver ESD Figure 6-8. SubLVDS Equivalent Input Circuit Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 13 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 Figure 6-9. LPSDR Input Hysteresis 6.8 Switching Characteristics Over operating free-air temperature range (unless otherwise noted)(1) PARAMETER tPD TEST CONDITIONS Output propagation, clock to Q, rising edge of LS_CLK (differential clock signal) input to LS_RDATA output.(2) TYP CL = 45 pF Slew rate, LS_RDATA MAX 15 0.5 Output duty cycle distortion, LS_RDATA_A and LS_RDATA_B (1) (2) MIN 40% UNIT ns V/ns 60% Device electrical characteristics are over Recommended Operating Conditions unless otherwise noted. See Figure 6-10 and Figure 6-11 LPSDR and Test Load Circuit Diagrams Figure 6-10. LPSDR Read Out Figure 6-11. Test Load Circuit for Output Propagation Measurement 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 6.9 System Mounting Interface Loads PARAMETER MIN NOM MAX UNIT Condition 1: Maximum load evenly distributed within each area (1) Thermal Interface Area 110.8 Electrical Interface Area 111.3 N Condition 2: Maximum load evenly distributed within each area (1) Thermal Interface Area 0 Electrical Interface Area (1) 222.1 N See Figure 6-12 System Interface Loads Diagram Figure 6-12. System Interface Loads 6.10 Physical Characteristics of the Micromirror Array VALUE UNIT M Number of active columns(1) PARAMETER 1152 micromirrors N Number of active rows(1) 1152 micromirrors ε Micromirror (pixel) pitch - diagonal(1) 7.6 µm P Micromirror (pixel) pitch - horizontal and vertical(1) 10.8 µm mm (1) (2) Micromirror active array width (P × M) + (P / 2) 12.447 Micromirror active array height (P x N) / 2 + (P / 2) 6.226 mm Micromirror active border Pond of micromirrors (POM) (2) 10 micromirrors/side See Figure 6-13 The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM. These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 15 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 Array Physical Characteristics Diagram Figure 6-13. Micromirror Array Physical Characteristics 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 6.11 Micromirror Array Optical Characteristics PARAMETER TEST CONDITIONS MIN 1 420 nm - 700 nm UNIT degree –1 DMD efficiency(3) (3) MAX 12 Micromirror tilt angle tolerance(2) (1) (2) NOM DMD landed state(1) Micromirror tilt angle degree 66% Measured relative to the plane formed by the overall micromirror array at 25°C. For some applications, it is critical to account for the micromirror tilt angle variation in the overall optical system design. With some optical system designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some optical system designs, the micromirror tilt angle variation between devices may result in colorimetry variations, system efficiency variations, or system contrast variations. DMD efficiency is measured photopically under the following conditions: 24° illumination angle, F/2.4 illumination and collection apertures, uniform source spectrum (halogen), uniform pupil illumination, the optical system is telecentric at the DMD, and the efficiency numbers are measured with 100% electronic micromirror landed duty-cycle and do not include system optical efficiency or overfill loss. This number is measured under conditions described above and deviations from these specified conditions could result in a different efficiency value in a different optical system. The factors that can influence the DMD efficiency related to system application include: light source spectral distribution and diffraction efficiency at those wavelengths (especially with discrete light sources such as LEDs or lasers), and illumination and collection apertures (F/#) and diffraction efficiency. The interaction of these system factors as well as the DMD efficiency factors that are not system dependent are described in detail in DLPA083A 6.12 Window Characteristics PARAMETER MIN Window material designation Window refractive index NOM UNIT Corning Eagle XG at wavelength 546.1 nm 1.5119 Window aperture (1) (1) MAX See (1) See the mechanical package ICD for details regarding the size and location of the window aperture. 6.13 Chipset Component Usage Specification The DLP5530S-Q1 is a component of a chipset. Reliable function and operation of the DLP5530S-Q1 requires that it be used in conjunction with the TPS99000S-Q1 and DLPC230S-Q1, and includes components that contain or implement TI DMD control technology. TI DMD control technology consists of the TI technology and devices used for operating or controlling a DLP DMD. Note TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 17 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 7 Detailed Description 7.1 Overview The DLP5530S-Q1 Automotive DMD consists of 1,327,104 highly reflective, digitally switchable, micrometersized mirrors organized in a two-dimensional array. As shown in Figure 6-13, the micromirror array consists of 1152 micromirror columns × 1152 micromirror rows in a diamond pixel configuration with a 2:1 aspect ratio. Around the perimeter of the 1152 × 1152 array of micromirrors is a uniform band of border micromirrors called the Pond of Micromirrors (POM). The border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has been applied to the device. There are 10 border micromirrors on each side of the 1152 × 1152 active array. Due to the diamond pixel configuration, the columns of each odd row are offset by half a pixel from the columns of the even row. Each mirror is switchable between two discrete angular positions: –12° and +12°. The mirrors are illuminated from the bottom which allows for compact and efficient system optical design. Although the native resolution of the DLP5530S-Q1 is 1152 × 1152, when paired with the DLPC230S-Q1 controller, the DLP5530S-Q1 can be driven with different resolutions to utilize the 2:1 aspect ratio. For example, Head-Up Display applications typically use a resolution of 1152 × 576. Please see the DLPC230S-Q1 automotive DMD controller data sheet (DLPS054) for a list of supported resolutions. Diamond pixel arrays also have the capability to increase display resolution beyond native resolution. Future controllers or video formatters may take advantage of this enhanced resolution. 7.2 Functional Block Diagram 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 7.3 Feature Description The DLP5530S-Q1 consists of a two-dimensional array of 1-bit CMOS memory cells driven by a sub-LVDS bus from the DLPC230S-Q1 and powered by the TPS99000S-Q1. The temperature sensing diode is used to continuously monitor the DMD array temperature. To ensure reliable operation the DLP5530S-Q1 must be used with the DLPC230S-Q1 DMD display controller and the TPS99000S-Q1 system management and illumination controller. 7.3.1 Sub-LVDS Data Interface The Sub-LVDS signaling protocol was designed to enable very fast DMD data refresh rates while simultaneously maintaining low power and low emission. Data is loaded into the SRAM under each micromirror using the sub-LVDS interface from the DLPC230S-Q1. This interface consists of 16 pairs of differential data signals plus two clock pairs into two separate buses A and B loading the left and right half of the SRAM array. The data is latched on both transitions creating a double data rate (DDR) interface. The sub-LVDS interface also implements a continuous training algorithm to optimize the data and clock timing to allow for a more robust interface. The entire DMD array of 1.3 million pixels can be updated at a rate of less than 100 µs as a result of the high speed sub-LVDS interface. 7.3.2 Low Speed Interface for Control The purpose of the low speed interface is to configure the DMD at power up and power down and to control the micromirror reset voltage levels that are synchronized with the data loading. The micromirror reset voltage controls the time when the mirrors are mechanically switched. The low speed differential interface includes 2 pairs of signals for write data and clock, and 2 single-ended signals for output (A and B). 7.3.3 DMD Voltage Supplies The micromirrors require unique voltage levels to control the mechanical switching from –12° to +12°. These voltage levels are nominally 16 V, 8.5 V, and –10 V (VBIAS, VOFFSET, and VRESET), and are generated by the TPS99000S-Q1. 7.3.4 Asynchronous Reset Reset of the DMD is required and controlled by the DLPC230S-Q1 via the signal DMD_DEN_ARSTZ. 7.3.5 Temperature Sensing Diode The DMD includes a temperature sensing diode designed to be used with the TMP411 temperature monitoring device. The DLPC230S-Q1 monitors the temperature sense diode via the TMP411. The DLPC230S-Q1 operation of the DMD timing can be adjusted based on the DMD array temperature, therefore this connection is essential to ensure reliable operation of the DMD. Figure 7-1 shows the typical connection between the DLPC230S-Q1, TMP411, and the DMD. Figure 7-1. Temperature Sense Diode Typical Circuit Configuration Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 19 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 7.3.5.1 Temperature Sense Diode Theory A temperature sensing diode is based on the fundamental current and temperature characteristics of a transistor. The diode is formed by connecting the transistor base to the collector. Three different known currents flow through the diode and the resulting diode voltage is measured in each case. The difference in their base–emitter voltages is proportional to the absolute temperature of the transistor. Refer to the TMP411-Q1 data sheet for detailed information about temperature diode theory and measurement. Figure 7-2 and Figure 7-3 illustrate the relationships between the current and voltage through the diode. IE1 IE2 TEMP_N + VBE 1,2 - TEMP_P û VBE (mV) VBE (mV) Figure 7-2. Temperature Measurement Theory 100uA 10uA 1uA Temperature (°C) Temperature (°C) Figure 7-3. Example of Delta VBE Versus Temperature 7.4 System Optical Considerations Optimizing system optical performance and image performance strongly relates to optical system design parameter trades. Although it is not possible to anticipate every conceivable application, projector image and optical performance is contingent on compliance to the optical system operating conditions described in the following sections. 7.4.1 Numerical Aperture and Stray Light Control The numerical aperture of the illumination and projection optics at the DMD optical area should be the same. This cone angle defined by the numerical aperture should not exceed the nominal device mirror tilt angle unless appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the projection lens. The mirror tilt angle defines the DMD's capability to separate the "On" optical path from any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens surfaces. 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 7.4.2 Pupil Match TI’s optical and image performance specifications assume that the exit pupil of the illumination optics is nominally centered and located at the entrance pupil position of the projection optics. Misalignment of pupils between the illumination and projection optics can degrade screen image uniformity and cause objectionable artifacts in the display’s border and/or active area. These artifacts may require additional system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle. 7.4.3 Illumination Overfill Overfill light illuminating the area outside the active array can create artifacts from the mechanical features and other surfaces that surround the active array. These artifacts may be visible in the projected image. The illumination optical system should be designed to minimize light flux incident outside the active array and on the window aperture. Depending on the particular system’s optical architecture and assembly tolerances, this amount of overfill light on the area outside of the active array may still cause artifacts to be visible. Illumination light and overfill can also induce undesirable thermal conditions on the DMD, especially if illumination light impinges directly on the DMD window aperture or near the edge of the DMD window. Heat load on the aperture in the areas shown in Figure 6-1 should not exceed the values listed in Recommended Operating Conditions. This area is a 0.5-mm wide area the length of the aperture opening. The values listed in Recommended Operating Conditions assume a uniform distribution. For a non-uniform distribution please contact TI for additional information. Note TI ASSUMES NO RESPONSIBILITY FOR IMAGE QUALITY ARTIFACTS OR DMD FAILURES CAUSED BY OPTICAL SYSTEM OPERATING CONDITIONS EXCEEDING LIMITS DESCRIBED PREVIOUSLY. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 21 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 7.5 DMD Image Performance Specification Table 7-1. DMD Image Performance PARAMETER(1) (2) Dark Blemishes - Viewed on a linear blue 60 MIN screen.(3) NOM MAX UNIT 4 Light Blemishes - Viewed on a linear gray 10 screen. 4 Bright Pixels - Viewed on a linear gray 10 screen. 0 micromirrors Dark Pixels - Viewed on a white screen. 4 micromirrors (1) (2) (3) See Section 7.4 Blemish counts do not include reflections or shadows of the same artifact. Any artifact that is not specifically called out in this table is acceptable. Viewing distance must be > 60 in. Screen size should be similar to application image size. All values referenced are in linear gamma. Non-linear gamma curves may be running by default, and it should be ensured with a TI applications engineer that the equivalent linear gamma value as specified is used to judge artifacts. Linear gray 5 may be substituted in monochrome applications. 7.6 Micromirror Array Temperature Calculation Figure 7-4. DMD Thermal Test Points The active array temperature can be computed analytically from measurement points on the outside of the package, the package thermal resistance, the electrical power, and the illumination heat load. Relationship between array temperature and the reference ceramic temperature (thermocouple location TP1 in Figure 7-4) is provided by the following equations: TARRAY = TCERAMIC + (QARRAY × RARRAY–TO–CERAMIC) (1) QARRAY = QELECTRICAL + QILLUMINATION (2) where • • • • • • • • TARRAY = computed DMD array temperature (°C) TCERAMIC = measured ceramic temperature, TP1 location in Figure 7-4 (°C) RARRAY–TO–CERAMIC = DMD package thermal resistance from array to thermal test point TP1 (°C/W), see Thermal Information QARRAY = total power, electrical plus absorbed, on the DMD array (W) QELECTRICAL = nominal electrical power dissipation by the DMD (W) QILLUMINATION = (CL2W × SL) CL2W = conversion constant for screen lumens to power on the DMD (W/lm) SL = measured screen lumens (lm) Electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating frequencies. Absorbed power from the illumination source is variable and depends on the operating state of the mirrors and the intensity of the light source. 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 Equations shown above are valid for a 1–chip DMD system with a total projection efficiency from DMD to the screen of 87%. The constant CL2W is based on the DMD array characteristics. It assumes a spectral efficiency of 300 lm/W for the projected light and illumination distribution of 83.7% on the active array, and 16.3% on the array border. The following is a sample calculation for a typical projection application: 1. SL = 50 lm 2. CL2W = 0.00293 W/lm 3. QELECTRICAL = 0.4 W (This number does not represent an actual DMD electrical power; for illustration purposes only) 4. RARRAY–TO–CERAMIC = 1.1°C/W 5. TCERAMIC = 55°C 6. QARRAY = 0.4 W + (0.00293 W/lm × 50 lm) = 0.5465 W 7. TARRAY = 55°C + (0.5465 W × 1.1°C/W) = 55.6°C Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 23 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 7.7 Micromirror Landed-On/Landed-Off Duty Cycle 7.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a percentage) that an individual micromirror is landed in the ON state versus the amount of time the same micromirror is landed in the OFF state. As an example, a landed duty cycle of 90/10 indicates that the referenced pixel is in the ON state 90% of the time (and in the OFF state 10% of the time), whereas 10/90 would indicate that the pixel is in the OFF state 90% of the time. Likewise, 50/50 indicates that the pixel is ON 50% of the time and OFF 50% of the time. Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other state (OFF or ON) is considered negligible and is thus ignored. Since a micromirror can only be landed in one state or the other (ON or OFF), the two numbers (percentages) always add to 100. 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 8 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 8.1 Application Information The DLP5530S-Q1 chipset is designed to support projection-based automotive applications such as head-up display systems. 8.2 Typical Application The chipset consists of three components—the DLP5530S-Q1 automotive DMD, the DLPC230S-Q1, and the TPS99000S-Q1. The DMD is a light modulator consisting of tiny mirrors that are used to form and project images. The DLPC230S-Q1 is a controller for the DMD; it formats incoming video and controls the timing of the DMD illumination sources and the DMD in order to display the incoming video. The TPS99000S-Q1 is a controller for the illumination sources (e.g. LEDs or lasers) and a management IC for the entire chipset. In conjunction, the DLPC230S-Q1 and the TPS99000S-Q1 can also be used for system-level monitoring, diagnostics, and failure detection features. Figure 8-1 is a system level block diagram with these devices in the DLP head-up display configuration and shows the primary features and functions of each device. VLED 6.5 V PreRegulator (optional) VBATT 6.5 V 3.3 V LDO External ADC inputs for general usage AC3 Flash MPU ECC LED drive Ultra wide dimming LED controller F E T s SPI(4) SEQ_START HOST_IRQ DLPC230S-Q1 Host D_EN 28 SEQ_CLK eSRAM frame buffer I2C(2) I2C_0 SPI(4) SPI_0 3.3 V VCC_FLASH VCC_INTF 1.8 V VIO 1.1 V VCORE PARKZ RESETZ INTZ GPIOx GPIOx Photo diode meas. system Spare GPIO Sys clock monitor shunt(2) RED GREEN BLUE Illumination Optics photo diode External watchdogs / over brightness / and other monitors COMPOUT Parallel LM3409 Low-side current measurement TPS99000S-Q1 S_EN OpenLDI CTRL 4 DATA 24 12 bit ADC ADC_CTRL(2) WD(2) LED_SEL(4) SPI_1 Supplies for DLPC230 and DMD High-side current limiting PROJ_ON Optional SPI Monitor SPI_2 1.1 V 1.8 V 3.3 V reg reg Reg Power sequencing and monitoring General Purpose PD neg LDO BIAS, RST, OFS (3) DMD bias regulator EEPROM I2C_1 TMP411 (2) DMD die temperature DMD Sub-LVDS Interface sub-LVDS DATA DLP5530S-Q1 Control Figure 8-1. Head-Up Display System Block Diagram Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 25 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 8.2.1 Application Overview Figure 8-1 shows the system block diagram for a DLP HUD system. The system uses the DLPC230S-Q1, TPS99000S-Q1, and the DLP5530S-Q1 automotive DMD to enable a head-up display with high brightness, high efficiency, and a large virtual image distance. The combination of the DLPC230S-Q1 and TPS99000S-Q1 removes the need for external SDRAM and a dedicated microprocessor. The chipset manages the illumination control of LED sources, power sequencing functions, and system management functions. Additionally, the chipset supports numerous system diagnostic and built-in self test (BIST) features. The following paragraphs describe the functionality of the chipset used for a HUD system in more detail. The DLPC230S-Q1 is a controller for the DMD and the light sources in the DLP HUD module. It receives input video from the host and synchronizes DMD and light source timing in order to achieve the desired video. The DLPC230S-Q1 formats input video data that is displayed on the DMD. It synchronizes these video segments with light source timing in order to create a video with a multi-colored display. The DLPC230S-Q1 receives inputs from a host processor in the vehicle. The host provides commands and input video data. Host commands can be sent using either the I2C bus or SPI bus. The bus that is not being used for host commands can be used as a read-only bus for diagnostic purposes. Input video can be sent over an OpenLDI bus or a parallel 24-bit bus. The SPI flash memory provides the embedded software for the DLPC230S-Q1’s ARM core and default settings. The TPS99000S-Q1 provides diagnostic and monitoring information to the DLPC230S-Q1 using an SPI bus and several other control signals such as PARKZ, INTZ, and RESETZ to manage power-up and power-down sequencing. The TMP411 uses an I2C interface to provide the DMD array temperature to the DLPC230S-Q1. The outputs of the DLPC230S-Q1 are configuration and monitoring commands to the TPS99000S-Q1, timing controls to the LED or laser driver, control and data signals to the DMD, and monitoring and diagnostics information to the host processor. The DLPC230S-Q1 communicates with the TPS99000S-Q1 over an SPI bus. It uses this to configure the TPS99000S-Q1 and to read monitoring and diagnostics information from the TPS99000S-Q1. The DLPC230S-Q1 sends drive enable signals to the LED or laser driver, and synchronizes this with the DMD mirror timing. The control signals to the DMD are sent using a sub-LVDS interface. The TPS99000S-Q1 is a highly integrated mixed-signal IC that controls DMD power and provides monitoring and diagnostics information for the DLP HUD system. The power sequencing and monitoring blocks of the TPS99000S-Q1 properly power up the DMD and provide accurate DMD voltage rails (–16 V, 8.5 V, and 10 V), and then monitor the system’s power rails during operation. The integration of these functions into one IC significantly reduces design time and complexity. The TPS99000S-Q1 also has several output signals that can be used to control a variety of LED or laser driver topologies. The TPS99000S-Q1 has several general-purpose ADCs that designers can use for system level monitoring, such as over-brightness detection. The TPS99000S-Q1 receives inputs from the DLPC230S-Q1, the power rails it monitors, the host processor, and potentially several other ADC ports. The DLPC230S-Q1 sends configuration and control commands to the TPS99000S-Q1 over an SPI bus and several other control signals. The DLPC230S-Q1’s clocks are also monitored by the watchdogs in the TPS99000S-Q1 to detect any errors. The power rails are monitored by the TPS99000S-Q1 in order to detect power failures or glitches and request a proper power down of the DMD in case of an error. The host processor can read diagnostics information from the TPS99000S-Q1 using a dedicated SPI bus, which enables independent monitoring. Additionally the host can request the image to be turned on or off using a PROJ_ON signal. Lastly, the TPS99000S-Q1 has several general-purpose ADCs that can be used to implement system level monitoring functions. The outputs of the TPS99000S-Q1 are diagnostic information and error alerts to the DLPC230S-Q1, and control signals to the LED or laser driver. The TPS99000S-Q1 can output diagnostic information to the host and the DLPC230S-Q1 over two SPI buses. In case of critical system errors, such as power loss, it outputs signals to the DLPC230S-Q1 that trigger power down or reset sequences. It also has output signals that can be used to implement various LED or laser driver topologies. The DMD is a micro-electro-mechanical system (MEMS) device that receives electrical signals as an input (video data), and produces a mechanical output (mirror position). The electrical interface to the DMD is a sub-LVDS interface with the DLPC230S-Q1. The mechanical output is the state of more than 1.3 million mirrors in the DMD array that can be tilted ±12°. In a projection system the mirrors are used as pixels in order to display an image. 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 8.2.2 Reference Design For information about connecting together the DLP5530S-Q1 DMD, DLPC230S-Q1 controller, and TPS99000SQ1, please contact the TI Application Team for additional information about the DLP5530S-Q1 evaluation module (EVM). TI has optical-mechanical reference designs available, see the TI Application team for more information. 8.2.3 Application Mission Profile Consideration Each application is anticipated to have different mission profiles, or number of operating hours at different temperatures. To assist in evaluation the Application Report Reliability Lifetime Estimates for DLP3030-Q1 and DLP553x-Q1 DMDs in Automotive Applications may be provided. See the TI Application team for more information. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 27 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 9 Power Supply Recommendations The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required. DMD power-up and power-down sequencing is strictly controlled by the TPS99000S-Q1 device. CAUTION For reliable operation of the DMD, the following power supply sequencing requirements must be followed. Failure to adhere to the prescribed power-up and power-down procedures may affect device reliability. VDD, VDDI, VOFFSET, VBIAS, and VRESET power supplies have to be coordinated during powerup and power-down operations. Failure to meet any of the below requirements will result in a significant reduction in the DMD’s reliability and lifetime. VSS must also be connected. 9.1 Power Supply Power-Up Procedure • • • • During power-up, VDD and VDDI must always start and settle before VOFFSET, VBIAS, and VRESET voltages are applied to the DMD. During power-up, it is a strict requirement that the delta between VBIAS and VOFFSET must be within the specified limit shown in the Recommended Operating Conditions. During power-up, the DMD’s LPSDR input pins shall not be driven high until after VDD and VDDI have settled at operating voltage. During power-up, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS. Power supply slew rates during power-up are flexible, provided that the transient voltage levels follow the requirements listed previously and in Figure 9-1. 9.2 Power Supply Power-Down Procedure • • • • • 28 The power-down sequence is the reverse order of the previous power-up sequence. VDD and VDDI must be supplied until after VBIAS, VRESET, and VOFFSET are discharged to within 4 V of ground. During power-down, it is not mandatory to stop driving VBIAS prior to VOFFSET, but it is a strict requirement that the delta between VBIAS and VOFFSET must be within the specified limit shown in the Recommended Operating Conditions (Refer to Note 2 in Section 9.3). During power-down, the DMD’s LPSDR input pins must be less than VDDI, the specified limit shown in the Recommended Operating Conditions. During power-down, there is no requirement for the relative timing of VRESET with respect to VOFFSET and VBIAS. Power supply slew rates during power-down are flexible, provided that the transient voltage levels follow the requirements listed previously and in Section 9.3. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 9.3 Power Supply Sequencing Requirements A. B. C. D. To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified in the Recommended Operating Conditions. OEMs may find that the most reliable way to ensure this is to power VOFFSET prior to VBIAS during power-up and to remove VBIAS prior to VOFFSET during power-down. Also, the TPS99000S-Q1 is capable of managing the timing between VBIAS and VOFFSET. To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified than the limit shown in the Recommended Operating Conditions. When system power is interrupted, the TPS99000S-Q1 initiates hardware power-down that disables VBIAS, VRESET and VOFFSET after the Micromirror Park Sequence. Drawing is not to scale and details are omitted for clarity. Figure 9-1. Power Supply Sequencing Requirements (Power Up and Power Down) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 29 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 10 Layout 10.1 Layout Guidelines Please refer to the DLPC230S-Q1 and TPS99000S-Q1 data sheets for specific PCB layout and routing guidelines. For specific DMD PCB guidelines, use the following: • • • • • • • Match lengths for the LS_WDATA and LS_CLK signals. Minimize vias, layer changes, and turns for the HS bus signals. Minimum of two 220-nF decoupling capacitors close to VBIAS. Minimum of two 220-nF decoupling capacitors close to VRESET. Minimum of two 220-nF decoupling capacitors close to VOFFSET. Minimum of four 100-nF decoupling capacitors close to VDDI and VDD. Temperature diode pins The DMD has an internal diode (PN junction) that is intended to be used with an external TI TMP411 temperature sensing IC. PCB traces from the DMD’s temperature diode pins to the TMP411 are sensitive to noise. Please see the TMP411 data sheet for specific routing recommendations. 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 11 Device and Documentation Support 11.1 Device Support 11.1.1 Device Nomenclature Figure 11-1. Part Number Description 11.1.2 Device Markings The device marking includes the legible character string GHJJJJK DLP553xxAFYSQ1. GHJJJJK is the lot trace code. DLP553xxAFYSQ1 is the part number. Figure 11-2. DMD Marking 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 11.4 Trademarks TI E2E™ is a trademark of Texas Instruments. DLP® is a registered trademark of Texas Instruments. All trademarks are the property of their respective owners. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 31 DLP5530S-Q1 www.ti.com DLPS200B – JULY 2020 – REVISED APRIL 2021 11.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.6 DMD Handling The DMD is an optical device so precautions should be taken to avoid damaging the glass window. Please see the application note DLPA019 DMD Handling for instructions on how to properly handle the DMD. 11.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 32 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DLP5530S-Q1 PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking (4/5) (6) DLP5530SAFYSQ1 ACTIVE CPGA FYS 149 33 RoHS & Green Call TI N / A for Pkg Type -40 to 105 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of