DLP7000BFLP

Product Folder Order Now Support & Community Tools & Software Technical Documents DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 DLP7000 DLP® 0.7 XGA 2x LVDS Type A DMD 1 Features • 1 • • • • • 0.7-Inch diagonal micromirror array – 1024 × 768 array of Al, micrometer-sized mirrors – 13.68-µm micromirror pitch – ±12° micromirror tilt angle (relative to flat state) – Designed for corner illumination Use with visible light (400 nm to 700 nm): – Window transmission 97% (single pass, through two window surfaces) – Micromirror reflectivity 88% – Array diffraction efficiency 86% – Array fill factor 92% Two 16-Bit, low voltage differential signaling (LVDS) double data rate (DDR) input data buses Iinput data clock rate up to 400 MHz 40.64 mm × 31.75 mm × 6.0 mm package Hermetic package 2 Applications • • Industrial – Digital imaging lithography – Laser marking – LCD and OLED repair – Computer-to-plate printers – SLA 3D printers – 3D scanners for machine vision and factory automation – Flat panel lithography Medical – Phototherapy devices – Ophthalmology – Direct manufacturing • – Hyperspectral imaging – 3D biometrics – Confocal microscopes Display – 3D imaging microscopes – Adaptive illumination – Augmented reality and information overlay 3 Description The DLP7000 XGA Chipset is part of the DLP® Discovery™ 4100 platform, which enables high resolution and high performance spatial light modulation. The DLP7000 is the digital micromirror device (DMD) fundamental to the 0.7 XGA chipset, and currently supports the fastest pattern rates in the DLP catalog portfolio. The DLP Discovery 4100 platform also provides the highest level of individual micromirror control with the option for random row addressing. Combined with a hermetic package, the unique capability and value offered by DLP7000 makes it well suited to support a wide variety of industrial, medical, and advanced display applications. In addition to the DLP7000 DMD, the 0.7 XGA Chipset includes these components: • Dedicated DLPC410 controller for high speed pattern rates of >32000 Hz (1-bit binary) and >4000 Hz (8-bit gray) • One unit DLPR410 (DLP Discovery 4100 Configuration PROM) • One unit DLPA200 (DMD Micromirror Driver) Device Information(1) PART NUMBER DLP7000 PACKAGE FLP (203) BODY SIZE (NOM) 40.64 mm × 31.75 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Description (continued)......................................... 5 Pin Configuration and Functions ......................... 5 Specifications....................................................... 12 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 8 Absolute Maximum Ratings .................................... 12 Storage Conditions.................................................. 12 ESD Ratings............................................................ 12 Recommended Operating Conditions..................... 13 Thermal Information ................................................ 14 Electrical Characteristics......................................... 15 LVDS Timing Requirements ................................... 16 LVDS Waveform Requirements.............................. 16 Serial Control Bus Timing Requirements................ 16 Systems Mounting Interface Loads....................... 19 Micromirror Array Physical Characteristics ........... 20 Micromirror Array Optical Characteristics ............. 21 Window Characteristics......................................... 22 Chipset Component Usage Specification ............. 22 Detailed Description ............................................ 23 8.1 Overview ................................................................. 23 8.2 8.3 8.4 8.5 Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Optical Interface and System Image Quality Considerations ........................................................ 8.6 Micromirror Array Temperature Calculation............ 8.7 Micromirror Landed-On/Landed-Off Duty Cycle ..... 9 23 25 32 34 35 37 Application and Implementation ........................ 40 9.1 Application Information............................................ 40 9.2 Typical Application .................................................. 41 10 Power Supply Recommendations ..................... 44 10.1 DMD Power-Up and Power-Down Procedures..... 44 11 Layout................................................................... 44 11.1 Layout Guidelines ................................................. 44 11.2 Layout Example .................................................... 45 12 Device and Documentation Support ................. 47 12.1 12.2 12.3 12.4 12.5 12.6 Device Support...................................................... Documentation Support ........................................ Related Links ........................................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 47 47 48 48 48 48 13 Mechanical, Packaging, and Orderable Information ........................................................... 48 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (May 2017) to Revision F Page • Deleted "Broadband" ............................................................................................................................................................. 1 • Changed values for high speed pattern rates ........................................................................................................................ 1 • Changed package type to FLP (203) ..................................................................................................................................... 1 • Changed package type to FLP; deleted reference to LCCC ................................................................................................. 5 • Changed FLP package figure "bottom view" .......................................................................................................................... 5 • Changed "Case temperature" to "Array temperature" ......................................................................................................... 12 • Changed "Case temperature" to "Array temperature" ......................................................................................................... 12 • Changed "Device temperature gradient - operational" to "Absolute temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1" ............................................................................................................. 12 • Deleted "RH" after "%" ........................................................................................................................................................ 12 • Changed "Applicable before the DMD is installed in the final product" to "Applicable for the DMD as a component or non-operating system" .......................................................................................................................................................... 12 • Changed ", non-condensing" to "(non-condensing)" ........................................................................................................... 12 • Changed "JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process." to "JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible if necessary precautions are taken." .................... 12 • Changed Table "Recommended Operating Conditions" ...................................................................................................... 13 • Added "RH" under "Environmental" ..................................................................................................................................... 13 • Added cross reference to table note at row "ILLVIS" ............................................................................................................ 13 • Changed Array temperature, Long-term operational MAX from "30" to "40" ....................................................................... 13 • Changed package type to FLP in table "THERMAL METRIC" ............................................................................................ 14 2 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 Revision History (continued) • Added "or the combined loads of the thermal and electrical areas reduced" ...................................................................... 19 • Deleted row "Window artifact size" in table "Window Characteristics"................................................................................. 22 • Changed mirror pitch to 13.68 μm ........................................................................................................................................ 25 • Changed figure "DLPC410 Data Flow" to correct signals of LVDS BUS B out.................................................................... 27 • Changed "Window Characteristics and Optics" to "Optical Interface and System Image Quality Considerations" ............ 34 • Changed "a Thermal Test Point locations 1 and 2" to "thermal test points TP1, TP2, and TP3" ........................................ 35 • Added "(typically used for display applications)" to "Micromirror Array Temperature Calculation - Lumens based" .......... 36 • Deleted Subsection "Fiducials" ............................................................................................................................................ 44 Changes from Revision D (November 2015) to Revision E Page • Clarified TGRADIENT footnote ................................................................................................................................................... 12 • Changed TC2 to TP1 to follow latest thermal test point nomenclature convention in Thermal Information ........................ 14 • Changed Micromirror active border from 10 to correct value of 6 ....................................................................................... 20 • Changed micromirror crossover to mean transition time and renamed previous crossover to micromirror switching time typical micromirror crossover time typo (16 µs to 13 µs).............................................................................................. 21 • Added typical micromirror switching time - 13 µs................................................................................................................. 21 • Changed "Micromirror switching time" to "Array switching time" for clarity ......................................................................... 21 • Added clarification to Micromirror switching time at 400 MHz with global reset ................................................................. 21 • Changed references to D4100 Discovery to DPC410 ......................................................................................................... 23 • Changed Thermal Test Point Location drawing to current numbering convention ............................................................. 35 • Changed Micromirror Array Temperature Calculations to indicate that it is based on lumens ............................................ 36 • Added Micromirror Array Temperature Calculation based on power ................................................................................... 37 • Updated Figure 22................................................................................................................................................................ 47 • Removed link to DLP Discovery 4100 chipset datasheet..................................................................................................... 47 • Added DLPR410 to Related Links table............................................................................................................................... 48 Changes from Revision C (April 2014) to Revision D Page • Updated Figure 21 and graphic for Device Nomenclature ................................................................................................... 47 • Updated Figure 22 and graphic for Device Marking............................................................................................................. 47 Changes from Revision B (June 2013) to Revision C Page • Added Pin Configuration and Functions section, ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 • Deleted / DLPR4101 Enhanced PROM from Chipset List ..................................................................................................... 1 • Corrected VCC2 max to 8 V ................................................................................................................................................ 12 • Added array temperature vs duty cycle graph...................................................................................................................... 14 • Replaced serial communications bus timing parameters ..................................................................................................... 18 • Converted interface loads to Newtons.................................................................................................................................. 19 • Grayed out LVDS buses that are unused on DLP7000 ....................................................................................................... 27 • Added micromirror landed duty cycle section....................................................................................................................... 37 • Changed to DLP7000 ........................................................................................................................................................... 42 • Deleted / DLPR4101 Enhanced PROM from Related Documentation................................................................................. 47 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 3 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com Changes from Revision A (September 2012) to Revision B Page • Added / DLPR4101 Enhanced PROM to DLPR410 in Chipset List ....................................................................................... 1 • Changed pin number of DCLK_AN From: D19 To: B22 ....................................................................................................... 9 • Changed pin number of DCLK_AP From: E19 To: B24 ........................................................................................................ 9 • Changed pin number of DCLK_BN From: M19 To: AB22 ..................................................................................................... 9 • Changed pin number of DCLK_BP From: N19 To: AB24 ..................................................................................................... 9 • Added / DLPR4101 Enhanced PROM to DLPR410 in Related Documentation .................................................................. 47 Changes from Original (August 2012) to Revision A • 4 Page Changed the device from 'Product Preview' to 'Production' ................................................................................................... 1 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 5 Description (continued) Reliable function and operation of the DLP7000 requires that it be used in conjunction with the other components of the chipset. A dedicated chipset provides developers easier access to the DMD as well as high speed, independent micromirror control. DLP7000 is a digitally controlled micro-electromechanical system (MEMS) spatial light modulator (SLM). When coupled to an appropriate optical system, the DLP7000 can be used to modulate the amplitude, direction, and/or phase of incoming light. Electrically, the DLP7000 consists of a two-dimensional array of 1-bit CMOS memory cells, organized in a grid of 1024 memory cell columns by 768 memory cell rows. The CMOS memory array is addressed on a row-by-row basis, over two 16-bit low voltage differential signaling (LVDS) double data rate (DDR) buses. Addressing is handled via a serial control bus. The specific CMOS memory access protocol is handled by the DLPC410 digital controller. 6 Pin Configuration and Functions FLP Package 203-Pin CLGA Bottom View 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 A B C D E F G H J K L M N P R T U V W Y AA AB AC Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 5 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com Pin Functions PIN (1) NO. TYPE (I/O/P) SIGNAL DATA RATE (2) INTERNAL TERM (3) CLOCK D_AN(0) B10 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 368.72 D_AN(1) A13 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 424.61 D_AN(2) D16 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 433.87 D_AN(3) C17 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 391.39 D_AN(4) B18 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 438.57 D_AN(5) A17 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 391.13 D_AN(6) A25 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 563.26 D_AN(7) D22 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 411.62 D_AN(8) C29 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A NAME DESCRIPTION TRACE DATA INPUT 595.11 Input data bus A (2x LVDS) D_AN(9) D28 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 543.07 D_AN(10) E27 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 455.98 D_AN(11) F26 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 359.5 D_AN(12) G29 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 542.67 D_AN(13) H28 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 551.51 D_AN(14) J27 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 528.04 D_AN(15) K26 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 484.38 D_AP(0) B12 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 366.99 D_AP(1) A11 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 417.47 (1) (2) (3) 6 The following power supplies are required to operate the DMD: VCC, VCC1, VCC2. VSS must also be connected. DDR = Double Data Rate. SDR = Single Data Rate. Refer to the LVDS Timing Requirements for specifications and relationships. Refer to Electrical Characteristics for differential termination specification. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 Pin Functions (continued) PIN (1) NAME NO. TYPE (I/O/P) SIGNAL DATA RATE (2) INTERNAL TERM (3) CLOCK D_AP(2) D14 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 434.89 D_AP(3) C15 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 394.67 D_AP(4) B16 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 437.3 D_AP(5) A19 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 389.01 D_AP(6) A23 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 562.92 D_AP(7) D20 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 410.34 D_AP(8) A29 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A D_AP(9) B28 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A D_AP(10) C27 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 456.78 D_AP(11) D26 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 360.68 D_AP(12) F30 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 543.97 D_AP(13) H30 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 570.85 D_AP(14) J29 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 527.18 D_AP(15) K28 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A 481.02 D_BN(0) AB10 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 368.72 D_BN(1) AC13 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 424.61 D_BN(2) Y16 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B D_BN(3) AA17 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 391.39 D_BN(4) AB18 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 438.57 DESCRIPTION Input data bus A continued (2x LVDS) Input data bus B (2x LVDS) TRACE 594.61 539.88 433.87 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 7 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com Pin Functions (continued) PIN (1) NO. TYPE (I/O/P) SIGNAL DATA RATE (2) INTERNAL TERM (3) CLOCK D_BN(5) AC17 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 391.13 D_BN(6) AC25 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 563.26 D_BN(7) Y22 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 411.62 D_BN(8) AA29 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 595.11 D_BN(9) Y28 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 543.07 D_BN(10) W27 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 455.98 D_BN(11) V26 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 360.94 D_BN(12) T30 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 575.85 D_BN(13) R29 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 519.37 D_BN(14) R27 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B D_BN(15) N27 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 441.14 D_BP(0) AB12 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 366.99 D_BP(1) AC11 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 417.47 D_BP(2) Y14 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 434.89 D_BP(3) AA15 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 394.67 D_BP(4) AB16 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 437.3 D_BP(5) AC19 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 389.01 D_BP(6) AC23 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 562.92 D_BP(7) Y20 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 410.34 NAME 8 Submit Documentation Feedback DESCRIPTION Input data bus B continued (2x LVDS) TRACE 532.59 Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 Pin Functions (continued) PIN (1) NO. TYPE (I/O/P) SIGNAL DATA RATE (2) INTERNAL TERM (3) CLOCK D_BP(8) AC29 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 594.61 D_BP(9) AB28 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 539.88 D_BP(10) AA27 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 456.78 D_BP(11) Y26 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B D_BP(12) U29 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B D_BP(13) T28 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 509.74 D_BP(14) P28 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 534.59 D_BP(15) P26 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B 440 B22 Input LVCMOS – Differential Terminated 100 Ω – NAME DESCRIPTION Input data bus B continued (2x LVDS) TRACE 360.68 578.46 DATA CLOCK DCLK_AN DCLK_AP B24 Input LVCMOS – Differential Terminated 100 Ω – DCLK_BN AB22 Input LVCMOS – Differential Terminated 100 Ω – DCLK_BP AB24 477.1 DCLK for data bus A (2x LVDS) 477.14 477.07 DCLK for data bus B (2x LVDS) Input LVCMOS – Differential Terminated 100 Ω – 477.14 DATA CONTROL INPUTS SCTRL_AN C21 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A SCTRL_AP C23 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_A SCTRL_BN AA21 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B SCTRL_BP AA23 Input LVCMOS DDR Differential Terminated 100 Ω DCLK_B Serial control for data bus A (2x LVDS) Serial control for data bus B (2x LVDS) 477.07 477.14 477.07 477.14 SERIAL COMMUNICATION AND CONFIGURATION SCPCLK E3 Input LVCMOS – Pull-down – Serial port clock 379.29 SCPDO B2 Output LVCMOS – SCPDI F4 Input LVCMOS – Pull-down SCPCLK Serial port output 480.91 SCPCLK Serial port input SCPENZ D4 Input LVCMOS – 323.56 Pull-down SCPCLK Serial port enable 326.99 PWRDNZ C3 Input LVCMOS – Pull-down – Device Reset 406.28 – Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 9 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com Pin Functions (continued) PIN (1) NAME NO. TYPE (I/O/P) SIGNAL DATA RATE (2) INTERNAL TERM (3) MODE_A D8 Input LVCMOS – Pull-down – Data bandwidth mode select A 396.05 MODE_B C11 Input LVCMOS – Pull-down – Data bandwidth mode select B 208.86 CLOCK DESCRIPTION TRACE MICROMIRROR BIAS CLOCKING PULSE MBRST(0) P2 Input Analog – – – MBRST(1) AB4 Input Analog – – – MBRST(2) AA7 Input Analog – – – MBRST(3) N3 Input Analog – – – MBRST(4) M4 Input Analog – – – MBRST(5) AB6 Input Analog – – – MBRST(6) AA5 Input Analog – – – MBRST(7) L3 Input Analog – – – MBRST(8) Y6 Input Analog – – – MBRST(9) K4 Input Analog – – – MBRST(10) L5 Input Analog – – – MBRST(11) AC5 Input Analog – – – MBRST(12) Y8 Input Analog – – – MBRST(13) J5 Input Analog – – – MBRST(14) K6 Input Analog – – – MBRST(15) AC7 Input Analog – – – VCC A7, A15, C1, E1, U1, W1, AB2, AC9, AC15 Power Analog – – – Power for LVCMOS Logic – VCC1 A21, A27, D30, M30, Y30, AC21, AC27 Power Analog – – – Power supply for LVDS Interface – VCC2 G1, J1, L1, N1, R1 Power Analog – – – Power for High Voltage CMOS Logic – Micromirror Bias Clocking Pulse "MBRST" signals "clock" micromirrors into state of LVCMOS memory cell associated with each mirror. POWER 10 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 Pin Functions (continued) PIN NAME VSS (1) NO. A1, A3, A5, A9, B4, B8, B14, B20, B26, B30, C7, C13, C19, C25, D6, D12, D18, D24, E29, F2, F28, G3, G27, H2, H4, H26, J3, J25, K2, K30, L25, L27, L29, M2, M6, M26, M28, N5, N25, N29, P4, P30, R3, R5, R25, T2, T26, U27, V28, V30, W5, W29, Y4, Y12, Y18, Y24, AA3, AA9, AA13, AA19, AA25, AB8, AB14, AB20, AB26, AB30 TYPE (I/O/P) SIGNAL DATA RATE (2) INTERNAL TERM (3) CLOCK Power Analog – – – Common return for all power inputs – DESCRIPTION TRACE RESERVED SIGNALS (NOT FOR USE IN SYSTEM) RESERVED _AA1 AA1 Input LVCMOS – Pull-down – Pins should be connected to VSS – RESERVED _B6 B6 Input LVCMOS – Pull-down – – – RESERVED _T4 T4 Input LVCMOS – Pull-down – – – RESERVED _U5 U5 Input LVCMOS – Pull-down – – – NO_CONN ECT AA11, AC3, C5, C9, D10, D2, E5, G5, H6, P6, T6, U3, V2, V4, W3, Y10, Y2 – – – – Do not connect – – Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 11 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT ELECTRICAL VCC Voltage applied to VCC (2) (3) –0.5 4 V VCCI Voltage applied to VCCI (2) (3) –0.5 4 V VCC2 Voltage applied to VVCC2 –0.5 8 V VMBRST Micromirror Clocking Pulse Waveform Voltage applied to MBRST[15:0] Input Pins (supplied by DLPA200) –28 28 V 0.3 V |VCC – VCCI| (2) (3) (4) Supply voltage delta (absolute value) Voltage applied to all other input pins (4) (2) VCC + 0.3 V |VID| Maximum differential voltage, damage can occur to internal termination resistor if exceeded, see Figure 3 –0.5 700 mV IOH Current required from a high-level output VOH = 2.4 V –20 mA IOL Current required from a low-level output VOL = 0.4 V 15 mA ENVIRONMENTAL TARRAY Array temperature: operational (5) 10 65 °C Array temperature: non-operational (5) –40 80 °C 10 °C 95 % TDELTA Absolute temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1 (6) RH Operating relative humidity (non-condensing) (1) (2) (3) (4) (5) (6) 0 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS (ground). VOFFSET supply transients must fall within specified max voltages. To prevent excess current, the supply voltage delta |VCC – VCCI| must be less than specified limit. DMD Temperature is the worst-case of any test point shown in Figure 18, or the active array as calculated by the Micromirror Array Temperature Calculation. As either measured, predicted, or both between any two points -- measured on the exterior of the package, or as predicted at any point inside the micromirror array cavity. Refer to Thermal Information and Micromirror Array Temperature Calculation. 7.2 Storage Conditions Applicable for the DMD as a component or non-operating in a system Storage temperature Tstg Storage humidity (non-condensing) MIN MAX –40 80 UNIT °C 95 % VALUE UNIT 7.3 ESD Ratings V(ESD) (1) 12 Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) All pins except MBRST[15:0] ±2000 Pins MBRST[15:0] ±250 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible if necessary precautions are taken. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 7.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) (1) ELECTRICAL MIN NOM MAX UNIT (2) (3) VCC Supply voltage for LVCMOS core logic 3.0 3.3 3.6 V VCC1 Supply voltage for LVDS receivers 3.0 3.3 3.6 V VCC2 Mirror electrode and HVCMOS supply voltage 7.25 7.5 7.75 V VMBRST Clocking Pulse Waveform Voltage applied to MBRST[29:0] Input Pins (supplied by DLPA200s) 26.5 V |VCCI–VCC| Supply voltage delta (absolute value) 0.3 V 95 % -27 (4) ENVIRONMENTAL RH Operating relative humidity (non-condensing) ENVIRONMENTAL TARRAY (5) For Illumination Source Between 420 nm and 700 nm Array temperature, Long–term operational (6) (7) (8) (9) Array temperature, Short–term operational (6) (7) (11) TWINDOW Window Temperature test points TP2 and TP3, Long-term operational (9) |TDELTA| Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1. (12) ILLVIS Illumination (13) ENVIRONMENTAL (5) 10 25-45 65 (10) °C 0 10 10 65 °C 10 °C Thermally limited W/cm2 For Illumination Source Between 400 nm and 420 nm (6) (7) (8) (9) TARRAY Array temperature, Long–term operational 30 °C TWINDOW Window Temperature test points TP2 and TP3, Long-term operational (9) 20 30 °C |TDELTA| Absolute Temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1. (12) 10 °C ILL Illumination (13) 11 W/cm2 16.2 ENVIRONMENTAL TARRAY TWINDOW ILL (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (5) W For Illumination Source 700 nm Array temperature, Long–term operational (6) (7) (8) (9) Array temperature, Short–term operational (6) (7) (11) Window Temperature test points TP2 and TP3, Long-term operational (9) Illumination (13) 20 40 (10) °C 0 20 10 65 °C 10 mW/cm2 The functional performance of the device specified in this data sheet is achieved when operating the device within the limits defined by the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the Recommended Operating Conditions limits. Voltages VCC, VCC1, and VCC2 are required for proper DMD operation. VSS must also be connected. All voltages are referenced to common ground VSS. Exceeding the recommended allowable absolute voltage difference between VCC and VCC1 may result in excess current draw. The difference between VCC and VCC1, |VCC – VCC1|, should be less than the specified limit. Optimal, long-term performance and optical efficiency of the Digital Micromirror Device (DMD) can be affected by various application parameters, including illumination spectrum, illumination power density, micromirror landed duty-cycle, ambient temperature (storage and operating), DMD temperature, ambient humidity (storage and operating), and power on or off duty cycle. TI recommends that application-specific effects be considered as early as possible in the design cycle. In some applications, the total DMD heat load can be dominated by the amount of incident light energy absorbed. See Micromirror Array Temperature Calculation for further details. The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1) shown in Figure 18 and the package thermal resistance in Thermal Information using Micromirror Array Temperature Calculation. Simultaneous exposure of the DMD to the maximum Recommended Operating Conditions for temperature and UV illumination will reduce device lifetime. Long-term is defined as the usable life of the device. Per Figure 1, the maximum operational case temperature should be derated based on the micromirror landed duty cycle that the DMD experiences in the end application. Refer to Micromirror Landed-On/Landed-Off Duty Cycle for a definition of micromirror landed duty cycle. Array temperatures beyond those specified as long-term are recommended for short-term conditions only (power-up). Short-term is defined as cumulative time over the usable life of the device and is less than 500 hours. The temperature delta is the highest difference between the ceramic test point (TP1) and window test points (TP2) and (TP3) in Figure 18. Total integrated illumination power density, above or below the indicated wavelength threshold or in the indicated wavelength range. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 13 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com Figure 1. Max Recommended DMD Temperature – Derating Curve 7.5 Thermal Information DLP7000 THERMAL METRIC FLP (Package) UNIT 203 PINS Thermal resistance, active area to TP1 (1) (1) 14 0.90 °C/W The DMD is designed to conduct absorbed and dissipated heat to the back of the package where it can be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the package within the temperature range specified in the Recommended Operating Conditions. The total heat load on the DMD is largely driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 7.6 Electrical Characteristics over the range of recommended supply voltage and recommended case operating temperature (unless otherwise noted). PARAMETERS TEST CONDITIONS High-level output voltage See Figure 11 VOH (1) , NOM MAX UNIT 2.4 V (1) VOL Low-level output voltage See Figure 11 VMBRST Clocking Pulse Waveform applied to MBRST[29:0] Input Pins (supplied by DLPA200) IOZ High impedance output current (1) IOH High-level output current (1) IOL VCC = 3.0 V, IOH = –20 mA MIN , Low-level output current (1) VCC = 3.6 V, IOH = 15 mA –27 VCC = 3.6 V 0.4 V 26.5 V 10 µA VOH = 2.4 V, VCC ≥ 3 V –20 VOH = 1.7 V, VCC ≥ 2.25 V –15 VOL = 0.4 V, VCC ≥ 3 V 15 VOL = 0.4 V, VCC ≥ 2.25 V 14 mA mA VIH High-level input voltage (1) 1.7 VCC + .3 V VIL Low-level input voltage (1) –0.3 0.7 V µA (1) IIL Low-level input current VCC = 3.6 V, VI = 0 V –60 IIH High-level input current (1) VCC = 3.6 V, VI = VCC 200 µA ICC Current into VCC pin VCC = 3.6 V 1475 mA ICCI Current into VCCI pin (2) VCCI = 3.6 V 450 mA ICC2 Current into VCC2 pin VCC2 = 8.75 V ZIN Internal Differential Impedance 95 ZLINE Line Differential Impedance (PWB, Trace) 90 CI Input capacitance (1) CO Output capacitance (1) CIM Input capacitance for MBRST[29:0] pins f = 1 MHz (1) (2) 25 mA 105 Ω 110 Ω f = 1 MHz 10 pF f = 1 MHz 10 pF 270 pF 220 100 Applies to LVCMOS pins only. Exceeding the maximum allowable absolute voltage difference between VCC and VCCI may result in excess current draw. See the Absolute Maximum Ratings for details. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 15 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com 7.7 LVDS Timing Requirements over operating free-air temperature range (unless otherwise noted). See Figure 2 MIN fDCLK_* DCLK_* clock frequency {where * = [A, or B]} 200 tc Clock Cycle - DLCK_* 2.5 tw Pulse Width - DLCK_* ts Setup Time - D_*[15:0] and SCTRL_* before DCLK_* th Hold Time, D_*[15:0] and SCTRL_* after DCLK_* tskew Skew between bus A and B NOM MAX UNIT 400 MHz ns 1.25 ns 0.35 ns 0.35 ns –1.25 1.25 ns 7.8 LVDS Waveform Requirements over operating free-air temperature range (unless otherwise noted). See Figure 3 |VID| Input Differential Voltage (absolute difference) VCM Common Mode Voltage VLVDS LVDS Voltage tr tr MIN NOM MAX UNIT 100 400 600 mV 1200 mV 0 2000 mV Rise Time (20% to 80%) 100 400 ps Fall Time (80% to 20%) 100 400 ps 7.9 Serial Control Bus Timing Requirements over operating free-air temperature range (unless otherwise noted). See Figure 4 and Figure 5 MIN MAX UNIT 50 NOM 500 kHz –300 300 ns 960 ns fSCP_CLK SCP Clock Frequency tSCP_SKEW Time between valid SCP_DI and rising edge of SCP_CLK tSCP_DELAY Time between valid SCP_DO and rising edge of SCP_CLK tSCP_EN Time between falling edge of SCP_EN and the first rising edge of SCP_CLK t_SCP Rise time for SCP signals 200 ns tf_SCP Fall time for SCP signals 200 ns 16 Submit Documentation Feedback 30 ns Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 tw DCLK_AN DCLK_AP th tw tc ts ts th SCTRL_AN SCTRL_AP tskew D_AN(15:0) D_AP(15:0) DCLK_BN DCLK_BP th tw tw tc ts ts th SCTRL_BN SCTRL_BP D_BN(15:0) D_BP(15:0) Figure 2. LVDS Timing Waveforms VLVDS (v) VLVDSmax = VCM + |½VID| VLVDSmax Tf (20% - 80%) VLVDS = V CM +/- | 1/2 V ID | VID VCM T r (20% - 80%) VLVDS min VLVDS min = 0 Time Figure 3. LVDS Waveform Requirements Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 17 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com tc SCPCLK fclock = 1 / tc 50% 50% tSCP_SKEW SCPDI 50% tSCP_DELAY SCPD0 50% Figure 4. Serial Communications Bus Timing Parameters tr_SCP tf_SCP Input Controller VCC SCP_CLK, SCP_DI, SCP_EN VCC/2 0v Figure 5. Serial Communications Bus Waveform Requirements 18 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 7.10 Systems Mounting Interface Loads MIN Maximum system mounting interface load to be applied to the: Thermal Interface area Electrical Interface area Datum “A” Interface area (1) (See Figure 6) (1) NOM MAX UNIT 111 N 423 N 400 N Combined loads of the thermal and electrical interface areas in excess of Datum “A” load shall be evenly distributed outside the Datum “A” area (425 + 111 – Datum “A"), or the combined loads of the thermal and electrical areas reduced. Thermal Interface Area Electrical Interface Area (all area except thermal area) Other Areas Datum 'A' Areas Figure 6. System Interface Loads Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 19 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com 7.11 Micromirror Array Physical Characteristics VALUE UNIT M Number of active columns PARAMETER 1024 micromirrors N Number of active rows 768 micromirrors P Micromirror (pixel) pitch µm M×P See Figure 7 14.008 mm Micromirror active array height N×P 10.506 mm Micromirror active border Pond of micromirror (POM) (1) 6 micromirrors/side M±4 M±3 M±2 M±1 The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM. These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF. 0 1 2 3 (1) 13.68 Micromirror active array width 0 1 2 3 DMD Active Array NxP M x N Micromirrors N±4 N±3 N±2 N±1 MxP P Border micromirrors omitted for clarity. Details omitted for clarity. P Not to scale. P P Refer to Micromirror Array Physical Characteristics table for M, N, and P specifications. Figure 7. Micromirror Array Physical Characteristics 20 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 7.12 Micromirror Array Optical Characteristics TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters. PARAMETER CONDITIONS MIN DMD “parked” state(1) (2) (3), see Figure 13 a Micromirror tilt angle β Micromirror tilt angle tolerance(1) (4) (6) (7) DMD “landed” state(1) (4) see Figure 13 (8) –1 1 4 (10) 13 Micromirror switching time Non-operating micromirrors(12) 22 10 adjacent micromirrors Micromirror array optical efficiency(14) (15) 400 nm to 700 nm, with all micromirrors in the ON state 0 44 µs µs Non-adjacent micromirrors See Figure 12 degrees µs 43 Orientation of the micromirror axis-ofrotation(13) UNIT degrees 12 Micromirror crossover time(9) Array switching time at 400 MHz with global reset(11) MAX 0 (5) See Figure 13 NOM 45 46 micromirrors degrees 68% (1) Measured relative to the plane formed by the overall micromirror array. (2) “Parking” the micromirror array returns all of the micromirrors to an essentially flat (0˚) state (as measured relative to the plane formed by the overall micromirror array). (3) When the micromirror array is “parked”, the tilt angle of each individual micromirror is uncontrolled. (4) Additional variation exists between the micromirror array and the package datums, as shown in the Mechanical, Packaging, and Orderable Information. (5) When the micromirror array is “landed”, the tilt angle of each individual micromirror is dictated by the binary contents of the CMOS memory cell associated with each individual micromirror. A binary value of “1” will result in a micromirror “landing” in an nominal angular position of “+12°”. A binary value of 0 results in a micromirror “landing” in an nominal angular position of “–12°”. (6) Represents the “landed” tilt angle variation relative to the Nominal “landed” tilt angle. (7) Represents the variation that can occur between any two individual micromirrors, located on the same device or located on different devices. (8) For some applications, it is critical to account for the micromirror tilt angle variation in the overall System Optical Design. With some System Optical Designs, the micromirror tilt angle variation within a device may result in perceivable non-uniformities in the light field reflected from the micromirror array. With some System Optical Designs, the micromirror tilt angle variation between devices may result in colorimetry variations and/or system contrast variations. (9) Micromirror crossover time is primarily a function of the natural response time of the micromirrors and is the time it takes for the micromirror to crossover to the other state, but does not include mechanical settling time. (10) Micromirror switching time is the time before a micromirror may be addressed again. Crossover time plus mechanical settling time. (11) Array switching is controlled and coordinated by the DLPC410 (DLPS024) and DLPA200 (DLPS015). Nominal Switching time depends on the system implementation and represents the time for the entire micromirror array to be refreshed (array loaded plus reset and mirror settling time). (12) Non-operating micromirror is defined as a micromirror that is unable to transition nominally from the –12° position to +12° or vice versa. (13) Measured relative to the package datums “B” and “C”, shown in Mechanical, Packaging, and Orderable Information. (14) The minimum or maximum DMD optical efficiency observed depends on numerous application-specific design variables, such as: – Illumination wavelength, bandwidth/line-width, degree of coherence – Illumination angle, plus angle tolerance – Illumination and projection aperture size, and location in the system optical path – IIlumination overfill of the DMD micromirror array – Aberrations present in the illumination source and/or path – Aberrations present in the projection path The specified nominal DMD optical efficiency is based on the following use conditions: – Visible illumination (400 nm – 700 nm) – Input illumination optical axis oriented at 24° relative to the window normal – Projection optical axis oriented at 0° relative to the window normal – f/3.0 illumination aperture – f/2.4 projection aperture Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 21 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com Based on these use conditions, the nominal DMD optical efficiency results from the following four components: – Micromirror array fill factor: nominally 92% – Micromirror array diffraction efficiency: nominally 86% – Micromirror surface reflectivity: nominally 88% – Window transmission: nominally 97% (single pass, through two surface transitions) (15) Does not account for the effect of micromirror switching duty cycle, which is application dependent. Micromirror switching duty cycle represents the percentage of time that the micromirror is actually reflecting light from the optical illumination path to the optical projection path. This duty cycle depends on the illumination aperture size, the projection aperture size, and the micromirror array update rate. 7.13 Window Characteristics PARAMETER (1) CONDITIONS Window material designation Corning 7056 Window refractive index at wavelength 589 nm Window flatness (2) 4 Illumination overfill Refer to Illumination Overfill (4) MAX UNIT fringes (3) See (1) (2) (3) TYP 1.487 Per 25 mm Window aperture Window transmittance, single–pass through both surfaces and glass (4) MIN At wavelength 405 nm. Applies to 0° and 24° AOI only. 95% Minimum within the wavelength range 420 nm to 680 nm. Applies to all angles 0° to 30° AOI. 97% Average over the wavelength range 420 nm to 680 nm. Applies to all angles 30° to 45° AOI. 97% See Optical Interface and System Image Quality Considerations for more information. At a wavelength of 632.8 nm. For details regarding the size and location of the window aperture, see the package mechanical characteristics listed in the Mechanical ICD in the Mechanical, Packaging, and Orderable Information. See the TI application report DLPA031, Wavelength Transmittance Considerations for DLP DMD Window. 7.14 Chipset Component Usage Specification The DLP7000 is a component of one or more DLP chipsets. Reliable function and operation of the DLP7000 requires that it be used in conjunction with the other components of the applicable DLP chipset, including those components that contain or implement TI DMD control technology. TI DMD control technology is the TI technology and devices for operating or controlling a DLP DMD. 22 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 8 Detailed Description 8.1 Overview Optically, the DLP7000 consists of 786,432 highly reflective, digitally switchable, micrometer-sized mirrors (“micromirrors”), organized in a two-dimensional array of 1024 micromirror columns by 768 micromirror rows (Figure 12). Each aluminum micromirror is approximately 13.68 microns in size (see the “Micromirror Pitch” in Figure 12), and is switchable between two discrete angular positions: –12° and +12°. The angular positions are measured relative to a 0° “flat state”, which is parallel to the array plane (see Figure 13). The tilt direction is perpendicular to the hinge-axis which is positioned diagonally relative to the overall array. The “On State” landed position is directed towards “Row 0, Column 0” (upper left) corner of the device package (see the “Micromirror Hinge-Axis Orientation” in Figure 12). In the field of visual displays, the 1024 by 768 “pixel” resolution is referred to as "XGA". Each individual micromirror is positioned over a corresponding CMOS memory cell. The angular position of a specific micromirror is determined by the binary state (logic 0 or 1) of the corresponding CMOS memory cell contents, after the micromirror "clocking pulse" is applied. The angular position (–12° or +12°) of the individual micromirrors changes synchronously with a micromirror “clocking pulse”, rather than being synchronous with the CMOS memory cell data update. Therefore, writing a logic 1 into a memory cell followed by a micromirror "clocking pulse" will result in the corresponding micromirror switching to a +12° position. Writing a logic 0 into a memory cell followed by a micromirror "clocking pulse" will result in the corresponding micromirror switching to a –12° position. Updating the angular position of the micromirror array consists of two steps. First, updating the contents of the CMOS memory. Second, application of a Micromirror Clocking Pulse to all or a portion of the micromirror array (depending upon the configuration of the system). Micromirror Clocking Pulses are generated externally by a DLPA200, with application of the pulses being coordinated by the DLPC410 controller. Around the perimeter of the 1024 by 768 array of micromirrors is a uniform band of “border” micromirrors. The border micromirrors are not user-addressable. The border micromirrors land in the –12° position once power has been applied to the device. There are 10 border micromirrors on each side of the 1024 by 768 active array. Figure 8 shows a DLPC410 and DLP7000 Chipset Block Diagram. The DLPC410 and DLPA200 control and coordinate the data loading and micromirror switching for reliable DLP7000 operation. The DLPR410 is the programmed PROM required to properly configure the DLPC410 controller. For more information on the chipset components, see Application and Implementation. For a typical system application using the DLPC410 chipset including the DLP7000, see Figure 19. 8.2 Functional Block Diagram Figure 8 is a simplified system block diagram showing the use of the following components: ● DLPC410 – Xilinx [XC5VLX30] FPGA configured to provide high-speed DMD data and control, and DLPA200 timing and control ● DLPR410 – [XCF16PFSG48C] serial flash PROM contains startup configuration information (EEPROM) ● DLPA200 – DMD micromirror driver for the DLP7000 DMD ● DLP7000 – Spatial Light Modulator (DMD) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 23 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com Figure 8. DLPC410 and DLP7000 Chipset Block Diagram 24 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 8.3 Feature Description 8.3.1 DLPC410 Chipset DMD Features Table 1. DLP7000 Overview DMD ARRAY PATTERNS/s DATA RATE (Gbps) MIRROR PITCH DLP7000 - 0.7”XGA 1024 × 768 32552 25.6 13.68 μm 8.3.1.1 DLPC410 - Digital Controller for DLP Discovery 4100 Chipset The DLP7000 chipset includes the DLPC410 controller which provides a high-speed LVDS data and control interface for DMD control. This interface is also connected to a second FPGA used to drive applications (not included in the chipset). The DLPC410 generates DMD and DLPA200 initialization and control signals in response to the inputs on the control interface. For more information, see the DLPC410 data sheet DLPS024. 8.3.1.2 DLPA200 - DMD Micromirror Driver DLPA200 micromirror driver provides the micromirror clocking pulse driver functions for the DMD. One DLPA200 is required for DLP7000. For more information on the DLPA200, see the DLPA200 data sheet DLPS015. 8.3.1.3 DLPR410 - PROM for DLP Discovery 4100 Chipset The DLPC410 is configured at startup from the serial flash PROM. The contents of this PROM can not be altered. For more information, see the DLPR410 data sheet (DLPS027) and the DLPC410 data sheet (DLPS024). 8.3.1.4 DLP7000 - DLP 0.7 XGA 2xLVDS Type-A DMD 8.3.1.4.1 DLP7000 XGA Chip Set Interfaces This section will describe the interface between the different components included in the chipset. For more information on component interfacing, see Application and Implementation. 8.3.1.4.1.1 DLPC410 Interface Description 8.3.1.4.1.1.1 DLPC410 IO Table 2 describes the inputs and outputs of the DLPC410 to the user. For more details on these signals, see the DLPC410 data sheet (DLPS024). Table 2. Input/Output Description PIN NAME DESCRIPTION I/O ARST Asynchronous active low reset I CLKIN_R Reference clock, 50 MHz I DIN_[A,B,C,D](15:0) LVDS DDR input for data bus A,B,C,D (15:0) I DCLKIN[A,B,C,D] LVDS inputs for data clock (200 - 400 MHz) on bus A, B, C, and D I DVALID[A,B,C,D] LVDS input used to start write sequence for bus A, B, C, and D I ROWMD(1:0) DMD row address and row counter control I ROWAD(10:0) DMD row address pointer I BLK_AD(3:0) DMD mirror block address pointer I BLK_MD(1:0) DMD mirror block reset and clear command modes I PWR_FLOAT Used to float DMD mirrors before complete loss of power I DMD_TYPE(3:0) DMD type in use O RST_ACTIVE Indicates DMD mirror reset in progress O INIT_ACTIVE Initialization in progress. O Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 25 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com Table 2. Input/Output Description (continued) PIN NAME DESCRIPTION I/O VLED0 System “heartbeat” signal O VLED1 Denotes initialization complete O 8.3.1.4.1.1.2 Initialization The INIT_ACTIVE (Table 2) signal indicates that the DLP7000, DLPA200, and DLPC410 are in an initialization state after power is applied. During this initialization period, the DLPC410 is initializing the DLP7000 and DLPA200 by setting all internal registers to their correct states. When this signal goes low, the system has completed initialization. System initialization takes approximately 220 ms to complete. Data and command write cycles should not be asserted during the initialization. During initialization the user must send a training pattern to the DLPC410 on all data and DVALID lines to correctly align the data inputs to the data clock. For more information about the interface training pattern, see the DLPC410 data sheet (DLPS024). 8.3.1.4.1.1.3 DMD Device Detection The DLPC410 automatically detects the DMD type and device ID. DMD_TYPE (Table 2) is an output from the DLPC410 that contains the DMD information. Only DMDs sold with the chipset or kit are recognized by the automatic detection function. All other DMDs do not operate with the DLPC410. 8.3.1.4.1.1.4 Power Down To ensure long term reliability of the DLP7000, a shutdown procedure must be executed. Prior to power removal, assert the PWR_FLOAT (Table 2) signal and allow approximately 300 µs for the procedure to complete. This procedure assures the mirrors are in a flat state. 8.3.1.4.2 DLPC410 to DMD Interface 8.3.1.4.2.1 DLPC410 to DMD IO Description Table 3 lists the available controls and status pin names and their corresponding signal type, along with a brief functional description. Table 3. DLPC410 to DMD I/O Pin Descriptions PIN NAME DESCRIPTION I/O DDC_DOUT_[A,B,C,D](15:0) LVDS DDR output to DMD data bus A,B,C,D (15:0) O DDC_DCLKOUT_[A,B,C,D] LVDS output to DMD data clock A,B,C,D O DDC_SCTRL_[A,B,C,D] LVDS DDR output to DMD data control A,B,C,D O 26 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 8.3.1.4.2.2 Data Flow Figure 9 shows the data traffic through the DLPC410. Special considerations are necessary when laying out the DLPC410 to allow best signal flow. LVDS BUS A DIN_A(15:0) DCLK_A DVALID_A LVDS BUS B DIN_B(15:0) DCLK_B DVALID_B LVDS BUS D LVDS BUS C DIN_D(15:0) DCLK_D DVALID_D DIN_C(15:0) DCLK_C DVALID_C DLPC410 LVDS BUS A LVDS BUS D DOUT_A(15:0) DCLKOUT_A SCTRL_A DOUT_D(15:0) DCLKOUT_D SCTRL_D LVDS BUS C DOUT_C(15:0) DCLKOUT_C SCTRL_C LVDS BUS B DOUT_B (15:0) DIN_B(15:0) DCLKOUT_B DCLK_B SCTRL_B DVALID_B Figure 9. DLPC410 Data Flow Two LVDS buses transfer the data from the user to the DLPC410. Each bus has its data clock that is input edge aligned with the data (DCLK). Each bus also has its own validation signal that qualifies the data input to the DLPC410 (DVALID). Output LVDS buses transfer data from the DLPC410 to the DLP7000. Output buses LVDS A and LVDS B are used as highlighted in Figure 9. 8.3.1.4.3 DLPC410 to DLPA200 Interface 8.3.1.4.3.1 DLPA200 Operation The DLPA200 DMD Micromirror Driver is a mixed-signal Application Specific Integrated Circuit (ASIC) that combines the necessary high-voltage power supply generation and Micromirror Clocking Pulse functions for a family of DMDs. The DLPA200 is programmable and controllable to meet all current and anticipated DMD requirements. The DLPA200 operates from a 12-V power supply input. For more detailed information on the DLPA200, see the DLPA200 data sheet. 8.3.1.4.3.2 DLPC410 to DLPA200 IO Description The Serial Communications Port (SCP) is a full duplex, synchronous, character-oriented (byte) port that allows exchange of commands from the DLPC410 to the DLPA200. One SCP bus is used for the DLP7000. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 27 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com DLPA200 SCP bus DLPC410 SCP bus DLPA200 (Only with 1080p DMD) Figure 10. Serial Port System Configuration There are five signal lines associated with the SCP bus: SCPEN, SCPCK, SCPDI, SCPDO, and IRQ. Table 4 lists the available controls and status pin names and their corresponding signal type, along with a brief functional description. Table 4. DLPC410 to DLPA200 I/O Pin Descriptions PIN NAME DESCRIPTION I/O A_SCPEN Active low chip select for DLPA200 serial bus O A_STROBE DLPA200 control signal strobe O A_MODE(1:0) DLPA200 mode control O A_SEL(1:0) DLPA200 select control O A_ADDR(3:0) DLPA200 address control O B_SCPEN Active low chip select for DLPA200 serial bus (2) O B_STROBE DLPA200 control signal strobe (2) O B_MODE(1:0) DLPA200 mode control O B_SEL(1:0) DLPA200 select control O B_ADDR(3:0) DLPA200 address control O The DLPA200 provides a variety of output options to the DMD by selecting logic control inputs: MODE[1:0], SEL[1:0] and reset group address A[3:0] (Table 4). The MODE[1:0] input determines whether a single output, two outputs, four outputs, or all outputs, will be selected. Output levels (VBIAS, VOFFSET, or VRESET) are selected by SEL[1:0] pins. Selected outputs are tri-stated on the rising edge of the STROBE signal and latched to the selected voltage level after a break-before-make delay. Outputs will remain latched at the last Micromirror Clocking Pulse waveform level until the next Micromirror Clocking Pulse waveform cycle. 8.3.1.4.4 DLPA200 to DLP7000 Interface 8.3.1.4.4.1 DLPA200 to DLP7000 Interface Overview The DLPA200 generates three voltages: VBIAS, VRESET, and VOFFSET that are supplied to the DMD MBRST lines in various sequences through the Micromirror Clocking Pulse driver function. VOFFSET is also supplied directly to the DMD as DMDVCC2. A fourth DMD power supply, DMDVCC, is supplied directly to the DMD by regulators. The function of the Micromirror Clocking Pulse driver is to switch selected outputs in patterns between the three voltage levels (VBIAS, VRESET and VOFFSET) to generate one of several Micromirror Clocking Pulse waveforms. The order of these Micromirror Clocking Pulse waveform events is controlled externally by the logic control inputs and timed by the STROBE signal. DLPC410 automatically detects the DMD type and then uses the DMD type to determine the appropriate Micromirror Clocking Pulse waveform. 28 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 A direct Micromirror Clocking Pulse operation causes a mirror to transition directly from one latched state to the next. The address must already be set up on the mirror electrodes when the Micromirror Clocking Pulse is initiated. Where the desired mirror display period does not allow for time to set up the address, a Micromirror Clocking Pulse with release can be performed. This operation allows the mirror to go to a relaxed state regardless of the address while a new address is set up, after which the mirror can be driven to a new latched state. A mirror in the relaxed state typically reflects light into a system collection aperture and can be thought of as “off” although the light is likely to be more than a mirror latched in the “off” state. System designers should carefully evaluate the impact of relaxed mirror conditions on optical performance. 8.3.1.5 Measurement Conditions The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. Figure 11 shows an equivalent test load circuit for the output under test. The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks. LOAD CIRCUIT RL From Output Under Test Tester Channel CL = 50 pF CL = 5 pF for Disable Time Figure 11. Test Load Circuit for AC Timing Measurements Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 29 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com Incident Illumination Package Pin A1 Corner Details Omitted For Clarity. Not To Scale. DMD Micromirror Array 0 (Border micromirrors eliminated for clarity) M±1 Active Micromirror Array 0 N±1 Micromirror Hinge-Axis Orientation Micromirror Pitch ³2Q-6WDWH´ Tilt Direction 45° P (um) P (um) P (um) ³2II-6WDWH´ Tilt Direction P (um) Figure 12. DMD Micromirror Array, Pitch, and Hinge-Axis Orientation 30 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 Ill Inc um id in en at t io n www.ti.com Package Pin A1 Corner Ill Inc um id in en at t io n DLP7000 Two “On-State” Micromirrors Two “Off-State” Micromirrors h Pat nt ide ht Inc n-Lig tio ina Projected-Light Path m Illu th nt t Pa ide gh Inc on-Li ati m in Illu For Reference t gh Li et a h St at ff- P Flat-State ( “parked” ) Micromirror Position O a±b -a ± b Silicon Substrate “On-State” Micromirror Silicon Substrate “Off-State” Micromirror Figure 13. Micromirror Landed Positions and Light Paths Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 31 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com 8.4 Device Functional Modes 8.4.1 DMD Operation The DLP7000 has only one functional mode, it is set to be highly optimized for low latency and high speed in generating mirror clocking pulses and timings. When operated with the DLPC410 controller in conjunction with the DLPA200 driver, the DLP7000 can be operated in several display modes. The DLP7000 is loaded as 16 blocks of 48 rows each. Figure 14, Figure 15, Figure 16, and Figure 17 show how the image is loaded by the different Micromirror Clocking Pulse modes. There are four Micromirror Clocking Pulse modes that determine which blocks are "reset" when a Micromirror Clocking Pulse command is issued: • Single block mode • Dual block mode • Quad block mode • Global mode 8.4.1.1 Single Block Mode In single block mode, a single block can be loaded and reset in any order. After a block is loaded, it can be reset to transfer the information to the mechanical state of the mirrors. Data Loaded Reset 1 6 Re se t Line s (0 – 15 ) Figure 14. Single Block Mode Diagram 8.4.1.2 Dual Block Mode In dual block mode, reset blocks are paired together as follows (0-1), (2-3), (4-5) . . . (14-15). These pairs can be reset in any order. After data is loaded a pair can be reset to transfer the information to the mechanical state of the mirrors. Data Loaded Reset 1 6 Re se t Line s (0 – 15 ) Figure 15. Dual Block Mode Diagram 32 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 Device Functional Modes (continued) 8.4.1.3 Quad Block Mode In quad block mode, reset blocks are grouped together in fours as follows (0-3), (4-7), (8-11) and (12-15). Each quad group can be randomly addressed and reset. After a quad group is loaded, it can be reset to transfer the information to the mechanical state of the mirrors. 1 6 Re se t Line s (0 – 15 ) Reset Data Loaded Figure 16. Quad Block Mode Diagram 8.4.1.4 Global Mode In global mode, all reset blocks are grouped into a single group and reset together. The entire DMD must be loaded with the desired data before issuing a Global Reset to transfer the information to the mechanical state of the mirrors. 1 6 Re se t Line s (0 – 15 ) Reset Data Loaded Figure 17. Global Mode Diagram Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 33 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com 8.5 Optical Interface and System Image Quality Considerations NOTE TI assumes no responsibility for image quality artifacts or DMD failures caused by optical system operating conditions exceeding limits described previously. 8.5.1 Optical Interface and System Image Quality TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment optical performance involves making trade-offs between numerous component and system design parameters. Optimizing system optical performance and image quality strongly relate to optical system design parameter trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical performance is contingent on compliance to the optical system operating conditions described in the following sections. 8.5.2 Numerical Aperture and Stray Light Control The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area should be the same. This angle should not exceed the nominal device mirror tilt angle unless appropriate apertures are added in the illumination and/or projection pupils to block out flat-state and stray light from the projection lens. The mirror tilt angle defines DMD capability to separate the "ON" optical path from any other light path, including undesirable flat-state specular reflections from the DMD window, DMD border structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture exceeds the mirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger than the illumination numerical aperture angle, objectionable artifacts in the display’s border and/or active area could occur. 8.5.3 Pupil Match TI recommends the exit pupil of the illumination is nominally centered within 2° of the entrance pupil of the projection optics. Misalignment of pupils can create objectionable artifacts in the display’s border and/or active area, which may require additional system apertures to control, especially if the numerical aperture of the system exceeds the pixel tilt angle. 8.5.4 Illumination Overfill The active area of the device is surrounded by an aperture on the inside DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical operating conditions. Overfill light illuminating the window aperture can create artifacts from the edge of the window aperture opening and other surface anomalies that may be visible on the screen. The illumination optical system should be designed to limit light flux incident anywhere on the window aperture from exceeding approximately 10% of the average flux level in the active area. Depending on the particular system’s optical architecture, overfill light may have to be further reduced below the suggested 10% level in order to be acceptable. 34 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 8.6 Micromirror Array Temperature Calculation Achieving optimal DMD performance requires proper management of the maximum DMD case temperature, the maximum temperature of any individual micromirror in the active array, the maximum temperature of the window aperture, and the temperature gradient between case temperature and the predicted micromirror array temperature. (see Figure 18). See the Recommended Operating Conditions for applicable temperature limits. 8.6.1 Package Thermal Resistance The DMD is designed to conduct absorbed and dissipated heat to the back of the Type A package where it can be removed by an appropriate heat sink. The heat sink and cooling system must be capable of maintaining the package within the specified operational temperatures, refer to Figure 18. The total heat load on the DMD is typically driven by the incident light absorbed by the active area; although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. 8.6.2 Case Temperature The temperature of the DMD case can be measured directly. For consistency, thermal test points TP1, TP2, and TP3 are defined, as shown in Figure 18. 3X 15.88 TP3 TP1 TP2 TP3 (TP2) Array TP3 TP2 10.16 TP1 Figure 18. Thermal Test Point Location Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 35 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com Micromirror Array Temperature Calculation (continued) 8.6.3 Micromirror Array Temperature Calculation - Lumens Based (typically used for display applications) Micromirror array temperature cannot be measured directly; therefore, it must be computed analytically from: • the measurement points (Figure 18) • the package thermal resistance • the electrical power • the illumination heat load The relationship between micromirror array temperature and the reference ceramic temperature (thermal test point TP1 in Figure 18) is provided by the following equations: TARRAY = T CERAMIC + (QARRAY × RARRAY-TO-CERAMIC) QARRAY = QELECTRICAL + QILLUMINATION where • • • • • • • • TARRAY = computed array temperature (°C) TCERAMIC = measured ceramic temperature (°C) (TP1 location) RARRAY-TO-CERAMIC = thermal resistance of DMD package (specified in Thermal Information) from array to ceramic TP1 (°C/W) QARRAY = total power (electrical + absorbed) on the array (Watts) QELECTRICAL = nominal electrical power (Watts) QILLUMINATION = (CL2W × SL) (Watts) CL2W = conversion constant for screen lumens to power on DMD (Watts/lumen) SL = measured screen lumens The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating frequencies. A nominal electrical power dissipation to use when calculating array temperature is 4.4 Watts. The absorbed power from the illumination source is variable and depends on the operating state of the micromirrors and the intensity of the light source. The conversion constant CL2W is based on the DMD input illumination characteristics. It assumes a spectral efficiency of 300 lumens/Watt for the projected light and an illumination distribution of 83.7% on the active array and 16.3% on the array border. The equations shown above are valid for a system with a total projection efficiency through the projection lens from the DMD to the projection surface of 87%. Sample calculation for typical application: • • • • • • • 36 TCeramic = 55°C (measured) SL = 2000 lm (measured) QELECTRICAL = 2.0 Watts RARRAY-TO-CERAMIC = 0.9 °C/W CL2W = 0.00274 W/lm QARRAY = 2.0 + (0.00274 W/lm × 2000 lm) = 7.48 W TARRAY = 55°C + (7.48 W x 0.9 °C) = 61.7 °C Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 Micromirror Array Temperature Calculation (continued) 8.6.4 Micromirror Array Temperature Calculation - Power Density Based Micromirror array temperature cannot be measured directly; therefore, it must be computed analytically from: • the measurement points (Figure 18) • the package thermal resistance • the electrical power • the illumination heat load The relationship between array temperature and the reference ceramic temperature (thermal test point TP1 in Figure 18) is provided by the following equations: TARRAY = T CERAMIC + (QARRAY × RARRAY-TO-CERAMIC) QARRAY = QELECTRICAL + (0.42 x QINCIDENT ) where • • • • • • TARRAY = computed array temperature (°C) TCERAMIC = measured ceramic temperature (°C) (TP1 location) RARRAY-TO-CERAMIC = thermal resistance of DMD package (specified in Thermal Information) from array to ceramic TP1 (°C/W) QARRAY = total power (electrical + absorbed) on the array (Watts) QELECTRICAL = nominal electrical power (Watts) QINCIDENT = total incident optical power on DMD (Watts) The electrical power dissipation of the DMD is variable and depends on the voltages, data rates, and operating frequencies. A nominal electrical power dissipation to use when calculating array temperature is 4.4 watts. The absorbed power from the illumination source is variable and depends on the operating state of the micromirrors and the intensity of the light source. The equations shown above are valid for each DMD chip in a system. It assumes an illumination distribution of 83.7% on the active array and 16.3% on the array border. Sample Calculation for each DMD in a system with a measured illumination power density: • • • • • • • • • • TCeramic = 20°C (measured) ILLDENSITY = 11 Watts per cm2 (optical power on DMD per unit area) (measured) Overfill = 16.3% (optical design) QELECTRICAL = 2.0 Watts RARRAY-TO-CERAMIC = 0.9 °C/W Area of array = ( 1.4008 cm x 1.0506 cm ) = 1.4717 cm2 ILLAREA = 1.4717 cm2 / (83.7%) = 1.7583 cm2 QINCIDENT =11 W/cm2 x 1.7583 cm2 = 19.34 W QARRAY = 2.0 W + (0.42 x 19.34 W) = 10.12 W TARRAY = 20°C + (10.12 W x 0.9 °C) = 29.11 °C 8.7 Micromirror Landed-On/Landed-Off Duty Cycle 8.7.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle The micromirror landed-on/landed-off duty cycle (landed duty cycle) denotes the amount of time (as a percentage) that an individual micromirror is landed in the On–state versus the amount of time the same micromirror is landed in the Off–state. As an example, a landed duty cycle of 100/0 indicates that the referenced pixel is in the On-state 100% of the time (and in the Off-state 0% of the time); whereas 0/100 would indicate that the pixel is in the Off-state 100% of the time. Likewise, 50/50 indicates that the pixel is On 50% of the time and Off 50% of the time. Note that when assessing landed duty cycle, the time spent switching from one state (ON or OFF) to the other state (OFF or ON) is considered negligible and is thus ignored. Since a micromirror can only be landed in one state or the other (On or Off), the two numbers (percentages) always add to 100. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 37 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com Micromirror Landed-On/Landed-Off Duty Cycle (continued) 8.7.2 Landed Duty Cycle and Useful Life of the DMD Knowing the long-term average landed duty cycle (of the end product or application) is important because subjecting all (or a portion) of the DMD’s micromirror array (also called the active array) to an asymmetric landed duty cycle for a prolonged period of time can reduce the DMD’s usable life. Note that it is the symmetry/asymmetry of the landed duty cycle that is of relevance. The symmetry of the landed duty cycle is determined by how close the two numbers (percentages) are to being equal. For example, a landed duty cycle of 50/50 is perfectly symmetrical whereas a landed duty cycle of 100/0 or 0/100 is perfectly asymmetrical. 8.7.3 Landed Duty Cycle and Operational DMD Temperature Operational DMD Temperature and Landed Duty Cycle interact to affect the DMD’s usable life, and this interaction can be exploited to reduce the impact that an asymmetrical Landed Duty Cycle has on the DMD’s usable life. This is quantified in the de-rating curve shown in Figure 1. The importance of this curve is that: • All points along this curve represent the same usable life. • All points above this curve represent lower usable life (and the further away from the curve, the lower the usable life). • All points below this curve represent higher usable life (and the further away from the curve, the higher the usable life). In practice, this curve specifies the Maximum Operating DMD Temperature that the DMD should be operated at for a give long-term average Landed Duty Cycle. 8.7.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application During a given period of time, the Landed Duty Cycle of a given pixel follows from the image content being displayed by that pixel. For example, in the simplest case, when displaying pure-white on a given pixel for a given time period, that pixel will experience a 100/0 Landed Duty Cycle during that time period. Likewise, when displaying pure-black, the pixel will experience a 0/100 Landed Duty Cycle. Between the two extremes (ignoring for the moment color and any image processing that may be applied to an incoming image), the Landed Duty Cycle tracks one-to-one with the gray scale value, as shown in Table 5. Table 5. Grayscale Value and Landed Duty Cycle GRAYSCALE VALUE LANDED DUTY CYCLE 0% 0/100 10% 10/90 20% 20/80 30% 30/70 40% 40/60 50% 50/50 60% 60/40 70% 70/30 80% 80/20 90% 90/10 100% 100/0 Accounting for color rendition (but still ignoring image processing) requires knowing both the color intensity (from 0% to 100%) for each constituent primary color (red, green, and/or blue) for the given pixel as well as the color cycle time for each primary color, where “color cycle time” is the total percentage of the frame time that a given primary must be displayed in order to achieve the desired white point. During a given period of time, the landed duty cycle of a given pixel can be calculated as follows: Landed Duty Cycle = (Red_Cycle_% × Red_Scale_Value) + (Green_Cycle_% × Green_Scale_Value) + (Blue_Cycle_% 38 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 × Blue_Scale_Value) where • Red_Cycle_%, Green_Cycle_%, and Blue_Cycle_%, represent the percentage of the frame time that Red, Green, and Blue are displayed (respectively) to achieve the desired white point. (1) For example, assume that the red, green and blue color cycle times are 50%, 20%, and 30% respectively (in order to achieve the desired white point), then the Landed Duty Cycle for various combinations of red, green, blue color intensities would be as shown in Table 6. Table 6. Example Landed Duty Cycle for Full-Color RED CYCLE PERCENTAGE 50% GREEN CYCLE PERCENTAGE 20% BLUE CYCLE PERCENTAGE 30% RED SCALE VALUE GREEN SCALE VALUE BLUE SCALE VALUE 0% 0% 0% 0/100 100% 0% 0% 50/50 0% 100% 0% 20/80 0% 0% 100% 30/70 12% 0% 0% 6/94 0% 35% 0% 7/93 0% 0% 60% 18/82 100% 100% 0% 70/30 LANDED DUTY CYCLE 0% 100% 100% 50/50 100% 0% 100% 80/20 12% 35% 0% 13/87 0% 35% 60% 25/75 12% 0% 60% 24/76 100% 100% 100% 100/0 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 39 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The DLP7000 devices require they be coupled with the DLPC410 controller to provide a reliable solution for many different applications. The DMDs are spatial light modulators which reflect incoming light from an illumination source to one of two directions, with the primary direction being into a projection collection optic. Each application is derived primarily from the optical architecture of the system and the format of the data coming into the DLPC410. Applications of interest include 3D measurement systems, lithography, medical systems, and compressive sensing. 40 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 9.2 Typical Application A typical embedded system application using the DLPC410 controller and DLP7000 is shown in Figure 19. In this configuration, the DLPC410 controller supports input from an FPGA. The FPGA sends low-level data to the controller, enabling the system to be highly optimized for low latency and high speed. Figure 19. DLPC410 and DLP7000 Embedded Example Block Diagram Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 41 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com 9.2.1 Design Requirements All applications using the DLP7000 XGA chipset require both the controller and the DMD components for operation. The system also requires an external parallel flash memory device loaded with the DLPC410 Configuration and Support Firmware. The chipset has several system interfaces and requires some support circuitry. The following interfaces and support circuitry are required: • DLPC410 System Interfaces: – Control Interface – Trigger Interface – Input Data Interface – Illumination Interface – Reference Clock • DLP7000 Interfaces: – DLPC410 to DLP7000 Digital Data – DLPC410 to DLP7000 Control Interface – DLPC410 to DLP7000 Micromirror Reset Control Interface – DLPC410 to DLPA200 Micromirror Driver – DLPA200 to DLP7000 Micromirror Reset 9.2.2 Device Description The DLP7000 XGA chipset offers developers a convenient way to design a wide variety of industrial, medical, telecom and advanced display applications by delivering maximum flexibility in formatting data, sequencing data, and light patterns. The DLP7000 XGA chipset includes the following four components: DMD Digital Controller (DLPC410), EEPROM (DLPR410), DMD Micromirror Driver (DLPA200), and a DMD (DLP7000). DLPC410 Digital Controller for DLP Discovery 4100 chipset • Provides high speed LVDS data and control interface to the DLP7000. • Drives mirror clocking pulse and timing information to the DLPA200. • Supports random row addressing. DLPR410 PROM for DLP Discovery 4100 chipset • Contains startup configuration information for the DLPC410. DLPA200 DMD Micromirror Driver • Generates Micromirror Clocking Pulse control (sometimes referred to as a "Reset") of DMD mirrors. DLP7000 DLP 0.7 XGA 2xLVDS Type-A DMD • Steers light in two digital positions (+12º and -12º) using 1024 x 768 micromirror array of aluminum mirrors. Table 7. DLPC410 Chipset Configuration for 0.7 XGA Chipset 42 QUANTITY TI PART DESCRIPTION 1 DLP7000 DLP 0.7 XGA 2xLVDS Type-A DMD 1 DLPC410 Digital Controller for DLP Discovery 4100 chipset 1 DLPR410 PROM for DLP Discovery 4100 chipset 1 DLPA200 DMD Micromirror Driver Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 DLP7000 www.ti.com DLPS026F – AUGUST 2012 – REVISED JUNE 2019 Reliable function and operation of DLP7000 XGA chipsets require the components be used in conjunction with each other. This document describes the proper integration and use of the DLP7000 XGA chipset components. The DLP7000 XGA chipset can be combined with a user programmable Application FPGA (not included) to create high performance systems. 9.2.3 Detailed Design Procedure The DLP7000 DMD is well suited for visible light applications requiring fast, spatially programmable light patterns using the micromirror array. See the Functional Block Diagram to see the connections between the DLP7000 DMD, the DLPC410 digital controller, the DLPR410 EEPROM, and the DLPA200 DMD micromirror drivers. See the Figure 19 for an application example. Follow the Layout Guidelines for reliability. Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated Product Folder Links: DLP7000 43 DLP7000 DLPS026F – AUGUST 2012 – REVISED JUNE 2019 www.ti.com 10 Power Supply Recommendations 10.1 DMD Power-Up and Power-Down Procedures Repeated failure to adhere to the prescribed power-up and power-down procedures may affect device reliability. The DLP7000 power-up and power-down procedures are defined by the DLPC410 data sheet (DLPS024). These procedures must be followed to ensure reliable operation of the device. 11 Layout 11.1 Layout Guidelines The DLP7000 is part of a chipset that is controlled by the DLPC410 in conjunction with the DLPA200. These guidelines are targeted at designing a PCB board with these components. A target impedance of 50 Ω for single ended signals and 100 Ω between LVDS signals is specified for all signal layers. 11.1.1 Impedance Requirements Signals should be routed to have a matched impedance of 50 Ω ±10% except for LVDS differential pairs (DMD_DAT_Xnn, DMD_DCKL_Xn, and DMD_SCTRL_Xn), which should be matched to 100 Ω ±10% across each pair. 11.1.2 PCB Signal Routing When designing a PCB for the DLP7000 controlled by the DLPC410 in conjunction with the DLPA200, the following are recommended: Signal trace corners should be no sharper than 45°. Adjacent signal layers should have the predominate traces routed orthogonal to each other. TI recommends that critical signals be hand routed in the following order: DDR2 Memory, DMD (LVDS signals), then DLPA200 signals. TI does not recommend signal routing on power or ground planes. TI does not recommend ground plane slots. High speed signal traces should not cross over slots in adjacent power and/or ground planes. Table 8. Important Signal Trace Constraints SIGNAL CONSTRAINTS LVDS (DMD_DAT_xnn, DMD_DCKL_xn, and DMD_SCTRL_xn) P-to-N data, clock, and SCTRL: